5 4 3 2 1

VCC3V3 U1B

V5
U1A VCC3V3 IO_L6N_T0_VREF_13
U7
IO_L11P_T1_SRCC_13
V7
FPGA_TMS R168 IO_L11N_T1_SRCC_13
M9 J6 T9
DXP_0 TMS_0 FPGA_TCK 10k IO_L12P_T1_MRCC_13
M10 F9 U10
DXN_0 TCK_0 FPGA_TDI R446 U1F IO_L12N_T1_MRCC_13
G6 Y7
TDI_0 FPGA_TDO IO_L13P_T2_MRCC_13
F6 Y6
TDO_0 330R C7 PS_POR_B C186 0.1uf IO_L13N_T2_MRCC_13
L9 PS_POR_B_500 Y9
VREFP_0 DONE E7 PS_CLK_33.333M IO_L14P_T2_SRCC_13
K10 R11 PS_CLK_500 Y8
D VREFN_0 DONE_0 VCC3V3 IO_L14N_T2_SRCC_13 D
V8
R140 5.1k E6 IO_L15P_T2_DQS_13
L6 PS_MIO0_500 W8
PROGRAM_B_0 RED A7 QSPI_CS IO_L15N_T2_DQS_13
K9 PS_MIO1_500 W10
VP_0 R141 5.1k LED3 B8 SPI_DQ0/MIO2 IO_L16P_T2_13
L10 R10 PS_MIO2_500 W9
VN_0 INIT_B_0
PS_MIO3_500
D6 SPI_DQ1/MIO3 PART_B IO_L16N_T2_13
IO_L17P_T2_13
U9
VCC3V3 B7 SPI_DQ2/MIO4 U8
PS_MIO4_500 SPI_DQ3/MIO5
7020 USE IO_L17N_T2_13
M6 VCC3V3 A6 W11
CFGBVS_0 PS_MIO5_500
A5 SPI_SCK/MIO6 7010 NC IO_L18P_T2_13
N6 PS_MIO6_500 Y11
RSVDVCC3 D8 VCFG0/MIO7 IO_L18N_T2_13
R6 PS_MIO7_500 T5
RSVDVCC2 D5 VCFG1/MIO8 IO_L19P_T3_13
VCC1V8 J9 T6 PS_MIO8_500 U5
VCCADC_0 RSVDVCC1 B5 IO_L19N_T3_VREF_13
J10 F10 PS_MIO9_500 Y12
GNDADC_0 RSVDGND E9 IO_L20P_T3_13
PS_MIO10_500 Y13
C6 IO_L20N_T3_13
PS_MIO11_500 V11
D9 IO_L21P_T3_DQS_13
PS_MIO12_500 V10
E8 IO_L21N_T3_DQS_13
PS_MIO13_500 V6
C5 IO_L22P_T3_13
XC7Z020_1CLG400C PS_MIO14_500 W6
C8 IO_L22N_T3_13
PS_MIO15_500

HELLOFPGA.COM
XC7Z020_1CLG400C XC7Z020_1CLG400C VCC3V3

R20
U1D U1G
C U1C C

10k
G14 GPIO_G14 B10 PS_SRST_B
GPIO_R19 IO_0_35 GPIO_C20_L1P PS_SRST_B_501
R19 C20 E11
IO_0_34 GPIO_T11_L1P IO_L1P_T0_AD0P_35 GPIO_B20_L1N PS_MIO_VREF_501
T11 B20
IO_L1P_T0_34 GPIO_T10_L1N IO_L1N_T0_AD0N_35 GPIO_B19_L2P
T10 B19 A19
IO_L1N_T0_34 GPIO_T12_L2P IO_L2P_T0_AD8P_35 GPIO_A20_L2N PS_MIO16_501
T12 A20 E14
IO_L2P_T0_34 GPIO_U12_L2N IO_L2N_T0_AD8N_35 GPIO_E17_L3P PS_MIO17_501
U12 E17 B18
IO_L2N_T0_34 GPIO_U13_L3P IO_L3P_T0_DQS_AD1P_35 GPIO_D18_L3N PS_MIO18_501
U13 D18 D10
IO_L3P_T0_DQS_PUDC_B_34 GPIO_V13_L3N IO_L3N_T0_DQS_AD1N_35 GPIO_D19_L4P PS_MIO19_501
V13 D19 A17
IO_L3N_T0_DQS_34 GPIO_V12_L4P IO_L4P_T0_35 GPIO_D20_L4N PS_MIO20_501
V12 D20 F14
IO_L4P_T0_34 GPIO_W13_L4N IO_L4N_T0_35 GPIO_E18_L5P PS_MIO21_501
W13 E18 B17
IO_L4N_T0_34 GPIO_T14_L5P IO_L5P_T0_AD9P_35 GPIO_E19_L5N PS_MIO22_501
T14 E19 D11
IO_L5P_T0_34 GPIO_T15_L5N IO_L5N_T0_AD9N_35 GPIO_F16_L6P PS_MIO23_501
T15 F16 A16
IO_L5N_T0_34 GPIO_P14_L6P IO_L6P_T0_35 GPIO_F17_L6N PS_MIO24_501
P14 F17 F15
IO_L6P_T0_34 GPIO_R14_L6N IO_L6N_T0_VREF_35 GPIO_M19_L7P HDMI_TX_TMDS_DAT1_P PS_MIO25_501
R14 M19 A15
IO_L6N_T0_VREF_34 GPIO_Y16_L7P IO_L7P_T1_AD2P_35 GPIO_M20_L7N HDMI_TX_TMDS_DAT1_N PS_MIO26_501
Y16 M20 D13
IO_L7P_T1_34 GPIO_Y17_L7N IO_L7N_T1_AD2N_35 GPIO_M17_L8P PS_MIO27_501
Y17 M17 C16
IO_L7N_T1_34 GPIO_W14_L8P IO_L8P_T1_AD10P_35 GPIO_M18_L8N PS_MIO28_501
W14 M18 C13
IO_L8P_T1_34 GPIO_Y14_L8N IO_L8N_T1_AD10N_35 GPIO_L19_L9P HDMI_TX_TMDS_DAT2_P PS_MIO29_501
Y14 L19 C15
IO_L8N_T1_34 GPIO_T16_L9P IO_L9P_T1_DQS_AD3P_35 GPIO_L20_L9N HDMI_TX_TMDS_DAT2_N PS_MIO30_501
T16 L20 E16
IO_L9P_T1_DQS_34 GPIO_U17_L9N IO_L9N_T1_DQS_AD3N_35 GPIO_K19_L10P PS_MIO31_501
U17 K19 A14
IO_L9N_T1_DQS_34 GPIO_V15_L10P IO_L10P_T1_AD11P_35 GPIO_J19_L10N PS_MIO32_501
V15 J19 D15
IO_L10P_T1_34 GPIO_W15_L10N IO_L10N_T1_AD11N_35 GPIO_L16_L11P PS_MIO33_501
W15 L16 A12
IO_L10N_T1_34 GPIO_U14_L11P IO_L11P_T1_SRCC_35 GPIO_L17_L11N PS_MIO34_501
B U14 L17 F12 B
IO_L11P_T1_SRCC_34 GPIO_U15_L11N IO_L11N_T1_SRCC_35 GPIO_K17_L12P PS_MIO35_501
U15 K17 A11
IO_L11N_T1_SRCC_34 GPIO_U18_L12P IO_L12P_T1_MRCC_35 GPIO_K18_L12N CLK_50M PS_MIO36_501
U18 K18 A10
IO_L12P_T1_MRCC_34 GPIO_U19_L12N IO_L12N_T1_MRCC_35 GPIO_H16_L13P PS_MIO37_501
U19 H16 E13
IO_L12N_T1_MRCC_34 GPIO_N18_L13P IO_L13P_T2_MRCC_35 GPIO_H17_L13N 备注 CLK_50接到的是普通的IO ， PS_MIO38_501
N18 H17 C18
IO_L13P_T2_MRCC_34 GPIO_P19_L13N IO_L13N_T2_MRCC_35 GPIO_J18_L14P 如打算自己画板建议接到MRCC 的P端口 PS_MIO39_501 SD_CLK
P19 J18 D14 22R R453
IO_L13N_T2_MRCC_34 GPIO_N20_L14P IO_L14P_T2_AD4P_SRCC_35 GPIO_H18_L14N PS_MIO40_501 SD_CMD
N20 H18 C17
IO_L14P_T2_SRCC_34 GPIO_P20_L14N IO_L14N_T2_AD4N_SRCC_35 GPIO_F19_L15P PS_MIO41_501 SD_D0
P20 F19 E12
IO_L14N_T2_SRCC_34 GPIO_T20_L15P IO_L15P_T2_DQS_AD12P_35 GPIO_F20_L15N PS_MIO42_501 SD_D1
T20 F20 A9
IO_L15P_T2_DQS_34 GPIO_U20_L15N IO_L15N_T2_DQS_AD12N_35 GPIO_G17_L16P PS_MIO43_501 SD_D2
U20 G17 F13
IO_L15N_T2_DQS_34 GPIO_V20_L16P HDMI_TX_TMDS_DAT0_P IO_L16P_T2_35 GPIO_G18_L16N PS_MIO44_501 SD_D3
V20 G18 B15
IO_L16P_T2_34 GPIO_W20_L16N HDMI_TX_TMDS_DAT0_N IO_L16N_T2_35 GPIO_J20_L17P PS_MIO45_501
W20 J20 D16
IO_L16N_T2_34 GPIO_Y18_L17P IO_L17P_T2_AD5P_35 GPIO_H20_L17N PS_MIO46_501 SD_CD
Y18 H20 B14
IO_L17P_T2_34 GPIO_Y19_L17N IO_L17N_T2_AD5N_35 GPIO_G19_L18P PS_MIO47_501
Y19 G19 B12
IO_L17N_T2_34 GPIO_V16_L18P IO_L18P_T2_AD13P_35 GPIO_G20_L18N PS_MIO48_501
V16 G20 C12
IO_L18P_T2_34 GPIO_W16_L18N IO_L18N_T2_AD13N_35 GPIO_H15_L19P PS_MIO49_501
W16 H15 B13
IO_L18N_T2_34 GPIO_R16_L19P IO_L19P_T3_35 GPIO_G15_L19N PS_MIO50_501
R16 G15 B9
IO_L19P_T3_34 GPIO_R17_L19N IO_L19N_T3_VREF_35 GPIO_K14_L20P PS_MIO51_501
R17 K14 C10
IO_L19N_T3_VREF_34 GPIO_T17_L20P IO_L20P_T3_AD6P_35 GPIO_J14_L20N PS_MIO52_501
T17 J14 C11
IO_L20P_T3_34 GPIO_R18_L20N IO_L20N_T3_AD6N_35 GPIO_N15_L21P PS_MIO53_501
R18 N15
IO_L20N_T3_34 GPIO_V17_L21P IO_L21P_T3_DQS_AD14P_35 GPIO_N16_L21N
V17 N16
IO_L21P_T3_DQS_34 GPIO_V18_L21N IO_L21N_T3_DQS_AD14N_35 GPIO_L14_L22P
V18 L14
IO_L21N_T3_DQS_34 GPIO_W18_L22P HDMI_CLK_TX_TMDS_P IO_L22P_T3_AD7P_35 GPIO_L15_L22N
W18 L15 XC7Z020_1CLG400C
IO_L22P_T3_34 GPIO_W19_L22N HDMI_CLK_TX_TMDS_N IO_L22N_T3_AD7N_35 GPIO_M14_L23P
W19 M14
IO_L22N_T3_34 GPIO_N17_L23P IO_L23P_T3_35 GPIO_M15_L23N
A N17 M15 A
IO_L23P_T3_34 GPIO_P18_L23N IO_L23N_T3_35 GPIO_K16_L24P
P18 K16
IO_L23N_T3_34 GPIO_P15_L24P IO_L24P_T3_AD15P_35 GPIO_J16_L24N
P15 J16
IO_L24P_T3_34 GPIO_P16_L24N IO_L24N_T3_AD15N_35 GPIO_J15
P16 J15
IO_L24N_T3_34 GPIO_T19 IO_25_35
T19
IO_25_34
Title
www.hellofpga.com
XC7Z020_1CLG400C
XC7Z020_1CLG400C Size Document Number Rev
B <Doc> <RevCode>

Date: Thursday, October 13, 2022 Sheet 1 of 3

5 4 3 2 1
 5 4 3 2 1

5V_DC

VCC1V5
C166 0.1uf VCC1V8
C167 0.1uf 5V_DC
R169
D U16 D
VCC1V5
U17
1 6 20k R157 VCC1V8 R160
GND VBST R159
9.53k 1 6 10k
L3 2.2uh 2a GND VBST
2 5 27k
SW EN C184 L7 2.2uh 2a 2 5
SW EN
5V_DC 3 4
C162 C163 VIN VFB 0.1uf 5V_DC 3 4
C164 C165 R158 C168 C169 VIN VFB
22uf 22uf TPS563201_3A 10k C170 C171 R161

POWER
10uf/10V
10uf/10V 22uf 22uf TPS563201_3A C182 20k
10uf/10V
10uf/10V 0.1uf

5V_DC
VCC3V3 VCC1V0
C
C177 0.1uf C172 0.1uf C
R166 5V_DC
VCC3V3
U19 U18
VCC3V3 20k VCC1V0
1 6 R165 1 6 R162
GND VBST GND VBST
33k 3k
R452 L9 2.2uh 2a 2 5 L8 2.2uh 2a 2 5
SW EN SW EN 10k R163
330R 5V_DC 3 4 5V_DC 3 4
C178 C179 VIN VFB C173 C174 VIN VFB
RED C180 C181 R167 C175 C176 R164
LED4 22uf 22uf TPS563201_3A C183 10k 22uf 22uf TPS563201_3A 10k
10uf/10V
10uf/10V 10uf/10V
10uf/10V
0.1uf

B
HELLOFPGA.COM B

USB_POWER 5V_DC
U14 D22 SS24 U7
USB_DP 1 8
UD+ V3 VCC3V3
1 USB_DN 2 7 RXD GPIO_U13_L3P
GND UD- RXD TXD GPIO_T12_L2P
2 3 6
VBUS GND TXD
3 4 5 VCC3V3
SBU2 RTS# VCC
4
CC1 USB_DN CH340N
P1 5
P1 DN2 C191
P2 6
P2 DP1 0.1uf
P3 7
P3 DN1 USB_DP
P4 8
P4 DP2
9
SBU1
10
CC2
11
VBUS_2
R448 5.1K

R449 5.1K

12
GND_2

TYPEC

USB & UART

A A

Title www.hellofpga.com

Size Document Number Rev

B <Doc> <RevCode>

Date: Thursday, October 13, 2022 Sheet 1 of 1

5 4 3 2 1
 5 4 3 2 1

VCC3V3

HDMI OUT

R436

R437

R438

R439

R440

R441

R442

R443
D D

49.9R

49.9R

49.9R

49.9R

49.9R

49.9R

49.9R

49.9R
5V_DC

J29
D24 MBR052018
+5V
HDMI_TX_TMDS_DAT0_P C154 0.1uf _HDMI_TX_TMDS_DAT0_P 7
DATA0+
8
HDMI_TX_TMDS_DAT0_N C187 0.1uf _HDMI_TX_TMDS_DAT0_N DATA0_SHIELD
9
DATA0-
HDMI_TX_TMDS_DAT1_P C188 0.1uf _HDMI_TX_TMDS_DAT1_P 4 20
DATA1+ SHIELD_1
5
HDMI_TX_TMDS_DAT1_N C157 0.1uf _HDMI_TX_TMDS_DAT1_N DATA1_SHIELD
6
DATA1-
HDMI_TX_TMDS_DAT2_P C158 0.1uf _HDMI_TX_TMDS_DAT2_P 1 21
DATA2+ SHIELD_2
2
HDMI_TX_TMDS_DAT2_N C189 0.1uf _HDMI_TX_TMDS_DAT2_N DATA2_SHIELD
3
DATA2-
HDMI_CLK_TX_TMDS_P C190 0.1uf _HDMI_CLK_TX_TMDS_P 10
CLK+
11
HDMI_CLK_TX_TMDS_N C161 0.1uf _HDMI_CLK_TX_TMDS_N CLK_SHIELD
12 22
CLK- SHIELD_3
C C
13
CEC
15
SCL
16 23
SDA SHIELD_4
19
HOT PLUG DET
17
DDC/CEC_GND
14
RSVD
U15 CONN_HDMI
HDMI_TX_TMDS_DAT1_N 1 10 HDMI_TX_TMDS_DAT1_N
HDMI_TX_TMDS_DAT1_P CH1 NC_4 HDMI_TX_TMDS_DAT1_P
2 9
CH2 NC_3
3 8

HELLOFPGA.COM
GND_1 GND_2
HDMI_TX_TMDS_DAT2_N 4 7 HDMI_TX_TMDS_DAT2_N
HDMI_TX_TMDS_DAT2_P CH3 NC_2 HDMI_TX_TMDS_DAT2_P
5 6
CH4 NC_1

PUSB3FR4

B U8 B

HDMI_CLK_TX_TMDS_P 1 10 HDMI_CLK_TX_TMDS_P
HDMI_CLK_TX_TMDS_N CH1 NC_4 HDMI_CLK_TX_TMDS_N
2 9
CH2 NC_3
3 8
GND_1 GND_2
HDMI_TX_TMDS_DAT0_N 4 7 HDMI_TX_TMDS_DAT0_N
HDMI_TX_TMDS_DAT0_P 5 CH3 NC_2 HDMI_TX_TMDS_DAT0_P
6
CH4 NC_1

PUSB3FR4

HDMI ESD
A A

Title
www.hellofpga.com

Size Document Number Rev

B <Doc> <RevCode>

Date: Thursday, October 13, 2022 Sheet 1 of 1

5 4 3 2 1
 5 4 3 2 1

DDR PART
J1
D DDR3_VREF2 DDR3_VREF2 U1E D

MEM_ADD0 N3 E3 DDR3_D0
A0 DQ0
MEM_ADD1 P7 F7 DDR3_D1
P6 V3 A1 DQ1
PS_DDR_VREF1_502 PS_DDR_DQ31_502 MEM_ADD2 P3 F2 DDR3_D2
H6 V2 A2 DQ2
PS_DDR_VREF0_502 PS_DDR_DQ30_502 MEM_ADD3 N2 F8 DDR3_D3
W3 A3 DQ3
PS_DDR_DQ29_502 MEM_ADD4 P8 H3 DDR3_D4
Y2 A4 DQ4
PS_DDR_DQ28_502 MEM_ADD5 P2 H8 DDR3_D5
F4 Y4 A5 DQ5
MEM_ADD14 PS_DDR_A14_502 PS_DDR_DQ27_502 MEM_ADD6 R8 G2 DDR3_D6
D4 W1 A6 DQ6
MEM_ADD13 PS_DDR_A13_502 PS_DDR_DQ26_502 MEM_ADD7 R2 H7 DDR3_D7
E4 Y3 A7 DQ7
MEM_ADD12 PS_DDR_A12_502 PS_DDR_DQ25_502 MEM_ADD8 T8
G4 V1 A8
MEM_ADD11 PS_DDR_A11_502 PS_DDR_DQ24_502 MEM_ADD9 R3
F5 U3 A9
MEM_ADD10 PS_DDR_A10_502 PS_DDR_DQ23_502 MEM_ADD10 L7 D7 DDR3_D8
J4 U2 A10/AP DQ8
MEM_ADD9 PS_DDR_A9_502 PS_DDR_DQ22_502 MEM_ADD11 R7 C3 DDR3_D9
K1 U4 A11 DQ9
MEM_ADD8 PS_DDR_A8_502 PS_DDR_DQ21_502 MEM_ADD12 N7 C8 DDR3_D10
K4 T4 A12/BC_L DQ10
MEM_ADD7 PS_DDR_A7_502 PS_DDR_DQ20_502 MEM_ADD13 T3 C2 DDR3_D11
L4 R1 A13 DQ11
MEM_ADD6 PS_DDR_A6_502 PS_DDR_DQ19_502 MEM_ADD14 T7 A7 DDR3_D12
L1 R3 A14/NC DQ12
MEM_ADD5 PS_DDR_A5_502 PS_DDR_DQ18_502 M7 A2 DDR3_D13
M4 P3 A15/NC DQ13
MEM_ADD4 PS_DDR_A4_502 PS_DDR_DQ17_502 B8 DDR3_D14
K3 P1 DQ14
MEM_ADD3 PS_DDR_A3_502 PS_DDR_DQ16_502 MEM_BANK0 M2 A3 DDR3_D15
M3 J1 BA0 DQ15
MEM_ADD2 PS_DDR_A2_502 PS_DDR_DQ15_502 DDR3_D15 MEM_BANK1 N8
K2 H1 BA1 VCC1V5
MEM_ADD1 PS_DDR_A1_502 PS_DDR_DQ14_502 DDR3_D14 MEM_BANK2 M3
N2 H2 BA2
MEM_ADD0 PS_DDR_A0_502 PS_DDR_DQ13_502 DDR3_D13 B2
J3 VDD0
PS_DDR_DQ12_502 DDR3_D12 MEM_RAS# J3 D9
H3 RAS_L VDD1
C PS_DDR_DQ11_502 DDR3_D11 MEM_CAS# K3 G7
G3 CAS_L VDD2 C2 C3 C4 C5 C6 C7 C150
C
PS_DDR_DQ10_502 DDR3_D10 MEM_WE# L3 K2
J5 E3 WE_L VDD3
MEM_BANK2 PS_DDR_BA2_502 PS_DDR_DQ9_502 DDR3_D9 K8
R4 E2 VDD4 10uf 1uf 1uf 0.1uf 0.1uf 0.1uf 10nf
MEM_BANK1 PS_DDR_BA1_502 PS_DDR_DQ8_502 DDR3_D8 MEM_CLK0_P J7 N1
L5 E1 CK VDD5
MEM_BANK0 PS_DDR_BA0_502 PS_DDR_DQ7_502 DDR3_D7 MEM_CLK0_N K7 N9
C1 CK_L VDD6
PS_DDR_DQ6_502 DDR3_D6 R1
D1 VDD7
PS_DDR_DQ5_502 DDR3_D5 MEM_DQS0_P F3 R9
D3 LDQS VDD8 VCC1V5
PS_DDR_DQ4_502 DDR3_D4 MEM_DQS0_N G3
B4 A4 LDQS_L
PS_DDR_DRST_B_502 PS_DDR_DQ3_502 DDR3_D3 MEM_DQS1_P C7
MEM_RESET# P4 A2 UDQS
PS_DDR_RAS_B_502 PS_DDR_DQ2_502 DDR3_D2 MEM_DQS1_N B7 A1
MEM_RAS# P5 B3 UDQS_L VDDQ0
PS_DDR_CAS_B_502 PS_DDR_DQ1_502 DDR3_D1 A8
MEM_CAS# N1 C3 VDDQ1
PS_DDR_CS_B_502 PS_DDR_DQ0_502 DDR3_D0 MEM_DM0 E7 C1
MEM_MA0_CS_L0 M5 LDM VDDQ2 C12 C13 C14 C15 C16 C17
PS_DDR_WE_B_502 MEM_DM1 D3 C9
MEM_WE# UDM VDDQ3
D2
Y1 VDDQ4 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 10nf
PS_DDR_DM3_502 MEM_MA0_CKE0 K9 E9
T1 CKE0 VDDQ5
PS_DDR_DM2_502 J9 F1
N3 F1 CKE1/NC VDDQ6
PS_DDR_CKE_502 PS_DDR_DM1_502 MEM_DM1 H2
MEM_MA0_CKE0 L2 A1 VDDQ7
PS_DDR_CKP_502 PS_DDR_DM0_502 MEM_DM0 MEM_MA0_CS_L0 L2 H9
MEM_CLK0_P M2 CS0_L VDDQ8
PS_DDR_CKN_502 L1
MEM_CLK0_N R10 80.6r CS1_L/NC
W5 MEM_MA0_ODT0 K1 B1
PS_DDR_DQS_P3_502 ODT0 VSSQ0
N5 W4 J1 B9
MEM_MA0_ODT0 PS_DDR_ODT_502 PS_DDR_DQS_N3_502 MEM_RESET# ODT1/NC VSSQ1
R2 MEM_RESET# T2 D1
PS_DDR_DQS_P2_502 RESET_L VSSQ2
T2 D8
PS_DDR_DQS_N2_502 VSSQ3
B G2 MEM_DQS1_P DDR3_VREF M8 E2 B
PS_DDR_DQS_P1_502 VREFCA VSSQ4

R12
R13 80.6r H5 F2 MEM_DQS1_N H1 E8
PS_DDR_VRP_502 PS_DDR_DQS_N1_502 VREFDQ VSSQ5
VCC1V5 R14 80.6r G5 C2 MEM_DQS0_P F9
PS_DDR_VRN_502 PS_DDR_DQS_P0_502 VSSQ6
B2 MEM_DQS0_N L8 G1
PS_DDR_DQS_N0_502 ZQ0 VSSQ7

5.1k
L9 G9
ZQ1/NC VSSQ8

R15
A9 J8
VSS0 VSS5
XC7Z020_1CLG400C B3 M1
VSS1 VSS6

240R
E1 M9
VSS2 VSS7
G8 P1
VSS3 VSS8
J2 P9
VCC1V5 VCC1V5 VSS4 VSS9
T1
VSS10
T9
DDR3_VREF2 VSS11
R16

R144 1k

C151 C159 DDR3_VREF C155 MT41K128M16JT-125

HELLOFPGA.COM
1k

0.1uf 10nf 0.1uf

R18

R145 1k

C21 C22 C156 C160

1k

0.1uf 10nf 0.1uf 0.1uf

A A

Title
www.hellofpga.com

Size Document Number Rev

B <Doc> <RevCode>

Date: Thursday, October 13, 2022 Sheet 1 of 1

5 4 3 2 1
 5 4 3 2 1

U11

SPI_DQ0/MIO2 R5 20k
SD_D2 1 VCC3V3 SPI_DQ1/MIO3 R6 20k
D SD_D3 DAT2 J15 SPI_DQ2/MIO4 R146 20k R447 1k D
2 VCC3V3
SD_CMD CD/DAT3 SPI_DQ3/MIO5 R147 20k R148 1k
3 1 2 VCC3V3
CMD GND_1 VREF FPGA_TMS C309 SPI_SCK/MIO6 R7 20k
VCC3V3 4 3 4
SD_CLK VDD NC_2 TMS FPGA_TCK VCFG0/MIO7 R8 20k
5 5 6
CLK NC_3 TCK FPGA_TDO 10uf/10V VCFG1/MIO8 R9 20k
6 7 8

4
SD_D0 VSS NC_4 TDO FPGA_TDI
7 9 10
SD_D1 DAT0 NC_1 TDI J30
8

4
DAT1

BOOT
VCC3V3 10k R444 9 JTAG SWAP
DEL_SW

P1
P2
P3
P4
SD_CD 22R R445 S2 S1

JTAG
TF

1
P1
P2
P3
P4
TF

1
HELLOFPGA.COM
BOOT S1 S2
C C

VCC3V3 VCC3V3 VCC3V3

JTAG
QSPI
R151 5.1k

C48
C18
U10 0.1uf VCC3V3
0.1uf 1 8
J2 2 A0 VCC 7
QSPI_CS A1 WP EEPROM_SCL GPIO_T20_L15PR33

SD
1 8 3 6 10K
SPI_DQ1/MIO3 CS VCC SPI_DQ3/MIO5 4 A2 SCL 5 EEPROM_SDA GPIO_T19 R34 10K
2 7
SPI_DQ2/MIO4 DO(IO1) HOLD(IO3) SPI_SCK/MIO6 VSS SDA
3 6
WP(IO2) CLK SPI_DQ0/MIO2 24c02
4 5
GND DI(IO0)
N25Q128A13ESE40

ON OFF
QSPI FLASH EEPROM
B B
VCC3V3
X2
4 3 CLK_50M
C310 VCC OUT 22R R132
1 2
GPIO_D18_L3N NC GND
0.1uf
VCC3V3 50MHZ
GPIO_F20_L15N

R50 R51 VCC3V3

X1
5.1k R450

5.1k R451

330R 330R 4 3 PS_CLK_33.333M

C1 VCC OUT 22R R1
GREEN GREEN 1 2
LED1 LED2 0.1uf NC GND
33.333M

KEY2 SW

CLOCK
GPIO_G15_L19N
KEY1 SW
GPIO_F16_L6P
A A

KEY LED Title

www.hellofpga.com

Size Document Number Rev

B <Doc> <RevCode>

Date: Thursday, October 13, 2022 Sheet 1 of 1

5 4 3 2 1
 5 4 3 2 1

D VCC3V3 D

C29 C34
U1H
22uf 0.1uf
VCC1V5
U1I K6
VCCO_0
G10 U6 D2 VCC3V3
GND_1 GND_31 VCCO_DDR_502_1
L18 K13 A3

C30

C35

C31

C36

C32

C37

C41

C33
GND_2 GND_32 VCCO_DDR_502_2
F7 Y15 H4 U11 C38
GND_3 GND_33 VCCO_DDR_502_3 VCCO_13_1
L8 C9 V4 W7 C39 C40
GND_4 GND_34 VCCO_DDR_502_4 VCCO_13_2
F3 W12 P2 T8 100uf

100uf

1uf

1uf
10uf

10nf
0.1uf

0.1uf

0.1uf
GND_5 GND_35 VCCO_DDR_502_5 VCCO_13_3
Y5 K7 R5 Y10 10uf 0.1uf
GND_6 GND_36 VCCO_DDR_502_6 VCCO_13_4
E20 V19 L3
GND_7 GND_37 VCCO_DDR_502_7
V9 K5 E5 VCC3V3
GND_8 GND_38 VCCO_DDR_502_8
E10 U16 VCC1V0 G1 R15
GND_9 GND_39 VCCO_DDR_502_9 VCCO_34_1
T7 J12 U1 N19

C195
C45

C46

C49

C50
GND_10 GND_40 VCCO_DDR_502_10 VCCO_34_2
D17 T13 VCC3V3 T18

C42

C43

C44
GND_11 GND_41 VCCO_34_3
R8 J8 Y20
GND_12 GND_42 VCCO_34_4
K11 T3 H10 W17

C52

C53

100uf
10uf

10uf
0.1uf

0.1uf
GND_13 GND_43 VCCBRAM_1 VCCO_34_5
P9 J2 G11 V14

10uf

10uf

0.1uf
GND_14 GND_44 VCCBRAM_2 VCCO_34_6
C14 R12
GND_15 GND_45
N10 H19 VCC3V3

10uf

0.1uf
C GND_16 GND_46 C
C4 P17 B6 F18
GND_17 GND_47 VCCO_MIO0_500_1 VCCO_35_1
M11 H13 D7 J17

C194
C54

C55

C58

C59
GND_18 GND_48 VCCO_MIO0_500_2 VCCO_35_2
B11 P11 K20
GND_19 GND_49 VCCO_35_3
L12 H11 M16

C60

C61

C62
GND_20 GND_50 VCC3V3 VCCO_35_4
B1 P7 E15 C19

100uf
10uf

10uf
0.1uf

0.1uf
GND_21 GND_51 VCCO_MIO1_501_1 VCCO_35_5
W2 H9 B16 H14
GND_22 GND_52 VCCO_MIO1_501_2 VCCO_35_6
A18 N12 D12

10uf

10uf

0.1uf
GND_23 GND_53 VCCO_MIO1_501_3
R20 H7 A13
GND_24 GND_54 VCCO_MIO1_501_4
A8 N8 VCC1V8
GND_25 GND_55
N14 G16 VCC1V0 R9
GND_26 GND_56 VCCAUX_1
N4 M13 P8 N11

C63

C67

C68

C69
C196

C192
GND_27 GND_57 VCCPINT_1 VCCAUX_2
M1 G12 R7 L11
GND_28 GND_58 VCCPINT_2 VCCAUX_3
K15 M7 J7 N9
GND_29 GND_59 VCCPINT_3 VCCAUX_4
P13 L7 P10

100uf

10uf

22uf
0.1uf

0.1uf

0.1uf
GND_30 VCCPINT_4 VCCAUX_5
N7 J11
VCCPINT_5 VCCAUX_6
XC7Z020_1CLG400C G7
VCCPINT_6
VCC1V0
VCC1V8 L13
VCCINT_1
N13

C74

C75

C76

C79

C80
C193

C197
F8 VCCPAUX_1 VCCINT_2
K8 M12
VCCPAUX_2 VCCINT_3
M8 R13
VCCPAUX_3 VCCINT_4

HELLOFPGA.COM
H8 G13

100uf
22uf

10uf

10uf
0.1uf

0.1uf

0.1uf
VCCPAUX_4 VCCINT_5
G9 J13
VCCPAUX_5 VCCINT_6
B VCC1V8 K12 B
VCCINT_7
H12
VCCINT_8
G8 P12 VCC1V8
VCCPLL VCCINT_9

C81
F11

C83
VCCBATT_0

0.1uf

0.1uf
XC7Z020_1CLG400C

A A

Title
www.hellofpga.com

Size Document Number Rev

B <Doc> <RevCode>

Date: Thursday, October 13, 2022 Sheet 1 of 1

5 4 3 2 1
 5 4 3 2 1

D D

U13
5V_DC 5V_DC
U12 VCC3V3
5V_DC 5V_DC
VCC3V3 VCC3V3 40 39
VCC3V3 40 39
C 40 39 38 37
40 39 38 37 C
38 37 36 35
38 37 GPIO_E17_L3P 36 35 GPIO_H15_L19P
36 35 34 33
GPIO_V15_L10P 36 35 GPIO_U14_L11P GPIO_F17_L6N 34 33 GPIO_G17_L16P
34 33 32 31
GPIO_T15_L5N 34 33 GPIO_U15_L11N GPIO_J16_L24N 32 31 GPIO_H16_L13P
32 31 30 29
GPIO_U17_L9N 32 31 GPIO_T16_L9P GPIO_H17_L13N 30 29 GPIO_H18_L14N
30 29 28 27
GPIO_T17_L20P 30 29 GPIO_V18_L21N GPIO_K17_L12P 28 27 GPIO_J18_L14P
28 27 26 25
GPIO_R17_L19N 28 27 GPIO_R16_L19P GPIO_K16_L24P 26 25 GPIO_G19_L18P
26 25 24 23
GPIO_P18_L23N 26 25 GPIO_P16_L24N GPIO_G20_L18N 24 23 GPIO_G18_L16N
24 23 22 21
GPIO_N16_L21N 24 23 GPIO_N17_L23P GPIO_B19_L2P 22 21 GPIO_D19_L4P
22 21 20 19
GPIO_T10_L1N 22 21 GPIO_M17_L8P GPIO_C20_L1P 20 19 GPIO_E18_L5P
20 19 18 17
GPIO_V12_L4P 20 19 GPIO_U12_L2N GPIO_E19_L5N 18 17 GPIO_D20_L4N
18 17 16 15
GPIO_V13_L3N 18 17 GPIO_W13_L4N GPIO_B20_L1N 16 15 GPIO_A20_L2N
16 15 14 13
GPIO_W14_L8P 16 15 GPIO_Y14_L8N GPIO_H20_L17N 14 13 GPIO_F19_L15P
14 13 12 11
GPIO_L16_L11P 14 13 GPIO_W15_L10N GPIO_J19_L10N 12 11 GPIO_J20_L17P
12 11 10 9
GPIO_Y16_L7P 12 11 GPIO_M18_L8N GPIO_K19_L10P 10 9 GPIO_N18_L13P
10 9 8 7
GPIO_Y17_L7N 10 9 GPIO_V16_L18P GPIO_N20_L14P 8 7 GPIO_L17_L11N
8 7 6 5
GPIO_Y18_L17P 8 7 GPIO_W16_L18N GPIO_P19_L13N 6 5 GPIO_P20_L14N
6 5 4 3
GPIO_Y19_L17N 6 5 GPIO_V17_L21P GPIO_R19 4 3 GPIO_R18_L20N
4 3 2 1
GPIO_U20_L15N 4 3 GPIO_U19_L12N 2 1
2 1
2 1

HEADER 20x2
HEADER 20x2
B B

HELLOFPGA.COM

A A

Title
www.hellofpga.com

Size Document Number Rev

B <Doc> <RevCode>

Date: Thursday, October 13, 2022 Sheet 1 of 1

5 4 3 2 1