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QM HW Design V01
QM HW Design V01
VCCINT_5 K10
3V3 VCCINT_6 K8
VCCINT_7 1V2
B13 C35 Spartan-6_XC6SLX16_FTG256
U3 C55 + C64 VCCO_0_0 B4
4 3 R12 C40 VCCO_0_1 B9 4.7uF
VIN SW 4.7uF 150K 22pF 47uF VCCO_0_2 D10 10V
C43 VCCO_0_3 D7 C36
VCCO_0_4 3V3
D15 100NF
4.7uF 1 5 VCCO_1_0 G13 C37
EN GND FB VCCO_1_1 J15 100NF
NCP1529 VCCO_1_2 K13
2 R14 VCCO_1_3 N15 1V5
100K VCCO_1_4 R13
VCCO_1_5 VCCO_1
N10
VCCO_2_0 N7
VCCO_2_1 R4 C53
1V2 1V2 1V2 VCCO_2_2 R8
VCCO_2_3 3V3
L3 4.7uH D2 4.7uF
M
VCCO_3_0 G4 10V
3V3 VCCO_3_1 J2 C28
+ C65 VCCO_3_2 K4 100NF
U5 C56 VCCO_3_3 N2 C29
VCCO_3_4 1V5
4 3 R21 C46 47uF 100NF
VIN SW 4.7uF 100K 22pF
C47
Spartan-6_XC6SLX16_FTG256
4.7uF 1 5
EN GND FB
NCP1529
2 R26
100K
3V3
3V3 R9 4.7K
3V3 3V3 3V3 3V3 3V3
U2E J2
C4 R11 4.7K
IO_L1P_HSWAPEN_0 1 1 OE
2 VDD 4
R221 R222 C14 TCK TCK C42
4.7K 4.7K TCK C12 TDI 3 TDO 50 MHz 100NF 3V3
TDI A15 4 2 VSS SYS_CLK
R131 R218 R217
TMS
TMS
5
TDI OUT 3
F1 1K 1K 1K E14 TDO TMS
A M
PROG_B BANK2_IO_T8 BANK2_IO_R7 TDO 6 A
P14 JTAG Y1 R13
F2 SUSPEND 1K
2 2 2
L11
M
SW1 SW2 SW3 CMPCS_B_2 SG-8002JC-50.0000M-PCB 3V3
P13 FPGA_DONE FPGA_DONE
DONE_2 3V3
1
R11 FPGA_CCLK U6
1 2 BANK2_IO_T9 IO_L1P_CCLK_2 P10 FPGA_MISO R15FPGA_CSO_B 1 8
IO_L3P_D0_DIN_MISO_MISO1_2 3V3 4.7K nCE VDD
C44 100NF R16 D2
D1 T10 FPGA_MOSI 1K Title
1 1 1 IO_L3N_MOSI_CSI_B_MISO0_2 T3 FPGA_CSO_B FPGA_MISO R17 0R 2 7 R18 4.7K Red
IO_L65N_CSO_B_2 SO HOLD 3V3
BANK2_IO_R9
1
D3
2
IO_L65P_INIT_B_2
R3 R19 4.7K 3V3 3V3 4.7K R20 3
WP SCK
6 FPGA_CCLK QM_XC6SLX16_DDR3_BOARD
2
Date:
Saturday, July 01, 2017 Sheet
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