5 4 3 2 1

Starload GPU borad Schematics

Skylake-U
D D

2016/02/18
REV : A00
C C

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cover Page
Size Document Number Rev

IO board A3

Date:
Starload-SKL-U
Thursday, February 18, 2016Sheet 1 of 13
A00
5 4 3 2 1
 5 4 3 2 1

Main Func = dGPU

3V3_AON_S0
PDP-06877-006

1
R7312 From GPIO21
dGPU Reset GC6_20 10KR2J-3-GP D7301
R7308 1 GPU_PEX_RST_HOLD [5]
3V3_AON_S0

2
GPU_PEX_RST# GPU_PEX_RST_D# 1D05V_VGA_S0
U7301 1 2 3 GC6_20 1.05V +/- 30mV
[13] DGPU_HOLD_RST# 1 5
A VCC SYS_PEX_RST_MON#
U74LVC1G08G-AL5-R-GP-U 0R2J-2-GP
2
3.3A
[13] PLT_RST# 2
B OPS
GC6_20
3 4 SYS_PEX_RST_MON# [5] BAT54A-1-GP
GND Y
75.00054.X7D
To GPIO8

1
D 73.01G08.EHG 2nd = 75.00054.R7D D

1
2ND = 73.7SZ08.EAH C7312 OPS C7310 OPS C7323 OPS C7326 OPS

SC1U10V2KX-1GP

SC4D7U6D3V3KX-GP

SC10U6D3V3MX-GP

SC22U6D3V3MX-1-GP
3RD = 73.01G08.L04 R7306 3rd = 75.BAT54.07D

2
R7304 1 DY 2 0R2J-2-GP OPS 100KR2F-L1-GP
4th = 75.00054.Y7D

2
3V3_AON_S0 GPU_PEX_RST# [5]

GPU1A 1 OF 14
Place close VDD ball Place close Chip
1/14 PCI_EXPRESS

2
Q7301
R7303 R7313 AB6
PEX_WAKE#
G OPS 10KR2J-3-GP
NON_GC6 PEX_IOVDD_1
AA22
D SYS_PEX_RST_MON# 1 2 GPU_PEX_RST# AC7 AB23
[13] CLKREQ_PEG#0

1
0R2J-2-GP PEX_RST# PEX_IOVDD_2
AC24
GPU_CLKREQ# PEX_IOVDD_3
OPS S AC6
PEX_CLKREQ# PEX_IOVDD_4
AD25
AE26
PEX_IOVDD_5
[13] CLK_PCIE_VGA AE8 AE27
2N7002K-2-GP PEX_REFCLK PEX_IOVDD_6
[13] CLK_PCIE_VGA# AD8
84.2N702.J31 PEX_REFCLK#
C7301 1OPS 2SCD22U10V2KX-1GP dGPU_TXP_CPU_RXP0 AC9
[13] CPU_RXP_C_dGPU_TXP0 PEX_TX0
[13] CPU_RXN_C_dGPU_TXN0 C7302 1OPS 2SCD22U10V2KX-1GP dGPU_TXN_CPU_RXN0 AB9
PEX_TX0#
1 DY 2 [13] dGPU_RXP_C_CPU_TXP0 AG6
PEX_RX0
[13] dGPU_RXN_C_CPU_TXN0 AG7 AA10
R7305 PEX_RX0# PEX_IOVDDQ_1
AA12
0R2J-2-GP C7303 1OPS dGPU_TXP_CPU_RXP1 PEX_IOVDDQ_2
[13] CPU_RXP_C_dGPU_TXP1 2SCD22U10V2KX-1GP AB10 AA13
C7304 1OPS dGPU_TXN_CPU_RXN1 PEX_TX1 PEX_IOVDDQ_3
[13] CPU_RXN_C_dGPU_TXN1 2SCD22U10V2KX-1GP AC10 AA16
PEX_TX1# PEX_IOVDDQ_4
AA18
PEX_IOVDDQ_5
[13] dGPU_RXP_C_CPU_TXP1 AF7 AA19
PEX_RX1 PEX_IOVDDQ_6
[13] dGPU_RXN_C_CPU_TXN1 AE7 AA20
PEX_RX1# PEX_IOVDDQ_7
AA21
C7305 1OPS dGPU_TXP_CPU_RXP2 PEX_IOVDDQ_8
[13] CPU_RXP_C_dGPU_TXP2 2SCD22U10V2KX-1GP AD11 AB22
C7306 1OPS dGPU_TXN_CPU_RXN2 PEX_TX2 PEX_IOVDDQ_9
[13] CPU_RXN_C_dGPU_TXN2 2SCD22U10V2KX-1GP AC11 AC23
PEX_TX2# PEX_IOVDDQ_10
C AD24 C
PEX_IOVDDQ_11
[13] dGPU_RXP_C_CPU_TXP2 AE9 AE25
PEX_RX2 PEX_IOVDDQ_12
[13] dGPU_RXN_C_CPU_TXN2 AF9 AF26
PEX_RX2# PEX_IOVDDQ_13
AF27
C7307 1OPS dGPU_TXP_CPU_RXP3 PEX_IOVDDQ_14
[13] CPU_RXP_C_dGPU_TXP3 2SCD22U10V2KX-1GP AC12
C7308 1OPS dGPU_TXN_CPU_RXN3 PEX_TX3
[13] CPU_RXN_C_dGPU_TXN3 2SCD22U10V2KX-1GP AB12
PEX_TX3#

[13] dGPU_RXP_C_CPU_TXP3 AG9

PEX_RX3
[13] dGPU_RXN_C_CPU_TXN3 AG10
PEX_RX3#
AB13
PEX_TX4
AC13
PEX_TX4#
AF10
PEX_RX4
AE10
PEX_RX4# 3.3V +/- 5%
NC FOR GF119 3V3_AON_S0
AD14
AC14
PEX_TX5
AA8
210mA
PEX_TX5# PEX_PLL_HVDD_1
AA9
PEX_PLL_HVDD_2
AE12
PEX_RX5
AF12
PEX_RX5#
AB8
PEX_SVDD_3V3

NC FOR GM108
AC15
PEX_TX6
AB15 Place close Chip

1
PEX_TX6# C7316 C7315 OPS
C7324 OPS
OPS

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
AG12

SCD1U25V2KX-GP
PEX_RX6
AG13

2
PEX_RX6#
AB16
PEX_TX7
AC16
PEX_TX7#
AF13
PEX_RX7
AE13
PEX_RX7#
AD17
PEX_TX8
AC17
PEX_TX8#
AE15
PEX_RX8
AF15
PEX_RX8#
AC18 F2 VGACORE_VDD_SENSE_1 [11]
B PEX_TX9 VDD_SENSE B
AB18
PEX_TX9# POWER IC
AG15 F1 VGACORE_GND_SENSE_1 [11]
PEX_RX9 GND_SENSE
AG16
PEX_RX9#
AB19
PEX_TX10
AC19
PEX_TX10#
AF16
PEX_RX10
AE16
PEX_RX10#
AD20
PEX_TX11
AC20
PEX_TX11#
AE18
PEX_RX11
AF18
PEX_RX11#
AC21
NC FOR GF117/GK208/GM108

PEX_TX12 R7307
AB21
PEX_TX12# 200R2F-L-GP
AG18 AF22 PEXTSTCLK_OUT 1 DY 2
PEX_RX12 PEX_TSTCLK_OUT
AG19 AE22 PEXTSTCLK_OUT# L7301
PEX_RX12# PEX_TSTCLK_OUT#
AD23 1D05V_VGA_S0
AE23
PEX_TX13
Place close VDD ball Place close Chip MHC1608S121PBP-GP 1.05V +/- 30mV
PEX_TX13#
AF19 AA14 VCC1R05VIDEO_PEX_PLLVDD 1
OPS
2
150mA
PEX_RX13 PEX_PLLVDD_1
AE19
PEX_RX13# PEX_PLLVDD_2
AA15 68.00335.151
AF24 C7318

1
PEX_TX14 C7317 C7319
AE24
PEX_TX14# OPS OPS OPS

SC4D7U6D3V3KX-GP

SC1U10V2KX-1GP
SCD1U16V2KX-3GP
AE21 R7302

2
PEX_RX14
AF21
PEX_RX14#
AD9 TESTMODE 1 OPS 2
TESTMODE 10KR2F-2-GP
AG24
PEX_TX15
AG25
PEX_TX15#
AG21
PEX_RX15
AG22
PEX_RX15#
A R7301 A

AF25 PEX_TERMP 1 OPS 2

PEX_TERMP 2K49R2F-GP

N16S-GM-S-A2-GP
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU(1/5)PEG
Size Document Number Rev
A2
Starload SKL-U A00
Date: Thursday, February 18, 2016 Sheet 2 of 13

5 4 3 2 1
 5 4 3 2 1

Main Func = dGPU

GPU1H 5 OF 14
5/14 IFPC
GPU1G 4 OF 14 IFPC
4/14 IFPAB
T6 GF119/GK208 GPU1J 7 OF 14
IFPC_RSET
7/14 IFPEF
AC4 DVI/HDMI DP
IFPA_TXC#
AC3 GF119/GK208
IFPA_TXC
D M7 I2CW_SDA IFPC_AUX_I2CW_SDA# N5 D
IFPC_PLLVDD_1 DVI-DL DVI-SL/HDMI DP
AA6 N7 I2CW_SCL N4
IFPAB_RSET IFPC_PLLVDD_2 IFPC_AUX_I2CW_SCL
Y3 I2CY_SDA I2CY_SDA J3
IFPA_TXD0# IFPE_AUX_I2CY_SDA#
Y4 I2CY_SCL I2CY_SCL J2
IFPA_TXD0 IFPE_AUX_I2CY_SCL
TXC N3 J7
IFPC_L3# IFPEF_PLLVDD_1
V7 TXC N2
IFPAB_PLLVDD_1 IFPC_L3
AA2 TXC TXC J1
IFPA_TXD1# IFPE_L3#
W7 AA3 TXD0 R3 TXC TXC K1
IFPAB_PLLVDD_2 IFPA_TXD1 IFPC_L2# IFPE_L3
TXD0 R2 K7
IFPC_L2 IFPEF_PLLVDD_2
K3
TXD0 TXD0 IFPE_L2#
AA1 TXD1 R1 K2
IFPA_TXD2# IFPC_L1# TXD0 TXD0 IFPE_L2
AB1 TXD1 T1
IFPA_TXD2 IFPC_L1
K6 TXD1 TXD1 M3
IFPEF_RSET IFPE_L1#

NC FOR GF117/GM108
TXD2 T3 TXD1 TXD1 M2
IFPC_L0# IFPE_L1
AA5 TXD2 T2
IFPA_TXD3# IFPC_L0

NC FOR GF117/GM108
AA4 M1

NC FOR GF117/GM108
IFPA_TXD3 TXD2 TXD2 IFPE_L0#
N1
GF117 TXD2 TXD2 IFPE_L0
AB4 P6 NC C3 IFPE
IFPB_TXC# IFPC_IOVDD GPIO15 NC FOR GK208
AB5

NC FOR GF117/GM108
IFPB_TXC

NC FOR GF117/GM108
N16S-GM-S-A2-GP
W6 AB2 HPD_E HPD_E C2
IFPA_IOVDD IFPB_TXD4# GPIO18
AB3
IFPB_TXD4
Y6
IFPB_IOVDD NC FOR GF117

AD2
IFPB_TXD5#
AD3 H6
IFPB_TXD5 GPU1I 6 OF 14 IFPE_IOVDD
GF119/GK208
6/14 IFPD J6
IFPF_IOVDD DVI-DL DVI-SL/HDMI DP
AD1
IFPB_TXD6#

NC FOR GF117/GK208/GM108
AE1 I2CZ_SDA H4
IFPB_TXD6 GF119/GK208 IFPF_AUX_I2CZ_SDA#
U6 I2CZ_SCL H3
IFPD_RSET IFPF_AUX_I2CZ_SCL
DVI/HDMI DP
AD5
IFPB_TXD7#
AD4 TXC J5
IFPB_TXD7 IFPF_L3#
T7 I2CX_SDA IFPD_AUX_I2CX_SDA# P4 TXC J4
IFPD_PLLVDD_2 IFPF_L3
I2CX_SCL P3
IFPD_AUX_I2CX_SCL
R7 TXD3 TXD0 K5
IFPD_PLLVDD_1 IFPF_L2#
GF117 TXD3 TXD0 K4
IFPF_L2
TXC R5
IFPD_L3#
C NC B3 TXC R4 TXD4 TXD1 L4 C
GPIO14 IFPD_L3 IFPF IFPF_L1#
IFPAB T5
TXD4 TXD1
IFPF_L1
L3
TXD0

NC FOR GF117/GM108
N16S-GM-S-A2-GP IFPD_L2#
TXD0 T4 TXD5 TXD2 M5
IFPD_L2 IFPF_L0#

NC FOR GF117/GM108
TXD5 TXD2 M4
IFPF_L0
TXD1 U4
IFPD IFPD_L1#

NC FOR GF117/GM108
TXD1 U3
IFPD_L1 NC FOR GK208

TXD2 V4
IFPD_L0#
TXD2 V3 HPD_F F7
IFPD_L0 GPIO19
GPU1K 3 OF 14
GF117 NC FOR GF117
3/14 DACA
R6 NC D4
GF117/GM108 GF117 GM108/GK208 IFPD_IOVDD GPIO17
RN301
W5 NC NC B7 GPU_I2CA_SCL 1 4 N16S-GM-S-A2-GP
DACA_VDD I2CA_SCL GPU_I2CA_SDA
NC I2CA_SDA
A7 2 DY 3
AE2 TSEN_VREF
DACA_VREF
SRN1K8J-GP
AF2 NC NC AE3
DACA_RSET DACA_HSYNC N16S-GM-S-A2-GP
NC AE4
DACA_VSYNC

NC AG3
DACA_RED

NC AF4
DACA_GREEN

NC AF3
DACA_BLUE
GM108
GK208
GF117

N16S-GM-S-A2-GP

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU(2/5)DIGITALOUT
Size Document Number Rev
A2
Starload SKL-U A00
Date: Thursday, January 07, 2016 Sheet 3 of 13
5 4 3 2 1
 5 4 3 2 1

Main Func = dGPU

1 DY 2 GC6_FB_EN [5,12,13]
R7519
GPU1B 2 OF 14 0R2J-2-GP
[7] FBA_D[0..31]
2/14 FBA
FBA_D0 E18 F3 FB_CLAM 1 OPS 2
FBA_D1 F18
FBA_D0 NC FB_CLAMP 1.35V +/- 3%
FBA_D1 12 OF 14 1D35V_VGA_S0
FBA_D2
FBA_D3
E16
F17
FBA_D2 GF119
R7518
10KR2J-3-GP
GPU1D
4.88A
FBA_D4 FBA_D3
12/14 FBVDDQ Under GPU
D20
FBA_D5 FBA_D4
D21 B26 Near GPU
FBA_D6 FBA_D5 FBVDDQ_01
F20 C25
FBA_D7 FBA_D6 FBVDDQ_02
E21 E23
FBA_D8 FBA_D7 FBVDDQ_03
E15 E26
FBA_D9 FBA_D8 FBVDDQ_04 C7501 C7502 C7525 C7507 C7513 C7514 C7517 C7520
D15 F14
FBA_D9 FBVDDQ_05

1
SC10U10V5KX-2GP
FBA_D10 F15 F21 OPS OPS OPS OPS OPS OPS OPS OPS

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
FBA_D10 FBVDDQ_06

SC22U6D3V3MX-1-GP
FBA_D11 F13 G13

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SC1U6D3V3KX-2GP

SC1U6D3V3KX-2GP
FBA_D12 FBA_D11 FBVDDQ_07
C13 G14

2
FBA_D13 FBA_D12 FBVDDQ_08
B13 G15
D FBA_D14 FBA_D13 FBVDDQ_09 D
E13 G16
FBA_D15 FBA_D14 FBVDDQ_10
D13 G18
FBA_D16 FBA_D15 FBVDDQ_11
B15 G19
FBA_D17 FBA_D16 FBVDDQ_12
C16 G20
FBA_D18 FBA_D17 FBVDDQ_13
A13 G21
FBA_D19 FBA_D18 FBVDDQ_14
A15 L22
FBA_D20 FBA_D19 FBVDDQ_19
B18 L24
FBA_D21 FBA_D20 FBVDDQ_20
A18 L26
FBA_D22 FBA_D21 FBVDDQ_21
A19 M21
FBA_D23 FBA_D22 FBVDDQ_22
C19 N21
FBA_D24 FBA_D23 FBVDDQ_23
B24 R21
FBA_D25 FBA_D24 FBVDDQ_24
C23 T21
FBA_D26 FBA_D25 FBVDDQ_25
A25 V21
FBA_D27 FBA_D26 FBVDDQ_26
A24 W21
FBA_D28 FBA_D27 FBVDDQ_27
A21
FBA_D29 FBA_D28
B21
FBA_D30 FBA_D29 GF117
C20
FBA_D31 FBA_D30 GF119
[8] FBA_D[32..63] C21
FBA_D32 FBA_D31 GK208
R22
FBA_D33 FBA_D32 FBA_CMD0
R24 C27 FBA_CMD0 [7] FBVDDQ H24
FBA_D34 FBA_D33 FBA_CMD0 FBA_CMD1 FBVDDQ_15
T22 C26 FBA_CMD1 [7] FBVDDQ H26
FBA_D35 FBA_D34 FBA_CMD1 FBA_CMD2 FBVDDQ_16
R23 E24 FBA_CMD2 [7] FBVDDQ J21
FBA_D36 FBA_D35 FBA_CMD2 FBA_CMD3 FBVDDQ_17
N25 F24 FBA_CMD3 [7] FBVDDQ K21
FBA_D37 FBA_D36 FBA_CMD3 FBA_CMD4 FBVDDQ_18
N26 D27 FBA_CMD4 [7]
FBA_D38 FBA_D37 FBA_CMD4 FBA_CMD5
N23 D26 FBA_CMD5 [7]
FBA_D39 FBA_D38 FBA_CMD5 FBA_CMD6
N24 F25 FBA_CMD6 [7]
FBA_D40 FBA_D39 FBA_CMD6 FBA_CMD7
V23 F26 FBA_CMD7 [7]
FBA_D41 FBA_D40 FBA_CMD7 FBA_CMD8
V22 F23 FBA_CMD8 [7]
FBA_D42 FBA_D41 FBA_CMD8 FBA_CMD9
T23 G22 FBA_CMD9 [7]
FBA_D43 FBA_D42 FBA_CMD9 FBA_CMD10
U22 G23 FBA_CMD10 [7]
FBA_D44 FBA_D43 FBA_CMD10 FBA_CMD11
Y24 G24 FBA_CMD11 [7]
FBA_D45 FBA_D44 FBA_CMD11 FBA_CMD12
AA24 F27 FBA_CMD12 [7]
FBA_D46 FBA_D45 FBA_CMD12 FBA_CMD13
Y22 G25 FBA_CMD13 [7]
FBA_D47 FBA_D46 FBA_CMD13 FBA_CMD14
AA23 G27 FBA_CMD14 [7]
FBA_D48 FBA_D47 FBA_CMD14 FBA_CMD15
AD27 G26 FBA_CMD15 [7]
FBA_D49 FBA_D48 FBA_CMD15 FBA_CMD16
AB25 M24 FBA_CMD16 [8]
FBA_D50 FBA_D49 FBA_CMD16 FBA_CMD17
AD26 M23 FBA_CMD17 [8]
FBA_D51 FBA_D50 FBA_CMD17 FBA_CMD18
AC25 K24 FBA_CMD18 [8]
FBA_D52 FBA_D51 FBA_CMD18 FBA_CMD19
AA27 K23 FBA_CMD19 [8] 1D35V_VGA_S0
FBA_D53 FBA_D52 FBA_CMD19 FBA_CMD20
AA26 M27 FBA_CMD20 [8]
FBA_D54 FBA_D53 FBA_CMD20 FBA_CMD21
W26 M26 FBA_CMD21 [8] Under GPU
FBA_D55 FBA_D54 FBA_CMD21 FBA_CMD22
Y25 M25 FBA_CMD22 [8]
FBA_D56 FBA_D55 FBA_CMD22 FBA_CMD23 R7505
R26 K26 FBA_CMD23 [8]
FBA_D57 FBA_D56 FBA_CMD23 FBA_CMD24 FB_CAL_PD_VDDQ
FBA_D58
T25
FBA_D57 FBA_CMD24
K22
FBA_CMD25
FBA_CMD24 [8] 2 OPS 1 D22
FB_CAL_PD_VDDQ
N27 J23 FBA_CMD25 [8]
FBA_D59 FBA_D58 FBA_CMD25 FBA_CMD26 40D2R2F-GP
R27 J25 FBA_CMD26 [8]
FBA_D60 FBA_D59 FBA_CMD26 FBA_CMD27 FB_CAL_PU_GND
V26 J24 FBA_CMD27 [8] C24
FBA_D61 FBA_D60 FBA_CMD27 FBA_CMD28 FB_CAL_PU_GND
V27 K27 FBA_CMD28 [8]
FBA_D62 FBA_D61 FBA_CMD28 FBA_CMD29
W27 K25 FBA_CMD29 [8]
FBA_D63 FBA_D62 FBA_CMD29 FBA_CMD30 FB_CAL_TERM_GND
W25 J27 FBA_CMD30 [8] B25
FBA_D63 FBA_CMD30 FBA_CMD31 FB_CAL_TERM_GND
J26 FBA_CMD31 [8]
FBA_CMD31
FBA_DQM0 D19 N16S-GM-S-A2-GP
[7] FBA_DQM0 FBA_DQM1 FBA_DQM0
D14
[7] FBA_DQM1 FBA_DQM2 FBA_DQM1 1D35V_VGA_S0
C17 GF117/GF119
[7] FBA_DQM2 FBA_DQM2

1
FBA_DQM3
[7] FBA_DQM3 FBA_DQM4
C22
FBA_DQM3 GK208
R7507 R7506
GDDR5:60.4R
[8] FBA_DQM4
P24
FBA_DQM4 OPS 60D4R2F-GP
FBA_DQM5 W24 B19 OPS

42D2R2F-GP
C [8] FBA_DQM5 FBA_DQM5 NC NC#B19 C
FBA_DQM6
[8] FBA_DQM6 FBA_DQM7
AA25
FBA_DQM6 FBA_DEBUG0 R7501 1 2 60D4R2F-GP
GDDR3:51.1R
U25 FBA_DEBUG0 F22 DY

2
[8] FBA_DQM7 FBA_DQM7 FBA_DEBUG0 FBA_DEBUG1 R7503 1
FBA_DEBUG1 J22 DY 2 60D4R2F-GP
FBA_DEBUG1
FBA_EDC0 E19
[7] FBA_EDC0 FBA_EDC1 FBA_DQS_WP0
C15
[7] FBA_EDC1 FBA_EDC2 FBA_DQS_WP1 FBA_CLK0P
B16 D24 FBA_CLK0P [7]
[7] FBA_EDC2 FBA_EDC3 FBA_DQS_WP2 FBA_CLK0 FBA_CLK0N
B22 D25 FBA_CLK0N [7]
[7] FBA_EDC3 FBA_EDC4 FBA_DQS_WP3 FBA_CLK0# FBA_CLK1P
R25 N22 FBA_CLK1P [8]
[8] FBA_EDC4 FBA_EDC5 FBA_DQS_WP4 FBA_CLK1 FBA_CLK1N
W23 M22 FBA_CLK1N [8]
[8] FBA_EDC5 FBA_EDC6 FBA_DQS_WP5 FBA_CLK1#
AB26
[8] FBA_EDC6 FBA_EDC7 FBA_DQS_WP6
T26
[8] FBA_EDC7 FBA_DQS_WP7

F19 D18 FBA_WCK01 FBA_WCK01 [7]

FBA_DQS_RN0 FBA_WCK01 FBA_WCK01#
C14 C18 FBA_WCK01# [7]
FBA_DQS_RN1 FBA_WCK01# FBA_WCK23
A16
A22
FBA_DQS_RN2 FBA_WCK23
D17
D16 FBA_WCK23#
FBA_WCK23 [7] Modify by change to GDDR5
FBA_DQS_RN3 FBA_WCK23# FBA_WCK23# [7]
P25
FBA_DQS_RN4 FBA_WCK45
T24 FBA_WCK45
FBA_WCK45#
FBA_WCK45 [8] Stanley Lioa 2015-09-01
W22 U24 FBA_WCK45# [8]
FBA_DQS_RN5 FBA_WCK45# FBA_WCK67
AB27 V24 FBA_WCK67 [8]
FBA_DQS_RN6 FBA_WCK67 FBA_WCK67#
T27 V25 FBA_WCK67# [8]
FBA_DQS_RN7 FBA_WCK67#

GF119
1D05V_VGA_S0
Modify by change to GDDR5 F16
62mA
FB_PLLAVDD_1
NC Under GPU Near GPU
P22 L7501
FB_PLLAVDD_2

FB_PLLAVDD H22
35mA FBA_PLL_AVDD 1 2
FB_DLLAVDD
OPS
GF117 MHC1608S300QBP-GP
C7505 C7506 C7518
1

1
OPS OPS OPS 68.00335.051

SC22U6D3V3MX-1-GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

2nd = 68.00334.051
2

2
TP7503 FB_VREF
30ohm@100MHZ(ESR=0.01ohm)
1 D23
FB_VREF_PROBE
Sourcer suggest to change to
N16S-GM-S-A2-GP 68.00335.051 from 68.00084.H41.
<DUMMY>

1D35V_VGA_S0 Note:
Reference NV-DDR5 CRB and DOH70 by GDDR5
2

R7516 R7524
10KR2F-2-GP

10KR2F-2-GP

B
OPS OPS B
1

FBA_CMD14
FBA_CMD30

FBA_CMD29
FBA_CMD13
2

R7520 R7521
10KR2F-2-GP

10KR2F-2-GP

OPS OPS
1

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU(3/5)VRAMI/F
Size Document Number Rev
A1
Starload SKL-U A00
Date: Thursday, February 18, 2016 Sheet 4 of 13
5 4 3 2 1
 5 4 3 2 1

Main Func = dGPU

30ohm@100MHz
1D05V_VGA_S0 DCR=0.04 ohm
Max current = 3000mA
L7601 52mA
1 2
OPS

SCD1U16V2KX-3GP
C7605

1
MHC1608S300QBP-GP OPS C7606 GPU1M 9 OF 14
SC2D2U10V2KX-GP 3V3_AON_S0
68.00335.051 OPS 9/14 XTAL_PLL
2nd = 68.00334.051

2
GPU_PLL_VDD L6
L7602 SP_PLLVDD CORE_PLLVDD
111mA M6
SP_PLLVDD

1
GPU1N 8 OF 14 3V3_AON_S0 MCB1608S181FBP-GP R7617
8/14 MISC1 1 OPS2 N6 NC
10KR2J-3-GP
SMBC_THERM_NV VID_PLLVDD
I2CS_SCL
D9
SMBD_THERM_NV
DY
I2CS_SDA
D8 68.00909.261 GF119/GK208 GF117/GM108

2
D A9 I2CC_SCL 4 1 RN7604 180ohm@100MHz C7601 C7604 C7602 D
I2CC_SCL DY

1
B9 I2CC_SDA 3 2 SRN2K2J-1-GP C7603 OPS
I2CC_SDA DCR=0.3 ohm

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
OPS DY OPS VIDEO_CLK_XTAL_SS A10 C10 N12P_XTAL_OUTBUFF
3V3_AON_S0 Max current = 300mA XTAL_SSIN XTAL_OUTBUFF

2
GF117

SC10U6D3V3MX-GP
SC4D7U6D3V3KX-GP
1 P2800_VGA_DXN E12 PDP-06877-006
TP7603 THERMDN I2CB_SCL
NC C9 3 2 RN7605 C11 B10
I2CB_SCL XTAL_IN XTAL_OUT
1 P2800_VGA_DXP F12 NC C8 I2CB_SDA 4 DY 1 SRN2K2J-1-GP
THERMDP I2CB_SDA

1
TP7604 N16S-GM-S-A2-GP R7602

1
R7633 20PF 5% 50V +/-0.25PF 0402 10KR2J-3-GP
N12P_JTAG_TCK AE5 GC6_20 10KR2J-3-GP OPS
N12P_JTAG_TMS JTAG_TCK
1
N12P_JTAG_TDI
AD6
JTAG_TMS OPS R7601 R7603
TP7602 1 AE6 10KR2J-3-GP 1MR2J-1-GP

2
TP7605 N12P_JTAG_TDO JTAG_TDI 27MHZ_IN 27MHZ_OUT
1 AF6 1 DY 2

2
TP7601 N12P_JTAG_TRST JTAG_TDO GC6_FB_EN_GPU GPIO5_GC6_PWR_EN_GPU
AG4 C6 X7601
JTAG_TRST# GPIO0
GPIO1
B2 3V3_MAIN_EN is an open-drain GPIO.

2
D6
GPIO2
3
4

C7 3D3V_VGA_S0 1 4
RN7602 GPIO3 R7636 R7604
OPS
F9 1K3R2J-GP
GPIO4 GPIO5_GC6_PWR_EN_GPU 3V3_AON_S0
SRN10KJ-5-GP A3 1 2 GPIO5_GC6_PWR_EN [12]
GPIO5 GPU_EVENT_GPU# 0R2J-2-GP
OPS GK208 A4

1
GPIO6

1
GM108 B6 GC6_20 2 3 27MHZ_OUT_R
GPIO7 OVERT_GPU# R7605
OVERT A6 OPS
2
1

GPIO8

1
F8 GPIO9_ALERT OPS 100KR2J-1-GP R7613
GPIO9

2
C5 GPIO10_FBVREF [7,8] 10KR2J-3-GP R7645
GPIO10 10KR2J-3-GP C7607 C7608
E7 VGA_CORE_VID [11] D7601 [2] GPU_PEX_RST# 1 2 OPS

2
GPIO11 PWR_LEVEL AC_PRESENT SC18P50V2JN-1-GP SC18P50V2JN-1-GP
D7 A K 1 DY

1
GPIO12 TP7608 XTAL-27MHZ-85-GP-U
B4 VGA_CORE_PSI [11] DY 1SS400CMT2R-GP OPS OPS

2
GPIO13
VIDEO_THERM_OVERT# OVERT# OVERT_GPU#
82.30034.641
R7631 10KR2J-3-GP 1 1 R7656 2
GM108 GK208 GF117 GF119
3V3_AON_S0 1 2 D7602 TP7606 2ND = 82.30034.651
GPIO16 GPIO16 NC D5 GC6_20 A K 0R0402-PAD 3RD = 82.30034.681
GPIO16 OVER_CURRENT_P8# [13]

1
GPIO20 GPIO20 NC GPIO20
E6 GC6_20 OPS 1SS400CMT2R-GP VGA_CORE IC not support ALERT#.
C4 GPU_PEX_RST_HOLD_GPU# 1 2 R7630 84.2N702.A3F OPS C7609
GPIO21 GPIO8 NC GPIO21 GPU_PEX_RST_HOLD [2]

4
SC2700P50V2KX-1-GP
GC6_20 0R2J-2-GP 83.1S400.E2F 2nd = 84.2N702.E3F

2
E9 SYS_PEX_RST_MON_GPU# 1 2 2nd = 83.1S427.01F Q7602 3rd = 75.00601.07C
GPIO8 NC NC CEC SYS_PEX_RST_MON# [2]
R7634 0R2J-2-GP 2N7002KDW-GP 4th = 84.DMN66.03F
N16S-GM-S-A2-GP
OPS
Connect to SYS_PEX_RST_MON#

3
if GC62.0 is implemented. R7653
Leave NC for GC6 1.0. P_H_S# 1 DY 2 PURE_HW_SHUTDOWN# 1
3V3_AON_S0 GPIO9_ALERT TP7607

1
0R2J-2-GP
R7612
DY C7610
3V3_AON_S0 1 2 SC2700P50V2KX-1-GP
3V3_AON_S0

2
GPIO10_FBVREF
OPS
DA-05691-001_V05 P15 10KR2J-3-GP
4
3

1 R7657 2 Q7601_G
GPIO20/21 NC : for ALL

1
0R0402-PAD RN7601
OPS SRN4K7J-8-GP R7610
100KR2J-1-GP
OPS
1
2

Q7601
C C

2
3 4 SMBD_THERM_NV
[13] SML1_SMBDATA
2 5 3V3_AON_S0
1 6

2N7002KDW-GP

2
OPS R7643

SMBC_THERM_NV
DY 10KR2J-3-GP

[13] SML1_SMBCLK

1
84.2N702.A3F
2nd = 84.2N702.E3F SYS_PEX_RST_MON_GPU#
3rd = 75.00601.07C
4th = 84.DMN66.03F

3V3_AON_S0
3D3V_VGA_S0

3D3V_VGA_S0

4K99R2F-L-GP

4K99R2F-L-GP
R7620

R7635
10KR2F-2-GP
GPU1L 10 OF 14

R7618
10/14 MISC2
1

1
R7619

R7609

R7614

R7625

R7628
49K9R2F-L-GP

49K9R2F-L-GP

49K9R2F-L-GP

49K9R2F-L-GP

49K9R2F-L-GP

DY

DY

DY
DY DY DY DY
E10
VMON_IN0
F10 D12
2

2
VMON_IN1 ROM_CS#
B12 GPU_ROM_SI
ROM_SI GPU_ROM_SO
A12
STRAP0 ROM_SO GPU_ROM_SCLK
D1 C12
STRAP1 STRAP0 ROM_SCLK
D2
STRAP2 STRAP1

Samsung2G
E4 NC FOR
STRAP3 STRAP2

Micron4G
4K99R2F-L-GP

4K99R2F-L-GP

Samsung4G

4K99R2F-L-GP

20KR2F-L-GP
E3 GM108
STRAP3
R7632

R7621

R7622
STRAP4

10KR2F-2-GP

Micron2G
34K8R2F-1-GP
D3
STRAP4

R7624

R7616

Hynix2G
1

1
R7606
OPS

OPS

R7637
C1 24K9R2F-L-GP
STRAP5
1

1
R7608

R7611

R7615

R7626

R7629

R7607
49K9R2F-L-GP

49K9R2F-L-GP

49K9R2F-L-GP

49K9R2F-L-GP

49K9R2F-L-GP

D11
40K2R2F-GP BUFRST#
2

2
DY DY 1 2 STRAP_REF0_GND_N9 F6 NC D10
MULTI_STRAP_REF0_GND PGOOD
DY DY DY N16V-GM GF117
GK208 GF117 GF119
2

N15V-GS supports Binary Mode. GM108 GK208

N16V-GM supports Multi-Level Strap. F4 GM108
MULTI_STRAP_REF1_GND NC

B F5 NC
B
MULTI_STRAP_REF2_GND

N16S-GM-S-A2-GP

3V3_AON_S0 3D3V_S0
2

3V3_AON_S0
2

R7648
Q7606
R7649 10KR2J-3-GP
10KR2J-3-GP G
GC6_20 GC6_20
GC6_20
1

R7623
D
1

GC6_FB_EN GPU_EVENT# [13]

[4,12,13] GC6_FB_EN 1 2 GC6_FB_EN_GPU
GPU_EVENT_GPU# S
0R2J-2-GP
1

R7627 2N7002K-2-GP
10KR2J-3-GP 84.2N702.J31
DY 2ND = 84.2N702.031
2

GC6_20

R7644
2 DY 1

10KR2J-3-GP

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU(4/5)GPIO/STRAP
Size Document Number Rev
Custom
Starload SKL-U A00
Date: Thursday, February 18, 2016 Sheet 5 of 13
5 4 3 2 1
 5 4 3 2 1

Main Func = dGPU GPU1F

13/14 GND
13 OF 14

A2 GND_001 GND_071 M13

VGA_CORE AB17 GND_005 GND_072 M15
AB20 GND_006 GND_073 M17
AB24 N10
GND_007 GND_074
AC2 GND_008 GND_075 N12
Under GPU GPU1E 11 OF 14
AC22
GND_009 GND_076
N14
AC26 N16
GND_010 GND_077
11/14 NVVDD AC5 N18
GND_011 GND_078
K10 AC8 P11
VDD_001 GND_012 GND_079
K12 AD12 P13
VDD_002 GND_013 GND_080
K14 VDD_003 AD13 GND_014 GND_081 P15
C7722 C7708 C7723 C7702 C7701 K16 A26 P17
1 VDD_004 GND_002 GND_082

1
K18 VDD_005 AD15 GND_015 GND_083 P2
SC4D7U6D3V3KX-GP

OPS
SC4D7U6D3V3KX-GP
OPS

SC4D7U6D3V3KX-GP
OPS

SC4D7U6D3V3KX-GP
OPS

SC4D7U6D3V3KX-GP
OPS L11
VDD_006
AD16
GND_016 GND_084
P23
L13 AD18 P26
2

2
VDD_007 GND_017 GND_085
D L15 VDD_008 AD19 GND_018 GND_086 P5 D
L17 VDD_009 AD21 GND_019 GND_087 R10
M10 VDD_010 AD22 GND_020 GND_088 R12
M12 AE11 R14
VDD_011 GND_021 GND_089
M14 VDD_012 AE14 GND_022 GND_090 R16
M16 VDD_013 AE17 GND_023 GND_091 R18
M18 VDD_014 AE20 GND_024 GND_092 T11
N11 AB11 T13
VDD_015 GND_003 GND_093
N13 VDD_016 AF1 GND_025 GND_094 T15
N15 VDD_017 AF11 GND_026 GND_095 T17
N17 AF14 U10
VDD_018 GND_027 GND_096
P10 AF17 U12
C7709 C7725 C7721 C7720 C7719 VDD_019 GND_028 GND_097
P12 AF20 U14
VDD_020 GND_029 GND_098
1

1
P14 AF23 U16
VDD_021 GND_030 GND_099
SC4D7U6D3V3KX-GP

OPS
SC4D7U6D3V3KX-GP

OPS
SC4D7U6D3V3KX-GP

OPS
SC4D7U6D3V3KX-GP

OPS
SC4D7U6D3V3KX-GP
OPS P16
VDD_022
AF5
GND_031 GND_100
U18
P18 AF8 U2
2

2
VDD_023 GND_032 GND_101
R11 VDD_024 AG2 GND_033 GND_102 U23
R13 VDD_025 AG26 GND_034 GND_103 U26
R15 VDD_026 AB14 GND_004 GND_104 U5
R17 VDD_027 B1 GND_035 GND_105 V11
T10 B11 V13
VDD_028 GND_036 GND_106
T12 B14 V15
VDD_029 GND_037 GND_107
T14 B17 V17
VDD_030 GND_038 GND_108
T16 B20 Y2
VDD_031 GND_039 GND_109
T18 B23 Y23
VDD_032 GND_040 GND_110
U11 B27 Y26
VDD_033 GND_041 GND_111
OPS OPS OPS OPS U13
VDD_034
B5
GND_042 GND_112
Y5
U15 B8
VDD_035 GND_043
U17 VDD_036 E11 GND_044
1

V10 E14
C7714 C7713 C7712 C7711 VDD_037 GND_045
V12 VDD_038 E17 GND_046
SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

V14 E2
2

VDD_039 GND_047
V16 VDD_040 E20 GND_048
V18 E22
VDD_041 GND_049
E25
GND_050
E5
N16S-GM-S-A2-GP GND_051
E8
GND_052
C H2 C
GND_053
H23
GND_054
H25
GND_055
H5 GND_056
K11 GND_057
Near GPU K13 GND_058
K15 GND_059
K17 GND_060
L10
GND_061
L12
GND_062
L14
GND_063
L16 GND_064
C7732 C7731 C7730 C7726 C7724 C7717 C7710 L18
GND_065
1

OPS OPS OPS OPS OPS OPS OPS L2

GND_066
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

L23
GND_067
SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

L25
2

GND_068
L5 AA7
GND_069 GND_F
M11 AB7
GND_070 GND_H

3D3V_VGA_S0
N16S-GM-S-A2-GP
Under GPU Near GPU

3.3V +/- 5%
C7734 C7729
85mA
1

OPS OPS C7728 C7703

SC1U10V2KX-1GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP

OPS
OPS
2

GPU1C 14 OF 14
14/14 XVDD/VDD33
B B
AD10 G8
NC#AD10 VDD33_1
AD7 G9
NC#AD7 GM108 VDD33_2
3V3_AON G10
VDD33_3
3V3_AON G12
VDD33_4
1 GPU_NC_F11 F11
TP601 3V3AUX 3V3_AON_S0
V5
NC#V5
V6
NC#V6 Under GPUNear GPU

CONFIGURABLE
POWER CHANNELS C7735
1

* nc on substrate OPS C7736 C7704

SC1U10V2KX-1GP
SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP

OPS
G1 OPS
2

NC#G1
G2
NC#G2
G3
NC#G3
G4
NC#G4
G5
NC#G5
G6
NC#G6
G7 NC#G7

V1
NC#V1
V2
NC#V2

W1
NC#W1
W2
NC#W2
W3
NC#W3
W4 NC#W4
A A

N16S-GM-S-A2-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU(5/5)PWR/GND
Size Document Number Rev
Custom
Starload SKL-U A00
Date: Thursday, January 07, 2016 Sheet 6 of 13
5 4 3 2 1
 5 4 3 2 1

SSID = VRAM

Place close VDD ball Place close VDD ball

1D35V_VGA_S0
1D35V_VGA_S0 1D35V_VGA_S0
VRAM2A 1 OF 2
1D35V_VGA_S0 VRAM1A 1 OF 2
Frame Buffer Patition A-Lower Half C5
VDD OPS VSS
B5
OPS OPS
C5 B5 C10 B10
VDD OPS VSS VDD VSS OPS

SC1U6D3V3KX-2GP
C7805

SC1U6D3V3KX-2GP
C7806

SC1U6D3V3KX-2GP
C7807

SC1U6D3V3KX-2GP
C7809

SCD1U10V2KX-4GP
C7808

SCD1U10V2KX-4GP
C7815
C10 B10 D11 D10

1
VDD VSS 1D35V_VGA_S0 VDD VSS C7804
D11 D10 G1 G5
VDD VSS VDD VSS

SC10U6D3V3MX-GP
G1 G5 G4 G10
G4
VDD VSS
G10 G11
VDD VSS
H1
OPS
OPS

2
VDD VSS VDD VSS
D G11 H1 G14 H14 D
VDD VSS VDD VSS

1
G14 H14 L1 K1
L1
VDD VSS
K1 R7806 R7805 L4
VDD VSS
K14 OPS
L4
VDD VSS
K14 549R2F-GP 549R2F-GP L11
VDD VSS
L5
OPS
VDD VSS VDD VSS
L11 L5 L14 L10
L14
VDD VSS
L10 OPS OPS P11
VDD VSS
P10

2
VDD VSS FBA_VREFC0 FBA_VREFD_L VDD VSS
P11 P10 R5 T5
VDD VSS 1D35V_VGA_S0 VDD VSS
R5 T5 R10 T10
VDD VSS VDD VSS Place close VDD ball

1
1D35V_VGA_S0

SC820P50V2KX-1GP
C7803

1K33R2F-GP
R7807

931R2F-1-GP
R7804

931R2F-1-GP
R7803

1K33R2F-GP
R7809

SC820P50V2KX-1GP
C7802
R10 T10

1
VDD VSS
B1 A1
VDDQ VSSQ 1D35V_VGA_S0
B1 A1 B3 A3
B3
VDDQ VSSQ
A3
OPS B12
VDDQ VSSQ
A12
OPS OPS OPS OPS OPS

2
VDDQ VSSQ VDDQ VSSQ
B12 A12 B14 A14

2
VDDQ VSSQ VDDQ VSSQ
B14 A14 D1 C1
D1
VDDQ VSSQ
C1 D3
VDDQ VSSQ
C3 OPS OPS
VDDQ VSSQ VDDQ VSSQ

SCD1U10V2KX-4GP
C7820

SCD1U10V2KX-4GP
C7821

SCD1U10V2KX-4GP
C7822

SCD1U10V2KX-4GP
C7823

SCD1U10V2KX-4GP
C7824

SCD1U10V2KX-4GP
C7825
D3 C3 D12 C4
VDDQ VSSQ VDDQ VSSQ DY

1
D12 C4 FBA_VREF_FET_L D14 C11
VDDQ VSSQ VDDQ VSSQ
D14 C11 E5 C12
E5
VDDQ VSSQ
C12 E10
VDDQ VSSQ
C14
OPS

2
VDDQ VSSQ VDDQ VSSQ
E10 C14 F1 E1

D
VDDQ VSSQ VDDQ VSSQ
F1 E1 F3 E3
F3
VDDQ VSSQ
E3 Q7801 F12
VDDQ VSSQ
E12
OPS OPS
VDDQ VSSQ VDDQ VSSQ
F12 E12 2N7002K-2-GP F14 E14
VDDQ VSSQ VDDQ VSSQ
F14 E14 G2 F5
VDDQ VSSQ 84.2N702.J31 VDDQ VSSQ
G2 F5 G13 F10
G13
VDDQ VSSQ
F10 OPS 2ND = 84.2N702.031 H3
VDDQ VSSQ
H2
VDDQ VSSQ VDDQ VSSQ
H3 H2 H12 H13
H12
VDDQ VSSQ
H13
3rd = 84.2N702.W31 K3
VDDQ VSSQ
K2
Place close VDDQ ball Place close VDDQ ball

S
VDDQ VSSQ VDDQ VSSQ
K3
VDDQ VSSQ
K2 Description K12
VDDQ VSSQ
K13
K12 K13 [5,8] GPIO10_FBVREF L2 M5 1D35V_VGA_S0 1D35V_VGA_S0
VDDQ VSSQ VDDQ VSSQ
L2 M5 L13 M10
VDDQ VSSQ VDDQ VSSQ
L13 M10 M1 N1
VDDQ VSSQ VDDQ VSSQ
M1 N1 M3 N3
VDDQ VSSQ VDDQ VSSQ
M3
VDDQ VSSQ
N3 FBVREF Termination M12
VDDQ VSSQ
N12
OPS OPS OPS OPS OPS

SC1U6D3V3KX-2GP
C7814

SC1U6D3V3KX-2GP
C7810

SC1U6D3V3KX-2GP
C7811

SC1U6D3V3KX-2GP
C7812

SCD1U10V2KX-4GP
C7816

SCD1U10V2KX-4GP
C7817

SCD1U10V2KX-4GP
C7818

SCD1U10V2KX-4GP
C7819
M12 N12 M14 N14

1
VDDQ VSSQ VDDQ VSSQ C7813
M14 N14 N5 R1
VDDQ VSSQ VDDQ VSSQ

SC10U6D3V3MX-GP
N5
VDDQ VSSQ
R1 Type FBVREF% Voltage GPU_GPIO10 N10
VDDQ VSSQ
R3
N10 R3 P1 R4

2
VDDQ VSSQ VDDQ VSSQ
P1 R4 P3 R11
VDDQ VSSQ VDDQ VSSQ
P3
VDDQ VSSQ
R11 Un-termination 50% 0.749V High P12
VDDQ VSSQ
R12
OPS OPS OPS OPS
P12 R12 P14 R14
VDDQ VSSQ VDDQ VSSQ
C P14 R14 T1 U1 C
VDDQ VSSQ VDDQ VSSQ
T1
VDDQ VSSQ
U1 Termination 70% 1.0617V Low T3
VDDQ VSSQ
U3
T3 U3 T12 U12
VDDQ VSSQ VDDQ VSSQ
T12 U12 T14 U14
VDDQ VSSQ VDDQ VSSQ
T14 U14
VDDQ VSSQ FBA_VREFC0 J14 A5
FBA_VREFC0 VREFC VPP/NC#A5
J14 A5 U5
VREFC VPP/NC#A5 FBA_VREFD_L VPP/NC#U5
U5 A10
FBA_VREFD_L VPP/NC#U5 VPP1 TP7801 TPAD14-OP-GP VREFD TP_VPPNC3 TP7803 TPAD14-OP-GP
A10 1 U10 1
VREFD VPP2 TP7802 TPAD14-OP-GP VREFD TP_VPPNC4 TP7804 TPAD14-OP-GP
U10 1 1
VREFD
SC820P50V2KX-1GP
C7826
1

H5GQ2H24AFR-T2C-GP
H5GQ2H24AFR-T2C-GP
OPS
2

FBA_EDC0 FBA_DQM0
[4] FBA_EDC0 FBA_DQM0 [4]
FBA_EDC1 FBA_DQM1 FBA_DQM1 [4]
[4] FBA_EDC1 FBA_EDC2 FBA_DQM2
[4] FBA_EDC2 FBA_DQM2 [4]
FBA_EDC3 FBA_DQM3
[4] FBA_EDC3 FBA_DQM3 [4]

Mirrored(MF=1)
B
Normal(MF=0) FBA_D[0..31] [4] B
VRAM2B 2 OF 2
VRAM1B 2 OF 2
FBA_D[0..31] [4] FBA_CMD10 FBA_D24
[4] FBA_CMD10 K4 A4
[4] FBA_CMD6 FBA_CMD6 K4 A4 FBA_D0 [4] FBA_CMD7 FBA_CMD7 H5
A8/A7 OPS DQ0
A2 FBA_D25
[4] FBA_CMD11 FBA_CMD11 H5
A8/A7 OPS DQ0
A2 FBA_D1 [4] FBA_CMD6 FBA_CMD6 H4
A9/A1 DQ1
B4 FBA_D26
FBA_CMD10 A9/A1 DQ1 FBA_D2 FBA_CMD11 A10/A0 DQ2 FBA_D27
[4] FBA_CMD10 H4 B4 [4] FBA_CMD11 K5 B2
FBA_CMD7 A10/A0 DQ2 FBA_D3 FBA_CMD9 A11/A6 DQ3 FBA_D28
[4] FBA_CMD7 K5 B2 [4] FBA_CMD9 J5 E4
FBA_CMD9 A11/A6 DQ3 FBA_D4 A12/RFU#J5/NC#J5 DQ4 FBA_D29
[4] FBA_CMD9 J5 E4 E2
A12/RFU#J5/NC#J5 DQ4 FBA_D5 FBA_CMD3 DQ5 FBA_D30
E2 [4] FBA_CMD3 H11 F4
FBA_CMD2 DQ5 FBA_D6 FBA_CMD1 BA0/A2 DQ6 FBA_D31
[4] FBA_CMD2 H11 F4 [4] FBA_CMD1 K10 F2
FBA_CMD4 BA0/A2 DQ6 FBA_D7 FBA_CMD2 BA1/A5 DQ7
[4] FBA_CMD4 K10 F2 [4] FBA_CMD2 K11 A11
FBA_CMD3 BA1/A5 DQ7 FBA_CMD4 BA2/A4 DQ8
[4] FBA_CMD3 K11 A11 [4] FBA_CMD4 H10 A13
FBA_CMD1 BA2/A4 DQ8 BA3/A3 DQ9
[4] FBA_CMD1 H10 A13 B11
BA3/A3 DQ9 FBA_CMD8 DQ10
B11 [4] FBA_CMD8 J4 B13
FBA_CMD8 DQ10 FBA_CMD15 ABI# DQ11
[4] FBA_CMD8 J4 B13 [4] FBA_CMD15 G3 E11
FBA_CMD12 ABI# DQ11 FBA_CMD5 RAS# DQ12
[4] FBA_CMD12 G3 E11 [4] FBA_CMD5 G12 E13 FBA_D[0..31] [4]
FBA_CMD0 RAS# DQ12 FBA_CMD12 CS# DQ13
[4] FBA_CMD0 G12 E13 FBA_D[0..31] [4] [4] FBA_CMD12 L3 F11
FBA_CMD15 CS# DQ13 FBA_CMD0 CAS# DQ14
[4] FBA_CMD15 L3 F11 [4] FBA_CMD0 L12 F13
FBA_CMD5 CAS# DQ14 WE# DQ15 FBA_D8
[4] FBA_CMD5 L12 F13 U11
WE# DQ15 FBA_D16 FBA_CLK0P DQ16 FBA_D9
U11 J12 U13
FBA_CLK0P DQ16 FBA_D17 FBA_CLK0N CK DQ17 FBA_D10
[4] FBA_CLK0P J12 U13 J11 T11
FBA_CLK0N CK DQ17 FBA_D18 FBA_CMD14 CK# DQ18 FBA_D11
[4] FBA_CLK0N J11 T11 [4] FBA_CMD14 J3 T13
1

FBA_CMD14 CK# DQ18 FBA_D19 CKE# DQ19 FBA_D12

[4] FBA_CMD14 J3 T13 N11
CKE# DQ19 FBA_D20 R7802 R7801 FBA_DQM3 DQ20 FBA_D13
N11 D2 N13
FBA_DQM0 DQ20 FBA_D21 40D2R2F-GP 40D2R2F-GP DBI0# DQ21 FBA_D14
D2 N13 D13 M11
DBI0# DQ21 FBA_D22 FBA_DQM1 DBI1# DQ22 FBA_D15
D13 M11 P13 M13
FBA_DQM2 P13
DBI1# DQ22
M13 FBA_D23 OPS OPS P2
DBI2# DQ23
U4
2

DBI2# DQ23 FBA_CLK0_MIDPT DBI3# DQ24

P2 U4 U2
DBI3# DQ24 FBA_CMD13 DQ25
U2 [4] FBA_CMD13 J2 T4
DQ25 RESET# DQ26
2

[4] FBA_CMD13 FBA_CMD13 J2 T4 T2

RESET# DQ26 C7801 FBA_SEN0 DQ27
T2 J10 N4
FBA_SEN0 J10
DQ27
N4 SCD01U16V2KX-3GP OPS FBA_ZQ1 J13
SEN DQ28
N2
1

FBA_ZQ0 SEN DQ28 FBA_MF2 ZQ DQ29

J13 N2 2 1 J1 M4
FBA_MF1 J1
ZQ DQ29
M4
1D35V_VGA_S0
R7812 OPS 1KR2J-1-GP MF DQ30
M2
MF DQ30 DQ31
2

1
1KR2J-1-GP
R7810

121R2F-GP
R7813

M2 FBA_WCK23 D4
1

DQ31 WCK01
121R2F-GP
R7808

1KR2J-1-GP
R7811

FBA_WCK01 D4 FBA_WCK23# D5 C2 FBA_EDC3

FBA_WCK01# WCK01 FBA_EDC0 WCK01# EDC0
D5 C2 C13
WCK01# EDC0
C13
OPS OPS FBA_WCK01 P4
EDC1
R13 FBA_EDC1
OPS OPS FBA_WCK23 P4
EDC1
R13 FBA_EDC2 FBA_WCK01# P5
WCK23 EDC2
R2
1

FBA_WCK23# WCK23 EDC2 WCK23# EDC3

P5 R2
2

WCK23# EDC3
A H5GQ2H24AFR-T2C-GP A
[4] FBA_WCK23
H5GQ2H24AFR-T2C-GP [4] FBA_WCK23#
[4] FBA_WCK01
[4] FBA_WCK01#

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM1,2 (1/4)
Size Document Number Rev
A2
Starload-SKL-U A00
Date: Thursday, February 18, 2016 Sheet 7 of 13
5 4 3 2 1
 5 4 3 2 1

SSID = VRAM

1D35V_VGA_S0 VRAM3A 1 OF 2 1D35V_VGA_S0 VRAM4A 1 OF 2 1D35V_VGA_S0

Frame Buffer Patition A-Upper Half Place close VDD ball
C5 B5 C5 B5
C10
VDD OPS VSS
B10 C10
VDD OPS VSS
B10
D11
VDD VSS
D10 1D35V_VGA_S0 D11
VDD VSS
D10
OPS

1
VDD VSS VDD VSS

SC1U6D3V3KX-2GP
C7924

SC1U6D3V3KX-2GP
C7904

SC1U6D3V3KX-2GP
C7905

SC1U6D3V3KX-2GP
C7906
G1 G5 G1 G5 C7907
VDD VSS VDD VSS

SC10U6D3V3MX-GP
G4 G10 G4 G10
VDD VSS VDD VSS
G11 H1 G11 H1

2
1

1
VDD VSS VDD VSS
G14 H14 G14 H14
L1
VDD VSS
K1 R7903 R7907 L1
VDD VSS
K1
OPS OPS OPS OPS
VDD VSS 549R2F-GP 549R2F-GP VDD VSS
L4 K14 L4 K14
VDD VSS VDD VSS
L11 L5 L11 L5
D
L14
VDD VSS
L10 OPS OPS L14
VDD VSS
L10
D

2
VDD VSS FBA_VREFC1 FBA_VREFD_H VDD VSS
P11 P10 P11 P10
VDD VSS VDD VSS
R5 T5 R5 T5

1
1D35V_VGA_S0 VDD VSS 1D35V_VGA_S0 VDD VSS 1D35V_VGA_S0

SC820P50V2KX-1GP
C7902

1K33R2F-GP
R7904

931R2F-1-GP
R7902

931R2F-1-GP
R7905

1K33R2F-GP
R7901

SC820P50V2KX-1GP
C7903
R10 T10 R10 T10
Place close VDD ball

1
VDD VSS VDD VSS
B1 A1 B1 A1
B3
VDDQ VSSQ
A3 OPS B3
VDDQ VSSQ
A3
OPS OPS OPS OPS

2
VDDQ VSSQ VDDQ VSSQ

SCD1U10V2KX-4GP
C7911

SCD1U10V2KX-4GP
C7912

SCD1U10V2KX-4GP
C7913

SCD1U10V2KX-4GP
C7914

SCD1U10V2KX-4GP
C7920

SCD1U10V2KX-4GP
C7926
B12 A12 B12 A12
OPS

1
VDDQ VSSQ VDDQ VSSQ
B14 A14 B14 A14
VDDQ VSSQ VDDQ VSSQ
D1 C1 D1 C1
VDDQ VSSQ VDDQ VSSQ
D3 C3 D3 C3

2
VDDQ VSSQ FBA_VREF_FET_H VDDQ VSSQ
D12 C4 D12 C4
VDDQ VSSQ VDDQ VSSQ
D14 C11 D14 C11
E5
VDDQ VSSQ
C12 E5
VDDQ VSSQ
C12 OPS OPS OPS OPS OPS OPS
VDDQ VSSQ VDDQ VSSQ
E10 C14 E10 C14

D
VDDQ VSSQ VDDQ VSSQ
F1 E1 F1 E1
VDDQ VSSQ Q7901 VDDQ VSSQ
F3 E3 F3 E3
VDDQ VSSQ VDDQ VSSQ 1D35V_VGA_S0
F12 E12 F12 E12
F14
VDDQ VSSQ
E14
2N7002K-2-GP
F14
VDDQ VSSQ
E14
Place close VDDQ ball
VDDQ VSSQ 84.2N702.J31 VDDQ VSSQ
G2 F5 G2 F5
G13
VDDQ VSSQ
F10
OPS 2ND = 84.2N702.031 G13
VDDQ VSSQ
F10
H3
VDDQ VSSQ
H2 3rd = 84.2N702.W31 H3
VDDQ VSSQ
H2 OPS
VDDQ VSSQ VDDQ VSSQ

1
SC1U6D3V3KX-2GP
C7919

SC1U6D3V3KX-2GP
C7915

SC1U6D3V3KX-2GP
C7916

SC1U6D3V3KX-2GP
C7917
H12 H13 H12 H13 C7918

S
VDDQ VSSQ VDDQ VSSQ

SC10U6D3V3MX-GP
K3 K2 K3 K2
VDDQ VSSQ VDDQ VSSQ
K12 K13 [5,7] GPIO10_FBVREF K12 K13

2
VDDQ VSSQ VDDQ VSSQ
L2 M5 L2 M5
VDDQ VSSQ VDDQ VSSQ
L13 M10 L13 M10
M1
VDDQ VSSQ
N1 M1
VDDQ VSSQ
N1
OPS OPS OPS OPS
VDDQ VSSQ VDDQ VSSQ
M3 N3 M3 N3
VDDQ VSSQ VDDQ VSSQ
M12
VDDQ VSSQ
N12 FBVREF Termination M12
VDDQ VSSQ
N12
M14 N14 M14 N14
VDDQ VSSQ VDDQ VSSQ
N5 R1 N5 R1
VDDQ VSSQ VDDQ VSSQ
N10
VDDQ VSSQ
R3 Type FBVREF% Voltage GPU_GPIO10 N10
VDDQ VSSQ
R3
Place close VDD ball Place close VDDQ ball
P1 R4 P1 R4
VDDQ VSSQ VDDQ VSSQ 1D35V_VGA_S0 1D35V_VGA_S0
P3 R11 P3 R11
VDDQ VSSQ VDDQ VSSQ
P12
VDDQ VSSQ
R12 Un-termination 50% 0.749V High P12
VDDQ VSSQ
R12
P14 R14 P14 R14
VDDQ VSSQ VDDQ VSSQ
T1 U1 T1 U1
VDDQ VSSQ VDDQ VSSQ
T3
VDDQ VSSQ
U3 Termination 70% 1.0617V Low T3
VDDQ VSSQ
U3

SCD1U10V2KX-4GP
C7910

SCD1U10V2KX-4GP
C7909

SCD1U10V2KX-4GP
C7921

SCD1U10V2KX-4GP
C7922

SCD1U10V2KX-4GP
C7923

SCD1U10V2KX-4GP
C7925
T12 U12 T12 U12
VDDQ VSSQ VDDQ VSSQ

1
C T14 U14 T14 U14 C
VDDQ VSSQ VDDQ VSSQ
FBA_VREFC1 J14 A5 FBA_VREFC1 J14 A5

2
VREFC VPP/NC#A5 VREFC VPP/NC#A5
U5 U5
FBA_VREFD_H A10
VPP/NC#U5 TP_VPPNC5 1 TP7901 TPAD14-OP-GP FBA_VREFD_H A10
VPP/NC#U5 OPS OPS OPS OPS
VREFD VREFD OPS OPS
SC820P50V2KX-1GP
C7908

U10 TP_VPPNC6 1 TP7902 TPAD14-OP-GP U10

1

VREFD VREFD

H5GQ2H24AFR-T2C-GP H5GQ2H24AFR-T2C-GP TP_VPPNC7 1 TP7903 TPAD14-OP-GP

2

TP_VPPNC8 1 TP7904 TPAD14-OP-GP

OPS

FBA_EDC4 FBA_DQM4
[4] FBA_EDC4 FBA_DQM4 [4]
FBA_EDC5 FBA_DQM5
[4] FBA_EDC5 FBA_DQM5 [4]
FBA_EDC6 FBA_DQM6 FBA_DQM6 [4]
[4] FBA_EDC6 FBA_EDC7 FBA_DQM7
[4] FBA_EDC7 FBA_DQM7 [4]

Normal(MF=0) Mirrored(MF=1) FBA_D[32..63] [4]

VRAM3B 2 OF 2 VRAM4B 2 OF 2
FBA_D[32..63] [4]
[4] FBA_CMD22 FBA_CMD22 K4 A4 FBA_D32 [4] FBA_CMD26 FBA_CMD26 K4 A4 FBA_D56
[4] FBA_CMD27 FBA_CMD27 H5
A8/A7 OPS DQ0
A2 FBA_D33 [4] FBA_CMD23 FBA_CMD23 H5
A8/A7 DQ0
A2 FBA_D57
[4] FBA_CMD26 FBA_CMD26 H4
A9/A1 DQ1
B4 FBA_D34 [4] FBA_CMD22 FBA_CMD22 H4
A9/A1 OPS DQ1
B4 FBA_D58
FBA_CMD23 A10/A0 DQ2 FBA_D35 FBA_CMD27 A10/A0 DQ2 FBA_D59
[4] FBA_CMD23 K5 B2 [4] FBA_CMD27 K5 B2
FBA_CMD25 A11/A6 DQ3 FBA_D36 FBA_CMD25 A11/A6 DQ3 FBA_D60
[4] FBA_CMD25 J5 E4 [4] FBA_CMD25 J5 E4
A12/RFU#J5/NC#J5 DQ4 FBA_D37 A12/RFU#J5/NC#J5 DQ4 FBA_D61
E2 E2
FBA_CMD18 DQ5 FBA_D38 FBA_CMD19 DQ5 FBA_D62
[4] FBA_CMD18 H11 F4 [4] FBA_CMD19 H11 F4
FBA_CMD20 BA0/A2 DQ6 FBA_D39 FBA_CMD17 BA0/A2 DQ6 FBA_D63
[4] FBA_CMD20 K10 F2 [4] FBA_CMD17 K10 F2
B FBA_CMD19 BA1/A5 DQ7 FBA_CMD18 BA1/A5 DQ7 B
[4] FBA_CMD19 K11 A11 [4] FBA_CMD18 K11 A11
FBA_CMD17 BA2/A4 DQ8 FBA_CMD20 BA2/A4 DQ8
[4] FBA_CMD17 H10 A13 [4] FBA_CMD20 H10 A13
BA3/A3 DQ9 BA3/A3 DQ9
B11 B11
FBA_CMD24 DQ10 FBA_CMD24 DQ10
[4] FBA_CMD24 J4 B13 [4] FBA_CMD24 J4 B13
FBA_CMD28 ABI# DQ11 FBA_CMD31 ABI# DQ11
[4] FBA_CMD28 G3 E11 [4] FBA_CMD31 G3 E11
FBA_CMD16 RAS# DQ12 FBA_CMD21 RAS# DQ12
[4] FBA_CMD16 G12 E13 [4] FBA_CMD21 G12 E13 FBA_D[32..63] [4]
FBA_CMD31 CS# DQ13 FBA_CMD28 CS# DQ13
[4] FBA_CMD31 L3 F11 FBA_D[32..63] [4] [4] FBA_CMD28 L3 F11
FBA_CMD21 CAS# DQ14 FBA_CMD16 CAS# DQ14
[4] FBA_CMD21 L12 F13 [4] FBA_CMD16 L12 F13
WE# DQ15 FBA_D48 WE# DQ15 FBA_D40
U11 U11
FBA_CLK1P DQ16 FBA_D49 FBA_CLK1P DQ16 FBA_D41
[4] FBA_CLK1P J12 U13 J12 U13
FBA_CLK1N CK DQ17 FBA_D50 FBA_CLK1N CK DQ17 FBA_D42
[4] FBA_CLK1N J11 T11 J11 T11
FBA_CMD30 CK# DQ18 FBA_D51 FBA_CMD30 CK# DQ18 FBA_D43
[4] FBA_CMD30 J3 T13 [4] FBA_CMD30 J3 T13
1

CKE# DQ19 FBA_D52 CKE# DQ19 FBA_D44

N11 N11
FBA_DQM4 DQ20 FBA_D53 R7906 FBA_DQM7 DQ20 FBA_D45
D2 N13 R7908 D2 N13
DBI0# DQ21 FBA_D54 40D2R2F-GP 40D2R2F-GP DBI0# DQ21 FBA_D46
D13 M11 D13 M11
FBA_DQM6 DBI1# DQ22 FBA_D55 FBA_DQM5 DBI1# DQ22 FBA_D47
P13 M13 P13 M13
P2
DBI2# DQ23
U4
OPS OPS P2
DBI2# DQ23
U4
2

DBI3# DQ24 FBA_CLK1_MIDPT DBI3# DQ24

U2 U2
FBA_CMD29 DQ25 FBA_CMD29 DQ25
[4] FBA_CMD29 J2 T4 [4] FBA_CMD29 J2 T4
RESET# DQ26 RESET# DQ26
2

T2 T2
FBA_SEN2 DQ27 C7901 FBA_SEN2 DQ27
J10 N4 J10 N4
FBA_ZQ2 J13
SEN DQ28
N2 SCD01U16V2KX-3GP OPS FBA_ZQ3 J13
SEN DQ28
N2
1

FBA_MF3 ZQ DQ29 FBA_MF4 ZQ DQ29

J1 M4 2 1 J1 M4
MF DQ30
M2
1D35V_VGA_S0 OPS
R7910 1KR2J-1-GP MF DQ30
M2
DQ31 DQ31
1

1
121R2F-GP
R7912

1KR2J-1-GP
R7911

1KR2J-1-GP
R7909

121R2F-GP
R7913

FBA_WCK45 D4 FBA_WCK67 D4
FBA_WCK45# WCK01 FBA_EDC4 FBA_WCK67# WCK01 FBA_EDC7
D5 C2 D5 C2
WCK01# EDC0 WCK01# EDC0
C13 C13
FBA_WCK67 P4
EDC1
R13 FBA_EDC6 OPS OPS FBA_WCK45 P4
EDC1
R13 FBA_EDC5
OPS OPS FBA_WCK67# P5
WCK23 EDC2
R2 FBA_WCK45# P5
WCK23 EDC2
R2
2

WCK23# EDC3 WCK23# EDC3

H5GQ2H24AFR-T2C-GP [4] FBA_WCK67 H5GQ2H24AFR-T2C-GP

[4] FBA_WCK67#
[4] FBA_WCK45
[4] FBA_WCK45#

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM3,4 (2/4)
Size Document Number Rev
A2
Starload-SKL-U A00
Date: Thursday, February 18, 2016 Sheet 8 of 13

5 4 3 2 1
 5 4 3 2 1

Main Func = dGPU

D D

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM5,6 (3/4)
Size Document Number Rev
A3
Starload SKL-U A00
Date: Thursday, January 07, 2016 Sheet 9 of 13
5 4 3 2 1
 5 4 3 2 1

Main Func = dGPU

D D

C C

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM7,8 (4/4)
Size Document Number Rev
A3
Starload SKL-U A00
Date: Thursday, January 07, 2016 Sheet 10 of 13

5 4 3 2 1
 5 4 3 2 1

Main Func = dGFX_CORE

DCBATOUT

D D

PC8208 PC8209

1
OPS

1
OPS

2
SCD1U25V2KX-GP
PC8210 PC8214 PC8220
FDMS3600-02-RJK0215-COLAY-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
FDMS3600-02-RJK0215-COLAY-GP
OPS OPS OPS

SC4D7U25V5KX-GP

SC4D7U25V5KX-GP
5V_S0 2 2

1
3 3
4 1 1 4

1
10 10
PR8223 OPS_84.03660.037
9 OPS_84.03660.037
9
2D2R3J-2-GP 7 7 Design Current=33.5A
6 8 8 6
OPS 5 5 79.5A <OCP< 95.4A

2
ZZ.00215.037 ZZ.00215.037
VGA_CORE
RT8812_PVCC
PU8202 PU8204 PL8201

1
PC8202 OPS PC8207 1 OPS 2
SCD1U50V3KX-GP COIL-D22UH-3-GP
2PWR_VGA_CORE_TON_1

1
1

2
68.R2210.20E
OPS PR8216 PT8207 PT8206
DY 2D2R5F-2-GP

18

1
SCD1U25V2KX-GP PU8201
79.33719.L01OPS 79.33719.L01
OPS

PVCC

SE330U2VDM-L-GP
2

2
PWR_VGA_SNUB1
PR8202 PR8201

SE330U2VDM-L-GP
OPS OPS 2 PWR_VGA_CORE_TON PWR_VGA_CORE_UGATE1

1
DCBATOUT 1 2 1 9 2
2D2R2F-GP 499KR2F-1-GP TON UGATE1 DYPC8206
SC330P50V2KX-3GP
PR8203 PR8210
PWR_VGA_CORE_BOOT1 1 2PWR_VGA_CORE_BOOT1_1 1

2
3V3_AON_S0 1 OPS 2 13 1 2
PGOOD BOOT1 0R3J-0-U-GP OPS
100KR2J-1-GP PC8211
OPS SCD1U50V3KX-GP
PWR_VGA_CORE_EN 3 20 PWR_VGA_CORE_PHASE1
[12,13] DGPU_PWROK EN PHASE1

PWR_VGA_CORE_PSI 4 19 PWR_VGA_CORE_LGATE1
PSI LGATE1 DCBATOUT
PR8207 PR8224 OCP setting (current limit ~ 60.3A)
[5] VGA_CORE_VID 1 2 0R2J-2-GP 1 2
OPS OPS
8K45R2F-2-GP OPS should be in DUMMY column.
PC8203 1 SC1KP50V2KX-1GP PWR_VGA_CORE_VID PWR_VGA_CORE_UGATE2 PC8212 PC8213
DY2 5 14 FDMS3600-02-RJK0215-COLAY-GP

1
OPS

1
OPS

2
VID UGATE2

SCD1U25V2KX-GP
FDMS3600-02-RJK0215-COLAY-GP PC8215 PC8224 PC8221
C C

SC10U25V5KX-GP

SC10U25V5KX-GP
PC8201 PR8211
DY 2 2 OPS OPS OPS

SC4D7U25V5KX-GP

SC4D7U25V5KX-GP
PWR_VGA_CORE_RGND 1 2 SCD1U16V2KX-3GP PWR_VGA_CORE_VREF 8 15 PWR_VGA_CORE_BOOT2 1
OPS 2PWR_VGA_CORE_BOOT2_1 1 2 3 3

1
VREF BOOT2 0R3J-0-U-GP OPS 4 1 1 4
PC8216
SCD1U50V3KX-GP 10 10
1

PWR_VGA_CORE_REFIN PWR_VGA_CORE_PHASE2
R2 7
REFIN PHASE2
16 9
7OPS_84.03660.037
OPS_84.03660.037
9
PR8206 R1 6 8
7
20KR2F-L-GP OPS PWR_VGA_CORE_REFADJ 6 17 PWR_VGA_CORE_LGATE2 5
8 6
5
REFADJ LGATE2
1

REFIN_VREF PR8222
2

20KR2F-L-GP
ZZ.00215.037
R3 PWR_VGA_CORE_SS 11 12 PWR_VGA_CORE_VSNS
PU8206
ZZ.00215.037 VGA_CORE
OPS SS VSNS PU8208 PL8202
1

PR8208 PC8205
OPSSC47P50V2JN-3GP PWR_VGA_CORE_RGND
2

1 OPS 2 21 10
GND RGND 1 OPS 2
2KR2F-3-GP COIL-D22UH-3-GP
N16V_GM_B1
2

68.R2210.20E

1
OPS RT8812AGQW-GP Config B

SE330U2VDM-L-GP
1

3V3_AON_S0 PR8215 PT8208

OPS

1
PC8223 2D2R5F-2-GP 79.33719.L01
SC2700P50V2KX-1-GP 74.08812.073 OPS
DY
2

2
C

2
PWR_VGA_CORE_RGND PR8258 PWR_VGA_SNUB2
10KR2J-3-GP

1
PC8218
OPS SC330P50V2KX-3GP
2

R4+R5 DY

2
1 PR8257 2 PWR_VGA_CORE_PSI
[5] VGA_CORE_PSI
1

PR8209 0R0402-PAD
N16V_GM_B1 OPS
1

18KR2F-GP PC8226
DY
2
SCD1U25V2KX-GP

PC8204 PR8259
Config B SCD01U50V2KX-1GP
DY 10KR2J-3-GP
2

DY
1
PWR_VGA_CORE_RGND

PWR_VGA_CORE_RGND

Design Current=33.5A VGA_CORE

2

56.65A <OCP< 66.7A

1
Component N15V-GM-S N16V-GM-B1 PR8212
B Config D Config B 100R2F-L1-GP-U B
Check
value OPS

2
27K 20K 1 PR8221 2
R1 (PR8222) 64.27025.6DL VGACORE_VDD_SENSE_1 [2]

1
64.20025.6DL 3D3V_VGA_S0
0R0402-PAD

1
PC8222
R2 (PR8206) 7.5K 20K
PR8256
OPS PC8219
DY SC47P50V2JN-3GP
64.75015.6DL DY

2
64.20025.6DL SC47P50V2JN-3GP
1 2 PWR_VGA_CORE_EN
PWR_VGA_CORE_EN [12]

2
0 2K 1KR2J-1-GP
R3 (PR8208)
63.R0034.1DL 64.20015.6DL
1 PR8220 2
2
SCD1U25V2KX-GP

7.87K 18K PC8225 VGACORE_GND_SENSE_1 [2]

1
R4+R5 (PR8209) 64.78715.6DL 64.18025.6DL
PR8260 DY PC8217
0R0402-PAD
DY

1
1

5.6nF 2.7nF SC47P50V2JN-3GP

C (PC8223) [12,13] DGPU_PWR_EN 1 DY 2 PR8213

2
78.56222.2FL 78.27224.2FL
100R2F-L1-GP-U
13KR2F-GP OPS
78.56222.2FL:OBS REASON: 50V is more popular, chage to 78.56224.2FL

2
For tuning VGA_CORE sequence.

I/P cap: 10U 25V K0805 X5R/ 78.10622.51L

Inductor:CHIP CHOKE 0.22UH PCMC104T-R22/ 1mohm/ Isat =60A rms /68.R2210.10C
O/P cap: CHIP CAP EL 330U 2.5V M6.3*4.4 Chemi-con/79.3371V.6CL
H/S: SIRA14DP-T1-GE3 / 6.8mohm/8.5mOhm@4.5Vgs/ 84.A14DP.037
L/S:SIRA06DP-T1-GE3 / 2.75mohm/3.5mOhm@4.5Vgs/ 84.SRA06.037

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RT8812_VGACORE
Size Document Number Rev
A2
Starload-SKL-U A00
Date: Thursday, February 18, 2016 Sheet 11 of 13
5 4 3 2 1
 5 4 3 2 1

Main Func = dGPU dGPU Power Discharge Circuit

[DG-07158-001 Rev03]Power up sequence:
3.3V ==> NVVDD (VGA_CORE) ==> PEX_VDD (1.05V) ==> FBVDD/Q (1.35V)
3D3V_AUX_S5
1D05V_VGA_S0
1D05V_VGA_S0

3D3V_S0
3D3V_S0 to 3V3_AON_S0 and 3D3V_VGA_S0 1 OPS 2 1D05V_VGA_EN#

3V3_AON_S0 3D3V_VGA_S0 PR8307

3D3V_VGA_S0
D G S
U8301 100KR2J-1-GP
3D3V_VGA_S0: 3A @ 3.3V 3D3V_VGA_S0

1
GC6 2.0 only DY C8307 5V_S0 4 13
SC1U10V2KX-1GP VBIAS OUT1#13 PQ8301 PR8306
OUT1#14
14
3D3V_VGA_CT_1 C8302 1
R8301
OPS OPS
12 2 2N7002KDW-GP 100R2J-2-GP

2
CT1
1
IN1#1 3V3_AON_S0 SC470P50V2KX-3GP
OPS 1 2
84.2N702.A3F
2 8 NON_GC6

2
IN1#2 OUT2#8 2nd = 84.2N702.E3F
1 PR8330 2 GPIO5_GC6_PWR_EN_R 3 9
[5] GPIO5_GC6_PWR_EN
0R0402-PAD 3V3_MAIN_EN is an open-drain GPIO.
EN1 OUT2#9
CT2
10 3V3_AON_CT_2
C8306
3V3_AON_S0 0R6J-3-GP
3rd = 75.00601.07C S G D Need to fine tune.

1
3D3V_S0 6 OPS 4th = 84.DMN66.03F
IN2#6

1
3D3V_VGA_S0 3V3_AON_S0

SC470P50V2KX-3GP
DY C8309 7 11 OPS
IN2#7 GND
5 15

SC1U10V2KX-1GP

2
EN2 GND

1
DY C8305 OPSC8301 1D05V_VGA_EN 1D05V_VGA_S0_DISCHG

2
2

1
C8304

SC1U10V2KX-1GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP
R8306 G5016KD1U-GP OPS

2
D D
NON_GC6 0R2J-2-GP

2
1
074.05016.0093
3D3V_AUX_S5

[11,13] DGPU_PWR_EN
1 PR8331 2 DGPU_PWR_EN_R
PR8315
PWR_VGA_CORE_EN#
VGA_CORE
0R0402-PAD
2 OPS 1
VGA_CORE
1

DY C8310 Need to fine tune.

SC1U10V2KX-1GP 100KR2J-1-GP
2

1
PQ8305 PR8309
OPS 3D3V_AUX_S5
2N7002KDW-GP
84.2N702.A3F
100R2J-2-GP
OPS PR8328
1D35V_VGA_S0

2
2nd = 84.2N702.E3F 2 OPS 1 1D35V_VGA_EN#
3D3V_VGA_S0
3rd = 75.00601.07C
100KR2J-1-GP
Need to fine tune.
4th = 84.DMN66.03F VGA_CORE_DISCHG

1
PQ8308 PR8329
[11] PWR_VGA_CORE_EN OPS
2N7002KDW-GP 100R2J-2-GP
3D3V_AUX_S5 84.2N702.A3F OPS
PR8317
3V3_AON_S0

2
2nd = 84.2N702.E3F
2 OPS 1 DGPU_PWR_EN# 3rd = 75.00601.07C
3V3_AON_S0
Need to fine tune. 4th = 84.DMN66.03F 1D35V_VGA_S0_DISCHG
100KR2J-1-GP

1
1D35V_VGA_EN
PQ8306 PR8316
2N7002KDW-GP OPS 100R2J-2-GP
84.2N702.A3F OPS Discharge schematic change (solution different)

2
2nd = 84.2N702.E3F
2010915 Alden chiang modify
3rd = 75.00601.07C
4th = 84.DMN66.03F 3V3_AON_S0_DISCHG

[11,13] DGPU_PWR_EN
3D3V_AUX_S5

PR8319
GPIO5_GC6_PWR_EN#
3D3V_VGA_S0
2 OPS 1
3D3V_VGA_S0

100KR2J-1-GP
Need to fine tune.

1
PQ8307 PR8318
2N7002KDW-GP OPS 100R2J-2-GP
84.2N702.A3F OPS

2
C 2nd = 84.2N702.E3F C

3rd = 75.00601.07C
4th = 84.DMN66.03F 3D3V_VGA_S0_DISCHG

[5] GPIO5_GC6_PWR_EN

3D3V_S0
RT8068A for 1D05_VGA Design Current = 2.1A
PG8301
2 1

GAP-CLOSE-PWR PU8301
Cyntec 5 x5 x 3mm
DCR: 13~14mOhm
1D05V_VGA_S0
3D3V_VGA_S0 PG8302 1D05V_VGA_S0
Idc : 7A , Isat : 11A

Note:ZZ.08068.A4301
2 1 PWR_1D05V_PVDD 10 1 1D05V_PWR
PR8301 PVIN LX#1
PL8301
GAP-CLOSE-PWR 1OPS 2 PWR_1D05V_SVIN 9 2 PWR_1D05V_PHASE PG8304
PVIN LX#2
1

PG8303 2D2R2F-GP 1OPS 2 2 1

1
PR8310 2 1 8 3
PC8301 SVIN LX#3 IND-2D2UH-161-GP-U
1KR2J-1-GP OPS GAP-CLOSE-PWR

1
GAP-CLOSE-PWR SC1U6D3V2KX-GP 7 PC8303 PC8304 PG8305
GC6_20 R1

2
NC#7

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP
PWR_1D05V_EN PR8303 PC8305
EN OPS OPS
5 2 1
2

SC22P50V2JN-4GP
R8305 PC8307 PC8306 6 38K3R2F-GPOPS

2
FB

1
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
1 2 1D05V_VGA_EN OPS DY PWR_1D05V_PGOOD 4 GAP-CLOSE-PWR
[11,13] DGPU_PWROK PGOOD
11 OPS OPS PG8306
2

2
0R2J-2-GP GND
2 1

2
NON_GC6 3V3_AON_S0 RT8068AZQWID-GP-U
2

PWR_1D05V_FB GAP-CLOSE-PWR
DY C8308 PG8307
SCD1U16V2KX-3GP
74.08068.A43 2 1
1

1
PR8304
Vo=0.6*(1+(R1/R2)) R2

1
DY PC8312 GAP-CLOSE-PWR
100KR2F-L1-GP PR8302OPS SC680P50V3KX-1-GP
OPS

1 2
1D05V_VGA_EN 1 PR8308 2 51KR2F-L-GP PWR_1D05V_FB_R

2
0R0402-PAD PR8313
PR8320

2
1

PC8302 18KR2F-GP
1D05V_VGA_S0_PWRGD
DY
DY SC22P50V2GN-GP
1 OPS 2
2

2
0R2J-2-GP

DCBATOUT PWR_DCBATOUT_1D35V
1D35V_VGA_S0 1D35V_PWR 1D35V_VGA_S0 B

PG8314
1 2 PG8308
1 2
GAP-CLOSE-PWR-3-GP
PG8315 GAP-CLOSE-PWR-3-GP
1 2
PG8310
GAP-CLOSE-PWR-3-GP 1 2
PG8316
1 2 GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP PG8309
PG8317 1 2
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG8311
1 2

SY8288RAC for 1D35V GAP-CLOSE-PWR-3-GP

PG8312
PWR_DCBATOUT_1D35V 1 2
3V3_AON_S0
GAP-CLOSE-PWR-3-GP

PG8318
PC8310 PC8315 PC8309 Cyntec 5 x5 x 3mm Design Current=6.8A
1

PR8311 1 2
1

DY DCR: 11~12mOhm OCP=8A

SC10U25V5KX-GP

SC10U25V5KX-GP

SCD01U50V2KX-1GP

100KR2F-L1-GP GAP-CLOSE-PWR-3-GP
OPS
PWR_1D35V_LDO_P5

Idc : 8.5A , Isat : 14A

1

PC8317
2

1D35V_PWR PG8319
SC2D2U10V3KX-1GP PL8302
0R3F-1-GP-U PC8319
2

1 2
PR8324 SCD1U25V2KX-GP
2

PWR_1D35V_BOOT 1 2 PWR_1D35V_BOOT_R 1 2 1 2 GAP-CLOSE-PWR-3-GP

PG8320

GAP-CLOSE-PWR-3-GP
TP8301 IND-D68UH-40-GP
PU8302

1
TPAD14-OP-GP 1D35V_PGOOD 1 2
75.00054.E7D 1 1 PR8321 2 PWR_1D35V_PGOOD

1
D8301 PC8320 PC8321 PC8311 PC8313 PC8314

PG8313
17 6 PWR_1D35V_PHASE GAP-CLOSE-PWR-3-GP

SCD1U16V2KX-3GP
1 0R0402-PAD VCC LX#6

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
2

2
[4,5,13] GC6_FB_EN 19

SC22U6D3V5MX-2GP

2
LX#19
1D35V_VGA_EN 20
GC6_20 1 PR8322 2 PWR_1D35V_EN

2
3 LX#20
1

2
SCD1U16V2KX-3GP
PC8316

IN#2 PWR_1D35V_PGOOD
2 0R0402-PAD DY 3
IN#3 NC#10
10 PWR_1D35V_VFB1
4 12
IN#4 NC#12 PWR_1D35V_LDO_P5
2

BAT54C-7-F-3-GP
5 16
IN#5 NC#16
1

PWR_1D35V_BOOT 1
1 2 BS
1

9 PR8327
R8303 PG
11 7 15KR2F-GP PC8308
0R2J-2-GP EN GND SC330P50V2KX-3GP
PR8323 1 DY PWR_1D35V_IMAX
1

2 13 8
NON_GC6
2

ILMT GND
R8304 0R2J-2-GP 14 18
2

FB GND
1D05V_VGA_S0_PWRGD 1MR2J-1-GP
15
BYP GND
21 R1
3D3V_S0
GC6_20
SY8288RAC-GP
2

A Vo=0.6x(1+R1/R2) A
1 PR8325 2
[DG-07158-001 Rev03] =0.6x(1+150/120)
1

0R0402-PAD
PC8318 =1.35V
OCP setting PWR_1D35V_BYP SC1U10V2KX-1GP
2

High 16A
PWR_1D35V_VFB
Float 12A
1D35V (solution different) Low 8A
1

2010915 Alden chiang modify PR8326

R2
12KR2F-L-GP

<Core Design>
2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DISCRETE VGA POWER

Size Document Number Rev
A1 Starload-SKL-U A00
Date: Thursday, February 18, 2016 Sheet 12 of 13
5 4 3 2 1
 5 4 3 2 1

Main Func = Connector

GPU3
D GPU2 D
A1 A1 B1 B1
A2 A2 B2 B2 CLK_PCIE_VGA# [2] DCBATOUT A1 A1 C1 C1
[2] dGPU_RXN_C_CPU_TXN1 A3 A3 B3 B3 CLK_PCIE_VGA [2] A2 A2 C2 C2
[2] dGPU_RXP_C_CPU_TXP1 A4 A4 B4 B4 A3 A3 C3 C3
A5 A5 B5 B5 dGPU_RXN_C_CPU_TXN3 [2] A4 A4 C4 C4
[2] dGPU_RXN_C_CPU_TXN0 A6 A6 B6 B6 dGPU_RXP_C_CPU_TXP3 [2] A5 A5 C5 C5
[2] dGPU_RXP_C_CPU_TXP0 A7 A7 B7 B7 A6 A6 C6 C6
A8 A8 B8 B8 dGPU_RXN_C_CPU_TXN2 [2]
[2] CLKREQ_PEG#0 A9 A9 B9 B9 dGPU_RXP_C_CPU_TXP2 [2] B1 B1 D1 D1
A10 A10 B10 B10 B2 B2 D2 D2
B3 B3 D3 D3
[11,12] DGPU_PW R_EN C1 C1 D1 D1 DGPU_HOLD_RST# [2] B4 B4 D4 D4
C2 C2 D2 D2 DGPU_PW ROK [11,12] B5 B5 D5 D5
[5] OVER_CURRENT_P8# C9 C9 D9 D9 B6 B6 D6 D6
[4,5,12] GC6_FB_EN C10 C10 D10 D10 PLT_RST# [2]
3D3V_S0 P1 P1 N1 N1
E1 E1 F1 F1 GPU_EVENT# [5] 5V_S0 P2 P2
[5] SML1_SMBDATA E2 E2 F2 F2 P3 P3 NP1 NP1
[5] SML1_SMBCLK E3 E3 F3 F3 CPU_RXN_C_dGPU_TXN3 [2] P4 P4 NP2 NP2
E4 E4 F4 F4 CPU_RXP_C_dGPU_TXP3 [2] NP3 NP3
[2] CPU_RXN_C_dGPU_TXN1 E5 E5 F5 F5
[2] CPU_RXP_C_dGPU_TXP1 E6 E6 F6 F6 CPU_RXN_C_dGPU_TXN2 [2]
E7 F7 UNI-CONN28-6R-GP-U
E7 F7 CPU_RXP_C_dGPU_TXP2 [2]
[2] CPU_RXN_C_dGPU_TXN0 E8 E8 F8 F8 020.F0588.0028
[2] CPU_RXP_C_dGPU_TXP0 E9 E9 F9 F9
E10 E10 F10 F10 3D3V_AUX_S5

NP1 NP1 N1 N1
C NP2 C
NP2
NP3 NP3

UNI-CONN48-6R-GP-U1
020.F0581.0048

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU_Connector
Size Document Number Rev
A3
Starload-SKL-U A00
Date: Thursday, February 18, 2016 Sheet 13 of 13
5 4 3 2 1
 5 4 3 2 1

Main Func = UnusedParts

D D

2015/11/18 Modify

HS1 HS2

H5 H1 H2 H3 H4 STFSR158R113H62-GP STFSR158R113H62-GP
HOLE335R178-GP HOLE335R178-GP HOLE335R229-GP HOLE335R178-GP HOLE335R178-GP

NP1
1

NP1
1
1

1
C C

Main Func = EMICapacitors

Mind the voltage rating of the caps.

DCBATOUT
1

EC9701 EC9702 EC9703 EC9704 EC9705 EC9706

DY
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP
2

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

UNUSED PARTS/EMI Capacitors

Size Document Number Rev
A3
Starload-SKL-U A00
Date: Thursday, January 07, 2016 Sheet 14 of 13
5 4 3 2 1