Lecture 5

EE214 Technology: fT and Intrinsic Gain

gm/ID Design Methodology

Boris Murmann
Stanford University
murmann@stanford.edu
Copyright © 2004 by Boris Murmann

B. Murmann EE 214 Lecture 5 (HO#8) 1

 Overview
• Reference
– F. Silveira et. al. "A gm/ID based methodology for the design
of CMOS analog circuits and its application to the synthesis
of a silicon-on-insulator micropower OTA," IEEE Journal of
Solid-State Circuits, Sept. 1996, pp. 1314-1319.

• Introduction
– Today, we'll continue to characterize the EE214 technology.
The two remaining figures of merit that are of interest to us
as circuit designers are fT and intrinsic device gain. In
conclusion, we find that VOV is not "directly" related to either
performance metric we care about. Hence, we switch
towards a strategy called "gm/ID design methodology", in
which gm/ID, rather than VOV is used directly as a central
design variable.

B. Murmann EE 214 Lecture 5 (HO#8) 2

 Performance Metrics of Interest

• Transconductor Efficiency
gm
ID

• Transit Frequency
gm
ωT =
C gs

• Intrinsic Gain
g m ro

B. Murmann EE 214 Lecture 5 (HO#8) 3

 fT Simulation

$ ft vs. gate overdrive

$ Boris Murmann, September 2004

.param gs=1

vgs g 0 dc 'gs'
mn1 g g 0 0 nch214 L=0.35um W=10um

.op
10/0.35
.dc gs 0.4V 1.2V 10mV

.probe ov = par('gs-vth(mn1)')
.probe ft = par('1/2/3.142*gmo(mn1)/(-cgsbo(mn1))')

.options post brief dccap

.lib './ee214_hspice.txt' nominal
.end

B. Murmann EE 214 Lecture 5 (HO#8) 4

 Result
NMOS W/L=10/0.35
30
EE214 technology
25 Long Channel Fit

20
f T [GHz]

15

10

0
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
VOV [V]
1 3 µVOV
Long Channel: fT =
2π 2 L2

B. Murmann EE 214 Lecture 5 (HO#8) 5

 Observations - fT

• Again, a simple long channel model doesn't do a very good job

– Large fT discrepancy in weak inversion and in strong
inversion, at large VOV
• The reasons for these discrepancies are exactly the same as
the ones we came across when looking at gm/ID
– Bipolar action in weak and moderate inversion
– Short channel effects at large VOV
• Less gm, hence lower gm/Cgs
• Same conclusion, we won't be able to make good predictions
with a simple long channel relationship

B. Murmann EE 214 Lecture 5 (HO#8) 6

 Another Look at gm/ID·fT
NMOS W/L=10/0.35

160

140 EE214 technology

Long Channel
120
gm/I D*f T [GHz/V]

100

80 Sweet spot (?)

60

40 Short channel
Long channel predicts effects
20 too much gm/ID
0
-0.1 0 0.1 0.2 0.3 0.4 0.5
VOV [V]

gm 1 3µ
Long Channel: ⋅ fT =
ID 2π L2

B. Murmann EE 214 Lecture 5 (HO#8) 7

 Intrinsic Gain Simulation
$ gm*ro vs. vds
$ Boris Murmann, September 2004

$ vt measured using .op run

.param vt1=580m
.param vt2=600m

mn1 d g1 0 0 nch214 L=0.35um W=10um

mn2 d g2 0 0 nch214 L=0.40um W=10um
vg1 g1 0 dc 'vt1+0.2'
vg2 g2 0 dc 'vt2+0.2' VGS=Vt +200mV
vd d 0 dc 1

.op
.dc vd 0 3.3V 10mV
.probe av1 = par('gmo(mn1)/gdso(mn1)')
.probe av2 = par('gmo(mn2)/gdso(mn2)')

.options post brief

.lib './ee214_hspice.txt' nominal
.end

B. Murmann EE 214 Lecture 5 (HO#8) 8

 Intrinsic Gain Plot (VOV=200mV)
NMOS W=10um NMOS W=10um
120 120
L=0.35um L=0.35um
L=0.4um L=0.4um
100 100

80 80
Long Channel
gmro=const.
gm*ro

gm*ro
60 60

40 40

20 20

0 0
0 1 2 3 0 0.2 0.4 0.6
VDS [V] VDS [V]

B. Murmann EE 214 Lecture 5 (HO#8) 9

 Observations – Intrinsic Gain
• The gm·ro product shows a strong dependence on VDS bias
– Mostly due to varying ro, (see lecture 2, slide 20)
• Also, there is a very smooth transition from triode to something
close to forward active behavior
– Long channel model would have predicted an abrupt change
to large intrinsic gain at VDS = VOV
– From the plots, we see that we need VDS > 1.5…3 VOV to get
appreciable gain
• At high VDS, ro and thus gm·ro decrease due to SCBE (substrate
current induced body-effect)
– Highly technology dependent, and usually not present in
PMOS devices
– If you are interested in more details, please refer to EE316
or a similar course

B. Murmann EE 214 Lecture 5 (HO#8) 10

 Why care about VOV?
• By now, it should be clear that VOV is not a very useful design
variable
– There is no simple expression that accurately links either
gm/ID, ft or gm·ro to VOV
– VOV does not even clearly define the onset of forward active
operation ("Vdsat")
• The primary variables we care about from a design and
performance perspective are gm/ID, ft and gm·ro
– So why not work exclusively with these?
– In case we need a rough estimate for "Vdsat", we can always
use Vdsat ≅ 2/(gm/ID)
• E.g. gm/ID=10V-1 ⇒ Vdsat ≅ 200mV
• Let's go back to a design example using a simple CS stage

B. Murmann EE 214 Lecture 5 (HO#8) 11

 Design Example 1
2V

RL
Vo

CL
vi

VB

• Given specifications
– DC gain=-2, ID ≤ 2mA, f-3dB=100MHz, CL=10pF
– Make transistor as small as possible

B. Murmann EE 214 Lecture 5 (HO#8) 12

 Hand Calculations (1)

• We know that in our technology gm·ro ~> 40, even for minimum
channel length. Hence, for a small signal gain of 2, the output
impedance of the amplifier will be dominated by RL
– OK to use L=Lmin=0.35µm
• We can now find RL and gm simply as
1 1 1 1
f −3dB = ⇒ RL = = 159Ω
2π RLC L 2π 100MHz ⋅10 pF
2
ADC = − g m RL = −2 ⇒ gm = = 12.6mS
159Ω

• If we use all the available current, we have

g m 12.6mS 1
= = 6.3
ID 2mA V

B. Murmann EE 214 Lecture 5 (HO#8) 13

 Hand Calculations (2)
• How about using less current?
• Recall that for fixed transconductance W ~ 1/VOV ~ gm/ID
– Using less current means larger gm/ID and thus larger device
• But specifications said to minimize device size
• As a last step, we need to determine the actual device width
– For design implementation and verification with Spice
• Using long channel equations will be very inaccurate
• Solution: Sizing chart
– Plot of ID/W as a function of the design variable gm/ID
– Can generate this chart once for several channel lengths
and use it throughout the design process

B. Murmann EE 214 Lecture 5 (HO#8) 14

 Current Density Chart
NMOS L=0.35um
90

80

70

60
I D/W [uA/um]

50

40

30

20

10

0
0 5 10 15 20 25
gm/I D [1/V]

B. Murmann EE 214 Lecture 5 (HO#8) 15

 A Better Current Density Chart
NMOS L=0.35um
35

30

25
23µA/µm
I D/W [uA/um]

20

15

10
(2/6.3)V=317mV
5

0
100 150 200 250 300 350 400
2/(gm/I D) [mV]

B. Murmann EE 214 Lecture 5 (HO#8) 16

 Spice Verification

ID 2000
• So, the device width is W=
ID
= µm = 87 µm
23
W

2V
• How to determine VB?
159Ω
• Adjust VB in Spice until gm/ID=6.3V-1
Vo
• Good initial guess
– VB ≅ Vt+2/(gm/ID) ≅ 600mV+317mV 87/0.35
10pF
• Fortunately, we'll find a way to build vi
circuits without VB VB
– No need to iterate in practice…

B. Murmann EE 214 Lecture 5 (HO#8) 17

 DC Operating Point

**** mosfets
subckt beta 60.5664m
element 0:mn1 gam eff 894.1238m
model 0:nch214 gm 12.7994m
region Saturation
gds 223.6427u
id 2.0147m
gmb 2.7928m
ibs 0.
ibd 0. cdtot 112.7289f
vgs 845.0000m cgtot 154.6957f
vds 1.6797 cstot 294.9323f
vbs 0. cbtot 300.7032f
vth 569.7473m cgs 107.6797f
vdsat 201.1145m cgd 19.7903f

g m 12.8mS 1
= = 6.37
I D 2.01mA V

B. Murmann EE 214 Lecture 5 (HO#8) 18

 AC Response
7

5.87dB=1.97
6

5
|vo/vi| [dB]

0 0 1 2
10 10 10
f [MHz]

B. Murmann EE 214 Lecture 5 (HO#8) 19

 Observations and Remarks
• The design is essentially "dead on" target!
– No need for any Spice tweaking
• We accomplished this by focusing on a performance related
parameter (gm/ID) in the design process
– Note that strictly speaking, device width is not a design
parameter, since it does not directly relate to any of the
specs that we were given!

Specifications
Design
gm, gm/ID, f T, ...

Determine device sizes

Implementation/
Verification Simulation results

B. Murmann EE 214 Lecture 5 (HO#8) 20

 gm/ID Design Methodology
• Determine gm
– Based on circuit and specifications
• Pick L
– Short channel → high fT, long channel → high ro, gm·ro
• Pick gm/ID
– Based on speed, power or other constraints
• Determine bias (VB or ID for current source bias)
– Adjust VB to yield desired gm/ID
– For current source bias, we can directly find ID=gm/(gm/ID)
• Determine W
– Using current density chart or Spice

B. Murmann EE 214 Lecture 5 (HO#8) 21