Voltage-Series Feedback

Two examples of the voltage-series topology are considered in this

section:
(a) The FET common drain amplifier (source follower), and
(b) The bipolar transistor common-collector amplifier (emitter
follower).
The FET Source Follower
The circuit is given in Fig. 13-12a.

For AC analysis, all

capacitors (dc blocking
and bypass) are
considered short
circuited and the biasing
voltages should be
grounded as shown in
Fig. 13-12.1.
 In Fig. 13-12.1 the terminals G and S are used for input and D and S
are used for output.
The feedback is the voltage Vf across R, and the sampled signal is the
output voltage Vo across R.
Hence, this is the case of voltage-series feedback.
We must now draw the basic amplifier without feedback where all
grounds are eliminated.
To find the input circuit, set Vo=0 (the output loop is shorted) as shown
in Fig. 13-12.2(a).

Hence Vs appears
directly between
G and S as shown
in Fig. 13-
12.2(b).
To find the Hence R appears only in the
output circuit, output loop.
set Ii=0 (the
input loop is
opened) shown
in Fig. 13-
12.3(a).

Finally, we obtained Fig. 13-12(b) by adding Fig. 13-12.2 (b) and

Fig. 13-12.3(b).
If the FET is
replaced by its
low-frequency
model, the
result is Fig.
13-12(c).

From the figure Vf and Vo are equal, and b= Vf / Vo =1.

This topology stabilizes voltage gain. AV is calculated by inspection of
fig. 13-12c. Since without feedback Vi=Vs, then
Vo g mVs rd R R
AV    (13  39) where,   g m rd
Vi (rd  R)Vs rd  R
R rd  (1   ) R
Thus, D  1  bAV  1   (13  40)
rd  R rd  R
A R
and AVf  V  (13  41)
D rd  (1   ) R
The input impedance of an FET is infinite, Ri=, and hence Rif=RiD=.
We are interested in finding the output resistance seen looking into the
FET source S. Then, Ro=rd.
Hence R is considered an external load RL. Thus RL= R. Then

RL 
AV  ; hence Av  lim AV  lim 
rd  RL RL  RL  rd / RL  1
Ro rd
We know for voltage - series topology : Rof   (13  42)
1  bAv 1  

R ' Rrd rd  R rd R
'
Again, Rof  o   (13  43)
D R  rd rd  (1   ) R rd  (1   ) R

Since three assumptions are satisfied, the above results are exact for
voltage-series feedback topology.
 The Emitter Follower
The circuit is given in Fig. 13-13a.
Equivalent circuit for ac analysis is shown in Fig. 13-13.1.
In Fig. 13-13.1 the terminals B and E are used for input and C and E
are used for output.
The feedback is the voltage Vf across Re, and the sampled signal is
the output voltage Vo across Re.

Hence, this is the

case of voltage-
series feedback.
We must now draw
the basic amplifier
without feedback
where all grounds
are eliminated.
To find the input circuit, set Vo=0 (the output loop is shorted) as shown
in Fig. 13-13.2(a).
Hence Vs in series
with Rs appears
between B and E.
To find the output
circuit, set Ii=0
(the input loop is
opened) shown in
Fig. 13-12.3(a). Hence R appears only in the
output loop.
Finally, we obtained Fig. 13-13(b) by adding Fig. 13-13.2 (b) and
Fig. 13-13.3(b).

If the transistor is replaced by its low-frequency approximate model,

the results is Fig. 13-13(c).
From this figure Vo=Vf and b=Vf/Vo=1.
This topology stabilizes the voltage gain. AV
is calculated by inspection of Fig. 13-13c.
Since Rs is considered as part of the amplifier
then Vi=Vs, and
Vo h feIb Re h feRe
AV    (13  44)
Vi Vs Rs  hie
h feRe Rs  hie  h feRe
D  1  bAV  1   (13  45)
Rs  hie Rs  hie

AV h feRe Rs  hie h feRe

AVf    (13  46)
D Rs  hie Rs  hie  h feRe Rs  hie  h feRe

For hfeRe>>Rs+hie, AVf1, as it should be for an emitter follower.

The input resistance without feedback is Ri=Rs+hie from Fig. 13-13c.
 Rs  hie  h feRe
Hence, Rif  Ri D  ( Rs  hie )
Rs  hie
Rif  Rs  hie  h feRe (13  47)

We are interested in the resistance seen looking into the emitter.

Hence Re is considered as an external load i.e. RL=Re.
From Fig. 13-13c, we are looking into a current Av  lim AV  
source Ro= and RL 
Thus for this voltage-series topology, Ro 
Rof   (13  48)
we get 1  bAv 
The indeterminacy in Eq. (13-48) may be resolved by first evaluating
Rof’ =and then going to the limit Re.
Thus, since Ro’ =Re.
' Ro' Re ( Rs  hie )
Rof   (13  49)
D Rs  hie  h feRe
 ' Rs  hie
and Rof  lim Rof  (13  50)
Re  h fe

It is seen form the above equations that the feedback

desensitizes voltage gain with respect to changes in hfe
and that it increases the input resistance and decreases
the output resistance.
The forgoing expressions for AVf, Rif and Rof are based on
the assumption of zero forward transmission through the
feedback network.
Since there is such forward transmission because the
input current passes through Re in fig. 13-13a, these
expressions are only approximately true.
 A Voltage-Series Feedback Pair
Fig. 13-14 shows two cascaded stages whose voltage gains
are AV1, and AV2.
The output of the second stage is
returned through the feedback
network R1R2 in opposition to the
input signal Vs. Clearly, then this
is a case of voltage-series negative
feedback.
The first basic assumption is not strictly satisfied for the
circuit of Fig. 13-14a because I’ represents transmission
through the feedback network from input to the output.
We shall neglect I’ compared with I on the realistic
assumption that the current gain of the second stage is
much larger than unity.
The input of the basic circuit without feedback is found by setting
Vo=0 and hence R2 appears in parallel with R1 as shown in Fig. 13.14.2
(a) and (b).

The output of the

basic amplifier
without feedback
is found by
opening the input
loop (set I’=0) and
hence R1 is placed
in series with R2 as
shown in Fig.
13.14.3 (a) and
(b).
Finally, we obtained Fig. 13-14(b) by adding Fig. 13-14.2 (b) and
Fig. 13-14.3(b).

According to Fig. 13-14b, the series feedback voltage Vf across

R1 in the output circuit. Thus,

V R
f
b  1
Vo R  R
1 2
Second-Collector to First-Emitter Feedback Pair
The circuit of Fig. 13-15 shows a two-stage amplifier
which makes use of voltage-series feedback by connecting
the second collector to the first emitter through the voltage
divider R1R2.
Capacitors C1, C2 (coupling), C5, and C6 are dc blocking
capacitors, and capacitors C3 and C4 are bypass capacitors
for the emitter bias resistors.

All these capacitances

represent negligible
reactances (short-circuited)
at the frequencies of
operation of this circuit.
Example: (i) Identify the topology of
the feed back amplifier of Fig. 13-15,
and (ii) Calculate AVf, Rof, and Rif for
the amplifier of Fig 13-15. Assume
Rs=0, hfe=1.1K, hre=hoe=0, and
identical transistors.
Solution:
(i) Fig. 13-15 shows two BJT common-emitter cascaded
stages.
The output of the second stage is returned through the
feedback network R1R2 in opposition to the input signal Vs.
The feedback signal is voltage. Thus, this is a case of
voltage-series negative feedback.
(ii) first calculate the overall voltage gain without feedback
from AV= AV1AV2.
The effective load RL1’ of transistor Q1 is
' R
RL 1 c1 Rb21 Rb22 hie  10 47 33 1.1 K  942 
The effective load RL2’ of transistor Q2 is
' R
RL 2 c 2 ( R1  R2 )  4.7 (0.1  4.7)K  2.37 K
The effective emitter impedance Re1 of transistor Q1 is
Re1  R1 R2  0.1 4.7 K  0.098K  98
The effective emitter impedance Re2 of transistor Q2 is zero (i.e. Re2=0).

Generally, the gain of a common-

emitter amplifier is as follows:

Vi  h feRL
AV  
Vo hie  (1  h fe ) Re
Thus, the voltage gain for the first stage amplifier of Q1 can be obtained
as follows: '
V1  h R
fe L1  50  0.942
AV 1     7.72
Vi hie  (1  h fe ) Re1 1.1  51 0.098
Similarly, the voltage gain for the first stage amplifier of Q2 can be
obtained as follows:
 h R ' h R '
  fe L2   502.37  108
V fe L2
A  o
V 2 V h  (1 h )R h 1.1
1 ie fe e2 ie
Hence, the voltage gain AV of the two stages in cascade without
feedback is V
A  o  A A  7.72108  834
V V V1 V 2
i
R
b  1  100  1
The feedback factor of Fig. 13-15 is as follows: R  R 4800 48
1 2
834
Thus: AV b   17.4
48
The return difference and gain with feedback is obtained as follows:
AV 834
D  1  AV b  18.4; AVf    45.4
D 18.4

The input resistance without external feedback is:

Ri  hie  (1  h fe ) Re1  1.1  51 0.098  6.1K

Hence, the input resistance with feedback is obtained as follows:

Rif  Ri D  (6.1)(18.4)  112 K

The output resistance without external feedback is:

Ro'  RL
'  2.37 K
2
Hence, the output resistance with feedback is obtained as follows:
' Ro' 2.37
Rof   K  129
D 18.4
 Current-Series Feedback
Transistor Configuration
The circuit of transistor configuration as current
series feedback is given in Fig. 13-16a.
The feedback signal is the voltage Vf across Re
and the sampled signal is the load current Io.
Hence, this is a case of current-series feedback.
Although Io is proportional to Vo, it is not
correct to conclude that this is a voltage-series
feedback.
Thus, if the output signal is taken as the voltage
Vo, then
V  I R R Since b is now a function of the load
b  f  o e  e RL, the third basic assumption given in
Vo IoR R
L L section 13-3 is violated.
The input circuit of the amplifier without
feedback is obtained by opening the output
loop (Io=0).
Hence Re must appear in the input side.
Similarly, the output circuit is obtained by
opening the input loop (Ii=0), and this places
Re also in the output side.
The resulting equivalent circuit is given in Fig. 13-16b.

The circuit of Fig. 13-16b

represents the basic amplifier
without feedback, but taking the
loading of the b network into
account.
 If the transistor of Fig. 13-16(b) is replaced by its low-frequency
approximate model, the results is Fig. 13-16(c).
Since the feedback voltage Vf V f  I o Re
appears across Re in the output b     Re (13  52)
Io Io
circuit, then from Fig. 13-16c
Since the input signal Vi
without feedback is the I o  h feI b  h fe
Vs of the Fig. 13-16c, GM    (13  53)
Vi Vs Rs  hie  Re
then
h feRe Rs  hie  (1  h fe ) Re
D  1  bGM  1   (13  54)
Rs  hie  Re Rs  hie  Re
 GM  h fe Rs  hie  Re
GMf  
D Rs  hie  Re Rs  hie  (1  h fe ) Re
 h fe
GMf  (13  55)
Rs  hie  (1  h fe ) Re
If (1+hfe)Re>>Rs+hie, and since hfe>>1, then GMf-1/Re, in agreement
with GMf1/b. If Re is stable resistor, the transconductance gain with
feedback is stabilized (desensitized).
The load current is given by
 h feVs Vs
I o  GMf Vs   (13  56)
Rs  hie  (1  h fe ) Re Re

Under the conditions (1+hfe)Re>>Rs+hie and hfe>>1, the load current is

directly proportional to the input voltage, and this current depends
only upon Re, and the not upon any other circuit or transistor
parameter.
The voltage gain is given by
I o RL  h feRL
AVf   GMf RL  (13  57)
Vs Rs  hie  (1  h fe ) Re
RL
Subject to the conditions (1+hfe)Re>>Rs+hie and hfe>>1, Vf A  
Re
and the voltage gain is stable if RL and Re are stable resistors.

From Fig. 13-16c, we see that Ri=Rs+hie+Re, hence

Rif  Ri D  Rs  hie  (1  h fe ) Re (13  58)

Since Ro=, then Rof=Ro(1+bGm)= .

Hence
' R R R
Rof L of L
Example: The circuit of Fig. 13-16a is to
have an overall transconductance gain of –
1mA/V, a voltage gain of –4, and a
desensitivity of 50. If Rs=1 K, hfe=150, and
rbb’ is negligible, find (a) Re, (b) RL, (c) Rif,
and (d) the quiescent collector current Ic at
room temperature.

Solution:
a. GMf= GM/D=-1 mA/V then GM= -50 mA/V.
Since b=-Re, then D=1+bGM=1+50Re= 50;
Or Re =0.98K 1 K.
b. AVf=GMfRL or RL=AVf/GMf= (-4)/(-1)= 4 K.
c. From Eq. (13-53)
GM=-50=(-hfe)/(Rs+hie+Re)=(-150)/(1+hie+1)
then hie=1 K.
Ri= Rs+hie+Re= 3 K
Rif= RiD= (3)(50)=150K
d. From Eqs. (11-9) and (11-6)
hie=rbb’+rb’e(hfe)/(gm)=(hfeVT/IC)
then IC=(hfeVT/hie)=(150)(0.026)/91)=3.9mA.
 FET Configuration
The circuit of FET CS Stage with a source
resistor R as current series feedback is given in
Fig. 13-17a.
The circuit of Fig. 13-17a is analogous for the
transistor (Fig. 13-16a) CE stage with an emitter
resistor Re.
Proceeding as we did for the transistor amplifier, we obtain the circuit
of Fig. 13-17b. Replacing the FET by its low-frequency model results
in Fig. 13-17c.
 Vf
b  R (13  60)
Io
Io Io  g mrd 
GM     (13  59)
Vi Vs rd  RL  R rd  RL  R
where,   g mrd
R rd  RL  (1   ) R
D  1  bGM  1   (13  61)
rd  RL  R rd  RL  R
GM 
GMf   (13  62)
D rd  RL  (1   ) R
Since, Ri   then Rif  Ri D   (13  63)
To calculate Rof  
Gm  lim GM  lim 
we need Gm RL 0 RL 0 rd  RL  R rd  R
 rd  R(1   )
1  bGm  1  ( R) 
rd  R rd  R
The output resistance without considering
load RL is Ro  rd  R
rd  (1   ) R
Rof  Ro (1  bGm )  (rd  R)
rd  R
Rof  rd  (1   ) R (13.65)

' ' (1  bGm ) (rd  R) RL rd  (1   ) R rd  RL  R

Rof  Ro 
D rd  RL  R rd  R rd  RL  (1   ) R

' RL [rd  (1   ) R]
Rof  (13.66)
rd  RL  (1   ) R
 Current-Shunt Feedback
Figure 13-18 shows two transistors in cascade with feedback from
the second emitter to the first base through the resistor R’.
The voltage Vi2 is much larger than Vi1 because of the voltage of Q1.
Also, Vi2 is 180o out of phase with Vi1. Because of emitter-follower
action, Ve2 is only slightly smaller than Vi2, and these voltages are in
phase.
Hence Ve2 is larger in
magnitude than Vi1 and is
180o out of phase with Vi1.
If the input signal
increases so that Is’
increases, If also
increases, and Ii=Is’-If is
smaller than it would be if
there is no feedback.
This action is characteristic of negative feedback.
Thus the circuit of Fig. 13-18 acts as a negative feedback.

Since Ve2>>Vi1, and neglecting the base current of Q2 compared with

the collector current, Vi1  Ve2 Ve2 ( I o  I f ) Re
If    (13.67)
R' R' R'
I R Ro
Or, I f  o e  bI o (13.68) where, b 
R' Re R' Re

Since the feedback current

is proportional to the
output current, this circuit
of Fig. 13-18 acts as a
current shunt feedback
amplifier.
 The current gain with feedback of 1 R' Re
AI f   (13.69)
this circuit is: b Ro

So, AIf is stable (desensitized) provided that R’ and Re are stable

resistances.
The voltage gain with feedback of this circuit is:
V I R R' Re Rc 2 Rc 2
AV f  o  o c 2   (13.70)
Vs I s Rs Re Rs bRs

If Re, R’, Rc2, and Rs are

stable elements, then AVf
is stable.
 Amplifier Without Feedback of Fig. 13-18
The input circuit of the amplifier without feedback is obtained by
opening the output loop at the emitter of Q2. This places R’ in series
with Re from base to emitter Q1.
The output circuit is found by shorting the input node (the base of Q1).
This places R’ in parallel with Re.
The resultant equivalent circuit is given in Fig. 13-19.
Since the feedback
signal is a current, the
source is represented by
a Norton’s equivalent
circuit with Is=Vs/Rs.
 Voltage-Shunt Feedback
Figure 13-20a shows a common-emitter stage with a resistor R’
connected from the output to the input.
In the circuit of Fig. 13-20a, the output voltage Vo is much greater
than the input voltage Vi and is 180o out of phase with Vi. Hence
V V V 1
I f  i o   o  bVo (13.77) where, b 
R' R' R'
Since the feedback current is
proportional to the output voltage, this
circuit acts as a voltage-shunt feedback
amplifier.
The transresistance with feedback is
obtained as follows:
Vo 1
RMf     R' (13.78)
Is b
 RMf   R

The transresistance equals the negative of the

feedback resistance from output to input of the
transistor and is stable if R’ is a stable resistance.
If we assume that Rif’=0, then the voltage gain
with feedback is
Vo Vo 1 R'
AVf     (13.79)
Vs I s Rs bRs Rs

If R’ and Rs are stable elements, then AVf is

stable.
 Amplifier Without Feedback of Fig. 13-20(a)
The input circuit of the amplifier without feedback is obtained by
shorting the output node (Vo=0). This places R’ from base to emitter
of the transistor.
The output circuit is found by shorting the input node (Vi=0), thus
connecting R’ from collector to emitter.
The resultant equivalent circuit is given in Fig. 13-20b.
Since the feedback signal is a current,
the source is represented by a Norton’s
equivalent with Is=Vs/Rs.
The feedback signal is the current If in
the resistor R’ which is in the output
circuit. From Fig. 13-20b
If the amplifier is deactivated by reducing hfe to zero, a current If
passes through the b network (the resistor R’) from input to output.
Vs
This current is given by If 
Rs  R' Rc
Vo AVf Vs
The output current Io with amplifier activated is I o  
Rc Rc
Hence the condition that the forward
transmission through the feedback
network can be neglected is Io>>If,
or
Rc
AVf 
Rs  R' Rc

Since the voltage gain is at least

unity, this inequality is easily
satisfied by selecting Rs+R’>>Rc.