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What is an interrupt?
Interrupt is a signal (to be of any form) which is used to establish data transfer
between CPU and other devices.
What are the different types of interrupts?
Interrupts
1. All external
Interrupts are
hardware initiated
External Internal 2. Internal interrupts
Interrupts Interrupts are initiated by both
hardware and
software
3. Only external
Hardware Software Hardware Software interrupts are Non-
Interrupts Interrupts Interrupts Interrupts
maskable
4. All Internal
interrupts are
maskable
Non- Maskable Non- Maskable Non- Maskable
Non- Maskable
maskabl maskabl maskabl
maskabl
e e e
e
Interrupts in DSPs
➢ External- Hardware initiated – Non-maskable interrupts – RS and NMI
RS – Reset (hardware reset) - Program execution stops, all registers initialized to original value
NMI – Non-maskable interrupt – Program execution stops, register contents are not affected
➢ External- Hardware initiated – maskable interrupts – INT0, INT1,INT2, INT3
INT0 – External user interrupt 0
INT 1 – External user interrupt 1
INT 2 – External user interrupt 2
INT 3 – External user interrupt 3
➢ Internal- Hardware initiated – maskable interrupts
➢ All on-chip peripherals have interrupts
TINT – Timer interrupt
XINT – Serial port transmit interrupt
RINT – Serial port receive interrupt
HINT – Host port interface interrupt
➢ Internal- software initiated – maskable interrupts
INTR, TRAP
➢ The occurrence of the interrupt to the processor will set ‘1’ the corresponding
bit in IFR until the CPU recognize the interrupt
➢ The format of IFR is same as IMR
Example: Let IPTR = 01, the interrupt number for INT0 is 16 (10h)
The ISRA generated for INT0 is concatenating IPTR (01h) with (10h)
left shifted by two.
we get ISRA as 00C0h
➢ ISRA generated by the processor has only four PM locations for each interrupt.
➢ ISR needs more than four memory locations.
➢ In the locations of PM pointed by ISRA has instructions (branch) to point to the
starting address of the PM where the actual ISR is present for the interrupt.
0 0 0 0 0 0 0 1 1 0 0 1 0
Program to enable interrupts
SET INTM - mask/disable globally the maskable interrupts
LD #32h, IMR – load control word to enable serial port interrupts
CLR INTM – unmask/enable globally the maskable interrupts
Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15
Interrupt Processing/Operation 24
Once an interrupt has been passed to the CPU, the CPU operates in the
following manner
Maskable Interrupts:
1. The corresponding bit in the IFR is set ‘1’, this gives the information to CPU
that interrupt has occurred.
2. Check for the conditions INTM = 0 and the corresponding bit in IMR =1, the
acknowledgment conditions are tested.
3. If the conditions are true, the CPU acknowledges the interrupt, generating
an IACK signal; otherwise, it ignores the interrupt and continues with the
main program.
4. When the interrupt has been acknowledged, its flag bit in the IFR is cleared
to 0 The INTM bit is set ‘1’ (to block other maskable interrupts).
5. ISRA is generated by the CPU with IPTR value and interrupt number
6. The PC is saved on the stack by PUSH operation and ISRA is loaded in PC
7. The CPU branches to and executes the interrupt service routine (ISR).
8. The ISR is concluded by a return instruction, which pops the return address
off the stack.
10. The CPU continues with the main program till next time IFR is set.
Non-maskable Interrupts:
1. The CPU immediately acknowledges the interrupt, generating an IACK
signal.
2. If the interrupt was requested by RS, NMI, or the INTR instruction, the the
INTM bit is set to 1 to block maskable hardware interrupts.
3. If the INTR instruction has requested one of the maskable interrupts, the
corresponding flag bit is cleared to 0.
4. The PC is saved on the stack.
5. The CPU branches to and executes the ISR.
6. The ISR is concluded by a return instruction, which pops the return address
of the stack.
7. The CPU continues with the main program
Interrupt latency is defined as the number of clock cycle delay from the clock
cycle the interrupt occurred to the interrupts service routine get executed.
What is minimum latency?
For a 4 level pipelined system the minimum latency is 8 clock cycles
▪ 3 cycles to execute instructions in the pipeline before executing a
software vector.
▪ 1 cycle for the interrupt to be recognized by the CPU
▪ 4 cycles to execute the interrupt instruction and flush the pipeline
The minimum latency depends on the number of pipeline stages and the
number of clock cycle required for the CPU to recognize.
What is maximum latency?
The maximum interrupt latency depends on the type of instructions in the
pipeline.
Instructions such as repeat, branch, call which are in the pipeline are to be
completely executed before recognizing the interrupt.
In power down mode the processor enters a dormant state and dissipates less
power than in the normal mode while maintaining the CPU contents
How to invoke power down mode?
• The power-down mode can be invoked by executing the IDLE 1, IDLE 2 or
IDLE 3 instructions.
• By driving the HOLD signal low with the HM status bit set to 1.
IDLE1
• The IDLE1 mode halts all CPU activities except the system clock.
• The system clock is applied to the peripherals, the peripheral circuits
continue to operate.
• The peripherals such as serial ports , timers etc can take the CPU out of
its
IDLE2power-down state.
• The IDLE2 mode halts the on-chip peripherals as well as the CPU.
• Power is significantly reduced because the device is completely stopped.
• Since, the on-chip peripherals are stopped, they cannot be used to wake
up from IDLE2.
• To terminate IDLE2, activate any of the external interrupt pins (RS, NMI,
and
INTx) with a 10-ns minimum pulse.
Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15
Power down modes cont… 29
IDLE3
• IDLE3 is used for a complete shutdown of the processor.
• The IDLE3 mode functions like IDLE2 but it also halts the PLL.
• The IDLE3 state allows you to reconfigure the PLL externally if the system
requires to operate at a lower speed to save power.
• In some architectures separate power down mode LOPOWER is available
which will operate the processor at a lower speed.
HOLD MODE
• It enables to put the address, data, and control lines into the
high-impedance state.
• Depending on the value of the HM bit, this mode is used to halt the CPU.
How the Basic pipeline phases are increased in `C54X to 6 level pipeline
Name of the Change in Operations performed
phase phase
Fetch Program • The program counter address is send to PM
prefetch through PAB.
Program • The Instruction word is read from that address and
fetch reaches CPU through PDB and PC is incremented.
Decode Decode •The instruction fetched is decoded, know the
operation to be performed
• Know the type of addressing mode
• If address of the operand is to be generated, the
DM address is generated
• ARU updates are performed
Read Access • The data memory address generated in decode
phase is send to DM through CAB.
• CAB and DAB used for dual access,
• EAB used for write
Read • The data is read from that address and reaches
CPU through DDB.
• Both CDB and DDB used for dual access
Execute Execute • Perform the operation
• Data memory write is performed, EDB is used for write
Due to memory
On-chip memory
• Write followed by dual operand access – due to DARAM
• If a dual-access memory block is mapped in both program and data
spaces, an instruction fetch will conflict with a data operand read
access if they are performed on the same memory block.
Off-chip memory
• One set of external address and data buses, a bus conflict occurs
between instruction fetch (F), operand read (R), and execute (E) write
phases if program, data or both memory are external.
End of Part-4