International Journal of Electronics

ISSN: 0020-7217 (Print) 1362-3060 (Online) Journal homepage: http://www.tandfonline.com/loi/tetn20

A power management system for energy

harvesting and wireless sensor networks
application based on a novel charge pump circuit

R. Aloulou, P-O Lucas De Peslouan, H. Mnif, F. Alicalapa, J. D. Lan Sun Luk &
M. Loulou

To cite this article: R. Aloulou, P-O Lucas De Peslouan, H. Mnif, F. Alicalapa, J. D. Lan Sun
Luk & M. Loulou (2016) A power management system for energy harvesting and wireless
sensor networks application based on a novel charge pump circuit, International Journal of
Electronics, 103:5, 841-852, DOI: 10.1080/00207217.2015.1072848

To link to this article: http://dx.doi.org/10.1080/00207217.2015.1072848

Accepted author version posted online: 15

Jul 2015.
Published online: 04 Aug 2015.

Submit your article to this journal

Article views: 103

View related articles

View Crossmark data

Full Terms & Conditions of access and use can be found at

http://www.tandfonline.com/action/journalInformation?journalCode=tetn20

Download by: [rahma aloulou] Date: 18 October 2016, At: 14:42

INTERNATIONAL JOURNAL OF ELECTRONICS, 2016
VOL. 103, NO. 5, 841–852
http://dx.doi.org/10.1080/00207217.2015.1072848

A power management system for energy harvesting and wireless

sensor networks application based on a novel charge pump
circuit
R. Alouloua,b, P-O Lucas De Peslouanb, H. Mnifa, F. Alicalapab, J. D. Lan Sun Lukb
and M. Louloua
a
LETI Lab, University of Sfax, Sfax, Tunisia; bLE2P Lab, University of La Reunion Saint Denis, Reunion France

ABSTRACT ARTICLE HISTORY

Energy Harvesting circuits are developed as an alternative solution to Received 28 December 2014
supply energy to autonomous sensor nodes in Wireless Sensor Networks. Accepted 27 June 2015
In this context, this paper presents a micro-power management system KEYWORDS
for multi energy sources based on a novel design of charge pump circuit Wireless sensor networks;
to allow the total autonomy of self-powered sensors. This work proposes energy harvesting;
a low-voltage and high performance charge pump (CP) suitable for micro-power management
implementation in standard complementary metal oxide semiconductor system; charge pump circuit
(CMOS) technologies. The CP design was implemented using Cadence
Virtuoso with AMS 0.35μm CMOS technology parameters. Its active area
is 0.112 mm2. Consistent results were obtained between the measured
findings of the chip testing and the simulation results. The circuit can
operate with an 800 mV supply and generate a boosted output voltage
of 2.835 V with 1 MHz as frequency.

1. Introduction
In recent years, much research has been oriented for Wireless Sensor Networks (WSN) due to their
wide application range in a variety of fields such as military, medical, environmental and industrial.
Sensor networks are the spatial distribution of large numbers of sensors with their computation
and communication capabilities (Freudiger, Jadliwala, Hubaux, Niemi, & Ginzboorg, 2013). Since
these nodes are deployed in various environments, including remote and dangerous environments
such as volcanic regions, the major problem in WSN is how to power a wireless transmission that
requires higher power levels from limited-power resources (Belleville et al., 2010). Consequently,
energy is the key issue that WSN deals with. Therefore, the concept of energy harvesting (EHV)
from the environment (light, vibration, radio frequency (RF) radiation) has gained popularity in
recent years (Iskender & Genc, 2010). Since the harvested energy level is very small, a power
management subsystem should be carefully designed to extract as much power as possible from
the transducers and transfer it to the electronic devices (Shao, Tsui, & Ki, 2010). Hence, the main
critical constraints that have to be taken into consideration are: low-power consumption, low-cost
process integration within a minimum chip area at a high generated output voltage (Do, 2011).
The remaining of this paper is organised as follows: in Section 2 a review of the basic concept of
EHV sources is investigated. Section 3 detailes the block diagrams of the proposed EHV micro-
power system. As the power management circuit was mainly built in a charge pump circuit (CPC),
Section 4 proposes a novel and efficient design of a charge pump (CP). This new design is also
detailed and discussed in Section 4. In order to prove the availability of the new design of CP, the

CONTACT: R. Aloulou aloulourahma@yahoo.fr

© 2015 Taylor & Francis
842 R. ALOULOU ET AL.

circuit implemented using AMS 0.35 µm complementary metal oxide semiconductor (CMOS)
process is simulated as described in Section 5. Section 6, however, is devoted to describe the
experimental results and to discuss their concordances with the simulation findings presented in
Section 5. Finally, conclusions are drawn in Section 7.

2. EHV sources
EHV can be defined as capturing energy in order to provide electricity to supply devices directly or
to be stored in capacitors or batteries for later use.
EHV sources such as light, RF radiation, thermal and vibration energy may enable wireless sensor
nodes to be completely battery-independent and self-powered (Viehweger, Keutel, & Kanoun,
2014). Table 1 presents a general overview of the concept of the basic concept of environmental
EHV sources and their estimated harvested power (Chang et al., 2010; Ramadass & Chandrakasan,
2010).

3. EHV micro-power system

To guarantee an autonomous self-powered sensor network, ambient energy is harvested to supply
the system load. This harvested energy, however, is not suitable to be directly used as a power
supply due to the random environmental conditions and the availability of resources over time
(Lopez, Ortega, & Jurado, 2015). Therefore, the key component in a micro power harvesting system
is the power management unit (PMU) that provides a hybridisation of diverse energy sources, and a
maximisation of the DC-regulated voltage level to supply the load unit and store energy for later
use (Chapman, 2009; Vullers, Van Schaijk, Doms, Van Hoof, & Mertens, 2009). This storage operation
is controlled by a voltage regulator, which is responsible for monitoring the voltage storage level as
described in Figure 1.
There are two main alternatives to store the regulated harvested energy, namely, the super-
capacitors and the rechargeable battery (Roundy, Otis, Chee, Rabaey, & Wright, 2003). In the
context of WSN and energy-harvesting application where sensor nodes are deployed in remote

Table 1. Comparison of basic, ambient energy sources and their estimated harvested power.
Energy harvesting resources Energy transducers Estimated power density
Light, intensity Solar cell or PV cell Indoor:10 μW/cm2
outdoor:10 mW/cm2
Thermal Thermo-electric, Generator (TEG) Human:40 μW/cm2
(Temperature differences) Industrial:10 mW/cm2
Vibrations/Motions Piezoelectric cell (PZ) ~ 200 μW
(Variability of vibration) Electrostatic cell(ES) 50–100 μW
Electromagnetic cell(EM) Less than 1μW
RF/Micro Wave Transmitter (rectenna) 0.1–100 μW/cm2
(RF emission)

Receiver power Power Management Storage System

Unit (PRU) Unit (PMU) Unit (SU) Load Unit
Energy
Transducers Charge pump Voltage E/R
-PV Regulator
-TEG Buffer µP
-RF Clock generator Storage device Sensor
-VIB (super-capacitor)
Bandgap ….

Figure 1. Block diagrams of the proposed EHV micro-power system.

 INTERNATIONAL JOURNAL OF ELECTRONICS 843

Table 2. Specifications of the PV cell (Aloulou et al., 2014).

Company SCHOTT company
Cell type ASi:Amorphous silicon
Size 21 cm2 (7 cm x 3 cm)
Standard STD AM1.5 G
Maximum power MPP [mW] 98
Short circuit current ISC [mA] 35
Open circuit voltage VOC [V] 4.9
Current, max power Impp [mA] 28
Voltage, max power Vmpp [V] 3.5

Table 3. Thermoelectric module characteristics (Palacios & Li, 1998).

Description Thermoelectric cooling module
Company Advanced thermoelectric
Size 1.5 inch (40 mm x 40 mm)
Maximum current, Imax [A] 6
Maximum voltage, Vmax [V] 15.5
Cooling capacity, Qmax [W] 53
Maximum delta T, ΔT max [°C] 70

and dangerous environments, the lifetime of the remote sensors is greatly important. Therefore,
the super-capacitor is used as a storage device in this work (Figure 1).
As described in Table 1 where some estimation of the harvested power levels are given, the
choice of EHV source is critical. It requires an in-depth understanding of several design constraints
and trade-offs, such as power requirement, cost and area.
For these various considerations, light and thermal resources can be significant energy-harvest-
ing sources and can guarantee a trade-off between different design requirements (Kalogirou, 2013).
Accordingly, a solar cell of type ASI from SCHOTT company (Table 2) and a Peltier cell from
Advanced Thermoelectric company (Table 3) were used for the experimental test bench. The
measured characteristics of each cells display a good agreement with the manufacturer’s data
(Aloulou et al., 2014).

4. PMU
Since the energy extracted from harvesting sources is very low, an efficient PMU is required to
boost the output energy of transducers. This is to meet the required amount of power by the
system or to be stored in an super-capacitor. This paper proposes a power-management
system mainly based on a novel CP as DC/DC converter (Figure 2). This new circuit of pump
is driven by a clock generator and a voltage reference designed and detailed by Aloulou et al.
(2015).
To validate the circuit, we set up the output voltages of the PV cell or the TEG modules to 800
mV or higher to avoid the problem of threshold in CPC. When the voltage extracted from the
transducers reaches 0.8 V, the oscillator starts operation and generates two anti-phase pumping
clocks in order to drive the CP through the buffer.
As the CPC is the key component in the micro-scale energy, the next section presents a novel
design of CP.

5. CP design
The CPC as a DC power converter is the key element in a micro-scale EHV system to adjust the
transducers’ voltages (often less than 1 V) into suitable levels to be stored in a super-capacitor
(Kimball, Flowers, & Chapman, 2004). Thus, in this work, the main challenge was to design a novel
844 R. ALOULOU ET AL.

PV cell / GTE
Vdd=V_ehv

V_ehv V_ehv V_ehv V_ehv

Clock generator Buffer Charge pump

CLK
Voltage regulator Vdd Vout
(Bandgap)

CLK

Figure 2. Architecture of the proposed PMU.

design of CP able to generate a high enough output voltage level to supply the autonomous
sensors nodes.

5.1. Basic, concept and operation of CPC

Most MOS CPs are based on the circuit proposed by Dickson (Dickson, 1976). This circuit consists of
two anti-phase pumping clocks Clk and Clk_bar, which have the same voltage amplitude of Vclk as
presented in Figure 3. The diode-connected N-channel metal oxide semiconductor (NMOS) tran-
sistors operate as switches characterised by the MOS threshold voltage Vtn (Aloulou, Mnif,
Alicalapa, & Loulou, 2011; Wu, Chang, 1998).
In steady state, the output voltage is given by
Vout ¼ Vin þ NðVClk  Vtn Þ  Vtn (1)
where Vin is the input voltage, and N is the number of stages (Chang & Hu, 2006; Tanzawa &
Tanaka, 1997).
However, the successive increase of the voltage on internal nodes causes an increase between
the substrate and the sources of NMOS transistors and consequently an increase in the threshold
voltage of each switch, due to the body effect. This causes degradation of the voltage gain as
expressed in Equation (1) (Choi, Park, Kim, Jung, & Suh, 1997). To solve this problem, various
technological solutions have been proposed, such as creating individual wells to separate the
substrates of transistors or using transistors with zero threshold voltage (Alicalapa, Lan Sun Luk,
Aloulou, Mnif, & Loulou, 2012). Despite the good results generated by such solutions, we notice

Vout
Vin
Cout
MD1 MD2 MD3 MD4 MD5

C1 C2 C3 C4

Clk

Clk_bar

Figure 3. Dickson CPC.

 INTERNATIONAL JOURNAL OF ELECTRONICS 845

that such a process is rather expensive and technologically complicated. To overcome this afore-
mentioned limitation, the authors Wu and Chang (1998) suggested using MOS switches with
backward control by using the established high voltage of the next stage. These switches named
CTS (Charge Transfer Switch) are used to increase the voltage pumping gain (Aloulou, Mnif,
Alicalapa, & Loulou, 2011). These structures are called NCP-1 and NCP-2. More details are given
in previous works (Aloulou, Mnif, Alicalapa, & Loulou, 2011; Alicalapa et al., 2012).

5.2. Proposed CPC

In order to reach a better performance in the context of EHV application and low-voltage circuit, a
new CP was proposed and presented in Figure 4.
As mentioned in previous researches (Aloulou, Mnif, Alicalapa, & Loulou, 2011; Alicalapa et al.,
2012), the NCP-1 is the most suitable circuit for low-voltage operation. Therefore, in the proposed
circuit, the idea was to design a heterogeneous design of CP (NCP-1/NCP-2) in order to benefit
from both advantages. In the novel design, the first two stages consist only of the CP NCP-1 to
boost the low input voltage harvested from transducers. This improvement on the design allows a
new circuit that is far less complicated than the conventional structure (NCP-2) to decrease the
circuit size and achieve a better performance. Hence, the proposed CP exploits a dynamic charge
pumping control scheme where the pass transistors (MN and MP) are introduced only at the third
stage to control each of CTS switches that can be turned off completely when required.
On the other hand, the conventional CP suffers from increased drain-source voltage drop across
every charge transfer MOS switch. Hence, if the problem of limitation of the configured output
stage diode can be solved, a better pumping performance can be achieved (Aloulou, Mnif,
Alicalapa, & Loulou, 2011). Therefore, in the proposed design the switch of the output stage is
replaced by a single PMOS switch MP_out to avoid the problems in the inner CTSs of the output
stage.
Referring to Figure 4, the control of the MP_out switch is obtained by connecting the gate of
MP_out to the CTS MOS switch of the previous stage. The operation of the modified output stage
can be explained as follows: when Clk goes high, voltage at Stage 7 is settled to the highest level.
This high potential allows MN5 to be turned on, MP5 to be turned off and MS7 to be turned off.
Hence, the transistor MP_out is forced to be turned on. Equation (2) justifies that the activation of
this output transistor MP_out guarantees high voltage transfer efficiency and provides a maximum
boosted output voltage.
Vout  ðVC7 þ ΔVÞ  VdsðMP outÞ (2)

MD1 MD2 MD3 MD4 MD5 MD6 MD7

MP_out
Vout
V1 V2 V3 V4 V5 V6 V7
Vin

MS1 MS2 MS3 MS4 MS5 MS6 MS7

Cout

MN1 MP1 MN2 MP2 MN3 MP3 MN4 MP4 MN5 MP5

C1 C2 C3 C4 C5 C6 C7

Clk

Clk_bar

Figure 4. The proposed CP design.

846 R. ALOULOU ET AL.

Table 4. Voltage nodes at different clock cycles.

When CLK goes low When CLK goes high
V2 is changed to V2 + ΔV V1 is changed to V1 + ΔV
V4 is changed to V4 + ΔV V3 is changed to V3 + ΔV
V6 is changed to V6 + ΔV V5 is changed to V5 + ΔV
Vj: the highest voltage V7 is changed to V7 + ΔV
(Vj = VCj+ ΔV) (j ∈2,4,6) Vi: the highest voltage
MN2 MN4 are ON (Vi = VCi+ ΔV) (i ∈1,3,5,7)
MP2 MP4 are OFF MN1 MN3 MN5 ON
MS1 MS3 MS5 are OFF MP1 MP3 MP5 OFF
MP_OUT is OFF MS2 MS4 MS6 OFF
C1 C3 C5 C7 is charged C2 C4 C6 is charged
Cout is isolated from the forestage MP_OUT is ON (maximum transfer of charge)

Since VdsðMP outÞ was very small, no voltage gain has been lost in the output switch. This
improvement guarantees a maximum transfer of charge to the output stage when the MP_out is
turned on and also leads to the decrease of the total size area. Conversely, for low Clk, MN5 is
turned off, MP5 is turned on and MS7 is turned on. Consequently, the transistor MP_out is turned
off and leads to the isolation of the output capacity from the forestage. To understand better the
operation of the proposed design, Table 4 reveals the details of each voltage node at different
pumping clock cycles.
The operation of the proposed structure can be summarised as follows: As the clock CLK1 is low,
the switch MD1 is turned ON and the voltage at Node 2 is higher than at Node 1. Later on, MP1 is
closed (turned on) and forces the transistor MS1 to be connected to Node 2. Consequently, the
switch MS1 is completely closed and the voltage drop is avoided. Also, in this condition MN1 is
turned OFF and the voltage at Node 1 is equal to the input harvested voltage VIN. For the next
clock half cycle, where CLK is high, the switch MD1 turns OFF, then, both the voltage at Node 2 and
Node 1 are equal and thereafter MP1 is turned OFF. Since the voltage at Node 1 is higher than VIN,
MN1 is turned on, the gate of MS1 is forced to be connected to VIN and consequently to be turned
OFF. Hence, the problem of reverse charge sharing was solved and the efficiency was improved.

6. Simulations results
In order to evaluate the proposed CP design and compare it with the conventional structures, various
simulations are performed using 0.35 μm CMOS process parameters. All the simulations were carried
out at 1 MHz. The values of output capacity and pumping capacitors in all the circuits are 150 pF and
10 pF, respectively. The number of pumping stages is N = 7 and the supply voltage is 800 mV.
Figure 5 displays the simulation comparison results for Dickson, NCP-2 and the proposed CP.
As illustrated in Figure 5, we can observe that the output voltage for the proposed design is the
highest for the same stage number and input voltage compared to previous architectures. The
output can reach above 2.835 V for 0.8 V input voltage. Under the same condition, the output
voltage is 2.1 V for the Dickson CP and is 2.3 V for the NCP-2.
As a result, through the proposed CP, the number of stages and chip areas could be reduced for
the applications where high output voltage and low-voltage input are required.
Figure 6 shows Spice simulation comparison results of output voltage at different low-supply
voltages. The circuit’s parameters are identical to those used in the simulations for Figure 5.
From Figure 6, it can be seen that the novel design presents the best performance for low-
voltage design which is very beneficial for EHV system.
In this same context, low-power design is also essential for energy-constrained systems.
Therefore, efficiency and power dissipations have been investigated for CPs topologies. Table 5
provides data which tend to indicate that the proposed design reaches the best efficiency for the
smallest area. Also, this table gives a comparison between the figures of merit (FOM) (Equation 3)
which reflects the advantages of the proposed structure.
 INTERNATIONAL JOURNAL OF ELECTRONICS 847

3.5

2.5
Output Voltage (V)

1.5

0.5

0
Dicks_CP NCP2_CP Proposed_CP

Figure 5. Output voltages of various seven-stage CPs.

Proposed CP
7
NCP-2 CP

6 Dickson CP
Output Voltage (V)

1
0.8 1 1.2 1.4 1.6 1.8 2
Supply Voltage (V)

Figure 6. Comparisons results of output voltages versus supply voltage.

Pout:η
FOM ¼ (3)
total area

These results prove that the proposed circuit improves the output voltage gain with 75% area
decrease.
848 R. ALOULOU ET AL.

Table 5. Comparison results of area and efficiency.

NCP-2 Proposed design
Area of transistors 1023,75 µm2 266 µm2 = 25% of initial area = > gain of 75% of silicium surface
Area of capacity Ci 8 * 0.039330 mm2 7 * 0.039330 mm2
Efficiency 35% 86%
FOM 0.097 2.218

Consequently, the proposed design allows both size and power consumption decrease and
produces a high voltage output and maximum charge transfer.

7. Experimental results
To validate the above findings, the proposed circuit was designed, fabricated and measured. The
test chip was fabricated using 0.35 µm standard CMOS technology. Figure 7 shows the micro-
photograph of the proposed design.
The summary of the measurement results is presented in Table 6. The measurements are carried
out with an external load capacitor of 150 pF.
Figure 8 is given to compare the simulated results with the measured findings of output
voltages as function of the supply voltages. However, Figure 9 is introduced to compare simulated
and measured output voltages versus the output currents.
Referring to these figures and relying on the experimental tests, we can conclude that measure-
ment results display a good agreement with the simulated findings. The slight offset observed
between the simulated and the measured performances can be justified by the effect of parasitic

Figure 7. Die photo of the proposed circuit.

Table 6. The measurement result summary of the proposed CPC.

Parameters Measured
Supply voltage range (V) 0.8–1.5
Output voltage (V) 2.59–4
Pumping frequency (MHz) 1
Area of the layout (mm2) 0.112
Technology 0.35-µm CMOS
 INTERNATIONAL JOURNAL OF ELECTRONICS 849

8
Simulation results
7
Measurement results
6

5
Vout (V)

0
0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
Vin (V)

Figure 8. Output voltage of the proposed CP as a Vin function.

5.5

Simulation results Vin = 0.8V

5 Measurement results Vin = 0.8V
Simulation results Vin = 0.9V

4.5 Measurement results Vin = 0.9V

Simulation results Vin = 1V
Measurement results Vin = 1V
4
Vout (V)

3.5

2.5

1.5
0 0.5 1 1.5 2 2.5 3 3.5
Iout (µA)

Figure 9. Output voltage of the proposed CP as a function of the output current.

850 R. ALOULOU ET AL.

Table 7. Performance comparison with other designs reported in the literature.

Jia, Ni, Shi, and Shin, Chung, Park, Ker, Chen, and This
Dickson (1976) Dai (2007) and Min (2000) Lee et al. (2006) Tsai (2004) work
Vin 14 0.9 ~ 2 1.4 3.3 1.8 0.8–1.5
Vout 3.9 3.2 ~ 6 11.4 4.5 ~ 5 8.39 2.59–4
Nb_stage 7 – 16 – 4 7
Freq (Hz) 1M 20 M 3M 400 K ~ 600 k – 1M
Ci (F) 2p 2p – – 1p 10p
Cload (F) 10p 20p – – 1p 150p
Iout (A) 3.9µ 2µ 1µ – 5µ 2.55µ
Area mm2 0.14 – – 0.25 – 0.112
Process – 0.35 µm 1.5 µm 0.13 µm 0.35 µm 0.35 µ m

(resistances and capacitances) associated with metal wires, bonding pad and bonding wires (Baker
& Boyce, 1997).
To show the reliability of the proposed CPC, the novel design is compared to other structures in
the literature. These comparisons are summarised in Table 7.

8. Conclusion
Extracting energy from an ultra-low voltage source of harvesting energy requires an efficient micro
power management system. In this context, this paper proposes a micro power management
circuit for multi energy sources based on a novel design of CPC as a DC–DC converter to allow
autonomous powered sensors and bring an environmentally friendly design with lower circuit
costs.
This CP is the key component in the micro power management design. It is introduced to boost
the output voltage of the transducers to a suitable level that enables energy storage in a super-
capacitor.
This paper describes an improved and high performance CP design suitable for low-voltage
operations and wireless sensor applications. Therefore, theoretical analyses have been presented to
prove that the proposed design does not suffer from problems of conventional structures. This new
CP can, therefore, reduce the threshold voltage drop, eliminate the body effect completely, and
then improve the pumping gain.
From simulation results, it has been asserted that the novel CP generates higher voltage than
conventional circuits for the same stage number, which makes it very interesting to low power
supply applications. Hence, it can be concluded that the proposed design follows the performance
predicted by the theoretical analysis. The circuit provides a boosted more effective voltage level
than the other circuits with a 75% optimisation design in terms of die area compared to the basic
structure.
Finally, the chip testing proved that the proposed DC/DC CP generates a stable DC (2.59 V)
voltage from 800 mV supply for harvesting energy applications with low power dissipation and
high pumping efficiency reaching as high as 86%.

Disclosure statement
No potential conflict of interest was reported by the authors.

References
Alicalapa, F., Lan Sun Luk, J. D., Aloulou, R., Mnif, H., & Loulou, M. (2012, September). PSO- based charge pump chip
area minimization. In 2012 international conference on synthesis, modeling, analysis and simulation methods and
applications to circuit design (SMACD) (pp. 133–136). IEEE.
 INTERNATIONAL JOURNAL OF ELECTRONICS 851

Aloulou, R., Armand, J., Mnif, H., Alicalapa, F., Loulou, M., & Luk, J. D. (2014, April). Improved circuit model of
photovoltaic cell for energy harvesting application. In Mediterranean electrotechnical conference (MELECON), 2014
17th IEEE (pp. 548–552). IEEE
Aloulou, R., Lucas, P. O., Armand, J., Mnif, H., Alicalapa, F., Loulou, M., & Luk, J. D. (2015). Contour graph approach of
micropower clock generator design for energy harvesting charge pump circuits. Journal of Microelectronics
Electronic Components and Materials, 45(1). 87–97.
Aloulou, R., Mnif, H., Alicalapa, F., & Loulou, M. (2011, December). An improved MOS charge pump circuit for low
voltage operations and wireless sensor applications. In 2011 international conference on Microelectronics (ICM) (pp.
1–4). IEEE.
Baker, H. L. R. J., and Boyce, D. (1997). CMOS: Circuit design, layout, and simulation. Wiley-IEEE Press.
Belleville, M., Fanet, H., Fiorini, P., Nicole, P., Pelgrom, M. J. M., Piguet, C., & Cantatore, E. (2010). Energy autonomous
sensor systems: Towards a ubiquitous sensor technology. Microelectronics Journal, 41(11), 740–745. doi:10.1016/j.
mejo.2010.01.009
Chang, L.-K., & Hu, C.-H. (2006). High efficiency MOS charge pumps based on exponential-gain structure with pumping
gain increase circuits. IEEE Transactions on Power Electronics, 21(3), 826–831. doi:10.1109/TPEL.2006.874795
Chang, M. H., Wu, J. Y., Hsieh, W. C., Lin, S. Y., Liang, Y. W., & Wei, H. (2010, December). High efficiency power
management system for solar energy harvesting applications. In 2010 IEEE Asia Pacific conference on circuits and
systems (APCCAS) (pp. 879–882). IEEE.
Chapman, P. L. (2009, January). Power management for energy harvesting devices. In Radio and wireless symposium,
2009. RWS’09. IEEE (pp. 9–12). IEEE.
Choi, K. H., Park, J. M., Kim, J. K., Jung, T. S., & Suh, K. D. (1997, June). Floating-well charge pump circuits for sub-2.0 V
single power supply flash memories. In 1997 Symposium on VLSI circuits, 1997. Digest of technical papers (pp. 61–62).
IEEE.
Dickson, J. F. (1976). On-chip high-voltage generation in MNOS integrated circuits using an improved voltage
multiplier technique. IEEE Journal of Solid-State Circuits, 11(3), 374–378. doi:10.1109/JSSC.1976.1050739
Do, H.-L. (2011). Integrated ZVS DC–DC converter with continuous input current and high voltage gain. International
Journal of Electronics, 98(9), 1199–1214. doi:10.1080/00207217.2011.593135
Freudiger, J., Jadliwala, M., Hubaux, J.-P., Niemi, V., & Ginzboorg, P. (2013). Privacy of community pseudonyms in
wireless peer-to-peer networks. Mobile Networks and Applications, 18(3), 413–428. doi:10.1007/s11036-012-0406-y
Iskender, I., & Genc, N. (2010). Design and analysis of a novel zero-voltage-transition interleaved boost converter for
renewable power applications. International Journal of Electronics, 97(9), 1051–1070. doi:10.1080/
00207217.2010.482021
Jia, H., Ni, W., Shi, Y., & Dai, F. F. (2007, June). A novel DC-DC charge pump circuit for passive RFID transponder. In
Proceeding of 2007 international workshop on electron devices and semiconductor technology, 2007. EDST 2007. (pp.
218–221). IEEE.
Kalogirou, S. A. (2013). Artificial neural networks and genetic algorithms for the modeling, simulation, and perfor-
mance prediction of solar energy systems. In Assessment and simulation tools for sustainable energy systems (pp.
225–245). London: Springer.
Ker, M. D., Chen, S. L., & Tsai, C. S. (2004, May). A new charge pump circuit dealing with gate-oxide reliability issue in
low-voltage processes. In Proceedings of the 2004 international symposium on circuits and systems, 2004. ISCAS’04.
(Vol. 1, pp. I–321). IEEE.
Kimball, J. W., Flowers, T. L., & Chapman, P. L. (2004). Issues with low-input-voltage boost converter design.
Lee, J.-Y., Kim, S.-E., Song, S.-J., Kim, J.-K., Kim, S., & Yoo, H.-J. (2006). A regulated charge pump with small ripple
voltage and fast start-up. IEEE Journal of Solid-State Circuits, 41(2), 425–432. doi:10.1109/JSSC.2005.862340
Lopez, J. C., Ortega, M., & Jurado, F. (2015). New topology for DC/DC bidirectional converter for hybrid systems in
renewable energy. International Journal of Electronics, 102(3), 418–432. doi:10.1080/00207217.2014.897380
Palacios, R., & Li, M. Z. (1998, September). Electrical properties of commercial thermoelectric modules. In Fourth
European Workshop on Thermoelectrics, ETS (Vol. 98, pp. 159–162)
Ramadass, Y. K., & Chandrakasan, A. P. (2010). A batteryless thermoelectric energy-harvesting interface circuit with 35mV
startup voltage. Institute of Electrical and Electronics Engineers.
Roundy, S., Otis, B. P., Chee, Y. H., Rabaey, J. M., & Wright, P. (2003). A 1.9 GHz RF transmit beacon using
environmentally scavenged energy. Optimization, 4(2), 4.
Shao, H., Tsui, C. Y., & Ki, W. H. (2010, January). Maximizing the harvested energy for micro-power applications through
efficient mppt and pmu design. In Proceedings of the 2010 Asia and South Pacific Design Automation Conference (pp.
75–80). IEEE Press.
Shin, J., Chung, I.-Y., Park, Y. J., & Min, H. S. (2000). A new charge pump without degradation in threshold voltage due
to body effect [memory applications]. IEEE Journal of Solid-State Circuits, 35(8), 1227–1230. doi:10.1109/4.859515
Tanzawa, T., & Tanaka, T. (1997). A dynamic analysis of the Dickson charge pump circuit. IEEE Journal of Solid-State
Circuits, 32(8), 1231–1240. doi:10.1109/4.604079
852 R. ALOULOU ET AL.

Viehweger, C., Keutel, T., & Kanoun, O. (2014, February). Energy harvesting for wireless sensor nodes in factory
environments. In 2014 11th international multi-conference on systems, signals & devices (SSD) (pp. 1–4). IEEE.
Vullers, R. J. M., Van Schaijk, R., Doms, I., Van Hoof, C., & Mertens, R. (2009). Micropower energy harvesting. Solid-State
Electronics, 53(7), 684–693. doi:10.1016/j.sse.2008.12.011
Wu, J.-T., & Chang, K.-L. (1998). MOS charge pumps for low-voltage operation. IEEE Journal of Solid-State Circuits, 33(4),
592–597. doi:10.1109/4.663564