PMC-851D

PMC-851D
Bus-Tie Breaker Protection and

Automatic Transfer Switch Relay
User Manual
CET Electric Technology Inc

Danger and Warning
This device can be installed by the professional personnel only. For any failure caused due to the
non-compliance with the instructions in this Manual, we will not bear any responsibility.
Important Notes
Thank you for using the product of CET Electric Technology Inc. In
order to use PMC-851D safely, correctly and efficiently, please pay
attention to the following important notes:
1) The User Manual is only applicable to the PMC-851D
multifunctional protection relay.
2) Please read the User Manual carefully, and carry out setting, testing
and operation according to the User Manual. If some documents are
provided together with PMC-851D, they shall prevail.
3) Never insert or pull out each plug-in unit of PMC-851D, or touch the
chip and components on printed circuit board when PMC-851D is
charged, in order to prevent damage of PMC-851D.
4) Please test and check PMC-851D with qualified testing instrument
and equipment.
5) In case PMC-851D has any abnormality, please contact our
after-sales technical service (0086-400-8860-418) in time.
6) The default password set for PMC-851D is: 0000.
I
The copyright of this Manual is reserved by CET Electric Technology Inc. No copy, distribution or use of this
Manual and its content is allowed without written permission.
We have checked relevant contents of this manual. As it is impossible to avoid all errors, we cannot
guarantee the complete consistency of the manual with actual device. The data in the manual will be reviewed
periodically and necessary amendments will be made in the documents of new version. You are welcomed to
bring forward suggestions on amendments. The change of later versions won’t be notified.
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Table of Contents
1. Introduction ............................................................................................................................................................... 1
1.1. Overview ................................................................................................................................................................ 1

1.2. Features .................................................................................................................................................................. 1
1.3. Functions ................................................................................................................................................................ 2
2. Technical specifications ............................................................................................................................................. 5
2.1. Environment Parameters ........................................................................................................................................ 5

2.2. Rated Parameters ................................................................................................................................................... 5
2.3. Accuracy ................................................................................................................................................................. 5
2.4. Digital Input Resolution .......................................................................................................................................... 6
2.5. Overload Capacity .................................................................................................................................................. 6
2.6. Digital Outputs ....................................................................................................................................................... 6
2.7. Digital Inputs .......................................................................................................................................................... 6
2.8. Marked degree of protection ................................................................................................................................. 6
2.9. Torque .................................................................................................................................................................... 7
2.10. Electrical Insulation Requirements ......................................................................................................................... 7
2.11. Mechanical Tests .................................................................................................................................................... 7
2.12. Electromagnetic Compatibility ............................................................................................................................... 7
3. Function description .................................................................................................................................................. 8
3.1. Protection function ................................................................................................................................................ 8

3.1.1. Auxiliary Element ........................................................................................................................................... 10
3.1.2. Phase Current SOTF Protection (SOTF-1, SOTF-2) .......................................................................................... 11
3.1.3. Phase Current Acceleration SOTF Protection (SOTF_ATS) .............................................................................. 11
3.1.4. Phase Current DI SOTF Protection (SOTF_DI) ................................................................................................. 12
3.1.5. Instantaneous Over-Current Protection with Definite Time (50P-1) ............................................................. 12
3.1.6. Definite Time Over-Current Protection (50P-2, 50P-3, 50P-4) ....................................................................... 13
3.1.7. Overload Protection (50P-5) .......................................................................................................................... 14
3.1.8. Inverse Time Over-Current Protection (51P).................................................................................................. 14
3.1.9. Neutral Current SOTF Protection (SOTF_I0-1, SOTF_I0-2) ............................................................................. 15
3.1.10. Neutral Current Acceleration SOTF Protection (SOTF_I0_ATS) ................................................................ 16
3.1.11. Neutral Over-Current Protection (50I0-1, 50I0-2) .................................................................................... 16
3.1.12. Inverse Time Neutral Over-Current Protection (51I0) ............................................................................. 16
3.1.13. Single-Bus Over-Voltage Protection (59PP_B1-1, 59PP_B1-2, 59PP_B2-1, 59PP_B2-2) .......................... 17
3.1.14. Single-Bus Under-Voltage Protection (27PP_B1-1, 27PP_B1-2, 27PP_B2-1, 27PP_B2-2) ........................ 17
3.1.15. Under-Voltage Protection (27PP) ............................................................................................................. 18
3.1.16. Single-Bus Over-Frequency Protection (81O_B1-1, 81O_B1-2, 81O_B2-1, 81O_B2-2) ........................... 19
3.1.17. Single-Bus Under-Frequency Protection (81U_B1-1, 81U_B1-2, 81U_B2-1, 81U_B2-2) ......................... 19
3.1.18. Under-Frequency Protection (81U) .......................................................................................................... 20
3.1.19. Power Protection (32P-1, 32P-2).............................................................................................................. 21
3.1.20. Synchronization Check (25)...................................................................................................................... 22
3.1.21. Loss of Potential (LOP_B1, LOP_B2) ......................................................................................................... 24
3.1.22. CT monitor ............................................................................................................................................... 24
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3.1.23. Control Circuit Monitor (74TC)................................................................................................................. 25
3.1.24. All Power Supply Under-Voltage Protection (27PS) ................................................................................. 25
3.1.25. All Power Supply Over-Current Protection (50PS) ................................................................................... 25
3.1.26. Line 1 Over-Current Protection (50P_L1) ................................................................................................. 26
3.1.27. Line 2 Over-Current Protection (50P_L2) ................................................................................................. 26
3.1.28. Breaker Status Monitor ............................................................................................................................ 26
3.1.29. Automatic Transfer Switch Block (ATS Block) ........................................................................................... 27
3.1.30. DI Block Automatic Transfer Switch (DI Block ATS) .................................................................................. 27
3.1.31. Automatic Transfer Switch of Busbar Ⅰ (ATS_B1) ................................................................................... 28
3.1.32. Automatic Transfer Switch of Busbar Ⅱ (ATS_B2) ................................................................................... 33
3.1.33. Automatic Transfer Switch of Line 1# (ATS_L1) ........................................................................................ 38
3.1.34. Automatic Transfer Switch of Line 2# (ATS_L2) ........................................................................................ 43
3.1.35. Synchronization Check of VS1 (25_L1) ..................................................................................................... 47
3.1.36. Synchronization Check of VS2 (25_L2) ..................................................................................................... 48
3.1.37. Line 1 Over-Current Load Shedding Protection (50LS_L1-1, 50LS_L1-2, 50LS_L1-3) ............................... 49
3.1.38. Line 2 Over-Current Load Shedding Protection (50LS_L2-1, 50LS_L2-2, 50LS_L2-3) ............................... 50
3.1.39. DI Protection ............................................................................................................................................ 50
3.2. Measurements ..................................................................................................................................................... 51
3.2.1. Measurement Data ........................................................................................................................................ 51
3.2.2. Protection Data .............................................................................................................................................. 51
3.2.3. Energy Data .................................................................................................................................................... 51
3.2.4. AO output ...................................................................................................................................................... 51
3.3. Remote Signal Function ........................................................................................................................................ 51
3.4. Control Functions ................................................................................................................................................. 52
3.5. Communication Function ..................................................................................................................................... 53
3.6. Log Function ......................................................................................................................................................... 54
3.6.1. SOE Logs ......................................................................................................................................................... 54
3.6.2. WFR logs ........................................................................................................................................................ 55
3.6.3. Instantaneous Capturing Function of Waveform ........................................................................................... 56
3.7. Harmonic Analyzing Function............................................................................................................................... 57
3.8. Unbalance Function.............................................................................................................................................. 57
3.9. Time Synchronization Function ............................................................................................................................ 58
3.10. Network Connection ............................................................................................................................................ 61
4. Operating Instructions ............................................................................................................................................. 64
4.1. Front Panel ........................................................................................................................................................... 64

4.2. Keys Operation ..................................................................................................................................................... 64
4.3. Signal Indicator Lights........................................................................................................................................... 65
4.4. Default Display Menu ........................................................................................................................................... 65
4.5. Logs ...................................................................................................................................................................... 67
4.6. Menu .................................................................................................................................................................... 67
4.6.1. Measurements ............................................................................................................................................... 69
4.6.2. View Setup ..................................................................................................................................................... 70
4.6.3. Config. Setup .................................................................................................................................................. 72
4.6.4. Logs Management ......................................................................................................................................... 80
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4.6.5. Power Quality ................................................................................................................................................ 82
4.6.6. Maintenance .................................................................................................................................................. 82
4.6.7. Factory ........................................................................................................................................................... 83
4.6.8. Settings List .................................................................................................................................................... 83
5. Installation and Debugging ...................................................................................................................................... 93
5.1. Installation ............................................................................................................................................................ 93

5.1.1. Installation Chart ............................................................................................................................................ 93
5.1.2. Backplane Terminal Layout ............................................................................................................................ 93
5.2. RTC battery ......................................................................................................................................................... 100
5.3. Power-On Test .................................................................................................................................................... 100
5.4. Debugging before being Put into Operation ...................................................................................................... 101
5.5. Device Fault Analysis .......................................................................................................................................... 103
6. Wiring Diagram ...................................................................................................................................................... 105
6.1. Schematic Wiring Diagram ................................................................................................................................. 105

6.2. Diagram of Operation Circuit.............................................................................................................................. 109
6.2.1. DC Operation Circuit .................................................................................................................................... 109
6.2.2. AC Operation Circuit .................................................................................................................................... 110
7. After-sales Service Commitment ........................................................................................................................... 112
7.1. Device Upgrading ............................................................................................................................................... 112

7.2. Quality Assurance Scope .................................................................................................................................... 112
7.3. After-sales Contact Method ............................................................................................................................... 112
III
PMC-851D User Manual
1. Introduction
1.1. Overview
PMC-851D is a bus-tie Breaker protection and automatic transfer switch relay developed meticulously by
CET and applicable to middle and high voltage level power system. PMC-851D adopts high-end configuration
in hardware design, and special protection algorithm and high-reliability real-time multi-task operating
system in software configuration, and supports Ethernet-based IEC-61850 international standard protocol.
1.2. Features
 Adopting high-performance 32-bit dual-core processor with dominant frequency of 300MHz, 64-bit
high-speed floating-point DSP, 16-bit high-performance synchronous sampling A/D, big-capacity
high-speed non-volatile memory chip with infinite number of reading and writing times, big liquid
crystal display, graphical interface;
 Two Ethernet communication interfaces (optional 10/100 base-T, 100 base-FX): Supporting ring
network, and failover switching function;
 Supporting IEC61850 protocol, MODBUS-TCP/RTU protocol and IEC 60870-5-103 protocol;
 PMC-851D is equipped with complete protection functions, has reliable performance, and operates
quickly;
 Online switching of eight groups of protection settings, and support copy one group of protection
setting to each other;
 Flexible configuration of protection outputs;
 Flexible design of operation circuit which is applicable to various kinds of electrical facilities;
 2nd~63th harmonic analysis of three-phase currents and three-phase voltages;
 Perfect remote control and central signal output functions: It’s available to control the switch
through communication port, device panel and binary input, etc.;
 Big capacity, and 512 entries of event logs supporting classified query (resolution 1ms);
 Long-time WFR records (available to maintain for more than 10 years in case of power failure), and
unique fault logs graph;
 Instantaneous high-speed waveform capturing function;
 Supporting IRIG-B timing, GPS hard pulse timing, and SNTP network timing;
 PMC-851D software and hardware have perfect self-check function;
 It supports online software upgrading;
 Fully-closed case is adopted to separate strong and weak current completely. Corresponding
anti-interference measure is adopted for software to realize top grade of various criteria of
electromagnetic compatibility;
 Meeting the most adverse application environment: Meeting the requirement of wide operating
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temperature (-25℃~+70℃);
 PMC-851D may be installed in a scattered way locally, or be installed by screen combination
collectively.
1.3. Functions
Table 1-1 Functions
PMC-851D Detailed Description

Bus-tie measuring current inputs: Ia, Ib, Ic
Bus-tie protection current inputs: IA, IB, IC
Line 1# current input: IA1
14-channel analog Line 2# current input: IA2
inputs BusⅠ voltage inputs: VAB1, VBC1
Line 1# voltage input: VS1(be connected to phase-to-phase voltage VAB)
Bus Ⅱ voltage inputs: VAB2, VBC2
Line 2# voltage input: VS2(be connected to phase-to-phase voltage VAB)
14-channel external digital inputs:
IN1: status of QF1 (line 1# breaker)
IN2: status of QF2 (line 2# breaker)
IN3: status QF3 (tie breaker)
IN4: digital input to enable ATS
IN5: digital input to enable ART
IN6: digital input to block 50P-1
19-channel digital IN7: manual synchronism closing input
inputs IN8: SOTF_DI input
IN9~IN14: user-defined to block ATS
5-channel internal digital inputs (get from operate board):
Remote Position
BRK Closed
BRK Open
Ext. Trip Position
KKJ signal
2
6-channel user-defined digital outputs:

OUT1~OUT6
7-channel defined digital outputs:
Close (operate automatically after ATS_B close tie BRK operate)
13-channel digital Trip (can collocated freely)
outputs R-trip
R-close (operate automatically after 25 remote close operate)
Alarm
KKJ OUT
Link output (doesn’t be controlled by CPU)
AO 1-channel AO (optional): 4～20mA, built-in 24V DC power supply
Timing interface 1-channel timing interface: Differential signal method (supporting IRIG-B and GPS timing)
Bus-Tie Breaker Protection:
SOTF-1, SOTF-2, SOTF ATS, SOTF DI
50P-1, 50P-2, 50P-3, 50P-4, 50P-5, 51P
SOTF_I0-1, SOTF_I0-2, SOTF_I0-ATS
50I0-1, 50I0-2, 51I0
59PP_B1-1, 59PP_B1-2, 59PP_B2-1, 59PP_B2-2, 27PP_B1-1, 27PP_B1-2, 27PP_B2-1,
27PP_B2-2, 27PP
81O_B1-1, 81O_B1-2, 81O_B2-1, 81O_B2-2, 81U_B1-1, 81U_B1-2, 81U_B2-1, 81U_B2-2,
Protection/
81U
Automatic Transfer
32P-1, 32P-2
Switch
25
LOP_B1, LOP_B2, CT Monitor, 74TC
DI Protection
Automatic Transfer Switch:
27PS, 50PS, 50P_L1, 50P_L2
ATS_B1, ATS_B2, ATS_L1, ATS_L2
25_L1, 25_L2
50LS_L1-1, 50LS_L1-2, 50LS_L1-3, 50LS_L2-1, 50LS_L2-2, 50LS_L2-3
Phase-to-phase voltages, phase currents, frequency, active power, reactive power, and
Measuring Function
apparent power, etc.
Metering Function Bi-directional active energy, Bi-directional reactive energy
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2nd~63th harmonic analysis of three-phase currents and three-phase voltages, in which

Harmonic Analyzing 2nd~31th harmonics meet the requirement of level B meter. Analyzing contents include
Function total harmonic distortion (THD), total odd/even harmonic distortion (TOHD/TEHD), and
harmonic ratio (HR).
Wave Recording COMTRADE Wave-recording File
Function Reserving the latest 8 WFR logs, the latest 5 WFC logs.
SOE Logs 512 events, including DI/DO logs, Relay logs, Diagnosis logs, Maintenance logs.
Ethernet communication port: 2 channels
(10/100 base-T, 100 base-FX optional, supporting switch mode, ring network mode, and
Communication
failover switching mode)
RS-485 communication port (optional): 1 channel;
Communication IEC61850 protocol, MODBUS-TCP protocol, MODBUS-RTU protocol
Protocol and IEC 60870-5-103 protocol
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2. Technical specifications
2.1. Environment Parameters
1) Operating temperature: -25℃ ～+70℃
2) Storage temperature: -40℃～+85℃
3) Atmospheric pressure: 70 kPa～110 kPa
4) Relative humidity: 5%～95% (Non-condensing)
5) Above sea level: <3000m
2.2. Rated Parameters

1) Power supply: 88～264V 50/60Hz AC/DC
2) Rated phase current: 5A, 1A
3) Rated phase-to-phase voltage: 100V
4) Rated operation board voltage: DC220V/100V or AC220V
5) Rated frequency: 50Hz/60Hz
6) Power consumption
 AC current loop: 5A configuration, no more than 1VA/phase;
1A configuration, no more than 0.5VA/phase
 AC voltage loop: No more than 0.5VA/phase
 Operating power supply circuit: No more than 10W
2.3. Accuracy
1) Accurate working scope
 Measurement current: 0.01In~1.2In
 Protective current: 0.04In~20In
 Frequency: 45.00~65.00Hz
 Voltage: 0.4~120V
2) Accuracy of protection settings
 Current setting: ≤±2.5% or ±0.01In
 Voltage setting: ≤±2.5% or 1V
 Frequency setting: ≤±0.02Hz
 Direction angle: ≤±3°
3) Time setting accuracy
 Natural action time: ≤40ms (impose 1.5X action setting excitation for over-protection, and 0.7X
action setting excitation for under-protection)
 Definite time-lag action time: ≤±40ms or 1% (impose 1.5X action setting excitation for
over-protection, and 0.7X action setting excitation for under-protection)
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 Inverse time limit action time: ≤±5% (1 – I/(Iset*80)) or ±40ms, I is the exciting current imposed,
while Iset is the set current value.
4) Measurement accuracy
Table 2-1 Measurement Accuracy
Parameters Accuracy Maximum resolution
Primary voltage 0.2% 0.001kV
Primary current 0.2% 0.001A
Secondary voltage 0.5% 0.01V
Secondary current 0.5% 0.001A
Active power 0.5% 0.001kW
Reactive power 0.5% 0.001kvar
Power factor 1.0% 0.001
Frequency 0.02Hz 0.001Hz
Harmonic analyzing Level B (2nd~31th) 0.01%
Bi-directional Real Energy Level 0.5S 1kWh
Bi-directional Reactive Energy Level 2 1kvarh
5) AO error: ±0.5% , (4～20mA), loading capacity 500Ω
2.4. Digital Input Resolution

The resolution of digital input is 1ms.
2.5. Overload Capacity

1) AC current loop: 2X rated current, working continuously; 10X rated current, 10s allowed; and 40X
rated current, 1s allowed
2) AC voltage loop: 2X rated voltage, working continuously; 3.0X rated voltage, 10s allowed
2.6. Digital Outputs

1) Turn-on capacity: 5A, continuous; 30A, 0.2s
2) Action time: <10 ms
3) Dropout time: <5 ms
4) Breaking capacity: DC, resistive 50W; inductive 35W (L/R = 0.04s), AC, 1250VA, max 5A
2.7. Digital Inputs

Excitation power supply: 220V DC/AC, 110V DC/AC
2.8. Marked degree of protection

Panel: IP51
6
2.9. Torque
Power supply terminal：0.8N.m
Voltage & Current Inputs terminal：1.5N.m
Other terminal： 0.5N.m
2.10. Electrical Insulation Requirements

1) Dielectric strength
Complies with IEC 60255-5; 2kV@1minute.
2) Insulation resistance
Complies with IEC 60255-5; >100MΩ/500V AC.
3) Impulse voltage
Complies with IEC 60255-5; 5kV, 1.2/50μs.
2.11. Mechanical Tests

1) Sinusoidal Vibration
 Response: Complies with IEC 60255-21-1, Level 1;
 Endurance: Complies with IEC 60255-21-1, Level 1.
2) Shock Test
 Response: Complies with IEC 60255-21-2, Level 1;
 Endurance: Complies with IEC 60255-21-2, Level 1.
3) Bump Test: Complies with IEC 60255-21-2, Level 1.
2.12. Electromagnetic Compatibility

1) Damped Oscillatory Burst: Complies with IEC 60255-22-1, Level III.;
2) Electrostatic Discharge Immunity: Complies with IEC 60255-22-2, Level Ⅳ;
3) Radiated electromagnetic field: Complies with IEC 60255-22-3, 10V/m highest severity level;
4) Electrical fast transient / burst immunity: Complies with IEC 60255-22-4, Level A;
5) Surge immunity: Complies with IEC 60255-22-5, Level Ⅳ;
6) Radio frequency conduction disturbances: Complies with IEC 60255-22-6, Level III.;
7) Power frequency magnetic field interference: Complies with IEC 61000-4-8, Level Ⅳ;
8) Power frequency immunity: Complies with IEC 60255-22-7, Level A;
9) Electromagnetic emission test: Complies with IEC 60255-25.
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3. Function description
3.1. Protection function
The protection function of PMC-851D includes bus-tie breaker protection and automatic transfer (ATS)
switch relay. ATS includes ATS_B1, ATS_B2, ATS_L1, ATS_L2, all of them can select ART (automatic retransfer)
function.
“System->Main Diagram” can be collocated to “Mode 1”, “Mode 2”, or “Mode 3”, as shown in following
figure:
QF
Bus Ⅰ Bus Ⅱ
Mode 1
Line 1# Line 2#
QF1 QF2
QF3
Bus Ⅰ Bus Ⅱ
Mode 2
Line 1# Line 2#
QF1 QF2
QF3
Bus Ⅰ Bus Ⅱ
Mode 3
If “System->Main Diagram” is collocated to “Mode 1”, PMC-851D only adopts bus-tie breaker protection,
without ATS.
If “System->Main Diagram” is collocated to “Mode 2”, PMC-851D adopts bus-tie breaker protection, ATS
and ART.
If “System->Main Diagram” is collocated to “Mode 3”, PMC-851D adopts bus-tie breaker protection and
ART.
The transfer diagram of ATS and ART is shown in following figure:
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Line 1# Line 2#
Status 1
QF1 Cloesd QF2 Cloesd
QF3 Open
Bus Ⅰ Bus Ⅱ
AT
1
_B
S _B
S
AT
2
B1
AR
T_
T_
AR
B2
Line 1# Line 2# Line 1# Line 2#
ATS_L2 or ART_L1
Status 2 ATS_L1 or ART_L2 Status 3

QF1 Cloesd QF2 Open QF1 Open QF2 Cloesd
QF3 Cloesd QF3 Cloesd
Bus Ⅰ Bus Ⅱ Bus Ⅰ Bus Ⅱ
Transfer diagram of ATS and ART
In status 1, under the condition of ATS_B1 logic, if Line 2# loses its power, it will trip QF2 first, and then
close QF3, and then the running status changes from status 1 to status 2. In status 2, after the voltage recovery
of Line 2#, if “ATS_B1-> ART_B1” is not collocated to “Off”, it will step in the logic of automatic recovery transfer.
If “ATS_B1-> ART_B1” is collocated to “Mode 1” and ART_B1 gets ready, PMC-851D will close QF2 when the
conditions of synchronization check are met, and then trip QF3; if “ATS_B1->ART_B1” is collocated to “Mode 2”,
PMC-851D will trip QF3 first, and then close QF2, and then the running status recovers from status 2 to status
1.
1.
In status 3, under the condition of ATS_L1 logic, if Line 2# loses its power, it will trip QF2 first, and then
of Line 2#, if “ATS_L1-> ART_L1” is not collocated to “Off”, it will step in the logic of automatic recovery transfer.
If “ATS_L1-> ART_L1” is collocated to “Mode 1” and ART_L1 gets ready, PMC-851D will close QF2 when the
conditions of synchronization check are met, and then trip QF1; if “ATS_L1->ART_L1” is collocated to “Mode 2”,
3.
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2.
3.1.1. Auxiliary Element
1) Compound voltage element (27E/59Neg.E)
Because PMC-851D has two busbars, compound voltage element is judged by voltages of two busbars. If
neither of two busbars is LOP(Loss-of-Potential), 27E/59Neg.E operates only when voltages of two busbars
meet the operating conditions; if one of two busbars is LOP, 27E/59Neg.E operates when the busbar voltage
which is not LOP meet the operating conditions; if both of two busbars are LOP, 27E/59Neg.E operates only
when “LOP_B1->27E/59Neg.E” and “LOP_B2->27E/59Neg.E” are both collocated to “Release”.
27 Element On
&
Ullmin < Ud ≥1
& “27E/59Neg.E Operate”
59Neg. Element On
&
U2 > U2d
LOP
&
LOP release 27E/59Neg. E.
&
27 Element Off
&
59Neg. Element Off
Fig. 3-1 Logic diagram of 27E/59Neg.E

Compound voltage element operates in case one of the following conditions occurs:
 27 Element is on and the minimum value of phase-to-phase voltages is less than fixed value(Ud);
 59Neg. Element is on and the negative sequence voltage is more than fixed value(U2d);
 LOP operates and selects “release” as the control option for compound voltage element.
Compound voltage element block condition is one of the following:
 LOP operates and selects “Block” as the control option for compound voltage element.
 27 Element and 59Neg. Element are all “Off”;
When operation condition and block condition exist at the same time, block has priority.
Drop-off to pick-up ratio of low voltage element is 1.05; Drop-off to pick-up ratio of negative sequence
voltage element is 0.95.
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2) Phase over-current elements (50P-E1, 50P-E2, 50P-E3)

PMC-851D has 3 sections phase over-current elements (50P-E1, 50P-E2, 50P-E3).
“50P-E1 Operate”
50P-E1 On
&
Imax > Id Output
Fig. 3-2 Logic Diagram of 50P-E1

When the phase over-current element is on, any of the three-phase current values is more than the fixed
value (Id), then the phase over-current element operates. Drop-off to pick-up ratio is 0.95.
3.1.2. Phase Current SOTF Protection (SOTF-1, SOTF-2)
PMC-851D has 2 sections phase current SOTF protections (SOTF-1, SOTF-2). Phase current SOTF
protection is released only during a period of time after the circuit breaker switches from open to close. The
period of time can be collocated under the “Config. Setup->Relay-> Aux. Element->SOTF Time” menu.
The status of tie breaker gets from operate board or digital input IN3 which can be collocated through
“System->Breaker State Config.->Tie BRK”.
SOTF-1 On
DI strap meets conditions “SOTF-1 Operate”
t 0
SOTF Release &
delay
Imax > Id Output
27E/59Neg.E Off
≥1
27E/59Neg.E Operate
Fig. 3-3 Logic diagram of SOTF-1

When the following conditions are met at the same time, after delay setting, SOTF-1 operates:
 SOTF-1 is on;
 DI strap meets conditions: DI strap selects “Off”, or selects input DI and corresponds to DI position;
 SOTF is released;
 Imax > Id. Imax is the maximum value of three-phase currents; Id is the fixed current value of SOTF-1;
 Compound voltage element is off or it operates.
After phase current SOTF protection operates, “Trip” indicator lamp lights up. Drop-off to pick-up ratio is
0.95.
3.1.3. Phase Current Acceleration SOTF Protection (SOTF_ATS)
Phase current Acceleration SOTF protection is released only during a period of time after ATS_B1 or
ATS_B2 operates and controls tie breaker switching from open to close. The period of time can be collocated
under the “Config. Setup->Relay-> Aux. Element->SOTF Time” menu.
11
SOTF_ATS On
DI strap meets conditions “SOTF_ATS Operate”
t 0
SOTF_ATS Release &
delay
Imax >Id Output
27E/59Neg.E Off
≥1
27E/59Neg.E Operate
Fig. 3-4 Logic diagram of SOTF_ATS

When the following conditions are met at the same time, after delay setting, SOTF_ATS operates:
 SOTF_ATS is on;
 SOTF_ATS is released;
 Imax > Id. Imax is the maximum value of three-phase currents; Id is the fixed current value of
SOTF_ATS;
After SOTF_ATS operates, “Trip” indicator lamp lights up. Drop-off to pick-up ratio is 0.95.
3.1.4. Phase Current DI SOTF Protection (SOTF_DI)
SOTF_DI is released during a period of time after the IN8 switches from open to close. The period of time
can be collocated under the “Config. Setup->Relay-> Aux. Element->SOTF Time” menu.
SOTF_DI On
DI strap meets conditions “SOTF_DI Operate”
t 0
SOTF_DI Release &
delay
Imax > Id Output
27E/59Neg.E Off
≥1
27E/59Neg.E Operate
Fig. 3-5 Logic diagram of SOTF_DI

When the following conditions are met at the same time, after delay setting, SOTF_DI operates:
 SOTF_DI is on;
 SOTF_DI is released;
 Imax > Id. Imax is the maximum value of three-phase currents; Id is the fixed current value of SOTF_
DI;
After SOTF_DI operates, “Trip” indicator lamp lights up. Drop-off to pick-up ratio is 0.95.
3.1.5. Instantaneous Over-Current Protection with Definite Time (50P-1)
If “Config. Setup->Relay-> 50P-1->DI Block” is collocated to “On”, when digital input IN6 is close, 50P-1 will
be blocked.
12
50P-1 On
DI strap meets conditions “50P-1 Operate”
t 0
Imax > Id &
delay
Output
DI Block Off
≥1
IN6 Deassert
27E/59Neg.E Off
≥1
27E/59Neg.E Operate
Fig. 3-6 Logic diagram of 50P-1

When the following conditions are met at the same time, after delay setting, instantaneous over-current
protection with definite time operates:
 Instantaneous over-current protection with definite time is on;
 Imax > Id. Imax is the maximum value of three-phase currents; Id is the fixed current value of 50P-1;
 “DI Block” is off, or IN6 is deasserted;
 Compound voltage elements is off or it operates.
After instantaneous over-current protection with definite time operates, “Trip” indicator lamp lights up.
Drop-off to pick-up ratio is 0.95.
3.1.6. Definite Time Over-Current Protection (50P-2, 50P-3, 50P-4)
PMC-851D has 3 sections definite time over-current protections (50P-2, 50P-3, 50P-4). These sections are
independent with each other, but their logics are all the same.
50P-2 On
DI strap meets conditions “50P-2 Operate”
t 0
Imax > Id &
delay
Output
27E/59Neg.E Off
≥1
27E/59Neg.E Operate

When the following conditions are met at the same time, after delay setting, 50P-2 operates:
 50P-2 is on;
 Imax > Id. Imax is the maximum value of three-phase currents; Id is the fixed current value of 50P-2;
 Compound voltage elements is off or it operates.
After definite time over-current protection operates, “Trip” indicator lamp lights up. Drop-off to pick-up
ratio is 0.95.
13
3.1.7. Overload Protection (50P-5)
50P-5 On “50P-5 Operate”

t 0
DI strap meets conditions &
delay
Imax > Id Output

When the following conditions are met at the same time, after delay setting, overload protection
operates:
 Overload protection is on;
 Imax > Id. Imax is the maximum value of three-phase currents; Id is the fixed current value of
overload protection.
After overload protection operates, “Trip” or “Alarm” indicator lamp is optional. Drop-off to pick-up ratio
is 0.90.
3.1.8. Inverse Time Over-Current Protection (51P)
51P On
&
DI strap meets conditions
“51P Operate”
Inverse
Imax
Curve
Output
Fig. 3-9 Logic diagram of 51P

Inverse time over-current protection supports 10 kinds of inverse curves including IEC and US standard.
IEC standard curves：
Curve Name Operate Formula Return Formula
C1  0.14   13.5 
tp=TD*   tr=TD*  2
 1 1  M 
0.02
Normal Inverse M
C2  13.5   47.3 
tp=TD*   tr=TD*  2
Very Inverse  M  1 1  M 
C3
 80.0   80.0 
Extremely tp=TD*   tr=TD*  2
 M  1 1  M 
2
Inverse
C4 120.0  120.0 
tp=TD*   tr=TD*  
Long Inverse  M  1 1  M 
C5  0.05   4.85 
tp=TD*  tr=TD*  2
 M 1 1  M 
0.04
Short Inverse
14
US standard curves：
Curve Name Operate Formula Return Formula
U1  0.0104   1.08 
tp=TD* 0.0226   tr=TD*  2
Moderately Inverse  M 0.02  1  1  M 
U2  5.95   5.95 
tp=TD* 0.180   tr=TD*  2
Inverse  M 2  1 1  M 
U3  3.88   3.88 
tp=TD* 0.0963   tr=TD*  2
Very Inverse  M 2  1 1  M 
U4
 5.67   5.67 
Extremely tp=TD* 0.0352   tr=TD*  2
 M 2  1 1  M 
Inverse
U5  0.00342   0.323 
tp=TD* 0.00262   tr=TD*  2
Short Inverse  M 0.02  1 1  M 
In the formulas above, M=Imax/Ip, Ip is the fixed value of pickup, Imax is the maximum value of
three-phase currents, TD is the multiple of time dial, tp is the operation time, tr is the reset time.
The “Time Dial” of C1~C5 curve should be collocated to 0.05~1.00, while “Time Dial” of U1~U5 curve
should be collocated to 0.50~15.00
The reset model of inverse time over-current protection can be selected as “At Once” or “Equation”. When
“At Once” is selected, the inverse protection will drop out and the accumulated time will be reset after the
maximum value of three-phase currents keeps less than 0.95 times of fixed current continuously for 30ms.
However, when “Equation” is selected, the accumulated time will be reduced according to the formula of tr.
After inverse time over-current protection operates, “Trip” or “Alarm” indicator lamp is optional.
3.1.9. Neutral Current SOTF Protection (SOTF_I0-1, SOTF_I0-2)
PMC-851D has 2 sections neutral current SOTF protections (SOTF_I0-1, SOTF_I0-2). As the same with
phase current SOTF, neutral current SOTF protection is also released only during a period of time after the
circuit breaker switches from open to close.
The status of tie breaker gets from operate board or digital input IN3 which can be collocated through
“System->Breaker State Config.->Tie BRK”.
SOTF_I0-1 On
DI strap meets conditions “SOTF_I0-1 Operate”
& t 0
SOTF_I0 Release
delay
I0 > Id Output
Fig. 3-10 Logic diagram of SOTF_I0-1

When the following conditions are met at the same time, after delay setting, SOTF_I0-1 operates:
15
 SOTF_I0-1 is on;
 SOTF_I0 is released;
 I0 > Id. I0 is the value of zero-sequence current; Id is the fixed value of SOTF_I0-1.
After neutral current SOTF protection operates, “Trip” indicator lamp lights up. Drop-off to pick-up ratio is
0.95.
3.1.10. Neutral Current Acceleration SOTF Protection (SOTF_I0_ATS)
As the same with SOTF_ATS, neutral current acceleration SOTF protection is released only during a period
of time after ATS_B1 or ATS_B2 operates and controls tie breaker switching from open to close. The period of
time can be collocated under the “Config. Setup->Relay-> Aux. Element->SOTF Time” menu.
SOTF_I0_ATS On
DI strap meets conditions “SOTF_I0_ATS Operate”
t 0
SOTF_I0_ATS Release &
delay
I0 >Id Output
Fig. 3-11 Logic diagram of SOTF_I0_ATS

When the following conditions are met at the same time, after delay setting, SOTF_I0_ATS operates:
 SOTF_I0_ATS is on;
 SOTF_I0_ATS is released;
 I0 > Id. I0 is the value of zero-sequence current; Id is the fixed value of SOTF_I0_ATS.
After SOTF_I0_ATS operates, “Trip” indicator lamp lights up. Drop-off to pick-up ratio is 0.95.
3.1.11. Neutral Over-Current Protection (50I0-1, 50I0-2)
PMC-851D has 2 sections neutral over-current protections (50I0-1, 50I0-2).
50I0-1 On “50I0-1 Operate”

t 0
delay
I0 > Id Output
Fig. 3-12 Logic diagram of 50I0-1

When the following conditions are met at the same time, after delay setting, 50I0-1 operates:
 50I0-1 is on;
 I0 > Id. I0 is the value of zero-sequence current; Id is the fixed value of 50I0-1.
After neutral over-current protection operates, “Trip” or “Alarm” indicator lamp is optional. Drop-off to
pick-up ratio is 0.95.
3.1.12. Inverse Time Neutral Over-Current Protection (51I0)
Inverse time neutral over-current protection supports 10 kinds of inverse curves including IEC and US
16
standard, which are all the same with Inverse time over-current protection (see 3.1.8 for details).
51I0 On
&
“51I0 Operate”
Inverse
I0
Curve
Output
Fig. 3-13 Logic diagram of 51I0

After inverse time neutral over-current protection operates, “Trip” or “Alarm” indicator lamp is optional.
3.1.13. Single-Bus Over-Voltage Protection (59PP_B1-1, 59PP_B1-2, 59PP_B2-1, 59PP_B2-2)
Two busbars have 2 sections over-voltage protections respectively (59PP_B1-1, 59PP_B1-2, 59PP_B2-1,
59PP_B2-2).
59PP_B1-1 On “59PP_B1-1 Operate”

t 0
delay
Ullmax > Ud Output
Fig. 3-14 Logic diagram of 59PP_B1-1

When the following conditions are met at the same time, after delay setting, 59PP_B1-1 operates:
 59PP_B1-1 is on;
 Ullmax > Ud; Ullmax is the maximum value of three phase-to-phase voltages of corresponding busbar;
Ud is the fixed value of 59PP_B1-1.
When Single-Bus over-voltage protection operates, “Trip” or “Alarm” indicator lamp is optional. Drop-off
to pick-up ratio is 0.98.
3.1.14. Single-Bus Under-Voltage Protection (27PP_B1-1, 27PP_B1-2, 27PP_B2-1, 27PP_B2-2)
Two busbars have 2 sections single-bus under-voltage protections respectively (27PP_B1-1, 27PP_B1-2,
27PP_B2-1, 27PP_B2-2).
The condition of “Ever Volt” can avoid output of the protection being operating continuously after busbar
of substation lose power.
Ever Volt ON “Ever Volt”

& ≥1 &
0.1s 0
Ullmax > 1.05 * Ud
Relay
27PP_B1-1 Start
Fig. 3-15 Logic diagram of “Ever Volt” in 27PP_B1-1

The flag of “Ever Volt” is set and latched when “Ever Volt” is on and Ullmax > 1.05Ud, in which Ullmax is
the maximum value of three phase-to-phase voltages of corresponding busbar, and Ud is the fixed value of
under-voltage. The flag of “Ever Volt” is reset when single-bus under-voltage protection operates.
17
27PP_B1-1 On
LOP “27PP_B1-1 Operate”
t 0
&
delay
Ever Volt Off Output
≥1
Ever Volt is set
Ullmax < Ud
&
dU/dt Block On
& ≥1
dU/dt > Pickup
Fig. 3-16 Logic diagram of 27PP_B1-1

When the following conditions are met at the same time, after delay setting, 27PP_B1-1 operates:
 27PP_B1-1 is on;
 LOP doesn’t operate;
 “Ever Volt” is off or its flag is set.
 Ullmax < Ud; Ullmax is the maximum value of three phase-to-phase voltages and Ud is the fixed value
of 27PP_B1-1;
 The flag of “du/dt Block” is reset.
The flag of “du/dt Block” is set and latched when “du/dt Block” is on and du/dt is more than the pickup
value. The flag of “du/dt Block” is reset when Ullmax is more than Ud.
After single-bus under-voltage protection operates, indicator lamp is optional; Drop-off to pick-up ratio is
1.05.
3.1.15. Under-Voltage Protection (27PP)
If “du/dt Block” is collocated to “On”, du/dt of two busbars will be judged.
If LOP_B1 and LOP_B2 don’t operate together, the flag of “du/dt Block” is set when du/dt of two busbars
are all more than the pickup value. If only LOP_B1 operates, the flag of “du/dt Block” is set when du/dt of
busbar Ⅱ is more than the pickup value. If only LOP_B2 operates, the flag of “du/dt Block” is set when du/dt
of busbar Ⅰ is more than the pickup value. If LOP_B1 and LOP_B2 operate together, 27PP will be blocked.
When the flag of “du/dt Block” is set, it will be latched, and be released when Ullmax_all is more than Ud.
18
27PP On
DI strap meets conditions “27PP Operate”
t 0
Imax > 0.02Inom
& Delay
Output
LOP_B1 Operate
&
LOP_B2 Operate
Ullmax_all < Ud
dU/dt Block
& ≥1 &
dU/dt > Pickup
Fig. 3-17 Logic diagram of 27PP

When the following conditions are met at the same time, after delay setting, 27PP operates:
 27PP is on;
 Imax>0.02Inom; Imax is the maximum value of three-phase currents; Inom is the rated current.
 LOP_B1 and LPP_B2 are not all operated;
 Ullmax_max < Ud; Ullmax_max is the maximum value of all phase-to-phase voltages of two busbars;
Ud is the fixed value of 27PP;
 The flag of “du/dt Block” is reset.
After under-voltage protection operates, indicator lamp is optional; Drop-off to pick-up ratio is 1.05.
3.1.16. Single-Bus Over-Frequency Protection (81O_B1-1, 81O_B1-2, 81O_B2-1, 81O_B2-2)
Two busbars have 2 sections single-bus over-frequency protections respectively (81O_B1-1, 81O_B1-2,
81O_B2-1, 81O_B2-2).
81O_B1-1 On “81O_B1-1 Operate”
t 0
delay
f > fd Output
Fig. 3-18 Logic diagram of 81O_B1-1

When the following conditions are met at the same time, after delay setting, 81O_B1-1 operates:
 81O_B1-1 is on;
 f > fd; f is frequency of corresponding busbar; fd is fixed value of frequency.
After single-bus over-frequency protection operates, the indicator lamp is optional. Frequency drop-off
value is 0.10Hz less than the fixed value.
3.1.17. Single-Bus Under-Frequency Protection (81U_B1-1, 81U_B1-2, 81U_B2-1, 81U_B2-2)
Two busbars have 2 sections single-bus under-frequency protections respectively (81U_B1-1, 81U_B1-2,
81U_B2-1, 81U_B2-2).
19
The flag of “df/dt Block” is set and latched when “df/dt Block” is on and df/dt is more than the pickup
value. The flag of “df/dt Block” is reset when frequency is more than fd.
Single-bus under-frequency protection will be blocked if the phase-to-phase voltages of corresponding
busbar are all less than 15V.
81U_B1-1 On
“81U_B1-1 Operate”
f < fd t 0
&
delay
Output
df/dt Block On &
& ≥1
df/dt > Pickup
Fig. 3-19 Logic diagram of 81U_B1-1

When the following conditions are met at the same time, after delay setting, 81U_B1-1 operates:
 81U_B1-1 is on;
 f < fd, f is system frequency of corresponding busbar, fd is fixed value of frequency;
 The flag of “df/dt Block” is reset.
After single-bus under-frequency protection operates, the indicator lamp is optional. Frequency drop-off
value is 0.10Hz more than the fixed value.
3.1.18. Under-Frequency Protection (81U)
Under-frequency protection adopts two frequencies of two busbars to judge. If f1 and f2 are all normal,
81U starts when f1 and f2 are all more than the pickup value; If only f1 is normal, 81U starts when f1 is more
than the pickup value; If only f2 is normal, 81U starts when f2 is more than the pickup value; If f1 and f2 are all
abnormal, 81U will be blocked.
If “df/dt Block” is collocated to “On”, df/dt of two busbar will be judged.
If f1 and f2 are all normal, the flag of “df/dt Block” is set when df/dt of two busbars are all more than the
pickup value. If only f1 is normal, the flag of “df/dt Block” is set when df/dt of busbar Ⅰ is more than the
pickup value. If only f2 is normal, the flag of “df/dt Block” is set when df/dt of busbar Ⅱ is more than the
pickup value.
When flag of “df/dt Block” is set, it will be latched, and be released when f1 and f2 are all more than
pickup value.
Under-frequency protection will be blocked if all phase-to-phase voltages of two busbars are all less than
15V.
20
81U On
Imax > 0.02Inom
“81U Operate”
f < fd t 0
&
delay
Output
df/dt Block On &
& ≥1
df/dt > Pickup
Fig. 3-20 Logic diagram of 81U

When the following conditions are met at the same time, after delay setting, 81U operates:
 81U is on;
 Imax>0.02Inom; Imax is the maximum value of three-phase current; Inom is the rated current.
 f < fd, f is system frequency of corresponding busbar, fd is fixed value of frequency;
 The flag of “df/dt Block” is reset.
After under-frequency protection operates, the indicator lamp is optional. Frequency drop-off value is
0.10Hz more than the fixed value.
3.1.19. Power Protection (32P-1, 32P-2)
PMC-851D has 2 sections power protections (32P-1, 32P-2).
32P-1 On “32P-1 Operate”

t 0
& delay
LOP Output
Direction forward
& ≥1
P > Pd
&
P < (-Pd)

When the following conditions are met at the same time, after delay setting, 32P-1 operates:
 32P-1 is on;
 The flag of LOP has been reset;
 P > Pd or P < (-Pd). P is the value of power; Pd is the fixed value of 32P-1.
The power is calculated by bus Ⅰ voltages and protection currents.
After power protection operates, “Trip” or “Alarm” indicator lamp is optional. Drop-off to pick-up ratio is
0.95.
21
3.1.20. Synchronization Check (25)
25 On
DI Strap meets conditions
25 Element Operate 10s 0
& “Busbar Voltage Abnormal”
Ullmin > 90V Delay
Breaker Closed
≥1
Imax > 0.02Inom
Fig. 3-22 Logic diagram of busbar voltage abnormal

When the following conditions are met at the same time, after delay 10s, busbar voltage abnormal
operates, “Alarm” indicator lamp lights up:
 Synchronization check is on;
 25 element doesn’t operate;
 The status of circuit breaker is closed, or Imax > 0.02Inom. Imax is the maximum value of three-phase
currents; Inom is the rated current.
25 On
UAB1 > 0.7Unom
UAB2 > 0.7Unom 25 Element Operate
&
Frequency Qualified
Angle Diff. Qualified
Voltage Diff. Qualified
Fig. 3-23 Logic diagram of 25 element

If all the following conditions are met at the same time, 25 element operates:
 Synchronization check is on.
 The magnitude of UAB1 is larger than 0.7 times of rated voltage.
 The magnitude of UAB2 is larger than 0.7 times of rated voltage.
 The frequency deviation of UAB1 and rated voltage, UAB2 and rated voltage should be less than 1Hz;
the frequency difference should be qualified.
 The voltage difference should be qualified.
 The angle difference should be qualified.
22
25 On
DI Strap meets conditions & 25 Close Release
25 Element Operate
≥1
Ull1max < 30V
Ull2max < 30V
0 30s
25 Close Operate
Fig. 3-24 Logic diagram of 25 close release

25 close is released when all the following conditions are met at the same time:
 Synchronization check is on;
 One of the following conditions occurs: 25 element operates, or Ull1max < 30V, or Ull2max < 30V,
Ull1max is the maximum value of phase-to-phase voltages of bus Ⅰ, Us is the maximum value of
phase-to-phase voltages of bus Ⅱ;
 25 close doesn’t operate in the latest 30s.
After 25 close operates (including 25 manual close and 25 remote close), the function will be blocked for
30s to avoid continuous closing operation.
25 Manual Close On “25 Manual Close Operate”

25 close Release
&
Output
1s 0
IN7 Asserted
delay
Fig. 3-25 Logic diagram of 25 manual close

25 manual close operates when all the following conditions are met at the same time:
 25 manual close is on;
 25 close is released;
 Manual synchronism closing input (IN7) is asserted for 1s.
25 Remote Close On “25 Remote Close Operate”

25 Close Release
&
Output
0 t
Remote Close Command
Fig. 3-26 Logic diagram of 25 remote close

25 remote close operates when all the following conditions are met at the same time:
 25 remote close is on.
23
 25 close is released.
 The closing command from communication is received in the check time.
If the check time reached and the 25 remote close is still not operated, then the log of “25 Remote Close
Fail” is generated.
3.1.21. Loss of Potential (LOP_B1, LOP_B2)
When the following conditions are met at the same time, after 10s of time delay, loss of potential
operates:
Two busbars have loss of potential protection respectively (LOP_B1, LOP_B2). If the “27E/59Neg.E” is
collocated to “Release”, the compound voltage element will be released if corresponding busbar is LOP; if the
“27E/59Neg.E” is collocated to “Block”, the compound voltage element will be blocked if corresponding busbar
is LOP.
LOP_B1 On
Ullmin > 0.9Unom
Imax > 0.02Inom “LOP_B1 Operate”

& 10s 0
Ullmax < 0.2Unom &
≥1 & delay ≥1
Output
|Uab-Ubc| > 0.2Unom

|Ubc-Uca| > 0.2Unom ≥1
|Uca-Ubc| > 0.2Unom
Fig. 3-27 Logic diagram of LOP_B1

When the following conditions are met at the same time, after 10s of time delay, loss of potential
operates and latches:
 Loss of potential is on;
 The maximum phase-to-phase voltages is less than 0.2 times of rated voltage and the maximum
current is larger than 0.02 times of rated current; or phase-to-phase voltages amplitude difference is
larger than the 0.2 times of rated voltage.
 The following condition is not met: the minimum phase-to-phase voltages is more than 0.9 times of
rated voltage.
Loss of potential reset condition: All phase-to-phase voltages are more than 0.9 times of rated voltage.
After loss of potential operates, “Alarm” indicator lamp lights up.
3.1.22. CT monitor
PMC-851D monitors metering and relay CT circuits respectively, and generates different logs (Protection
CT Abnormal, or Meter CT Abnormal) when the corresponding CT circuit is detected abnormal.
“CT Abnormal”
10s 0
CT Monitor On
& delay
Max (I2、I0) > 0.04In + 0.1Imax Output
Fig. 3-28 Logic diagram of CT monitor

When CT circuit is abnormal, “Alarm” indicator lamp lights up.
24
3.1.23. Control Circuit Monitor (74TC)
“74TC Abnormal”
t 0
74TC On
& delay
BRK Closed = BRK Open Output
Fig. 3-29 Logic diagram of 74TC

If the status of tie breaker gets from operate board, control circuit monitor is released. After control circuit
is abnormal, “Alarm” indicator lamp lights up.
3.1.24. All Power Supply Under-Voltage Protection (27PS)
27PS On
US1 < Ud & “27PS Operate”
US2 < Ud
Ullmax_all < Ud
Fig. 3-30 Logic diagram of 27PS

When the following conditions are met at the same time, after delay setting, all power supply under-voltage
protection operates:
 27PS is on;
 US1 < Ud, US2 < Ud, Ullmax_all < Ud. Ud is the fixed value of 27PS, Ullmax_all is the maximum value
of all phase-to-phase voltages of two busbars.
After all power supply under-voltage protection operates, “Trip” or “Alarm” indicator lamp is optional.
3.1.25. All Power Supply Over-Current Protection (50PS)
50PS On “50PS Operate”

t 0
delay
IA1+IA2 > Id Output
Fig. 3-31 Logic diagram of 50PS

When the following conditions are met at the same time, after delay setting, all power supply
over-current protection operates:
 50PS is on;
 IA1+IA2 > Id; IA1+IA2 is the sum of the vector IA1 and vector IA2; Id is the fixed value of 50PS.
When all power supply over-current protection operates, “Trip” or “Alarm” indicator lamp is optional.
25
3.1.26. Line 1 Over-Current Protection (50P_L1)
50P_L1 On “50P_L1 Operate”

t 0
delay
IA1 > Id Output
Fig. 3-32 Logic diagram of 50P_L1

When the following conditions are met at the same time, after delay setting, line 1 over-current
 50P_L1 is on;
 IA1 > Id; Id is the fixed value of 50P_L1.
When line 1 over-current protection operates, “Trip” or “Alarm” indicator lamp is optional. Drop-off to
3.1.27. Line 2 Over-Current Protection (50P_L2)
50P_L2 On “50P_L2 Operate”

t 0
delay
IA1 > Id Output
Fig. 3-33 Logic diagram of 50P_L2

When the following conditions are met at the same time, after delay setting, line 2 over-current
 50P_L2 is on;
 IA > Id; Id is the fixed value of 50P_L2.
When line 2 over-current protection operates, “Trip” or “Alarm” indicator lamp is optional. Drop-off to
3.1.28. Breaker Status Monitor
Breaker status monitor protection is always on.
“BRK1 Abnormal Operate”

IA1 > 0.02Inom t 0
&
BRK1 Open delay
Output
Fig. 3-34 Logic diagram of BRK1 abnormal

When the following conditions are met at the same time, after delay 1s, BRK1 abnormal operates, and
“Alarm” indicator lamp lights up:
 IA1 > 0.02Inom; Inom is the rated current;
 The status of line 1# breaker is open.
26
“BRK2 Abnormal Operate”

IA2 > 0.02Inom t 0
&
BRK2 Open delay
Output
Fig. 3-35 Logic diagram of BRK2 abnormal
“Tie BRK Abnormal Operate”

Imax > 0.02Inom t 0
&
Tie BRK Open delay
Output
Fig. 3-36 Logic diagram of Tie BRK abnormal

The logic of BRK2 abnormal and tie BRK abnormal are similar with the logic of BRK1 abnormal. Imax is the
maximum value of three-phase currents.
3.1.29. Automatic Transfer Switch Block (ATS Block)
ATS is not enable(IN4=0)

50PS Operate
50P_L1 Operate
≥1 “ATS Block Operate”
50P_L2 Operate
BRK1 Abnormal Operate
BRK2 Abnormal Operate
Fig. 3-37 Logic diagram of ATS Block

ATS block operates in case one of the following conditions occurs:
 ATS is not enable (the status of IN4 is open);
 All power supply over-current protection operates;
 Line 1 over-current protection operates;
 Line 2 over-current protection operates;
 BRK1 abnormal operates;
 BRK2 abnormal operates.
3.1.30. DI Block Automatic Transfer Switch (DI Block ATS)
DI block ATS includes following settings: “DI Mode”, “BLK ATS_B1”, “BLK ATS_B2”, “BLK ATS_L1”, “BLK
ATS_L2”. The setting scope of these settings are all between 000000~111111 (6 bits binary number indicates
IN9~IN14, the most left bit indicates IN9 while the most right bit indicates IN14).
“DI Mode”: when a certain bit is collocated to 0, it indicates that ATS is blocked if the status of
corresponding DI is open; when a certain bit is collocated to 1, it indicates that ATS is blocked if the status of
corresponding DI is closed. For example, if “DI Mode” is collocated to 110000, it indicates that ATS is blocked if
the status of IN9 and IN10 is closed, or if the status of IN11~IN14 is open.
“BLK ATS_B1”: when a certain bit is collocated to 1, it indicates that the corresponding DI is used to block
ATS_B1. For example, if “BLK ATS_B1” is collocated to 110000, it indicates that IN9 and IN10 are used to block
ATS_B1.
“BLK ATS_B2”: when a certain bit is collocated to 1, it indicates that the corresponding DI is used to block
ATS_B2. For example, if “BLK ATS_B2” is collocated to 110000, it indicates that IN9 and IN10 are used to block
ATS_B2.
27
“BLK ATS_L1”: when a certain bit is collocated to 1, it indicates that the corresponding DI is used to block
ATS_L1. For example, if “BLK ATS_L1” is collocated to 110000, it indicates that IN9 and IN10 are used to block
ATS_L1.
“BLK ATS_L2”: when a certain bit is collocated to 1, it indicates that the corresponding DI is used to block
ATS_L2. For example, if “BLK ATS_L2” is collocated to 110000, it indicates that IN9 and IN10 are used to block
ATS_L2.
“DI Block ATS Delay” of IN9~IN14 can be collocated separately.
3.1.31. Automatic Transfer Switch of Busbar Ⅰ (ATS_B1)
ATS_B1
Status 1 Status 2
ART_B1
QF1 Cloesd QF2 Closed QF1 Closed QF2 Open
QF3 Open QF3 Closed

Fig. 3-38 Logic diagram of ATS_B1

1.
The status of QF1 gets from digital input IN1, the status of QF2 gets from digital input IN2, The status of
tie breaker gets from operate board or digital input IN3 which can be collocated through “System->Breaker
State Config.->Tie BRK”. IN1~IN3 can be collocated to “NO” (normally open contact) or “NC” (normally closed
contact).
Logic diagram of ATS_B1 charging is shown as follow：
ATS_B1 On
QF1 Closed
t1 0 0 t2
QF2 Closed & “ATS_B1 is Ready”
Delay Delay
QF3 Open
Ullmax_all>Ulive
Fig. 3-39 Logic diagram of ATS_B1 charging

When the following conditions are met at the same time, ATS_B1 begins to charge:
 ATS_B1 is on
 QF1 is closed;
 QF2 is closed;
28
 QF3 is open;
 Ullmax_all > Ulive. Ullmax_all is the maximum value of all phase-to-phase voltages of two busbars;
Ulive is the fixed value of “Live Volt.”.
When the above conditions are met, after delay setting of “Ready Delay” (t1), ATS_B1 is ready, and gets a
SOE recorded of “ATS_B1 is Ready”; when anyone of above conditions is not met, after delay setting of
“Un-Ready Delay” (t2), ATS_B1 is Un-ready.
ATS Block Operate

ATS_B1 Off
Tie BRK Abnormal Operate
QF3 Close ≥1 “ATS_B1 is Un-Ready”
ATS_B1 Close Tie BRK Opreate
ATS_B1 Succeed or failed
DI Block ATS_B1
Fig. 3-40 Logic diagram of ATS_B1 discharge

When anyone of the following conditions is met, ATS_B1 will discharge instantaneously and get a SOE
recorded of “ATS_B1 is Un-Ready”：
 ATS block operates;
 ATS_B1 is off;
 Tie BRK abnormal operates;
 QF3 is close;
 ATS_B1 close tie BRK operates;
 ATS_B1 succeed or failed;
 DI block ATS_B1.
ATS_B1 is Ready
“ATS_B1 Trip BRK2 Operate”
IA2 < 0.02Inom t3 0
&
Ullmax2 < Udead Delay
Output
Trip Check LiveLine Off
≥1
Ullmax1 > Ulive
Fig. 3-41 Logic diagram of ATS_B1 trip BRK2

When the following conditions are met at the same time, after delay setting of “ATS_B1->Trip Delay” (t3),
ATS_B1 trip BRK2 operates, and “Trip” indicator lamp lights up:
 ATS_B1 is Ready;
 IA2<0.02Inon; Inom is the rated current.
 Ullmax2<Udead; Ullmax2 is the maximum value of three phase-to-phase voltages of busbar Ⅱ;
Udead is the fixed value of “Dead Volt.”.
29
 “Trip Check Liveline” is off, or Ullmax1>Ulive, Ullmax1 is the maximum value of three phase-to-phase
voltages of busbar Ⅰ; Ulive is the fixed value of “Live Volt.”.
ATS_B1 is Ready
QF2 Open “ATS_B Close Tie BRK Operate”
t4 0
QF3 Open &
Delay
Ullmax1 > Ulive Output
IA2 < 0.02Inom t3 0

&
Fig. 3-42 Logic diagram of ATS_B1 close tie BRK

When the following conditions are met at the same time, after delay setting of “ATS_B1->Close Delay”
(t4), ATS_B1 close tie BRK operates, and “Trip” indicator lamp lights up:
 QF2 is open;
 QF3 is open;
 Ullmax1>Ulive; Ullmax1 is the maximum value of three phase-to-phase voltages of busbar Ⅰ.
 IA2<0.02Inon, and Ullmax2<Udead are met at the same time over delay setting of “ATS_B1->Trip
Delay” (t3). Inom is the rated current, Udead is the fixed value of “Dead Volt.”.
After ATS_B1 close tie BRK operates, “Close OUT” of operate board will close.
0 4s Falling Edge
ATS_B1 Close Tie BRK Operate
Delay & “ATS_B Succeed”
QF3 Closed
Fig. 3-43 Logic diagram of ATS_B1 succeed

After ATS_B1 close tie BRK operates, its operating signal will keep for 4s. if the status of tie BRK is closed
after the end of 4s, ATS_B1 succeed.
0 t5 Falling Edge
ATS_B1 Trip BRK2 Operate
Delay Falling Edge ≥1 & “ATS_B Fail”
0 4s
Delay
QF3 Open
Fig. 3-44 Logic diagram of ATS_B1 fail

After ATS_B1 Trip BRK2 operates, its operating signal will keep for t5(“ATS_B1->Close Delay” + 5s); after
ATS_B1 close tie BRK operates, its operating signal will keep for 4s. if the status of tie BRK is open after the end
of above time, ATS_B1 fail.
30
ART is enable(IN5 = 1)
ART_B1: Mode 1/Mode 2 ART_B1 Enable Flag

& ≥1 &
ATS_B1 Succeed Rising Edge
&
QF1 Open
t8 0
QF2 Closed ≥1
Delay
QF3 Open
Mode 1
0 1
ART Trip Tie BRK Operate &
Delay Falling
Edge
≥1
0 t7+2
ART Close BRK2 Operate
Delay Falling
Edge
Mode 2
0 1
ART Close BRK2 Operate &
Delay Falling
Edge
≥1
0 t6+2
ART Trip Tie BRK Operate
Delay Falling
Edge
Fig. 3-45 Logic diagram of ART_B1 enable flag

After ATS_B1 succeed, if ART_B1 is collocated to “Mode 1” or “Mode 2”, ART_B1 enable flag will be set
and keep.
If the status of QF1~QF3 changes (QF1 is open, or QF2 is closed, or QF3 is open), ART_B1 enable flag will
be reset after delay of t8 (t6+t7+2s). t6 is delay setting of “ART_B1->Close Delay”, while t7 is delay setting of
“ART_B1->Close Delay”.
“ART_B1” can be collocated to “Mode 1” (close first and then trip), and “Mode 2” (trip first and then
close).
If “ART_B1” is collocated to “Mode 1”, the logic diagram of ART_B1 is illustrated in Fig. 3-46~Fig. 3-47.
ART_B1 Enable Flag “ART Close BRK2 Operate”

t6 0
ART_B1: Mode 1
& Delay &
QF2 Open Output
VS2 > Ulive
25_L2 Operate
Fig. 3-46 Logic diagram of ART_B1 close BRK2

When the following conditions are met at the same time, after delay setting of “ART_B1->Close Delay”
(t6), if 25_L2 operates, ART_B1 close BRK2 operates, and “Trip” indicator lamp lights up.
31
 ART_B1 enable flag is set;

 “ART_B1” is collocated to “Mode 1”;
 QF2 is open;
 VS2>Ulive; Ulive is the fixed value of “Live Volt.”.
ART_B1 Enable Flag

ART_B1: Mode 1 “ART Trip Tie BRK Operate”
t7 0
QF1 Closed &
Delay
QF2 Closed Output
QF3 Closed
Fig. 3-47 Logic diagram of ART_B1 trip tie BRK

If ART_B1 close BRK2 successfully, after delay setting of “ART_B1->Trip Delay” (t7), ART_B1 trip tie BRK
operates, and “Trip” indicator lamp lights up.
ART_B1 Enable Flag

t7 0
QF1 Closed &
Delay
QF3 Closed Output
VS2 > Ulive

When the following conditions are met at the same time, after delay setting of “ART_B1->Trip Delay” (t7),
ART_B1 trip tie BRK operates, and “Trip” indicator lamp lights up.
 QF1 is closed;
 QF3 is closed;
ART_B1 Enable Flag

“ART Close BRK2 Operate”
ART_B1: Mode 2 t6 0
&
QF2 Open Delay
Output
QF3 Open

If ART_B1 trip tie BRK successfully and QF2 is open, after delay setting of “ART_B1->Close Delay” (t6),
ART_B1 close BRK2 operates, and “Trip” indicator lamp lights up.
32
3.1.32. Automatic Transfer Switch of Busbar Ⅱ (ATS_B2)

ATS_B2
Status 1 Status 3
ART_B2
QF1 Cloesd QF2 Closed QF1 Open QF2 Closed
QF3 Open QF3 Closed

Fig. 3-50 Logic diagram of ATS_B2

1.
contact).
Logic diagram of ATS_B2 charging is shown as follow：
ATS_B2 On
QF1 Closed
t1 0 0 t2
QF2 Closed & “ATS_B2 is Ready”
Delay Delay
QF3 Open
Ullmax_all>Ulive
Fig. 3-51 Logic diagram of ATS_B2 charging

When the following conditions are met at the same time, ATS_B2 begins to charge:
 ATS_B2 is on
 QF1 is closed;
 QF2 is closed;
 QF3 is open;
 Ullmax_all > Ulive. Ullmax_all is the maximum value of all phase-to-phase voltages of two busbars;
Ulive is the fixed value of “Live Volt.”.
When the above conditions are met, after delay setting of “Ready Delay” (t1), ATS_B2 is ready, and gets a
SOE recorded of “ATS_B2 is Ready”; when anyone of above conditions is not met, after delay setting of
“Un-Ready Delay” (t2), ATS_B2 is Un-ready.
33
ATS Block Operate

ATS_B2 Off
Tie BRK Abnormal Operate
QF3 Close ≥1 “ATS_B2 is Un-Ready”
ATS_B2 Close Tie BRK Opreate
ATS_B2 Succeed or failed
DI Block ATS_B2
Fig. 3-52 Logic diagram of ATS_B2 discharge

When anyone of the following conditions is met, ATS_B2 will discharge instantaneously and get a SOE
recorded of “ATS_B2 is Un-Ready”：
 ATS_B is off;
 Tie BRK abnormal operates;
 QF3 is close;
 ATS_B2 close tie BRK operates;
 ATS_B2 succeed or failed;
 DI block ATS_B2.
ATS_B2 is Ready
“ATS_B2 Trip BRK1 Operate”
IA1 < 0.02Inom t3 0
&
Output
≥1
Ullmax2 > Ulive
Fig. 3-53 Logic diagram of ATS_B2 trip BRK1

When the following conditions are met at the same time, after delay setting of “ATS_B2->Trip Delay” (t3),
ATS_B2 trip BRK operates, and “Trip” indicator lamp lights up:
 Ullmax1<Udead; Ullmax1 is the maximum value of three phase-to-phase voltages of busbarⅠ;
Udead is the fixed value of “Dead Volt.”.
 “Trip Check Liveline” is off, or Ullmax2>Ulive, Ullmax2 is the maximum value of three phase-to-phase
voltages of busbar Ⅱ; Ulive is the fixed value of “Live Volt.”.
34
ATS_B2 is Ready
QF1 Open “ATS_B Close Tie BRK Operate”
t4 0
QF3 Open &
Delay
Ullmax2 > Ulive Output
IA1 < 0.02Inom t3 0

&
Fig. 3-54 Logic diagram of ATS_B2 close tie BRK

When the following conditions are met at the same time, after delay setting of “ATS_B2->Close Delay”
(t4), ATS_B2 close tie BRK operates, and “Trip” indicator lamp lights up:
 QF1 is open;
 QF3 is open;
 Ullmax>Ulive; Ullmax2 is the maximum value of three phase-to-phase voltages of busbar Ⅱ.
 IA1<0.02Inon, and Ullmax1<Udead are met at the same time over delay setting of “ATS_B2->Trip
Delay” (t3). Inom is the rated current, Udead is the fixed value of “Dead Volt.”.
After ATS_B2 close tie BRK operates, “Close OUT” of operate board will close.
0 4s Falling Edge
Delay & “ATS_B Succeed”
QF3 Closed
Fig. 3-55 Logic diagram of ATS_B2 succeed

After ATS_B2 close tie BRK operates, its operating signal will keep for 4s. if the status of tie BRK is closed
after the end of 4s, ATS_B2 succeed.
0 t5 Falling Edge
ATS_B2 Trip BRK1 Operate
Delay Falling Edge ≥1 & “ATS_B Fail”
0 4s
Delay
QF3 Open
Fig. 3-56 Logic diagram of ATS_B2 fail

After ATS_B2 Trip BRK1 operates, its operating signal will keep for t5(“ATS_B2->Close Delay” + 5s); after
ATS_B2 close tie BRK operates, its operating signal will keep for 4s. if the status of tie BRK is open after the end
of above time, ATS_B2 fail.
35
ART_B2: Mode 1/Mode 2 ART_B2 Enable Flag

& ≥1 &
ATS_B2 Succeed Rising Edge
&
QF1 Closed
t8 0
QF2 Open ≥1
Delay
QF3 Open
Mode 1
0 1
ART Trip Tie BRK Operate &
Delay Falling
Edge
≥1
0 t7+2
Delay Falling
Edge
Mode 2
0 1
Delay Falling
Edge
≥1
0 t6+2
ART Trip Tie BRK Operate
Delay Falling
Edge
Fig. 3-57 Logic diagram of ART_B2 enable flag

After ATS_B2 succeed, if ART_B2 is collocated to “Mode 1” or “Mode 2”, ART_B2 enable flag will be set
and keep.
If the status of QF1~QF3 changes (QF1 is closed, or QF2 is open, or QF3 is open), ART_B2 enable flag will
be reset after delay of t8 (t6+t7+2s). t6 is delay setting of “ART_B2->Close Delay”, while t7 is delay setting of
“ART_B2->Close Delay”.
“ART_B2” can be collocated to “Mode 1” (close first and then trip), and “Mode 2” (trip first and then
close).
ART_B2 Enable Flag “ART Close BRK1 Operate”

t6 0
ART_B2: Mode 1
& Delay &
QF1 Open Output
VS1 > Ulive
25_L1 Operate

When the following conditions are met at the same time, after delay setting of “ART_B2->Close Delay”
(t6), if 25_L1 operates, ART_B2 close BRK1 operates, and “Trip” indicator lamp lights up.
36

 QF is open;
ART_B2 Enable Flag

t7 0
QF1 Closed &
Delay
QF2 Closed Output
QF3 Closed

If ART_B2 close BRK1 successfully, after delay setting of “ART_B2->Trip Delay” (t7), ART_B2 trip tie BRK
ART_B2 Enable Flag

t7 0
QF2 Closed &
Delay
QF3 Closed Output
VS1 > Ulive

When the following conditions are met at the same time, after delay setting of “ART_B2->Trip Delay” (t7),
ART_B2 trip tie BRK operates, and “Trip” indicator lamp lights up.
 QF2 is closed;
 QF3 is closed;
ART_B2 Enable Flag

ART_B2: Mode 2 t6 0
&
QF1 Open Delay
Output
QF3 Open

If ART_B2 trip tie BRK successfully and QF is open, after delay setting of “ART_B2->Close Delay” (t6),
ART_B2 close BRK1 operates, and “Trip” indicator lamp lights up.
37
3.1.33. Automatic Transfer Switch of Line 1# (ATS_L1)

ATS_L1
Status 3 Status 2
ART_L1
QF1 Open QF2 Closed QF1 Closed QF2 Open
QF3 Closed QF3 Closed

Fig. 3-62 Logic diagram of ATS_L1

3.
contact).
Logic diagram of ATS_L1 charging is shown as follow：
ATS_L1 On
QF1 Open
QF2 Closed t1 0 0 t2
& “ATS_L1 is Ready”
QF3 Closed Delay Delay
Us1>Ulive
Us2>Ulive
Fig. 3-63 Logic diagram of ATS_L1 charging

When the following conditions are met at the same time, ATS_L1 begins to charge:
 ATS_L1 is on
 QF1 is open;
 QF2 is closed;
 QF3 is closed;
 Us1>Ulive; Ulive is the fixed value of “Live Volt.”.
 Us2>Ulive.
When the above conditions are met, after delay setting of “Ready Delay” (t1), ATS_L1 is ready, and gets a
38
SOE recorded of “ATS_L1 is Ready”; when anyone of above conditions is not met, after delay setting of
“Un-Ready Delay” (t2), ATS_L1 is Un-ready.
ATS Block Operate

ATS_L1 Off
QF1 Close “ATS_L1 is Un-Ready”

≥1
ATS_L1 Close BRK1 Opreate
ATS_L1 Succeed or failed
DI Block ATS_L1
Fig. 3-64 Logic diagram of ATS_L1 discharge

When anyone of the following conditions is met, ATS_L1 will discharge instantaneously and get a SOE
recorded of “ATS_L1 is Un-Ready”：
 ATS_L1 is off;
 QF1 is close;
 ATS_L1 close BRK1 operates;
 ATS_L1 succeed or failed;
 DI block ATS_L1.
ATS_L1 is Ready
“ATS_L1 Trip BRK2 Operate”
IA2 < 0.02Inom t3 0
&
Us2 < Udead Delay
Output
Ullmax_all < Udead

≥1
Us1 > Ulive
Fig. 3-65 Logic diagram of ATS_L1 trip BRK2

When the following conditions are met at the same time, after delay setting of “ATS_L1->Trip Delay” (t3),
ATS_L1 trip BRK2 operates, and “Trip” indicator lamp lights up:
 ATS_L1 is Ready;
 Us2<Udead; Udead is the fixed value of “Dead Volt.”.
 Ullmax_all<Udead; Ullmax_all is the maximum value of all phase-to-phase voltages of two busbars.
 “Trip Check Liveline” is off, or Us1>Ulive, Ulive is the fixed value of “Live Volt.”.
39
ATS_L1 is Ready
QF1 Open
QF2 Open
“ATS_L1 Close BRK1 Operate”
IA2 < 0.02Inom t3 0 t4 0
& &
Ullmax_all < Udead Delay Delay
Output

≥1
Us1 > Ulive
Fig. 3-66 Logic diagram of ATS_L1 close BRK1

When the following conditions are met at the same time, after delay setting of “ATS_L1->Close Delay”
(t4), ATS_L1 close BRK1 operates, and “Trip” indicator lamp lights up:
 QF1 is open;
 QF2 is open;
 IA2<0.02Inon, and Ullmax_all<Udead are met at the same time over delay setting of “ATS_L1->Trip
Delay” (t3). Inom is the rated current; Ullmax_all is the maximum value of all phase-to-phase
voltages of two busbars; Udead is the fixed value of “Dead Volt.”.
0 4s Falling Edge
ATS_L1 Close BRK1 Operate
Delay & “ATS_L1 Succeed”
QF1 Closed
Fig. 3-67 Logic diagram of ATS_L1 succeed

After ATS_L1 close BRK1 operates, its operating signal will keep for 4s. if the status of BRK1 is closed after
the end of 4s, ATS_L1 succeed.
0 t5 Falling Edge
ATS_L1 Trip BRK2 Operate
Delay Falling Edge ≥1 & “ATS_L1 Fail”
0 4s
Delay
QF1 Open
Fig. 3-68 Logic diagram of ATS_L1 fail

After ATS_L1 Trip BRK2 operates, its operating signal will keep for t5(“ATS_L1->Close Delay” + 5s); after
ATS_L1 close BRK1 operates, its operating signal will keep for 4s. if the status of BRK1 is open after the end of
above time, ATS_L1 fail.
40
ART_L1: Mode 1/Mode 2 ART_L1 Enable Flag

& ≥1 &
ATS_L1 Succeed Rising Edge
&
QF1 Open
t8 0
QF2 Closed ≥1
Delay
QF3 Open
Mode 1
0 1
ART_L1 Trip BRK1 Operate &
Delay Falling
Edge
≥1
0 t7+2
Delay Falling
Edge
Mode 2
0 1
Delay Falling
Edge
≥1
0 t6+2
ART_L1 Trip BRK1 Operate
Delay Falling
Edge
Fig. 3-69 Logic diagram of ART_L1 enable flag

After ATS_L1 succeed, if ART_L1 is collocated to “Mode 1” or “Mode 2”, ART_L1 enable flag will be set and
keep.
If the status of QF1~QF2 changes (QF1 is open, or QF2 is closed), ART_L1 enable flag will be reset after
delay of t8 (t6+t7+2s). t6 is delay setting of “ART_L1->Close Delay”, while t7 is delay setting of “ART_L1->Close
Delay”.
“ART_L1” can be collocated to “Mode 1” (close first and then trip), and “Mode 2” (trip first and then
close).
If “ART_L1” is collocated to “Mode 1”, the logic diagram of ART_L1 is illustrated in Fig. 3-70~Fig. 3-71.
ART_L1 Enable Flag “ART Close BRK2 Operate”

t6 0
ART_L1: Mode 1
& Delay &
QF2 Open Output
VS2 > Ulive
25_L2 Operate
Fig. 3-70 Logic diagram of ART_L1 close BRK2

When the following conditions are met at the same time, after delay setting of “ART_L1->Close Delay” (t6),
if 25_L2 operates, ART_L1 close BRK2 operates, and “Trip” indicator lamp lights up.
41
 ART_L1 enable flag is set;

 “ART_L1” is collocated to “Mode 1”;
 QF2 is open;
ART_L1 Enable Flag

ART_L1: Mode 1 “ART_L1 Trip BRK1 Operate”
t7 0
QF1 Closed &
Delay
QF2 Closed Output
QF3 Closed
Fig. 3-71 Logic diagram of ART_L1 trip BRK1

If ART_L1 close BRK2 successfully, after delay setting of “ART_L1->Trip Delay” (t7), ART_L1 trip BRK1
ART_L1 Enable Flag

ART_L1: Mode 2 “ART_1 Trip BRK1 Operate”
t7 0
QF1 Closed &
Delay
QF3 Closed Output
VS2 > Ulive

When the following conditions are met at the same time, after delay setting of “ART_L1->Trip Delay” (t7),
ART_L1 trip BRK1 operates, and “Trip” indicator lamp lights up.
 QF1 is closed;
 QF3 is closed;
ART_L1 Enable Flag

ART_L1: Mode 2 t6 0
&
QF1 Open Delay
Output
QF2 Open

If ART_L1 trip BRK1 successfully and QF2 is open, after delay setting of “ART_L1->Close Delay” (t6),
ART_L1 close BRK2 operates, and “Trip” indicator lamp lights up.
42
3.1.34. Automatic Transfer Switch of Line 2# (ATS_L2)

ATS_L2
Status 2 Status 3
ART_L2
QF1 Closed QF2 Open QF1 Open QF2 Closed
QF3 Closed QF3 Closed

Fig. 3-74 Logic diagram of ATS_L2

2.
contact).
Logic diagram of ATS_L2 charging is shown as follow：
ATS_L2 On
QF1 Closed
QF2 Open t1 0 0 t2
& “ATS_L2 is Ready”
QF3 Closed Delay Delay
Us1>Ulive
Us2>Ulive
Fig. 3-75 Logic diagram of ATS_L2 charging

When the following conditions are met at the same time, ATS_L2 begins to charge:
 ATS_L2 is on
 QF1 is closed;
 QF2 is open;
 QF3 is closed;
 Us1>Ulive; Ulive is the fixed value of “Live Volt.”.
 Us2>Ulive.
When the above conditions are met, after delay setting of “Ready Delay” (t1), ATS_L2 is ready, and gets a
43
SOE recorded of “ATS_L2 is Ready”; when anyone of above conditions is not met, after delay setting of
“Un-Ready Delay” (t2), ATS_L2 is Un-ready.
ATS Block Operate

ATS_L2 Off
QF2 Close
≥1 “ATS_L2 is Un-Ready”
ATS_L2 Close BRK2 Opreate
ATS_L2 Succeed or failed
DI Block ATS_L2
Fig. 3-76 Logic diagram of ATS_L2 discharge

When anyone of the following conditions is met, ATS_L2 will discharge instantaneously and get a SOE
recorded of “ATS_L2 is Un-Ready”：
 ATS_L2 is off;
 QF2 is close;
 ATS_L2 close BRK2 operates;
 ATS_L2 succeed or failed;
 DI block ATS_L2.
ATS_L2 is Ready
“ATS_L2 Trip BRK1 Operate”
IA1 < 0.02Inom t3 0
&
Us1 < Udead Delay
Output
Ullmax_all < Udead

≥1
Us2 > Ulive
Fig. 3-77 Logic diagram of ATS_L2 trip BRK1

When the following conditions are met at the same time, after delay setting of “ATS_L2->Trip Delay” (t3),
ATS_L2 trip BRK1 operates, and “Trip” indicator lamp lights up:
 Us1<Udead; Udead is the fixed value of “Dead Volt.”.
 Ullmax_all<Udead; Ullmax_all is the maximum value of all phase-to-phase voltages of two busbars.
44
ATS_L2 is Ready
QF1 Open
QF2 Open
“ATS_L2 Close BRK2 Operate”
IA1 < 0.02Inom t3 0 t4 0
& &
Ullmax_all < Udead Delay Delay
Output

≥1
Us2 > Ulive
Fig. 3-78 Logic diagram of ATS_L2 close BRK2

When the following conditions are met at the same time, after delay setting of “ATS_L2->Close Delay”
(t4), ATS_L2 close BRK2 operates, and “Trip” indicator lamp lights up:
 QF1 is open;
 QF2 is open;
 IA1<0.02Inon, and Ullmax_all<Udead are met at the same time over delay setting of “ATS_L2->Trip
Delay” (t3). Inom is the rated current; Ullmax_all is the maximum value of all phase-to-phase
voltages of two busbars; Udead is the fixed value of “Dead Volt.”.
0 4s Falling Edge
Delay & “ATS_L2 Succeed”
QF2 Closed
Fig. 3-79 Logic diagram of ATS_L2 succeed

After ATS_L2 close BRK2 operates, its operating signal will keep for 4s. if the status of BRK2 is closed after
the end of 4s, ATS_L2 succeed.
0 t5 Falling Edge
ATS_L2 Trip BRK1 Operate
Delay Falling Edge ≥1 & “ATS_L2 Fail”
0 4s
Delay
QF2 Open
Fig. 3-80 Logic diagram of ATS_L2 fail

After ATS_L2 Trip BRK1 operates, its operating signal will keep for t5(“ATS_L2->Close Delay” + 5s); after
ATS_L2 close BRK2 operates, its operating signal will keep for 4s. if the status of BRK2 is open after the end of
above time, ATS_L2 fail.
45
ART_L2: Mode 1/Mode 2 ART_L2 Enable Flag

& ≥1 &
ATS_L2 Succeed Rising Edge
&
QF1 Closed
t8 0
QF2 Open ≥1
Delay
QF3 Open
Mode 1
0 1
ART_L2 Trip BRK2 Operate &
Delay Falling
Edge
≥1
0 t7+2
Delay Falling
Edge
Mode 2
0 1
Delay Falling
Edge
≥1
0 t6+2
ART_L2 Trip BRK2 Operate
Delay Falling
Edge
Fig. 3-81 Logic diagram of ART_L2 enable flag

After ATS_L2 succeed, if ART_L2 is collocated to “Mode 1” or “Mode 2”, ART_L2 enable flag will be set and
keep.
If the status of QF1~QF2 changes (QF1 is closed, or QF2 is open), ART_L2 enable flag will be reset after
delay of t8 (t6+t7+2s). t6 is delay setting of “ART_L2->Close Delay”, while t7 is delay setting of “ART_L2->Close
Delay”.
“ART_L2” can be collocated to “Mode 1” (close first and then trip), and “Mode 2” (trip first and then
close).
ART_L2 Enable Flag “ART Close BRK1 Operate”

t6 0
ART_L2: Mode 1
& Delay &
QF1 Open Output
VS1 > Ulive
25_L1 Operate

When the following conditions are met at the same time, after delay setting of “ART_L2->Close Delay” (t6),
if 25_L1 operates, ART_L2 close BRK1 operates, and “Trip” indicator lamp lights up.
46

 QF1 is open;
ART_L2 Enable Flag

ART_L2: Mode 1 “ART_L2 Trip BRK2 Operate”
t7 0
QF1 Closed &
Delay
QF2 Closed Output
QF3 Closed

If ART_L2 close BRK1 successfully, after delay setting of “ART_L2->Trip Delay” (t7), ART_L2 trip BRK2
ART_L2 Enable Flag

ART_L2: Mode 2 “ART_2 Trip BRK2 Operate”
t7 0
QF2 Closed &
Delay
QF3 Closed Output
VS1 > Ulive

When the following conditions are met at the same time, after delay setting of “ART_L2->Trip Delay” (t7),
ART_L2 trip BRK2 operates, and “Trip” indicator lamp lights up.
 QF2 is closed;
 QF3 is closed;
ART_L2 Enable Flag

ART_L2: Mode 2 t6 0
&
QF1 Open Delay
Output
QF2 Open

If ART_L2 trip BRK2 successfully and QF1 is open, after delay setting of “ART_L2->Close Delay” (t6),
ART_L2 close BRK1 operates, and “Trip” indicator lamp lights up.
3.1.35. Synchronization Check of VS1 (25_L1)
When “ATS_B2->ART_B2” or “ATS_L2->ART_L2” is collocated to “Mode 1”, “25_L1” must be collocated to
“On”, otherwise, ATS close BRK1 cannot operate because of 25_L1 cannot operate.
47
25_L1 On
25_L1 Operate 10s 0
& “VS1 Abnormal”
Ullmin1 > 90V Delay
QF1 Closed
≥1
IA1 > 0.02Inom
Fig. 3-86 Logic diagram of VS1 abnormal

When the following conditions are met at the same time, after delay 10s, VS1 abnormal operates, “Alarm”
indicator lamp lights up:
 25_L1 is on;
 25_L1 doesn’t operate;
 Ullmin1>90V; Ullmin1 is the manimum value of three phase-to-phase voltages of busbar Ⅰ.
 QF1 is closed, or IA1 > 0.02Inom. Inom is the rated current.
25_L1 On
UAB1 > 0.7Unom
Us1 > 0.7Unom 25_L1 Operate
&
Frequency Qualified
Fig. 3-87 Logic diagram of 25_L1

If all the following conditions are met at the same time, 25_L1 operates:
 25_L1 is on;
 The magnitude of UAB1 is larger than 0.7 times of rated voltage;
 The magnitude of Us1 is larger than 0.7 times of “VS1 Sec. Vnom”;
 The frequency deviation of UAB1 and rated voltage, Us1 and rated voltage should be less than 1Hz;
 The voltage difference should be qualified;
3.1.36. Synchronization Check of VS2 (25_L2)
When “ATS_B1->ART_B1” or “ATS_L1->ART_L1” is collocated to “Mode 1”, “25_L2” must be collocated to
“On”, otherwise, ATS close BRK2 cannot operate because of 25_L2 cannot operate.
48
25_L2 On
25_L2 Operate 10s 0
& “VS2 Abnormal”
Ullmin2 > 90V Delay
QF2 Closed
≥1
IA2 > 0.02Inom
Fig. 3-88 Logic diagram of VS2 abnormal

When the following conditions are met at the same time, after delay 10s, VS2 abnormal operates, “Alarm”
indicator lamp lights up:
 25_L2 is on;
 25_L2 doesn’t operate;
 Ullmin2>90V; Ullmin2 is the manimum value of three phase-to-phase voltages of busbar Ⅱ.
 QF2 is closed, or IA2 > 0.02Inom. Inom is the rated current.
25_L2 On
UAB2 > 0.7Unom
Us2 > 0.7Unom 25_L2 Operate
&
Frequency Qualified
Fig. 3-89 Logic diagram of 25_L2

If all the following conditions are met at the same time, 25_L2 operates:
 25_L2 is on;
 The magnitude of UAB2 is larger than 0.7 times of rated voltage;
 The magnitude of Us2 is larger than 0.7 times of “VS2 Sec. Vnom”;
 The frequency deviation of UAB2 and rated voltage, Us2 and rated voltage should be less than 1Hz;
 The voltage difference should be qualified;
3.1.37. Line 1 Over-Current Load Shedding Protection (50LS_L1-1, 50LS_L1-2, 50LS_L1-3)
PMC-851D has 3 sections line 1 over-current load shedding protections (50LS_L1-1, 50LS_L1-2, 50LS_L1-3),
the protection is released for 900s after ATS operates.
49
50LS_L1-1 On “50LS_L1-1 Operate”

t 0
delay
IA1 > Id Output
Fig. 3-90 Logic diagram of 50LS_L1-1

When the following conditions are met at the same time, after delay setting, 50LS_L1-1 operates:
 50LS_L1-1 is on;
 IA1>Id; Id is the fixed value of 50LS_L1-1.
When line 1 over-current load shedding protection operates, “Trip” or “Alarm” indicator lamp is optional.
3.1.38. Line 2 Over-Current Load Shedding Protection (50LS_L2-1, 50LS_L2-2, 50LS_L2-3)
PMC-851D has 3 sections line 2 over-current load shedding protections (50LS_L2-1, 50LS_L2-2, 50LS_L2-3),
the protection is released for 900s after ATS operates.
50LS_L2-1 On “50LS_L2-1 Operate”

t 0
delay
IA2 > Id Output
Fig. 3-91 Logic diagram of 50LS_L2-1

When the following conditions are met at the same time, after delay setting, 50LS_L2-1 operates:
 50LS_L2-1 is on;
 IA2>Id; Id is the fixed value of 50LS_L2-1.
When line 2 over-current load shedding protection operates, “Trip” or “Alarm” indicator lamp is optional.
3.1.39. DI Protection
IN1~IN14 and Ext. Trip can be configured as DI protection.
DI protection can select “off” or “on”; operate message is optional. Signal configuration selects “alarm”,
“trip” and “event”.
DI action mode can set DI as “open” or “close”.
IN10 Alarm/Trip/Event SOE describe is optional

t 0
&
Mode select “Open” delay
Output
& ≥1
IN10 = 0
&
Fig. 3-92 Logic diagram of DI protection
50
3.2. Measurements
3.2.1. Measurement Data
Table 3-1 Measurement Data
Uab1, Ubc1, Uca1, Us1, Uab2, Ubc2, Uca2, Us2
Primary value Ia, Ib, Ic
P, Q, S, PF
3.2.2. Protection Data

Table 3-2 Protection Data
Busbar Ⅰ：UAB1, UBC1, UCA1, US1, U1, U2

Busbar Ⅱ：UAB2, UBC2, UCA2, US2, U1, U2
IA, IB, IC, IA1, IA2, I1 , I2 , I0
Secondary f1, f2, fs1, fs2
value P, Q
Accumulative value of inverse time protection: Phase current, zero sequence
current
Synchronization check state: 25, 25_L1, 25_L2
3.2.3. Energy Data

PMC-851D can meter positive/negative active energy, positive/negative reactive energy. The energy data
can be reset or preset to user-defined values through HMI in maintenance menu.
3.2.4. AO output
AO: It refers to an auxiliary output of PMC-851D and is equivalent to a normal electrical quantity
transducer such as voltage transducer or power transducer.
Options of output volume: U, I, P
Output scope: 4-20mA; overload capacity: 1.2 times
Load capacity: 500Ω
Power supply: 24V DC power supply with isolator is collocated inside.
note: the unit of voltages is kV; the unit of currents is A, the unit of active power is kW, the unit of reactive
power is kvar.
3.3. Remote Signal Function

There are 19 digital inputs in PMC-851D, all of them have been pre-defined.
 IN1 (A2): status of QF1 (line 1# breaker). If “System->Breaker State Config.->BRK1” is collocated to
“NO” (normally open contact), QF1 is closed when IN1 asserted, QF1 is open when IN1 deasserted. If
“System->Breaker State Config.->BRK1” is collocated to “NC” (normally closed contact), QF1 is open
when IN1 asserted, QF1 is closed when IN1 deasserted. If status of QF1 has not to be detected, IN1
51
can be used freely.

 IN2 (A3): status of line QF2 (line 2# breaker). If “System->Breaker State Config.->BRK2” is collocated
to “NC” (normally closed contact), QF2 is closed when IN2 asserted, QF2 is open when IN2
deasserted. If “System->Breaker State Config.->BRK2” is collocated to “NO” (normally open contact),
QF2 is open when IN1 asserted, QF2 is closed when IN2 deasserted. If status of QF2 has not to be
detected, IN2 can be used freely.
 IN3 (A4): status of QF3 (tie breaker). If “System->Breaker State Config.->Tie BRK” is collocated to “Ext.
NC” (normally closed contact), QF3 is closed when IN3 asserted, QF3 is open when IN3 deasserted. If
“System->Breaker State Config.->Tie BRK” is collocated to “Ext. NO” (normally open contact), QF3 is
open when IN3 asserted, QF3 is closed when IN3 deasserted. If “System->Breaker State Config.->Tie
BRK” is collocated to “Normal”, the status of QF3 gets from operate board, and IN3 can be used
freely.
 IN4 (A5): digital input to enable ATS. ATS is enable when IN4 asserted, ATS is not enable when IN4
deasserted. IN4 can be used freely when ATS is off.
 IN5 (A6): digital input to enable ART. ART is enable when IN5 asserted, ART is not enable when IN5
deasserted. IN5 can be used freely when ART is off.
 IN6 (A7): digital input to block 50P-1 (Instantaneous Over-Current Protection with Definite Time).
50P-1 is blocked when IN6 asserted, 50P-1 is released when IN6 deasserted. IN6 can be used freely
when 50P-1 is off or “50P-1->DI Block” is collocated to “Off”.
 IN7 (A8): Manual synchronism closing input. If IN7 asserted for 1s and other conditions of 25 are
met, 25 manual close operate. IN7 can be used freely when “25->Manual Close” is collocated to
“Off”.
 IN8 (A9): SOTF_DI input. SOTF_DI is released during a period of time after the IN8 switches from
open to close. IN8 can be used freely when SOTF_DI is collocated to “Off”.
 IN9~IN14 (A10~A15): user-defined to block ATS. A certain DI can be used freely when it’s not
collocated to block ATS.
 Remote location:
 BRK Closed status;
 BRK Open status;
 Ext. Trip position;
 KKJ status.
3.4. Control Functions

There are 13 digital outputs in PMC-851D, seven of which have been defined, the rest six outputs refer to
the freely collocated outputs. The corresponding output terminal refers to OUT1~OUT6. OUT1~OUT6 refers to
open contact output (OUT1 and OUT6 can be changed to closed contact output by jumper wire). The seven
52
defined outputs as following respectively: close (operate automatically after ATS_B close tie BRK operate), trip
(can be set), remote trip output, remote close output (operate automatically after 25 remote close operate),
abnormal alarm, KKJ output, link output (don’t be controlled by CPU).
Remote trip output, remote close output and OUT1~OUT6 digital outputs enjoy the remote control
function. Remote control is conducted by starting relay, remote trip relay, remote close relay, and OUT1~OUT6
relay together. After PMC-851D received the command of remote control from supervisory control system, it
will send out a response message, when supervisory control system received the response message and send
out the remote control command again, the remote trip relay (or remote close relay, OUT1~OUT6 relay) of the
device will operate. if the remote control status of PMC-851D is “Local”, the supervisory control system is
unable to remote control the device. Remote control function is featured as a very high reliability since
multiple maloperation preventive measures are considered in the hardware and software of PMC-851D. if the
“SBO” (select before operating) is collocated to “Off”, it is unnecessary to send preset message before remote
control.
There are 3 kinds of operation board (board D): DC 220V operation board, DC 110V operation board and
AC 220V operation board. Users should select the right operation board according to the actual operation
power supply type.
3.5. Communication Function

PMC-851D is collocated with numerous communication ports to connect with various power monitoring
networks, realize remote measuring, remote signaling, remote control, SOE log, WFR log, remote transmission
of unit automatic inspection information and malfunction recording data and thus construct a digital
substation. It supports numerous communication protocols, such as IEC61850, Modbus RTU, Modbus TCP and
IEC60870-5-103.
Ethernet communication port: 2 channels; it supports the looped network function, switched mode, and
double internet hot backup; three models are selected at disposal: RJ45 port of 10/100 base-T Ethernet; optical
fiber port of 100 base-FX Ethernet.
RS485 communication port: 1 channel (optional).
Table 3-3 List of communication protocol functions
Protocol IEC61850 Modbus RTU Modbus TCP IEC60870-5-103

Measurements ● ● ● ●
Power quality ● ● ● ●
SOE logs ● ● ● ●
WFR logs ● ● ● ●
WFC logs ● ● ● ●
53
3.6. Log Function

3.6.1. SOE Logs
PMC-851D is able to store 512 SOE logs in total, including relay logs, DI/DO logs, diagnosis logs, and
maintenance logs; all the logs refer to the latest data and are refreshed automatically; the SOE log is not lost in
case of power cutoff. The first log is the latest log while the second log takes the second position; in case of no
effective log, “No Log” is displayed.
● Relay logs
The relay logs include the category of protective action (over-current etc.), characteristic value of
protective action and time of protective action (year, month, day, hour, minute, second and millisecond).
The latest events of protective action can be mutually verified by searching for the WFR logs.
● DI/DO logs
PMC-851D is responsible for collecting the status of digital inputs and digital outputs. In case of signal
displacement in any switch volume (that is to say, the contact changes from combined to separated or from
separated to combined), a remote signal is produced and occurrence time and switch volume change status
are recorded.
● Diag. logs
Upon electrification of PMC-851D, the self-inspection and monitoring are implemented to PMC-851D
operation status in fixed time; in case of serious malfunction inspected in the components, PMC-851D is locked
up for protection and alarm signal is output.
Self-inspection and monitoring contents include:
 CPU and hardware system
 AC and sampling system
 Data storage
 Fixed value and its storage system
 Voltage of inside clock battery
 Work power supply system inside PMC-851D
● Maint. logs
PMC-851D will automatically log the event upon relay protection and debugging personnel’s revision of
parameters set by PMC-851D. The log includes the operation contents and time; it can’t be revised and is not
lost in case of power cutoff; it is adopted as the basis of accident analysis together with the form of protection
fixed value, log of protective event and log of malfunction recording.
The maint. log of PMC-851D includes the following contents:
 Power charging and cutoff of PMC-851D
 Removal of event log, recording log and wave form log
 Local and communication reset signal
54
 Revision of unit time

 Revision of user password
 Transfer of fixed value group
 Energy Preset
 Revision of parameters
 Calibration of analog quantity
● The concrete record and displayed contents of event log report are as follows:
Table 3-4 Contents of event log
Item Contents Remark
Event No.
Correspon
Action category: Protective action corresponding to XXX
ding setup
Relay logs Malfunction measuring value recorded at the time of protective
of output
action
action
Action time: Output or delay time from year to millisecond
Event No.
Displacement contact and method: The contact changes from
DI/DO logs --
combined to separated or from separated to combined
Displacement time of remote signaling: From year to millisecond
Event No. Output
Malfunction self-inspection contents alarm
signal and
Diag. logs
lock up
Malfunction self-inspection time: From year to millisecond
protective
action
Event No.
Maint. logs Operation contents of unit --
Operation time of unit: From year to millisecond
Remark: The priority of self-inspection lockup output is superior to the action of protective output.
3.6.2. WFR logs
Upon the start, action or return of protection (when the “Signal” of DI Relay is select “Trip”, its protection
action will start WFR logs), the WFR logging is started to record the fault voltage, current wave form and break
status change. A new WFR log won’t start until the last WFR log is finished. The logging result has data and
time mark stored in a special storage and read by the panel and communication methods. In the reading of
logging data by the panel, it is able to search for the logging wave form of latest 8 protection actions; a log is
added before each section of WFR logging to bring convenience to searching and display the start time, fault
55
category, fault characteristic value(such as short circuit current or voltage) and then wave form; the wave form
is displayed in pair(phase voltage and phase current are in a page, while break status changes are in another
page); the wave form curve is searched by moving to the left and right; 4 cycles are moved once; the cycle
scale is marked below; the second method aims to read the graph of fault recording in the monitoring
computer—The wave form is even distinct.
The full length of WFR logging is 100 cycles; the recorded wave form includes 5 cycles before the
malfunction and 95 cycles after that; there are 32 points in the first 10 cycles and 16 points in the last 90
cycles. The wave form of latest 8 WFR logging is reserved in PMC-851D; these data are reserved in the
nonvolatile storage; the communication supports the summoning of WFR logging data.
PMC-851D is able to start WFR logging in remote control method.
3.6.3. Instantaneous Capturing Function of Waveform
A huge amount of current and voltage harmonic waves exist in the industrial, commercial and civil power
consumption which have increasingly become the common concern of power system and user. It is necessary
to diagnose the root cause by wave form analytic tools and confirm necessary protective measures to upgrade
the power supply quality.
PMC-851D is able to provide 10 cycles (128 points in each cycle) of wave form sampling service for
three-phase currents and voltages input through manual remote control function and protection action; the
sampled wave form data is stored in the nonvolatile storage and read by the computer through communication
port as shown in the figure. The real-time monitoring software PECSTAR developed by the company is able to
obtain the wave form data, make FFT to each wave form and display 63 harmonic waves in the form of bar
chart which is beneficial for the user to swiftly diagnose the source and severity of harmonic wave.
PMC-851D is able to start wave form record in remote control method.
56
Fig. 3-93 Graph of wave form record
3.7. Harmonic Analyzing Function

PMC-851D could perform harmonic analyzing to phase-to-phase voltages (Uab1, Ubc1, Uca1, Uab2, Ubc2,
Uca2), and three-phase currents (Ia, Ib, Ic) according to the requirement of level B meter. With the sampling
rate of 128 points/cycle, up to 63th harmonic can be analyzed.
The contents of harmonic analyzing include:
 The total harmonic distortion, total odd harmonic distortion, total even harmonic distortion, and
2nd-63th harmonic ratio (HR) of three phase-to-phase voltages of busbar Ⅰ (Uab1, Ubc1, Uca1);
2nd-63th harmonic ratio (HR) of three phase-to-phase voltages of busbar Ⅱ (Uab2, Ubc2, Uca2);
2nd-63th harmonic ratio (HR) of three-phase currents (Ia, Ib, Ic).
3.8. Unbalance Function

PMC-851D supports the function of unbalance analyzing of voltage and current. The calculation formulas
are as follows:
U2
u   100%
U1
I2
i   100%
I1
57
3.9. Time Synchronization Function

PMC-851D supports software time synchronization and hardware pulse time synchronization.
The software time synchronization supports SNTP network synchronization and communication
synchronization. SNTP network synchronization aims to automatically obtain high precision time from the
network time server; communication synchronization aims to enable the upper computer to synchronize
PMC-851D through Modbus protocol and 103 protocol;
Hardware time synchronization supports IRIG-B synchronization and GPS hardware pulse synchronization.
Hardware Software
IRIG-B GPS SNTP Modbus IEC103
Fig. 3-94 Time synchronization methods

PMC-851D is permitted to select one out of four clock sources as the synchronization clock source:
real-time clock (RTC), GPS synchronization pulse, IRIG-B synchronization signal and SNTP network clock source;
the communication synchronization (including Modbus, 103 protocol synchronization) is adopted as the
auxiliary synchronization mechanism and co-existent with the above clock source and operated together with
it.
The real-time clock (RTC) aims to provide reliable system time inside PMC-851D; it includes
year/month/day/hour/minute/second; since it is supplied by backup battery, it is able to operate normally
under system shutdown status. As the default clock source, it is adopted in the operation environment without
clock synchronization equipment to guarantee the system time precision. It is coordinated with communication
synchronization to guarantee PMC-851D compatibility with other equipment time; the typical application is
shown in Figure 3.9b.
58
Communication time syn. 485 bus
RTC RTC
PMC-851D PMC-851D
Fig. 3-95 Typical application of RTC synchronization source

GPS is the abbreviation of Global Positioning system which adopts GPS unit as the standard timing clock; it
is widely applied in the protection unit and automatic system of power system. PMC-851D supports the minute
and second pulse synchronization; besides, it adapts to the outside pulse signal without setting. Since GPS
pulse synchronization only includes the integral minute/second border signal and fails to provide concrete
hour/minute/second, it is coordinated with the communication synchronization function in the real practice to
reach the level of precise clock synchronization and below 1ms error in the whole station. The typical
application is shown in Figure 3.9c.
Communication time syn. 485 bus
PMC-851D PMC-851D PMC-851D PMC-851D
GPS
GPS clock source
Fig. 3-96 Typical application of GPS synchronization source

The outstanding strengths in IRIG-B synchronization signal and IRIG time code lie in the addition of time
synchronization signal and time code information (day, hour, minute, second) into 1kHz signal carrier. IRIG-B
59
synchronization method is able to analyze precise year/month/day/hour/minute/second from the input signal;
it is able to realize millisecond timing accuracy without other synchronization methods. Communication
synchronization is not recommended to avoid mutual interruption between numerous clocks. The following
parameters are set up for IRIG-B synchronization of PMC-851D.
 Time zone of the system: It means the gap between regional time and GMT in PMC-851D of minute;
the default value is +480; correct setup of existing time zone will obtain a correct result. For instance,
China mainland adopts Beijing time which is 8h later than GMT; this value is +480 (default value).
 Calibration of IRIG-B: The connected IRIG-B signal may not be in standard GMT; the parameter is
adopted to transfer input IRIG-B clock into standard GMT in PMC-851D of minute; the default value is
0. For instance, the output signal of IRIG-B clock source is Beijing time which is later than GMT for 8h;
the parameter is set to be -480 in order to transfer Beijing time into GMT. Please refer to Figure 3.9d
for the typical application.
IRIG-B
IRIG-B source
Fig. 3-97 Typical application of IRIG-B synchronization source

The full name of SNTP is Simple Network Time Protocol; it is compatible with NTP network
synchronization protocol and widely applied in LAN or Internet at large. SNTP protocol is able to maintain the
synchronization between unit time and time server; it has not only saved the frequent maintenance of time
adjustment and guaranteed the time accuracy of various event logs, but also brought convenience to accident
analysis.
PMC-851D supports the unicast mode and broadcast mode in SNTP protocol. Unicast mode aims to obtain
time from the time server at a certain interval; broadcast mode aims to enable the time server to broadcast
existing time to LAN at a certain interval and make PMC-851D receive passively. The following parameters are
set up for SNTP protocol in this unit:
 Time zone of the system: SNTP protocol adopts UTC time (coordinated world time); correct setup of
the existing time zone will obtain a correct result. For instance, Beijing time is set to be +480.
 SNTP synchronization cycle: 0～9999min; PMC-851D is positively connected with the server for
synchronization according to the set time interval. Once 0 is set up, SNTP synchronization function will
60
stop.
 Address of SNTP server: IP address is set up for SNTP time server; the address has to guarantee same
network segment with PMC-851D or visit through the gateway.
Since the broadcast synchronization function fails to identify the source of synchronization message as
legal time server, the gap between existing time and broadcast synchronization time is required to be less than
5 minutes in PMC-851D; otherwise, the synchronization message will be abandoned. Please refer to Figure
3.9e for the typical application.
SNTP server
PMC swtich
SNTP broadcast
Fig. 3-98 Typical application of SNTP synchronization source

The communication synchronization is implemented through Modbus and IEC103 protocol to avoid setup
impact of clock source.
3.10. Network Connection

Two Ethernet ports are collocated for PMC-851D to support flexible network topological form. Ethernet
port can be set into three modes: Switched mode, PMC-Ring mode and Failover mode.
Switched mode: This mode is expected to activate the exchanger inside PMC-851D; two Ethernet ports
are deemed as expansion of unmanaged exchanger inside PMC-851D. PMC-851D is able to not only serve as
the single network port and establish a star network, but also realize cascade connection and ring network
connection. The network connection is very flexible.
Under the switched mode, PMC-851D is able to establish a ring network with ring network exchanger of
third party through RSTP protocol. Special attention is paid to the following point: ring network exchanger
must support the standard RSTP or compatible protocol expanded based on standard RSTP protocol in order to
establish a ring network with PMC-851D. Not all the exchangers supporting ring network functions can operate
normally since it depends on the ring network protocol of the exchanger.
61
Ethernet
Switch
P1 P1 P1 P1 P1 P1
PMC-851X PMC-851M PMC-851D PMC-851T PMC-8700 PMC-851V
Fig. 3-99 Schematic diagram of topological structure in the start connection
Ethernet
Switch
P1 P2 P1 P2 P1 P2
PMC-851X PMC-851M PMC-851D
P1 P2 P1 P2 P1 P2
PMC-851T PMC-8700 PMC-851V
Fig. 3-100 Schematic diagram of topological structure in the cascade connection
Ethernet
Switch with RSTP protocol
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
Fig. 3-101 Schematic diagram of topological structure in the switched mode

PMC-Ring mode: Upon start of this mode, a PMC ring network exchanger is integrated in PMC-851D. It
enjoys the unique PMC ring network calculation methods of PMC ring network exchanger; it is able to establish
62
a self-healing ring network with PMC-2205/2208 looped network exchanger in CLP Technology.
Ethernet
PMC-2205
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
Fig. 3-102 Schematic diagram of topological structure in PMC-Ring mode

Failover mode: Upon start of this mode, two ports become mutually standby chains. Once the network of
main chain is disconnected, the standby chain will be automatically transferred to the main chain; upon
resuming of malfunction chain, it will automatically become the standby chain. The mode is able to upgrade
the chain reliability in the star network.
Ethernet
Switch Switch
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
Fig. 3-103 Schematic diagram of network topological structure in failover mode
63
4. Operating Instructions
4.1. Front Panel
Fig. 4-1 Front panel view
4.2. Keys Operation

Total eight keys are set up below the liquid crystal screen on the front panel of PMC-851D, and they are
Enter Esc Reset Menu

, , , , , , , , with detailed functions as shown below:
64
: Shift up of cursor, being setting +1 in editing mode;
: Shift down of cursor, being setting -1 in editing mode;
: Shift left of cursor or page up, “◄” appears at the upper corner of the page of which page-up is
available when entering the last layer of menu;
: Shift right of cursor or page down, “►” appears at the upper corner of the page of which page-up
is available when entering the last layer of menu;
Menu
: Default that the interface enters the main menu;
Enter
: Confirm the current selection or parameter revision;
Esc
: Exit from current operation or parameter revision;
Reset
: Reset the protection light, alarm light, and configuration Output.
4.3. Signal Indicator Lights

PMC-851D has eight signal indicator lights in total:
Run : Flashing indicates normal work of PMC-851D;
Comm. : Indicator light flashes during communication process of PMC-851D;
Trip
: Red light ON indicates protective action on tripping, and can be turned off by pressing “Reset”
key if all protective action on tripping return;
Alarm : Yellow light ON indicates self-check fault of device or protection action on signals, and can be
turned off by pressing “Reset” key if all protective action on signals return;
Closed : Red light ON indicates breaker is closed;
Open
: Green light ON indicates breaker is open;
79R : Yellow light flashing indicates the condition of ATS ready is satisfied and starts time delay; yellow
light ON indicates ATS is ready; yellow light OFF indicates not ready.
4.4. Default Display Menu

After PMC-851D is powered on, the operating system is started, conducts initialization and self-check of
device, and enters the default interface display, as shown in Fig. 4-2. Press “◄”, “►” key to switch the page
display, the specific page display as shown in Fig. 4-5 ~ Fig. 4-9. Press “ESC” key to return to the default page.
65
The Wiring Diagram on the left side of default page can be collocated through “Config. Setup->System->Main
Diagram” to “Mode 1”, “Mode 2”, or ”Mode 3”.
If PMC-851D is not operated in 10min, the system will return to the page automatically, and meanwhile,
the backlight will be turned off.
kV kV
A
A
A
kW
PF I II
kV kV
2012 -01 - 10 09:36:49 2012 -01 - 10 09:36:49
Fig. 4-2 Default Display (Mode 1) Fig. 4-3 Default Display (Mode 2)
Relay Metering
UAB1 0.00V 0.0°
UBC1 0.00V 0.0°
UCA1 0.00V 0.0°
US1 0.00V 0.0°
I II UAB2 0.00V 0.0°
UBC2 0.00V 0.0°
kV kV
UCA2 0.00V 0.0°
US2 0.00V 0.0°
2012 -01 - 10 09:36:49
Fig. 4-4 Default Display (Mode 3) Fig. 4-5 Relay Metering
Relay Metering Energy

IA 0.000A 0.0° kWh Import
IB 0.000A 0.0° 6908kWh
IC 0.000A 0.0° kvarh Import
IA1 0.000A 0.0° 19kvarh
IA2 0.000A 0.0° kWh Export
I1 0.000A 0.0° 0kWh
I2 0.000A 0.0° kvarh Export
I0 0.000A 0.0° 618kvarh
Fig. 4-6 Relay Metering Fig. 4-7 Energy Data
66
Relay Metering Relay Metering

Active Group 1 ATS_B1 Un-Ready
ATS_B2 Un-Ready
ATS_L1 Un-Ready
ATS_L2 Un-Ready
ART_B1 Un-Ready
ART_B2 Un-Ready
ART_L1 Un-Ready
ART_L2 Un-Ready
Fig. 4-8 Relay Metering Fig. 4-9 Relay Metering
4.5. Logs
SOE report display screen is as shown in Fig. 4-10. The screen is bounced out in case of that protection
operates or fault is discovered with PMC-851D from self-check. In case the protection operates, the “Trip” light
or “Alarm” light will be turned on according to the protection configuration; if fault or error is discovered from
self-check, “Alarm” light will be turned on. The page popped up will display the fault nature, characteristic
value and action time.
Each page may display one SOE report. After “Esc” key is pressed, this page will disappear, and the default
page will be displayed. If multiple SOE reports are displayed, “◄”, “►” may be used for page up and page
down.
▶
001 50P-1 Operate
13-04-22 09:36:52:662
IA=1.53A IB =0.00A
IC=0.00A
Page 001/Total 002
Fig. 4-10 SOE report
4.6. Menu
In case of default display page, press “Menu” key to access the main menu page, as shown in Fig. 4-11.
Here, press “▲”, “▼” key for selection, and the menu selected is highlighted. Here, press “Enter” key to access
the next-level menu.
67
Main Menu
1 Measurements
2 View Setup
3 Config. Setup
4 Logs
5 Power Quality
6 Maintenance
7 Factory
Fig. 4-11 Main menu page
Various functions of PMC-851D device may be accessed through menu, and the menu structure of
PMC-851D is as shown below:
Main menu Measurements Measurements Metering View Setup System
View Setup Relay Metering Relay
Config. Setup Digital Inputs Digital Inputs
Logs Digital Outputs Digital Outputs
Energy Analog Output

Power Quality
Maintenance Communication
Factory Time Sync.
Config.Setup System Logs SOE Logs DI/DO Logs
Relay Select Relay Logs
Relay Diag. Logs
Digital Inputs Maint. Logs
Digital Outputs WFR Logs WFR[1~8]
Analog Output Diagnosis
Communicaton
Group Operate
Time Sync.
68
Power Quality U/Freq Deviation Maintenance Clear SOE Logs
Unbalance Clear WFR Logs
Ia Harmonic Clear WFC Logs
Ib Harmonic Energy Preset
Ic Harmonic User Password
Uab1 Harmonic Clock Setup
Ubc1 Harmonic LCD Contrast
Uca1 Harmonic Version
Uab2 Harmonic
Ubc2 Harmonic
Uca2 Harmonic
Fig. 4-12 Menu structure
4.6.1. Measurements
Select “Measurements” with cursor, and press “Enter” key to access the next-level menu.
“Measurements” menu is as shown in Fig. 4-13; the sub menu is shown as following:
Metering: Display all the primary measuring values such as current, voltage, power, energy, etc. See Fig.
4-14.
Relay Metering: Display all the secondary measuring values such as current, voltage, positive-sequence
current, negative-sequence current, zero-sequence current, etc. See Fig. 4-15.
Digital Inputs: Display the real-time status of binary quantity, as shown in Fig. 4-16.
Digital Outputs: Display the real-time status of outputs, as shown in Fig. 4-17.
Energy: Display the real-time energy accumulation, as shown in Fig. 4-18.
Measurements Metering ▶
1 Metering Uab1 0.000kV 0.0°
2 Relay Metering Ubc1 0.000kV 0.0°
3 Digital Inputs Uca1 0.000kV 0.0°
4 Digital Outputs Us1 0.000kV 0.0°
5 Energy Uab2 0.000kV 0.0°
Ubc2 0.000kV 0.0°
Uca2 0.000kV 0.0°
Us2 0.000kV 0.0°
Fig. 4-13 Menu of Measurements Fig. 4-14 Menu of Metering
69
Relay Metering ▶ Digital Inputs ▶

Busbar1 IN1 OFF IN2 OFF
UAB1 0.00V 0.0° IN3 OFF IN4 OFF
UBC1 0.00V 0.0° IN5 OFF IN6 OFF
UCA1 0.00V 0.0° IN7 OFF IN8 OFF
US1 0.00V 0.0° IN9 OFF IN10 OFF
U1 0.00V 0.0° IN11 OFF IN12 OFF
U2 0.00V 0.0°
IN13 OFF IN14 OFF
Fig. 4-15 Menu of Relay Metering Fig. 4-16 Menu of Digital Inputs
Digital Output ▶ Energy

R-Close OFF kWh Import
R-Trip OFF 6908kWh
Close OFF kvarh Import
Trip OFF 19kvarh
kWh Export
0kWh
kvarh Export
618kvarh
Fig. 4-17 Menu of Digital Outputs Fig. 4-18 Menu of Energy Data
4.6.2. View Setup

On view setup page, it’s only available to view parameters, but not to setup parameters. Select “View
Setup” and press “Enter” key to access the next-level menu, as shown in Fig. 4-19. These settings are the data
having been set up and are in operation, can’t be revised.
System parameters:
It’s available to view the rated value of primary voltage and second voltage, transformation ratio of
current transformer, and the main diagram, etc. as shown in Fig. 4-20.
Relay settings:
1. After accessing the page of relay settings, we may view the eight setting groups, as shown in Fig.
4-21.
2. After selecting the setting group number to be viewed, we may view the settings of each
protection, as shown in Fig. 4-22.
3. After selecting the protection to be viewed, we may access the view page of detailed protection
parameters, as shown in Fig. 4-23.
Digital Inputs:
1. After accessing Digital Inputs page, we may select the DI configuration to be viewed, as shown in
Fig. 4-24.
2.After selecting the DI configuration to be viewed, we may view the detailed parameters of DI
configuration, as shown in Fig. 4-25.
70
Digital Outputs: It’s available to view the output broadening time of configuration outputs, as shown
in Fig. 4-26.
Analog Output: It’s available to view AO configuration parameters, as shown in Fig. 4-27.
Communication:
1. Access the page of communication parameters and then select the communication parameters to
be viewed, as shown in Fig. 4-28.
2. Select the communication parameter to be viewed, and then view the concrete parameter, as
shown in Fig. 4-29.
Time Sync.: It’s available to view the time synchronism parameters, as shown in Fig. 4-30.
View Setup System ▶
1 System Pri. Vnom 10.00kV

Sec. Vnom 100.00V
2 Relay
VS1 Pri. Vnom 10.00kV
3 Digital Inputs
VS1 Sec. Vnom 100.00V
4 Digital Outputs
5 Analog Output
6 Communication
M. CT Ratio 500
7 Time Sync.
P. CT Ratio 500
Fig. 4-19 Menu of View Setup Fig. 4-20 Menu of System
Group Settings Relay ▶
Group1 01 Aux. Element

Group2 02 SOTF-1 Off
Group4 04 SOTF_ATS Off
Group5 05 SOTF_DI Off
Group6 06 50P-1 Off
Group7 07 50P-2 Off
Group8 08 67P-3 Off
Fig. 4-21 Menu of Group Settings Fig. 4-22 Menu of Relay
Aux. Element ▶ Digital Inputs ▶
SOTF Time 3.00s 01 IN1 Settings

27 Element Off 02 IN2 Settings
Pickup 70.00V 03 IN3 Settings
59Neg Element Off 04 IN4 Settings
Pickup 5.00V 05 IN5 Settings
06 IN6 Settings
07 IN7 Settings
08 IN8 Settings
Fig. 4-23 Menu of Auxiliary Element Fig. 4-24 Menu of Digital Inputs
71
IN1 Settings Digital Output ▶
DI Protection Off R-Close 0.01 s

Mode Closed R-Trip 0.01 s
Type Pressure Close 0.01 s
Delay 1.00 s Trip 0.01 s
Output 0000000
Signal Event
Fig. 4-25 Menu of IN1 Settings Fig. 4-26 Menu of Digital Outputs
Analog Output Communication
Key Ia 1 RS-485
Zero 0 2 Ethernet
Full 99999999 3 SNTP
Fig. 4-27 Menu of Analog Output Fig. 4-28 Menu of Communication
RS-485 Time Sync.
Protocol MODBUS UTC Offset 480min

Baudrate 9600 IRIG-B Offset 0min
Slave ID 1 Sync. Source RTC
Parity Even
Stop Bits 1
Fig. 4-29 Menu of RS-485 Fig. 4-30 Menu of Time Sync.
4.6.3. Config. Setup

Input user password for setting up or revising settings. The detailed operating steps are as shown below:
1. Select “Config. Setup” and press “Enter” key to access the next-level menu, as shown in Fig. 4-31;
2. Select the parameter item to be set up and press “Enter” key to bounce out the menu of “user
password”, as shown in Fig. 4-32;
3. Input password and press “Enter” key, and if the password is wrong, the prompt of wrong password
will be bounced out, as shown in Fig. 4-33; if the password is correct, parameter setup screen will be
bounced out, as shown in Fig. 4-34.
4. Select the parameter to be revised and press “Enter” key on the Config. Setup page, and press “◄”,
“►”, “▲”, “▼” keys to revise parameters, as shown in Fig. 4-35;
5. After revision of a parameter, press “Enter” key to confirm the parameter input, or press “Esc” key
72
to cancel parameter revision, and the parameter will return to original value saved;
6, When “Esc” key is pressed to exit from every parameter setup page, PMC-851D will bounce out
“confirm the save setup” page, as shown in Fig. 4-36; press “◄”, “►” to select “Yes” or “No”, and press
“Enter” key to save or not according to the option selected. If “Esc” is pressed on the screen, the data
won’t be saved, and the operation will exit from the previous screen directly.
Default password before delivery: “0000”.
Config. Setup ▶ System
1 System User Password

2 Relay Select 0000
3 Relay
4 Digital Inputs
5 Digital Outputs
6 Analog Output
7 Communication
8 Group Operate
Fig. 4-31 Settings setup menu Fig. 4-32 Password input
System System ▶
User Password Pri. Vnom 10.00kV

0000 Sec. Vnom 100.00A
error！ VS1 Pri. Vnom 10.00kV
M. CT Ratio 500
P. CT Ratio 500
Fig. 4-33 Input password error page Fig. 4-34 System Parameters setup page
System ▶ System
Pri. Vnom 010.00kV Save Changes
Sec. Vnom 100.00A
Yes No
M. CT Ratio 500
P. CT Ratio 500
Fig. 4-35 System parameters setup page Fig. 4-36 Settings save page
1) System parameters setup

Select “System” and press “Enter” key to access the system parameters setup page. System parameters
setup consists of four pages, as shown in Fig. 4-37. Press “◄”, “►” key for switching among different pages.
73
▶
▶
System System ▶
Pri. Vnom 10.00kV IA1 Ratio 100
Sec. Vnom 100.00A IA2 Ratio 100
VS1 Pri. Vnom 10.00kV System Freq. 50Hz
VS1 Sec. Vnom 100.00V DI Source DC
VS2 Pri. Vnom 10.00kV SBO On
VS2 Sec. Vnom 100.00V Main Diagram Mode 1
Language English
M. CT Ratio 500
P. CT Ratio 500
▶ ▶
System ▶ System
Breaker State Config. Events Setting

BRK1 NO Start Events Off
BRK2 NO Dropout Event Off
Tie BRK Ext. NC
Fig. 4-37 System parameters setup page
Note 1: “DI Source” is defaulted to be “DC”, indicating supporting DC voltage excitation; if it is collocated
to “AC”, it indicates supporting AC voltage excitation. If AC voltage excitation is used, it shall please be
collocated to “AC”.
Note2: “BRK1” (or BRK2) is defaulted to be “NO” (normally open contact). If “BRK1” (or BRK2) is
collocated to “NO”, QF1 (or QF2) is closed when IN1 (or IN2) asserted, QF1 (or QF2) is open when IN1(or IN2)
deasserted. If “BRK1” (or BRK2) is collocated to “NC” (normally closed contact), QF1 (or QF2) is closed when
IN1 (or IN2) asserted, QF1 (or QF2) is open when IN1(or IN2) deasserted.
Note3: “Tie BRK” is defaulted to be “Normal”. If “Tie BRK” is collocated to “Ext. NC” (normally closed
contact), QF3 is closed when IN3 asserted, QF3 is open when IN3 deasserted. If “Tie BRK” is collocated to “Ext.
NO” (normally open contact), QF3 is open when IN3 asserted, QF3 is closed when IN3 deasserted. If “Tie BRK”
is collocated to “Normal”, the status of QF3 gets from operate board, detected by BRK closed status and BRK
open status.
Note 4: the default value of Events Setting is all “Off”.
If “On” is selected for “Start Events” and “Dropout Events”, then relevant protection start-up events,
trip events, and return events will be recorded.
If “On” is selected for “Start Events”, but “Off” is selected for “Dropout Events”, then relevant
protection start-up events and trip events will be recorded.
If “Off” is selected for “Start Events”, but “On” is selected for “Dropout Events”, then relevant
protection trip events and return events will be recorded.
If “Off” is selected for “Start Events” and “Dropout Events”, then relevant protection trip events will
only be recorded.
74
2) Relay select settings setup

Select “Relay Select” and press “Enter” key to access the relay select parameters setup page, as shown in
Fig. 4-38. press “▲”, “▼” key to move cursor, press “◄”, “►” key for switching among different pages, press
“Enter” to select or cancel corresponding protection.
Relay Select ▶
01 Aux. Element
02 SOTF-1 □
03 SOTF-2 □
04 SOTF_ATS □
05 SOTF_DI □
06 50P-1 □
07 50P-2 □
08 67P-3 □
Fig. 4-38 Setting group selection page
Only selected protection is visible in “Config. Setup” and “View Setup”.

3) Relay settings setup
PMC-851D has eight setting groups. It’s available to pre-set multiple setting groups, and activate different
settings according to actual working conditions, as shown in Fig. 4-39. Press “▲”, “▼” key to select one setting
group, and press “Enter” key to access the setup of this setting group.
On setting page, press “▲”, “▼”, “◄”, “►” key to move cursor. Press ◄”, “►” key to move cursor for
paging left or right. If the symbol “◄”, “►” displayed on the top of page, it indicates that the current page can
be moved left and right. Press “Enter” key to enter the sub menu or to edit the parameter.
Group Settings Relay ▶
Group1 01 Aux. Element

Group4 04 SOTF_ATS Off
Group5 05 SOTF_DI Off
Group6 06 50P-1 Off
Group7 07 50P-2 Off
Group8 08 67P-3 Off
Fig. 4-39 Setting group selection page Fig. 4-40 Relay setup page
75
50P-1 Output
DI Strap Off Trip □

DI Block Off OUT1 □ OUT2 □
27E/59Neg.E Off OUT3 □ OUT4 □
Pickup 20.00 OUT5 □ OUT6 □
Delay 1.00s
Output 0000000
Fig. 4-41 50P-1 setup page Fig. 4-42 Output configuration page
As shown in Fig. 4-40, we shall press “►”, “◄” key to move to the location of the right “50P-1” Relay,
select “On” or “Off”, and press “Enter” key to access setting; press “▲”, “▼” key to select “On” or “Off”, and
press “Enter” key to confirm “50P-1” Relay setting.
Select corresponding protection function. For example, select “50P-1” menu, press “Enter” key to access
the setup page, and then set up the “50P-1”, as shown in Fig. 4-41.
Select value of “Output” and press “Enter” to access the setup page of output, as shown in Fig. 4-42.
press “Enter” to select output, press “Enter” again to cancel the output, press “Esc” to return to the previous
menu.
4) Digital Inputs settings setup
Digital Inputs is as shown in Fig. 4-43, and the operation is the same as that of relay settings setup;
Digital Inputs ▶ IN1 Settings
01 IN1 Settings DI Protection Off

02 IN2 Settings Mode Closed
03 IN3 Settings Type Pressure
04 IN4 Settings Delay 1.00 s
05 IN5 Settings Output 0000000
06 IN6 Settings Signal Event
07 IN7 Settings
08 IN8 Settings
Fig. 4-43 Digital inputs setup page
5) Digital Outputs
The page for setup of Digital Output width is as shown in Fig. 4-44, and the operation is the same as that
of relay settings setup;
If the output is set up to be “1.00s”, it indicates that after action of output, the contact is maintained until
protection dropout and then is reset 1s later automatically.
If the output is set up to be “Latch”, it indicates that, after action of output, the contact is maintained, and
not reset until “Reset” key is pressed or “reset” is executed through remote control.
76
Digital Outputs ▶ Digital Outputs ◀

R-Close 0.01 s OUT1 0.01 s
R-Trip 0.01 s OUT2 0.01 s
Close 0.01 s OUT3 0.01 s
Trip 0.01 s OUT4 0.01 s
OUT5 0.01 s
OUT6 0.01 s
Fig. 4-44 Digital outputs setup page
6) Analog output setup

Analog output parameters may be revised under this page, and parameters will take effect immediately
after being saved.
Analog Output
key Ia
Zero 0
Full 9999999
Fig. 4-45 Analog output setup page
7) Communication
Communication menu page is as shown in Fig. 4-46, and the operation is the same as that of system
parameters setup;
PMC-851D has dual Ethernet ports, and supports four port modes: Failover, switch, PMC-Ring, and
standalone. Users may make choice according to the actual form of network topology.
If the port IP address is wrongly set up, the prompt “Config. Error!” will appear, and the parameter wont’
be saved.
If the port mode is set up to be PMC-Ring network mode, it’s available to form self-cure ring network
together with CET’s PMC serial industrial ring network, and the ID of ring network must be set up accordant
with that of ring network switch for the sake of communication. If the port mode is set up to be
primary-standby switching and switchboard, the ID of ring network won’t work. The specific port mode and
application situations can refer to content of the section 3.10.
PMC-851D supports SNTP network timing. The timing server address and time query interval are set up in
the “SNTP” interface, and wherein, the update rate is the interval between PMC-851D’s timing and the server’s
synchronous clock, and if it is set up to be 0, timing won’t act.
77
Communication RS-485
1 RS-485 Protocol MODBUS

2 Ethernet Baudrate 9600
3 SNTP Slave ID 1
Parity Even
Stop Bits 1
Fig. 4-46 Communication setup menu Fig. 4-47 RS-485 setup page
Ethernet Ethernet
Port Mode PMC-Ring Port Mode Standalone

Ring ID 1 Ring ID 1
IP 192.168. 0.100 IP1 192.168. 0.100
MASK 255.255.255. 0 MASK1 255.255.255. 0
GW 192.168. 0. 1 GW1 192.168. 0. 1
IP2 192.168. 1.100
MASK2 255.255.255. 0
GW2 192.168. 1. 1
Fig. 4-48 Ethernet setup page Fig. 4-49 Ethernet setup page
SNTP
Server
IP 0. 0. 0. 0
Update Rate 1min
Fig. 4-50 SNTP setup page
8) Group operate
Group operation includes two functions: active group switching, and group copying.
Group Operate
1 Active Group
2 Group Copy
Fig. 4-51 Setting group operation menu
The setting group currently in operation may be switched online on the page of Active Group and settings
78
will take effect immediately after being saved.
Active Group
Present Group 1
Select Group 2
Fig. 4-52 Active groups switching page
On the page of group copying, all the parameters of one setting group may be totally copied to another
setting group.
On this page, select the source group number and the target group number successively, move the cursor
to behind the copy button, then press “Enter” button, and all parameters of the source group will be copied to
the target group. After group copy, there will be a prompt of successful copy, and the page won’t be closed.
Here, another target setting group may be selected for continuous copy operation.
Group Copy
Source Group 1
Target Group 2
Exit Copy
Fig. 4-53 Setting group copy page
9) Time sync. setup

It’s available to revise UTC Offset, IRIG-B Off. And Sync. Source on this page and parameters will take effect
immediately after being saved.
UTC Offset is the difference between current local time and international standard UTC time, with minute
as the unit. For example, Beijing time is UTC time + 8h, then UTC Offset will be set to be 8 X 60min = 480min.
IRIG-B Off. is used to correct the difference between IRIG-B signal time and international standard UTC
time, and to adjust the input IRIG-B time to international standard UTC time, with minute as the unit.
The time of this device may be maintained synchronous through the high-precision RTC with temperature
compensation inside PMC-851D, SNTP server, IRIG-B signal and GPS timing pulse. At the same time, device can
select only one Synchronism Source, which shall be configured according to actual situations.
79
Time Sync.
UTC Offset 480min

IRIG-B Off. 0min
Sync. Source RTC
Fig. 4-54 Time Sync. setup
4.6.4. Logs Management

The Logs page is as shown in Fig. 4-55. Press “▲”, “▼” key to make choice, and the menu selected is
highlighted. Press “Enter” key to access next-level menu, as shown in Fig. 4-56.
Logs SOE Logs
1 SOE Logs 1 DI/DO Logs

2 WFR Logs 2 Relay Logs
3 Diagnosis 3 Diag. Logs
4 Maint. Logs
Fig. 4-55 Logs page Fig. 4-56 SOE Logs page
1) SOE Logs
As shown in Fig. 4-57～4-60, each page may display 1～2 events at one stroke. Press “◄”, “►” key to
page down or page up for viewing records. There are 512 entries of SOE Logs at the most.
DI/DO Logs ▶ Relay Logs ▶
001 OUT1 Dropout 001 67P-1 Operate

11-04-22 12:17:35:132 11-04-22 12:17:35:962
IA=1.84A IB=0.02A
002 Protect Trip Dropout IC=0.02A
11-04-22 12:17:35:132
Page 001/Total 002 Page 001/Total 002
Fig. 4-57 DI/DO logs page Fig. 4-58 Relay logs page
80
Diag. Logs Maint. Logs ▶
001 FRAM Fault Operate 001 Power Up

11-04-20 12:17:35:132 11-04-22 12:17:35:132
002 Power Down

11-04-22 12:17:10:100
Page 001/Total 001 Page 001/Total 005
Fig. 4-59 Diag. logs page Fig. 4-60 Maint. logs page
2) WFR
WFR page is as shown in Fig. 4-61~4-64. Press “▲”, “▼” key to display WFR index and log, then display
waveform. The length of each complete wave record is 100 cycles. Press “►”, “◄” to view waveforms, and 4
cycles are moved each time.
WFR Logs WFR1
1 WFR1 67P-1 Operate

2 WFR2 IA=1.84A IB=0.02A
3 WFR3 IC=0.02A
4 WFR4
5 WFR5 Triggered At
6 WFR6 11-04-22 12:17:35:962
7 WFR7
8 WFR8
Fig. 4-61 WFR Logs page Fig. 4-62 WFR logs
WFR1 WFR1
IA/A 1-4 BRK Closed 1-4
77.4
-77.4
IB/A BRK Open
77.4
-77.4
Fig. 4-63 WFR display Fig. 4-64 WFR display
3) Diagnosis
Diagnosis page is as shown in Fig. 4-65, and it shows Diagnosis information.
81
Diagnosis
Relay CPU OK
EEPROM OK
NVRAM OK
A/D OK
Settings OK
Analog Ch. OK
Fig. 4-65 Diagnosis page
4.6.5. Power Quality

As shown in Fig. 4-66, PMC-851D provides the analyzing functions of U/Freq deviation, unbalance,
harmonics of three-phase currents, and harmonics of three-phase voltages.
Power Quality ▶ Power Quality
1 U/Freq Deviation 1 U/Freq Deviation

2 Unbalance 2 Unbalance
3 Ia Harmonics 3 Ia Harmonics
4 Ib Harmonics 4 Ib Harmonics
5 Ic Harmonics 5 Ic Harmonics
6 Ua Harmonics
7 Ub Harmonics
8 Uc Harmonics
U/Freq Deviation Uab Harmonics ▶
UAB1 ev. -100% THD 0.00%

UBC1 Dev. -100% TOHD 0.00%
UCA1 Dev. -100% TEHD 0.00%
f1 Dev. -50.00Hz HD2 0.00% HD3 0.00%
UAB2 ev. -100% HD4 0.00% HD5 0.00%
UBC2 Dev. -100% HD6 0.00% HD7 0.00%
UCA2 Dev. -100% HD8 0.00% HD9 0.00%
f2 Dev. -50.00Hz HD10 0.00% HD11 0.00%
Fig. 4-66 page of power quality
4.6.6. Maintenance
The following work may be completed after accessing this page: Clear SOE Logs, WFR, WFC; set up original
value of energy; revise user password; revise system time; display device information, as shown in Fig. 4-67.
82
Maintenance Clear SOE Logs
1 Clear SOE Logs Clear SOE Logs

2 Clear WFR Logs Yes No
3 Clear WFC Logs
4 Energy Preset
5 User Password
6 Clock Setup
7 LCD Contrast
8 Version
Fig. 4-67 page of maintenance
4.6.7. Factory
The page is used for factory calibration.
PMC-851D has been subject to strict debugging and calibration before being delivered, and shall not be
changed at random by non-professional maintenance personnel! Factory password is required for accessing
this menu.
4.6.8. Settings List
Table 4-1 Settings List
Parameter Name Unit Setting Scope Default Value
Pri. Vnom kV 0.10～550.00 10.00

Sec. Vnom V 50.00～120.00 100.00
VS1 Pri. Vnom kV 0.10～550.00 10.00
VS1 Sec. Vnom V 50.00～120.00 100.00
VS2 Pri. Vnom kV 0.10～550.00 10.00
VS2 Sec. Vnom V 50.00～120.00 100.00
M. CT Ratio 1～9999 100
P. CT Ratio 1～9999 100
System IN Ratio 1～9999 100

Parameters IX Ratio 1～9999 100
IA1 Ratio 1～9999 100
IA2 Ratio 1～9999 100
System Freq. Hz 50/60 50
DI Source DC/AC DC
SBO Off/On On
Main Diagram Mode 1/Mode 2/Mode 3 Feeder
Language Chinese/ English Chinese
BRK1 NO/ NC NO
83
BRK2 NO/ NC NO
Tie BRK Ext. N0/ Ext. NC/Normal Normal
Start Events Off/On Off
Dropout Events Off/On Off
SOTF Time s 0.20～20.00 3.00

27 Element Off/On Off
Pickup V 1.00～120.00 70.00
59Neg Element Off/On Off
Pickup V 1.00～36.00 5.00
50P-E1 Off/On Off
0.25～100.00(5A rated)
Pickup A 20.00
0.05～20.00(1A rated)
Aux. Element Output 0000000~1111111(Binary) 0
50P-E2 Off/On Off
0.25～100.00(5A rated)
Pickup A 20.00
0.05～20.00(1A rated)
Output 0000000~1111111(Binary) 0
50P-E3 Off/On Off
0.25～100.00(5A rated)
Pickup A 20.00
0.05～20.00(1A rated)
Output 0000000~1111111(Binary) 0
SOTF-1 Off/On Off
DI Strap Off/IN1～IN14 Off
27E/59Neg.E Off/On Off
SOTF-1,2 0.25～100.00(5A rated)
Pickup A 20.00
0.05～20.00(1A rated)
Delay s 0.00～3.00 0.00
Output 0000000~1111111(Binary) 0
SOTF_ATS Off/On Off
SOTF_ATS 27E/59Neg.E Off/On Off
0.25～100.00(5A rated)
Pickup A 20.00
0.05～20.00(1A rated)
84
Delay s 0.00～3.00 0.00
Output 0000000~1111111(Binary) 0
SOTF_DI Off/On Off

SOTF_DI 0.25～100.00(5A rated)
Pickup A 20.00
0.05～20.00(1A rated)
Delay s 0.00～3.00 0.00
Output 0000000~1111111(Binary) 0
50P-1 Off/On Off
DI Block Off/On Off
50P-1
0.25～100.00(5A rated)
Pickup A 20.00
0.05～20.00(1A rated)
Delay s 0.00～99.99 1.00
Output 0000000~1111111(Binary) 0
50P-2 Off/On Off
50P-2,3,4 0.25～100.00(5A rated)
Pickup A 20.00
0.05～20.00(1A rated)
Delay s 0.00～99.99 1.00
Output 0000000~1111111(Binary) 0
50P-5 Off/On Off
0.25～100.00(5A rated)
Pickup A 20.00
50P-5 0.05～20.00(1A rated)
Delay s 0.00～600.00 1.00
Output 0000000~1111111(Binary) 0
Signal Alarm/Trip Alarm
51P Off/On Off

51P
85
Curve C1/C2/C3/C4/C5/U1/U2/U3/U4/U5 C3
0.25～15.00(5A rated)
Pickup A 3.00
0.05～3.00(1A rated)
Time Dial 0.05～15.00 1.00
Output 0000000~1111111(Binary) 0
Signal Alarm/ Trip Alarm
Reset Type At Once/Equation At Once
SOTF_I0-1 Off/On Off
0.25～100.00(5A rated)
SOTF_I0-1,2 Pickup A 20.00
0.05～20.00(1A rated)
Delay s 0.00～3.00 0.00
Output 0000000~1111111(Binary) 0
SOTF_I0_ATS Off/On Off
0.25～100.00(5A rated)
SOTF_I0_ATS Pickup A 20.00
0.05～20.00(1A rated)
Delay s 0.00～3.00 0.00
Output 0000000~1111111(Binary) 0
50I0-1 Off/On Off
0.25～100.00(5A rated)
Pickup A 20.00
50I0-1,2 0.05～20.00(1A rated)
Delay s 0.00～99.99 1.00
Output 0000000~1111111(Binary) 0
51I0 Off/On Off
Curve C1/C2/C3/C4/C5/U1/U2/U3/U4/U5 C3
0.25～15.00(5A rated)
51I0 Pickup A 3.00
0.05～3.00(1A rated)
Time Dial 0.05～15.00 1.00
Output 0000000~1111111(Binary) 0
86
Reset Type At Once/Equation At Once

59PP_B1-1 Off/On Off
59PP_B1-1,2 Pickup V 1.00～180.00 150.00

59PP_B2-1,2 Delay s 0.00~600.00 1.00
Output 0000000~1111111(Binary) 0
27PP_B1-1 Off/On Off
Ever Volt Off/On Off
dU/dt Block Off/On Off
27PP_B1-1,2
dU/dt Pickup V/s 5.00~192.00 10.00
27PP_B2-1,2
Pickup V 1.00~120.00 70.00
Delay s 0.00~99.99 1.00
Output 0000000~1111111(Binary) 0
27PP Off/On Off
dU/dt Block Off/On Off
dU/dt Pickup V/s 5.00~192.00 10.00
27PP
Pickup V 1.00~120.00 70.00
Delay s 0.00~99.99 1.00
Output 0000000~1111111(Binary) 0
81O_B1-1 Off/On Off
81O_B1-1,2 Pickup Hz 50.00~65.00 55.00

81O_B2-1,2 Delay s 0.10~99.99 1.00
Output 0000000~1111111(Binary) 0
81U_B1-1 Off/On Off
81U_B1-1,2
81U_B2-1,2
Df/dt Block Off/On Off
87
Df/dt Pickup Hz/s 1.00～10.00 10.00

Pickup Hz 45.00～60.00 45.00
Delay s 0.10～99.99 1.00
Output 0000000~1111111(Binary) 0
81U Off/On Off
Df/dt Block Off/On Off
Df/dt Pickup Hz/s 1.00～10.00 10.00
81U
Pickup Hz 45.00～60.00 45.00
Delay s 0.10～99.99 1.00
Output 0000000~1111111(Binary) 0
32P-1 Off/On Off
Direction FWD/REV FWD
10.00～500.00(5A rated)
32P-1,2 Pickup W 100.00
2.00～100.00(1A rated)
Delay s 0.10～99.99 1.00
Output 0000000~1111111(Binary) 0
25 Off/On Off
Max. Angle ° 10～90 30
Max. Frequency Hz 0.10～1.00 1.00
Max. Voltage V 1.00～24.00 5.00
25
Manual Close Off/On Off
Output 0000000~1111111(Binary) 0
Remote Close Off/On Off
Check Time s 1.00～99.99 1.00
Output 0000000~1111111(Binary) 0
LOP_B1 Off/On Off
LOP_B1，2
27E/59Neg.E Release/Block Release
88
Output 0000000~1111111(Binary) 0
CT Monitor Off/On Off
CT Monitor
Output 0000000~1111111(Binary) 0
74TC Off/On Off
74TC Delay s 0.50～99.99 1.00
Output 0000000~1111111(Binary) 0
Live Volt. V 1.00～144.00 70.00
Dead Volt. V 1.00～120.00 30.00
Ready Delay V 1.00～99.99 15.00
Un-Ready Delay s 1.00～60.00 10.00
Trip Check
Off/On On
LiveLine
Close Check
Off/On On
LiveLine
Aux. Para.
DI Mode 000000~111111(Binary) 000000
BLK ATS_B1 000000~111111(Binary) 000000
BLK ATS_B2 000000~111111(Binary) 000000
BLK ATS_L1 000000~111111(Binary) 000000
BLK ATS_L2 000000~111111(Binary) 000000
DI Block ATS
Delay s 0.00～99.99 0.00
IN9~IN14
27PS Off/On Off
Pickup V 1.00～120.00 30
27PS
Delay s 0.00～99.99 1.00
Output 0000000~1111111(Binary) 0
50PS Off/On Off
0.25～100.00(5A rated)
50PS Pickup A 20.00
0.05～20.00(1A rated)
Delay s 0.00～99.99 1.00
Output 0000000~1111111(Binary) 0
89

50P_L1 Off/On Off
0.25～100.00(5A rated)
Pickup A 20.00
50P_L1,2 0.05～20.00(1A rated)
Delay s 0.00～600.00 1.00
Output 0000000~1111111(Binary) 0
50LR Off/On Off
0.50～100.00(5A rated)
Pickup A 20.00
50LR 0.10～20.00(1A rated)
Delay s 0.10～99.99 1.00
Output 0000000~1111111(Binary) 0
ATS_B1 Off/On Off
Trip Delay s 0.00～60.00 1.00
Trip Output 0000000~1111111(Binary) 0
Close Delay s 0.00～60.00 0.50
Close Output 0000000~1111111(Binary) 0
ATS_B1,2
ART_B1 Off/Mode 1/Mode 2 Off
Close Delay s 0.00～30.00 1.00
Trip Delay s 0.00～30.00 1.00
ATS_L1 Off/On Off
Trip Delay s 0.00～60.00 1.00
Close Delay s 0.00～60.00 0.50
ATS_L1,2
ART_L1 Off/Mode 1/Mode 2 Off
Close Delay s 0.00～30.00 1.00
Close Output s 0000000~1111111(Binary) 0
90
Trip Delay s 0.00～30.00 1.00

25_L1 Off/On Off
25_L1,2 Max. Angle ° 10～90 30
Max. Frequency Hz 0.10～1.00 1.00
Max. Voltage V 1.00～24.00 5.00
50LS_L1-1 Off/On Off
0.25～100.00(5A rated)
50LS_L1-1,2,3 Pickup A 20.00
0.05～20.00(1A rated)
50LS_L2-1,2,3
Delay s 0.00～99.99 1.00
Output 0000000~1111111(Binary) 0
DI Protection Off/On Off

Mode Closed/Open Closed
DI Protection
Type Refer to the note. Pressure
(IN1~IN10,
Delay s 0.00～99.99 1.00
Ext. Trip)
Output 0000000~1111111(Binary) 0
Signal Alarm/ Trip/ Event Event
DI Protection Off/On Off
Mode Closed/Open Closed
DI Protection Type Refer to the note . Pressure

(IN11~IN14) Delay s 0～7200 1
Output 0000000~1111111(Binary) 0
Signal Alarm/ Trip/ Event Event
R-Close s 0.01～99.99/Latch 1.00

R-Trip s 0.01～99.99/Latch 1.00
Digital Output Close s 0.01～99.99/Latch 1.00
Trip s 0.01～99.99/Latch 1.00
OUT1 s 0.01～99.99/Latch 1.00
91
OUT2 s 0.01～99.99/Latch 1.00

OUT3 s 0.01～99.99/Latch 1.00
OUT4 s 0.01～99.99/Latch 1.00
OUT5 s 0.01～99.99/Latch 1.00
OUT6 s 0.01～99.99/Latch 1.00
Ia/Ib/Ic/Iavg/UAB1/UBC1/UCA1/
Key Ia
UAB2/UBC2/UCA2/P/Q
AO
Zero -9999999～9999999 0
Full -9999999～9999999 5
Protocol MODBUS/IEC103 MODBUS
Baud rate 2400/4800/9600/19200/38400 9600
Slave ID 1～247 1
Parity None/ Odd/Even Even
Stop Bits 1/2 1
Failover/ Switched/ PMC-Ring/
Port Mode Failover
Standalone
Ring ID 1~255 1
Communication
IP1 192.168.0.100
MASK1 255.255.255.0
GW1 192.168.0.1
IP2 192.168.0.100
MASK2 255.255.255.0
GW2 192.168.0.1
Server 0.0.0.0
Update Rate min 0~9999 1
UTC Offset min -720~780 480
Time IRIG-B Off. min -1440~1440 0
Sync. Source RTC/ GPS/SNTP/IRIG-B RTC
NOTES:
1. The event type of digital inputs is optional: Pressure, Temp. 1, Temp. 2, Temp. 3, DCS1, DCS2, DCS3,
Spring, and DCS4.
2. 5A rated and 1A rated in current setting of phase protection current indicate the rated value of phase
current.
3. When digital output width is set up to be ”0.00s”, the setting is displayed as “Latch”.
92
5. Installation and Debugging

5.1. Installation
PMC-851D should be installed in a dry environment with no dust and kept away from heat, radiation and
electrical noise sources.
5.1.1. Installation Chart
PMC-851D is fixed with two metal clamps at the upside and downside. The installation method and size
are as shown in the Fig. 5-1.
Fig. 5-1 Panel Cutout

5.1.2. Backplane Terminal Layout
The connecting terminal is as shown in the following chart. PMC-851D has four backplanes which may be
inserted and pulled out, and they are power panel, operation board, main board, and AC board respectively.
There are different combinations according to different option, as shown in following charts.
The terminal drawing of the DC operation board and dual 10/100 Base-T device is as shown in Fig. 5-2:
93
Fig. 5-2 Wiring terminal drawing of DC operation board and dual 10/100 Base-T
94
The terminal drawing of the DC operation board and dual 100 Base-FX device is as shown in Fig. 5-3:
Fig. 5-3 Wiring terminal drawing of DC operation board and dual 100 Base-FX
95
The terminal drawing of the AC operation board and dual 10/100 Base-T device is as shown in Fig. 5-4:
Fig. 5-4 Wiring terminal drawing of AC operation board and dual 10/100 Base-T
96
The terminal drawing of the AC operation board and dual 100 Base-FX device is as shown in Fig. 5-5:
Fig. 5-5 Wiring terminal drawing of AC operation board and dual 100 Base-FX
97
Table 5-1 Terminal Diagram Description

Backpla Terminal
Description
ne No. identification
COM DI public end
IN1 Status of QF1 (line 1# breaker)
IN2 Status of QF2 (line 2# breaker)
IN3 Status of QF3 (tie breaker)
IN4 Digital input to enable ATS
IN5 Digital input to enable ART
A IN6 Digital input to block 50P-1
IN7 Manual synchronism closing input
IN8 SOTF_DI input
IN9~IN14 User-defined to block ATS
Alarm Device self-check alarm contact
Power supply for PMC-851D, DC+ is positive, and – is negative;
L/+, N/-
AC L is phase line, and N is neutral line.
L Power supply for AC operation board, phase line
N Power supply for AC operation board, neutral line
+WC Power supply for DC operation board, DC positive
-WC Power supply for DC operation board, DC negative
OpePS Operation power supply
RemPS Enable to remote control
M-Close IN Input of manual close
Close IN Input of relay close
B Close OUT Output of relay close(reclosing)
M-Trip IN Input of manual trip
Trip IN Input of relay trip
Trip OUT Output of relay trip
Link OUT Output of link trip
Link IN Input of link trip
C-Coil Coil of close
T-Coil Coil of trip
Supervi Supervisor of BRK Open
98
KKJ Manual Control Switch Position After Closing

OUT1~OUT6 User-defined output, normally-open contact
Ethernet interface 1, default: electric interface (optical
P1
interface is optional)
Ethernet interface 2, default: electric interface (optical
P2
C interface is optional)
D+/D-/SH RS-485 interface（optional）, signals A, B and shield grounding
GPS+/GPS-/SH Differential GPS timing, pulse A, B and shield grounding
AO+/AO- Analog output +/-（optional）
A phase meter current input, becoming synonym end with “•”
Ia·/Ia
added.
B phase meter current input, becoming synonym end with “•”
Ib·/Ib
added.
C phase meter current input, becoming synonym end with “•”
Ic·/Ic
added.
A phase protective current input, becoming synonym end with
IA·/IA
“•” added.
B phase protective current input, becoming synonym end with
Z IB·/IB
“•” added.
C phase protective current input, becoming synonym end with
IC·/IC
“•” added.
IA1·/IA1 Line 1# current input, becoming synonym end with “•” added.
IA2·/IA2 Line 2# current input, becoming synonym end with “•” added.
VS1/VS1N Line 1# voltage input (defaulted UAB)
VS2/VS2N Line 2# voltage input (defaulted UAB)
VA1/VB1/VC1 3-phase voltage inputs of busbar Ⅰ
VA2/VB2/VC2 3-phase voltage inputs of busbar Ⅱ
Power panel: The working power supply for PMC-851D, 14-channel digital inputs and power-failure alarm
(sharing the contact with self-check alarm), panel number A;
operation board: divide into two kinds that one is DC operation board, the other is AC operation board,
board number B;
Main board: CPU board, communication port for external output, as well as AO, GPS interface, board
number C.
AC board: AC input board, 6-channel voltage inputs, 8-channel current inputs, board number Z.
99
5.2. RTC battery

The RTC battery locates at Board Number C, which supply the power of device clock (data and time) if
external power is off. The RTC battery is fastener cell which is 3V. The RTC battery is just in a low self-discharge
state, while device is supplied by external power.
If PMC-851D cannot recover correct time and date after power off, the RTC battery should be replaced.
Make sure the device is power off, pull out Board Number C, and replace the RTC battery, notice the positive
pole of battery is upside, restore the device at last. Set the data and time through the front panel or serial
interface of PMC-851D.
5.3. Power-On Test

1) The following documents shall be prepared before debugging:
 Specifications of PMC-851D, and the design drawings for screen combination of tested protection
screen;
 Design Institute’s design atlas about the connection of tested protection screen with other external
circuits;
 Related drawings and parameters about the main wiring of primary equipment protected by the
tested protection screen, and relevant secondary equipment.
2) Inspection before power on
 Exit from the protection of all straps, and disconnect all air switches;
 Check whether the model and parameters of PMC-851D are accordant with that ordered, and ensure
the rated voltage of DC power supply to match with onsite voltage;
 Check whether plug-in units get loose, whether PMC-851D has mechanical damage, and whether the
location of each plug-in unit is accordant with that regulated in drawings;
 Check whether the wiring has the phenomena like loose crimping and line break, etc.;
 Use a multi-meter to check whether the power circuit has failures like short circuit or circuit break;
 Confirm that PMC-851D is grounded reliably;
 Check whether the appearance of PMC-851D is sound, and whether the terminal, keys, and LCD unit
are sound.
3) Electrification
 Close the air switch of working power supply to make “L/+” and “N/-” terminals connected to normal
working power supply;
 Close the air switch of operation power supply to make operation board normal working.
4) Power-on inspection
 If the software of PMC-851D powered on starts to operate normally, then the “Run” indicator light
of PMC-851D will turn on, and we may simply judge whether each CPU board and program are
normal;
100
 Check whether the liquid crystal screen displays normally;

 Check whether the software version meets requirement by referring to the user manual of
PMC-851D.
 Check the parameter setting of this device. If the default setting before delivery of PMC-851D does
not meet onsite requirements, corresponding setting shall be conducted by referring to the user
manual of PMC-851D.
5.4. Debugging before being Put into Operation

After passing power-on test, PMC-851D may be connected to AC voltage and current to carry out
protection and measurement test before being put into operation; if there are communication requirements,
PMC-851D shall be connected to communication port for test simultaneously. After being proved normal
through various tests, PMC-851D may be put into use.
In case any problem is discovered, users shall notify the manufactory or onsite service personnel
immediately.
1) Metering analog debugging
It is conducted under the “Measurements->Metering” menu, and the AC quantity inputs includes: UAB1,
UBC1, US1, UAB2, UBC2, US2, Ia, Ib, Ic. Set PT ratio and CT ratio of PMC-851D to default value. Charge rated
voltage and rated current from above channels respectively. For example, the typical Rated values of
PMC-851D are: phase-to-phase voltage 100V, current 5A. After 100V is added to all voltage, the accuracy of
primary metering value of voltages displayed by PMC-851D shall be within the scope of ±0.2%; after 5A is
added to the current of three phases Ia, Ib, Ic respectively, the accuracy of primary metering value of the
three-phase currents displayed by PMC-851D shall be within the scope of ±0.2%.
2) Protection analog debugging
It is conducted under the “Measurements->Relay Metering” menu, and the AC quantity inputs includes:
UAB1, UBC1, US1, UAB2, UBC2, US2, IA, IB, IC, IA1, IA2. Charge rated voltage and rated current from above
channels respectively. For example, the typical rated values of PMC-851D are: phase-to-phase voltage 100V,
current 5A. After 100V is added to all voltages, the accuracy of secondary metering value of voltages displayed
by PMC-851D shall be within the scope of ±0.5%; after 5A is added to the three-phase currents of IA, IB, IC
respectively, the accuracy of secondary metering value of currents displayed by PMC-851D shall be within the
scope of ±0.5%.
3) DI debugging
DI debugging is conducted under the “Measurements->Digital Inputs” menu. Charge rated voltage from
14 channels respectively. For example, the rated value of PMC-851D’s digital input is 220V, then access “Config.
Setup-> System” to set up “DI Source” as “DC”, connect the negative pole of DI 220VDC excitation to the A-1
terminal (DI public terminal) of PMC-851D, then connect the positive pole of DI 220VDC excitation to (A-2)～
(A-15) of PMC-851D respectively, and the DI status displayed is changed from “OFF” to “ON”; disconnect the
101
positive pole and (A-2)～(A-15) of PMC-851D, and the DI status displayed is changed from “ON” to “OFF”.
4) DO debugging
DO debugging may be conducted in “DO Test” of “Factory”. Select the output to be debugged, and press
“Enter” key to test whether the output operate correctly.
5) Relay action test
Conduct debugging according to concrete project setting.
6) Communication function debugging
It is conducted under “Config. Setup-> Communication” menu to confirm the continuous number of each
protection device inside the substation, and that there is no repeated address number. Connect PMC-851D
with communication management machine, and connect it to the monitoring background. Conduct related
operations at the background, like reading the metering value and protection setting, revising and
downloading settings, remote resetting, protection time check, DI/DO call, reading protection action event
information and WFR information, etc., and check whether the protection device can normally respond to and
correctly execute commands; meanwhile, observe whether the communication between the protection device
and upper-position computer is normal by monitoring the communication management machine and
background messages.
7) Work before PMC-851D is put into operation
 Confirm that all straps are off;
 Confirm that the wiring of PMC-851D and external circuit is correct strictly before PMC-851D is put
into operation;
 Check the cables behind the screen, confirm that they are accordant with installation drawings, and
all interim wires and anti-error measures have been restored;
 Check whether each plug-in unit of PMC-851D is connected reliably, and whether each cable and
terminal are connected firmly and reliably, and screw down the bolts firmly;
 Switch on DC power supply, calibrate that AC circuit is sound, and the crest and phase position of
voltage and current are normal;
 Confirm that the communication number of PMC-851D is continuous, and make sure that there is no
repeated address number and the communication of PMC-851D is normal;
 Confirm that the simulation diagram of bus line displayed on the defaulted page is matched with
actual working mode;
 Check the clock of PMC-851D;
 Set up the settings of PMC-851D strictly according to the advice note on setup of dispatching
settings, configure unnecessary protection to be Off, and confirm that the setting group is correct;
 Clear all records available to clear;
 After other items of PMC-851D are proved correct after inspection, input corresponding trip output
strap, protection strap and other functional straps according to the requirements of dispatching, and
102
put PMC-851D into operation formally;

 After normal operation of PMC-851D, it’s available to view online the analog, DI, protection setting,
and various record information without affecting the operation of protection.
8) Notes
Never insert or pull out each plug-in unit in case of power on;
In case of any error in self check, find out the faults, and replace panels in time;
PMC-851D can monitor its communication status by watching the communication status symbol on the
main page of PMC-851D. If communication is broken off by interference temporary, the communication
system will recover automatically in short time, meanwhile, the information which has been suspended will be
transmitted again. If hardware failure results in the communication can’t recover in long time, the light signed
“COMM” won’t flash. But the protection works normally;
If the system has fault protection output or PMC-851D works abnormally, all records in the accident
analysis function of PMC-851D shall be moved out for analysis, including protection action SOE logs, WFR logs,
and device operation logs, etc. Before the logs are moved out, never make any debugging of PMC-851D, or
conduct the operation of switch power supply, and switch shift, etc. For any difficult problem, please contact
the manufactory in time.
5.5. Device Fault Analysis

1) The “Run” light does not work normally.
 Check whether the power supply for PMC-851D is connected correctly, and whether the voltage is
correct;
 If the “Run” light is ok, but the LCD is abnormal or the key is not working, please check whether the
front panel gets loose;
 If PMC-851D bounces out abnormal event alarm, please check whether each panel is well inserted.
2) The meter value of PMC-851D is incorrect.
 Check whether the wire connection of voltage and current channels is normal;
 Check whether PT and CT are sound, and whether the PT and CT ratio is set up correctly;
 Check whether GND is correctly grounded.
3) The reading of active power or power factor is incorrect, but that of voltage and current is correct.
Compare the voltage and current input of actual wiring and wiring diagram, and check whether the
phase location and phase sequence are correct.
4) The DI input is incorrect.
 Check whether the input contact is accessed correctly;
 Check whether DI power supply excitation in system parameters is set up correctly;
 Check whether the DI excitation power supply is normal, and ensure that the ripple factor is less than
5%;
103
5) RS-485 communication is abnormal.

 Check whether communication parameters are correct, including ID, baud rate, parity check bit, and
stop bit;
 PMC-851D Protocol MODBUS only supports RTU mode;
 Check whether the baud rate set of RS-232/RS-485 converter is correct;
 Check whether the whole communication network circuit is correct;
 If the communication interface chip or optical coupler is abnormal, please contact with manufactory;
 Check whether communication interface wire is sound, and whether background software works
normally;
 Close PMC-851D and PC host computer, and restart them for re-trial.
6) Ethernet communication is abnormal.
 Check IP, subnet mask, gateway and network model, and confirm that the IP of PMC-851D and that
of the host computer are in the same network segment;
 Check whether the access port is correct: MODBUS port is 502; IEC61850 port is 102;
 Check whether communication interface wire is sound, and whether background software works
normally;
 Close PMC-851D and PC host computer, and restart them for re-trial.
Note: If you have any problem you can’t solve, please contact our after-sales service department in time.
104
6. Wiring Diagram
6.1. Schematic Wiring Diagram
L2
*
*
QF2 TA4 PMC-851D
* *
TV2
Z13b
UL *
*
Z14b VS2
*
Z8a
*
*
* UN Z8b IA2
* Z10b
*
*
* Z11b VAB2
*
Z12b VBC2
*
UN
TV02
Z1a
*
Z1b Ia
A B C
M2 Z2a
*
Z2b Ib
Z3a
*
Z3b Ic
Z4a
*
Z4b IA
Z5a
*
Z5b IB
Z6a
*
Z6b IC
*
*
*
*
*
*
*
*
*
*
*
*
QF3 TA2 TA3
UL
*
*
*
* UN
* Z10a
*
*
* Z11a VAB1
*
Z12a VBC1
*
*
Z7a
*
TV01 Z7b IA1
Z13a *
Z14a VS1
* *
TV1
L1
*
*
QF1 TA1
A B C
M1
Fig. 6-1 Schematic wiring diagram of PMC-851D
105
L2
*
*
QF2 TA4 PMC-851D
* *
TV2
Z13b
UL *
*
Z14b VS2
*
Z8a
*
*
* UN Z8b IA2
* Z10b
*
*
* Z11b VAB2
*
Z12b VBC2
*
*
UN
TV02
Z1a
*
Z1b Ia
A B C
M2 Z2a
*
Z2b Ib
Z3a
*
Z3b Ic
Z4a
*
Z4b IA
Z5a
*
Z5b IB
Z6a
*
Z6b IC
*
*
*
*
*
*
*
*
*
*
*
*
QF3 TA2 TA3
UL
*
*
*
* UN
* Z10a
*
*
* Z11a VAB1
*
Z12a VBC1
*
*
Z7a
*
TV01 Z7b IA1
Z13a *
Z14a VS1
* *
TV1
L1
*
*
QF1 TA1
A B C
M1
Fig. 6-2 Schematic wiring diagram of PMC-851D
106
PMC-851D
Z1a *
+WC B1
Ia
Z1b RemPS B2
Z2a *
M-Close IN B3
Ib
Z2b Close IN B4
Z3a *
Close OUT B5
Ic
Z3b Supervi B6
Z4a * C-Coil B7
IA
Z4b M-Trip IN B8
Z5a * Trip IN B9
IB
Z5b Trip OUT B10
Z6a * T-Coil B11
IC
Z6b Link IN B12
Z7a * Link OUT B13
IA1
Z7b -WC B14
Z8a *
B15
IA2 KKJ
Z8b B16
*
Z10a B17
VAB1 OUT1
Z11a B18
* VBC1
Z12a B19
* OUT2
Z10b B20
VAB2
Z11b B21
* VBC2 OUT3
Z12b
B22
* B23
Z11b OUT4
VS1
Z12b B24
Z13b * B25
VS2 OUT5
Z14b B26
A1 COM B27
OUT6
B28
A2 IN1
A18
Alarm
A3 IN2 A19
D+
IN3 C1
A4 D- C2
RS-485
SH C3
A5 IN4
GPS+
C5
A6 IN5 GPS-
Time Sync. C6
SH C7
A7 IN6
AO+
A8 IN7 C9
AO Output AO-
C10
A9 IN8
A10 IN9
Ethernet P1
A11 IN10
A12 IN11
Ethernet P2
A13 IN12
A14 IN13 L/+

A23
A15 IN14
N/- A24
GND
Fig. 6-3 Schematic Wiring Diagram of PMC-851D (with DC operation board)
107
PMC-851D
Z1a * OpePS B1
Ia RemPS B2
Z1b
Z2a * M-Close IN B3
Ib Close IN B4
Z2b
Z3a * Jump B4a
Ic Close OUT B5
Z3b
* M-Trip IN B6
Z4a
IA Trip IN B7
Z4b
* Trip OUT B8
Z5a
IB Link OUT B9
Z5b
* Link IN B10
Z6a
IC C-Coil B11
Z6b
* Supervi B11a
Z7a
IA1 T-Coil B12
Z7b
Z8a * L/+ B13
IA2 N/- B14
Z8b
*
Z10a B15
VAB1 KKJ
Z11a B16
* VBC1
Z12a B17
* OUT1
Z10b B18
VAB2
Z11b B19
Z12b * VBC2 OUT2
B20
* B21
Z11b OUT3
VS1 B22
Z12b
Z13b * B23
OUT4
VS2 B24
Z14b
A1 B25
COM OUT5
B26
A2 IN1
B27
OUT6
A3 IN2 B28
A18
Alarm
A4 IN3 A19
A5 IN4 D+
C1
RS-485 D- C2
A6 IN5 SH C3
A7 IN6 GPS+
C5
Time Sync. GPS- C6
A8 IN7 SH C7
A9 IN8 AO+
C9
AO Output AO-
A10 IN9 C10
A11 IN10
Ethernet P1
A12 IN11
A13 IN12 Ethernet P2
A14 IN13 L/+

A23
A15
N/- A24
GND
Fig. 6-4 Schematic Wiring Diagram of PMC-851D (with AC operation board)
108
6.2. Diagram of Operation Circuit

6.2.1. DC Operation Circuit
+WC -WC
220VDC
QA
TBV
R3 JP1
Operation Power Supply+ HBJ TBJ Operation Power Supply-
B01 TBV B14
Relay Close
XB3 Output CHZ
B05 HBJ LC
Relay Close Input TBV QF
B04 B07
SC KKJ BRK Open
M-Close Input R2
3 4 S Monitor
B03 B06
Remote YKH
5 6
B02
YKT
KKJ
M-Trip Input R1
1 2 R
B08
Relay Trip Input
TBJ LT
B09 QF
TBJ
B11
BHT
XB2 Relay Trip
Output
B10
WBH
XB3 Ext. Link Trip
Output
B13 WBH
Ext. Link Trip R4
Input
P B12
Signal Collect
Fig. 6-5 Diagram of DC operation board

Note 1: In Fig. 6-5, +WC, -WC is the positive and negative of the control miniature bus;
TBJ is trip latch relay; HBJ is close latch relay;
BHH is relay close contact, close automatically when ATS_B close tie BRK operate; BHT is relay trip
contact; WBH is external trip relay;
YKH is remote close contact, close when 25 Remote Close Operate; YKT is remote trip contact;
KKJ is manual after-closing relay or contact, TBV is TBJ releasing relay.
LT and LC are trip winding and close winding.
Note 2: When trip-prevent circuit is not needed, extract the operation board and cut the short line of JP1.
Note 3: In order to reduce the duplication wiring, operation circuit collects 5 DI signals: BRK Closed, BRK
Open, Remote, Ext. Trip Position, KKJ signal.
Note 4: When BRK open signal cannot be obtained through close circuit, B6 should not be connected to B7,
109
and the user should connect the open status contact of breaker to B6 through –WC directly.
Note 5: When external trip protection is not needed to operate on trip, please open the external trip output
protection strap, then the protection external trip will only send signals without tripping.
6.2.2. AC Operation Circuit
L N
220VAC
QA
TBV
TBV
R1
Operation Power Supply+ HBJ TBJ
B13 B14
Relay Close QF K0
XB3 Output CHZ
HBJ
B05 K0
TBV Close Coil QF QF LC
Relay Close Input
B04 B11
SHJ
BRK Open
Jump Monitor
B04a SHJ B11a
SC B01 R2
M-Close Input
3 4
B03
Remote YKH
5 6
B02 STJ
YKT
M-Trip Input R3
1 2
B06
STJ TBJ
LT
Relay Trip Input QF
B07 B12
TBJ
Trip Coil
BHT
Relay Trip KKJ
XB1 Output
B08 R4
S
KKJ
R5
R
WBH
XB2 Ext. Link Trip RL1
Output
B09
Ext. Link Trip R6
Input
P B10
WBH
RL1 R7
R8
Signal Collect
Fig. 6-6 Diagram of AC operation board

Note 1: TBJ is trip relay, HBJ is close relay;
KKJ is manual after-closing relay or contact; TBV is TBJ releasing relay; LT is trip coil, LC is close coil.
Note 2: When trip-prevent circuit is not needed, B04a should be connected to B04.
Note 3: In order to reduce the duplication wiring, operation circuit collects 5 DI signals: BRK Closed, BRK
Open, Remote, Ext. Trip Position, KKJ signal.
110
Note 4: When external trip protection is not needed to operate on trip, please open the external trip output
protection strap, then the protection external trip will only send signals without tripping.
111
7. After-sales Service Commitment

7.1. Device Upgrading
Users may use upgraded software of PMC-851D for free. The Company will notify users of the information
on software upgrading by all means.
7.2. Quality Assurance Scope

The following problems of PMC-851D don’t belong to the scope of quality assurance:
a) Damage caused by incorrect installation, use and storage;
b) Abnormal operation and application conditions not meeting the regulations of the product;
c) Devices repaired by any institution or individual not authorized by the Company;
d) Device after the period of quality assurance for free.
7.3. After-sales Contact Method

0086-400-8860-418
112 UMPMC851DV15A-1803

PMC-851D - User Manual - V1.5A

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Bus-Tie Breaker Protection and

CET Electric Technology Inc

order to use PMC-851D safely, correctly and efficiently, please pay

attention to the following important notes:

1) The User Manual is only applicable to the PMC-851D

multifunctional protection relay.

and operation according to the User Manual. If some documents are

provided together with PMC-851D, they shall prevail.

chip and components on printed circuit board when PMC-851D is

charged, in order to prevent damage of PMC-851D.

4) Please test and check PMC-851D with qualified testing instrument

5) In case PMC-851D has any abnormality, please contact our

after-sales technical service (0086-400-8860-418) in time.

6) The default password set for PMC-851D is: 0000.

1.1. Overview ................................................................................................................................................................ 1

2. Technical specifications ............................................................................................................................................. 5

2.1. Environment Parameters ........................................................................................................................................ 5

3. Function description .................................................................................................................................................. 8

3.1. Protection function ................................................................................................................................................ 8

4. Operating Instructions ............................................................................................................................................. 64

4.1. Front Panel ........................................................................................................................................................... 64

5. Installation and Debugging ...................................................................................................................................... 93

5.1. Installation ............................................................................................................................................................ 93

6. Wiring Diagram ...................................................................................................................................................... 105

6.1. Schematic Wiring Diagram ................................................................................................................................. 105

7. After-sales Service Commitment ........................................................................................................................... 112

7.1. Device Upgrading ............................................................................................................................................... 112

PMC-851D Detailed Description

6-channel user-defined digital outputs:

2nd~63th harmonic analysis of three-phase currents and three-phase voltages, in which

2.2. Rated Parameters

5) AO error: ±0.5% , (4～20mA), loading capacity 500Ω

2.4. Digital Input Resolution

2.5. Overload Capacity

2.6. Digital Outputs

2.7. Digital Inputs

2.8. Marked degree of protection

2.10. Electrical Insulation Requirements

2.11. Mechanical Tests

2.12. Electromagnetic Compatibility

Status 2 ATS_L1 or ART_L2 Status 3

QF3 Cloesd QF3 Cloesd

Bus Ⅰ Bus Ⅱ Bus Ⅰ Bus Ⅱ

Transfer diagram of ATS and ART

Fig. 3-1 Logic diagram of 27E/59Neg.E

2) Phase over-current elements (50P-E1, 50P-E2, 50P-E3)

Fig. 3-2 Logic Diagram of 50P-E1

Fig. 3-3 Logic diagram of SOTF-1

Fig. 3-4 Logic diagram of SOTF_ATS

Fig. 3-5 Logic diagram of SOTF_DI

Fig. 3-6 Logic diagram of 50P-1

Fig. 3-7 Logic diagram of 50P-2

3.1.7. Overload Protection (50P-5)

50P-5 On “50P-5 Operate”

Fig. 3-8 Logic diagram of 50P-5

Fig. 3-9 Logic diagram of 51P

Fig. 3-10 Logic diagram of SOTF_I0-1

Fig. 3-11 Logic diagram of SOTF_I0_ATS

50I0-1 On “50I0-1 Operate”

Fig. 3-12 Logic diagram of 50I0-1

Fig. 3-13 Logic diagram of 51I0

59PP_B1-1 On “59PP_B1-1 Operate”