Course Title: Electronic Circuit Design Course Code: EEN-225

Class: BEE – 4 B CLO-PLO: 3-2

Course Instructor: ENGR. M FAISAL SIDDIQUI Date: 9-June-2022
Due Date: 1-July-2022 Max. Marks: 10 Points

ASSIGNMENT No. 3

Submitted by:

Name: MARYAM UMAR

Registration #: 70077

Class/Section: BEE-4B
 ASSIGNMENT No. 3

Course Title: Electronic Circuit Design Course Code: EEN-225

Class: BEE – 4 B CLO-PLO: 3-2
Course Instructor: ENGR. ENGR. M FAISAL SIDDIQUI Date: 9-June-2022
Due Date: 1-July-2022 Max. Marks: 10

Points INSTRUCTIONS

1. Only neat and clean answers are accepted

2. Take print out and fill title page. Attach it as a first page to your assignment
3. Assignment should be done only on A4 size paper
4. Individual Viva will be taken at the time of assignment submission
5. The assignment is complex engineering problem

CLO BT PLO (WA) Knowledge CEP Attributes (WP)

Mapping Level Mapping Profile
(WK)
CLO-3 C6 PLO-2 WP1 (Depth of Knowledge), WP3 (Depth of Analysis),
WK5

CEP Statement:
In this problem, you will use the knowledge you acquired throughout the course to design a
Multistage Amplifier with the given structure.

a) MOSFET M1operating in the C-S configuration provides high input resistance and
moderate voltage gain.
b) BJT Q2 in a C-E configuration, the second stage, provides high gain.
c) BJT Q3, an emitter-follower gives low output resistance and buffers the high gain stage from
the relatively low value of load resistance.

Problem Identification:
Typical specification for a general-purpose operational amplifier
– Input resistance ~ 1MΩ
– Output resistance ~ 100Ω
– Voltage gain ~ 100,000
No single transistor amplifier can satisfy these specification
By using the Cascading multiple stages of amplifiers to meet the above-mentioned specification.
Cascade:

– An input stage to provide required input resistance

– A middle stage(s) to provide gain
– An output stage to provide required output resistance
It is important to note that the input resistance of the follow-on stage becomes the load of the
previous stage.

To be used
a) Input and output of overall amplifier is ac-coupled through capacitors C1 and C6.
b) Bypass capacitors C2 and C4 are used to get maximum voltage gain from the two inverting
amplifiers.
c) Interstage coupling capacitors C3 and C5 transfer ac signals between amplifiers but provide
isolation at dc and prevent Q-points of the transistors from being affected.
d) Assume the Values of all components to get the required
result.

Objective:

1. Construct the circuit using MultiSim.

2. Perform DC analysis using Multisim simulation.
3. Draw the small signal model of the circuit.
4. Apply AC signal and simulate the circuit.
5. Calculate and measure the Current Gain, voltage Gain and Power Gain.
6. Characteristics curve between Voltage gain and Frequency. Use FL = 500Hz and FH=500KHz
7. Output voltage (Vo) graph to be present.

Required Result:

Current Gain: approx. 4 x 106 (130 dB)

Voltage Gain (AV): approx. 9.8 x 102 (60 dB)

Power Gain: approx. 4 x 109 (96 dB)

1. DC ANALYSIS MULTISIM CIRCUIT:-

2. SMALL SIGNAL MODEL:-

3. AC ANALYSIS MULTISIM CIRCUIT:-

4. CALCULATE AND MEASURE THE CURRENT GAIN, VOLTAGE GAIN AND POWER
GAIN.
5. CHARACTERISTICS CURVE BETWEEN VOLTAGE GAIN AND
FREQUENCY:-

6. OUTPUT VOLTAGE GRAPH:-