INT6400 and INT1400 Thermal Management

Application Note
February 2010

1 Introduction
Atheros Communications INT6400 200-Mbps MAC/PHY and INT1400 AFE Integrated Circuits (ICs) are
based on the HomePlug® AV specification. The INT6400 and INT1400 chip set are single ICs consisting of
the baseband IC and the Analog Front End. The Ethernet Adapter may take the form of a stand-alone
product, or may be embedded into higher function devices.
The demand for higher speed and performance in compact consumer products makes thermal engineering an
essential part of the design process today. This application note discusses thermal management for
INT6400/INT1400 based product design.

2 Device Packages

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The INT6400 uses a thermally enhanced plastic Ball Grid Array (BGA) package to achieve low cost and to

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simplify the board assembly process. The characteristics of the INT6400 BGA package are:

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15 x 15 mm Low Profile Ball Grid Array
196 balls in a 14 x 14 low profile BGA ball array
0.5 mm diameter balls, 1.0 mm ball pitch
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1.4 mm package height
1.27 W typical power dissipation
Commercial Operating Temperature Range 0ºC to +70ºC with no INT6400 heat sink
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Industrial Operating Temperature Range -40ºC to +85ºC with no INT6400 heat sink
Lead Free “G” Green package
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The INT1400 is delivered in a space saving Quad Flat No leads (QFN) package. This package has excellent
thermal conductivity due to the exposed lead frame pad on the bottom of the package. This pad provides
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both chip ground and a low thermal resistance path to the PCB metal layer.
5 x 5 mm 32-pads for signal and power connections
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Excellent thermal performance due to ground pad on bottom of package

Low electrical noise due to multiple ground pads and large bottom ground pad
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Simple footprint for easy assembly

Commercial Operating Temperature Range 0ºC to +70ºC
Industrial Operating Temperature Range -40ºC to +85ºC
Lead Free “G” Green package

© 2009-2010 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, No
New Wires®, Orion® , PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®,
Total 802.11®, U-Nav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™,
Signal-Sustain Technology™, Ethos™, Install N Go™, IQUE™, ROCm™, amp™, Simpli-Fi™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of
Atheros Communications, Inc. The Atheros logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective
holders. Subject to change without notice.

COMPANY CONFIDENTIAL
 Table of Contents
1 Introduction ........................................................................................................................................... 1
2 Device Packages .................................................................................................................................. 1
3 PC Board Design .................................................................................................................................. 3
3.1 Commercial Temperature Range Designs................................................................................... 3
3.2 Industrial Temperature Range Designs ....................................................................................... 3
4 Power Dissipation Calculation Model ................................................................................................... 5
5 Board Layers ........................................................................................................................................ 7
5.1 Top Copper Layer ........................................................................................................................ 7
5.2 Mid-Layer 1 .................................................................................................................................. 8
5.3 Mid-Layer 2 .................................................................................................................................. 9
5.4 Bottom Layer.............................................................................................................................. 10
6 INT1400 PCB Layout and Copper Design ......................................................................................... 11
7 Thermal via Array Connects All Layers .............................................................................................. 12
8 Thermal Simulation............................................................................................................................. 14
8.1 INT6400 Simple ΘJA Model ...................................................................................................... 14
9 Design Improvement Ideas................................................................................................................. 15

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9.1 PCB Technology ........................................................................................................................ 15
9.2 Enclosure Design ....................................................................................................................... 15

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10 Revision History.................................................................................................................................. 15

Table of Figures
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Figure 1: RD6400-ETH Ethernet Adapter PCB Outline ................................................................................ 4
Figure 2: RD6400-ETH Ethernet Adapter Four Layer PC Board .................................................................. 7
Figure 3: PCB Top Copper Layer (Component Side) ................................................................................... 7
Figure 4: PCB Mid-Layer 1 is a Signal and Ground Pour Area..................................................................... 8
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Figure 5: PCB Mid-Layer 2 Signal and Power Distribution ........................................................................... 9

Figure 6: PCB Bottom Layer (Ground and Decoupling).............................................................................. 10
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Figure 7: Shows the INT1400 5 x 5 mm QFN Foot Print and Ground Paddle............................................ 11
Figure 8: Middle 1 Copper Layer under the INT1400 ................................................................................. 12
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Figure 9: Middle 2 Copper under INT1400.................................................................................................. 12

Figure 10: Bottom Copper under INT1400.................................................................................................. 13
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Atheros Communications, Inc. INT6400 and INT1400 Thermal Management Application Note • 2
COMPANY CONFIDENTIAL February 2010
3 PC Board Design
The recommended INT6400-based Ethernet Adapter board uses 4-layer PCB technology with 4-mil features
and a 4-mil spacing design rule. This technology was selected to provide good thermal and electrical
performance while facilitating the connection of over 150 I/O lines. The characteristics of the 4-layer PCB
are:
4-Layer stack up, 1 mm total thickness
Fine pitch 4-mil features, 4-mil spacing design rule
10 mil hole size, plated to fill
½ oz copper (0.018 mm) for outer starting layer and 1 oz copper on two inner layers
Gold or Silver over nickel immersion was used on the top and bottom layer

3.1 Commercial Temperature Range Designs

All Atheros reference designs are intended to operate over an environmental temperature of 0 to 50 degrees
Centigrade. The commercial temperature range INT6400 and INT1400 components operate in an ambient

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air temperature up to +70°C. Non Atheros supporting components found in the RD6400-ETH wall adapter
Reference Design are selected for commercial temperature range operation.

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3.2 Industrial Temperature Range Designs

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The designer of industrial temperature range applications must select all system components that meet the
temperature requirements of the operating environment. When using the Atheros industrial temperature
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INT6400 and INT1400 integrated circuits, the designer is responsible for the selecting of all supporting
components that meet the environmental requirements of that industrial temperature application.
Figure 1 shows the RD6400-ETH recommended component placement and reference numbers for the power
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dissipation information listed below this graphic.

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Figure 1: RD6400-ETH Ethernet Adapter PCB Outline

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U6 = INT6400 (1.27 W) U8 = PHY Chip (0.44 W)

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U9= SDRAM (0.08 W on top side) U7 = Core Regulator (0.60 W)

U5 = FLASH (0.013 W)
U11 = INT1400 AFE/Driver (0.99 W transmitting)

Atheros Communications, Inc. INT6400 and INT1400 Thermal Management Application Note • 4
COMPANY CONFIDENTIAL February 2010
4 Power Dissipation Calculation Model
The tables below are a model of INT6400 wall plug adapter power consumption. This model calculates the
transmit and receive DC power. This model assumes certain DC power supply efficiencies. In all cases, the
thermal layout in the board design below takes into account the maximum power dissipation.
Table 1: INT6400 Add-in DC Power Requirements
+25°C Middle Range of Leakage Current 50% Rx/Tx TCP

Function Transmit Receive

Circuits (VDC) 11 3.3 1.05 11 3.3 1.05
INT6400 – IO & CORE (mA) 33 352 33 532
INT6400 – ANALOG (mA) 90 40 77 60
SDRAM (1) (Vdd + Vddq) (mA) 19 26
Flash (mA) 4 4
INT1400 (mA) (Note 1) 90 25 2 50

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LEDs (mA) 16 16

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IC+ IP101 PHY chip (mA) 140 140
Total Circuit current (mA) 90 327 392 2 346 592
Total Circuit Power (mW) (Note 2)
Power supply efficiency
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90% TI
1079.1 411.6
100% 90%
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90%
1141.8 621.6
100% 90%
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Individual Circuit Power 1100 1079 457 24 1142 691
Total Circuit Power 1100 1536 24 1832
Total DC power (W) 2.64 1.86
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Average DC power Dissipation (W) 2.25

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(Note 3)
Note 1. Maximum leakage current for INT1400 assumed.
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Note 2. Using recommended operating voltages.

Note 3. This assuming 50% transmit duty cycle.
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Atheros Communications, Inc. INT6400 and INT1400 Thermal Management Application Note • 5
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 Table 2: INT6400 Add-in DC Power Requirements
Maximum UDP Receive Rate @ +25°C Maximum Leakage Current

Function Receive
Circuits (VDC) 11 3.3 1.05
INT6400 – IO & CORE (mA) 33 882
INT6400 – ANALOG (mA) 77 60
SDRAM (1) (Vdd + Vddq) (mA) 26
Flash (mA) 4
INT1400 (mA) 2 50
LEDs (mA) 16
IC+ IP101 PHY chip (mA) 140
Total Circuit current (mA) 2 346 942
Total Circuit Power (mW) (Note 1) 22 1141.8 989.1
Power supply efficiency 90% 100% 90%

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Individual Circuit Power 24 1142 1099

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Total Circuit Power (mW) 24 2241
Total DC power (W) 2.27

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Note 1. Using recommended operating voltages.
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Table 3: INT6400 Add-in DC Power Requirements
Maximum UDP Receive Rate @ +85°C Maximum Leakage Current
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Function Receive
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Circuits (VDC) 11 3.3 1.05

INT6400 – IO & CORE (mA) 33 1123
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INT6400 – ANALOG (mA) 77 60

SDRAM (1) (Vdd + Vddq) (mA) 26
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Flash (mA) 4
INT1400 (mA) 2 50
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LEDs (mA) 16
IC+ IP101 PHY chip (mA) 140
Total Circuit current (mA) 2 346 1183
Total Circuit Power (mW) (Note 1) 22 1141.8 1242.15
Power supply efficiency 90% 100% 90%
Individual Circuit Power 24 1142 1380
Total Circuit Power (mW) 24 2522
Total DC power (W) 2.55
Note 1. Using recommended operating voltages.

Atheros Communications, Inc. INT6400 and INT1400 Thermal Management Application Note • 6
COMPANY CONFIDENTIAL February 2010
5 Board Layers
The RD6400-ETH Ethernet Adapter is currently fabricated on a four-layer board. Figure 2 shows the details
of the stack.

TOP SILK
TOP MASK
TOP SIDE PLATING ( ≈ 1 oz)
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TOP LAYER (2 oz Copper/Starting)
PREPEG 0.010 to 0.014
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MID LAYER 1 (2 oz Copper)
0.060 CORE 0.026 to 0.028
1
MID LAYER 2 (2 oz Copper)
PREPEG 0.010 to 0.014
1
BOTTOM LAYER (2 oz Copper/Starting)
BOTTOM SIDE PLATING ( ≈ 1 oz)

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BOTTOM SOLDER MASK
BOTTOM SILK

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Figure 2: RD6400-ETH Ethernet Adapter Four Layer PC Board

5.1 Top Copper Layer

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The active components and the majority of the passive components are surface mount devices located on the
Top copper Layer of the PCB. The copper layer view is shown here.
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Figure 3: PCB Top Copper Layer (Component Side)

Atheros Communications, Inc. INT6400 and INT1400 Thermal Management Application Note • 7
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Figure 3 is a magnified view of the INT6400 mounting area looking down onto the Top Layer. Blue circles
are via and the green circles are the BGA pads on the top layer of copper. These green circles are in fact
solid copper areas.
The majority of the signal traces connect to, and route away from, the device on the Top Layer (narrow
traces shown in red). All ball contacts of the device attach to the PCB top copper at the small red pads
evenly spaced in a 14 by 14 pattern. These pads are on the Top Layer and do not contain vias. A via is
associated with one or more pads and helps to take heat away from the package
Notice the honey comb pattern in the center of the ball array. This required pattern allows all solder balls to
come up to a uniform temperature during reflow.
The INT6400 IC uses the vias attached to all layers to reduce package heat. These vias connect to ground
planes on inner board layers as well as the ground plane present on the outer bottom copper layer.
Connecting all these layers helps to reduce INT6400 IC package temperature.

5.2 Mid-Layer 1
Mid-Layer 1, as shown in Figure 4, is located just below the Top Layer in the PCB layer stack. This layer

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contains logic signal routing with ground plane flooding the remaining area. The thermal vias tie directly
into the ground copper pour on this layer. This layer helps to transport heat away from the INT6400,

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reducing the package and die temperatures and provide a low impedance ground. Notice there are no thermal
reliefs on these thermal vias. This provides good heat conduction to metal layers.

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Figure 4: PCB Mid-Layer 1 is a Signal and Ground Pour Area

Atheros Communications, Inc. INT6400 and INT1400 Thermal Management Application Note • 8
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5.3 Mid-Layer 2
Mid-Layer 2, as shown in Figure 5, is located just below the Mid-Layer 1 in the PCB layer stack. The colors
indicate the layer order. This layer contains some signal routing and large power planes flooding the
remaining area. This layer does contribute to the thermal management to some extent. There are vias with no
thermal relief that spread some heat to this layer. This layer is critical for power distribution to the INT6400
and INT1400.

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Figure 5: PCB Mid-Layer 2 Signal and Power Distribution

Atheros Communications, Inc. INT6400 and INT1400 Thermal Management Application Note • 9
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5.4 Bottom Layer
Figure 6 is the Bottom Copper Layer. This is outer layer located at the bottom of the PCB layer stack.
INT6400 thermal vias tie directly to the ground plane, with no thermal relief under the INT6400
providing a low resistance thermal path to the bottom copper area. This arrangement provides the best heat
flow away from the INT6400 package. The large numbers of thermal vias without thermal relief are
essential here.
The Bottom Layer design should maximize the copper coverage and connections to the central thermal via
area. More than half of the device heat is transferred to the ambient air by copper on this outer layer. This
layer contains a large ground plane area, shown in blue and power decoupling capacitor vias shown in red.
Notice that each 0306 bypass capacitor has two on pad vias.
NOTE: no thermal relief ‘wagon wheel spokes’.

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Figure 6: PCB Bottom Layer (Ground and Decoupling)

Atheros Communications, Inc. INT6400 and INT1400 Thermal Management Application Note • 10
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6 INT1400 PCB Layout and Copper Design
The required solid copper heat sink area, under the INT1400 bottom pad, is outlined by the red rectangle
below. This area contains 13 thermal vias to provide both good circuit ground and remove heat from the
INT1400 package.

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Figure 7: Shows the INT1400 5 x 5 mm QFN Foot Print and Ground Paddle
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A side note follows.

NOTE: Notice the use of wide traces for large bypass capacitors where ever possible. Wide traces are also used
on high frequency interface signals to improve signal integrity by decreasing skin effect on these
interconnect traces.

The use of multiple traces for ground connections around the INT1400 helps to reduce board noise and
assure a low noise floor for the INT1400 analog transmit and receive amplifiers..

Atheros Communications, Inc. INT6400 and INT1400 Thermal Management Application Note • 11
COMPANY CONFIDENTIAL February 2010
7 Thermal via Array Connects All Layers
Vias provide both electrical/ground connections between layers and thermal paths from components on the
top copper. Use many vias in this area for best noise reduction and the lowest thermal resistance to ambient
air temperature. Vias are attached to solid cooper with no thermal relief spokes.

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Thermal and ground vias are required.
Vias connect to all four layers if possible
Vias have no thermal relief.
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Figure 8: Middle 1 Copper Layer under the INT1400

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Figure 9: Middle 2 Copper under INT1400

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COMPANY CONFIDENTIAL February 2010
The designer may want to add a small solder mask over the bottom copper of the INT1400 heat sink via
area. This is shown in the black box below. This area will be plated during the Gold/Silver immersion
process to further improve heat conduction and radiation into the ambient air. This mask allows air to
contact the exposed area and provide better cooling through air conduction and to some extent radiation to
the surrounding housing.

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Figure 10: Bottom Copper under INT1400

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Since we are describing PCB design here lets look at one other consideration. Notice the large footprints for
0306 bypass capacitors located directly on the power pads of the INT1400. While these components have
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some impact on the thermal characteristics they are important from electrical noise consideration. The wide
traces and pads also help carry some heat away from the INT1400 because of the multiple on pad vias.
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These ultra low inductance capacitors significantly reduce the power supply noise and EMI radiated from
the INT1400/Line Driver IC.

Atheros Communications, Inc. INT6400 and INT1400 Thermal Management Application Note • 13
COMPANY CONFIDENTIAL February 2010
8 Thermal Simulation
Detailed thermal models were created for the INT6400 BGA and for all other major power dissipating
components. A detailed model of the Ethernet Adapter design was generated including thermal vias and
copper coverage. An enclosure model was also generated. Thermal simulations of various combinations of
these elements are performed using FloTherm Computational Fluid Dynamic software from Flomerics. A
still-air operating environment derived from JEDEC JESD51-2 is used for simulation runs.

8.1 INT6400 Simple ΘJA Model

A detailed thermal model of the INT6400 IC including die, substrate, bond wires, solder balls, thermal vias,
and encapsulent was generated using FloPak Package Modeling Software from Flomerics. This package
model was simulated on the JEDEC51-9 four-layer test board environment (FR-4, 101 x 114 x 1.6 mm,
2S2P). The thermal resistance ӨJA was derived for natural convection and forced airflow as presented in
Table 4.
Table 4: INT6400 and INT1400 Thermal Model Results

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ӨJA Atheros Model ӨJA Atheros Model

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INT6400 (°C/W) INT1400 (°C/W)
0.1 M/S (convection)
AIR = 20°C
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PCB = 38°C
DIE = 63°C
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1 M/S (forced)
AIR = 20°C
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24.2 26
PCB = 29°C
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DIE = 53°C
Note: INT6400 ӨJC = 8.6 (°C/W) and INT1400 ӨJC = 3.0 (°C/W)
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The JEDEC test board environment is significantly different than the typical application circuit board
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environment. The JEDEC test places a single device on a relatively large PCB. Real products will place
many heat generating devices near the INT6400 on a relatively small PCB. For this reason, ӨJA alone
should not be used to calculate operating junction temperature.

Atheros Communications, Inc. INT6400 and INT1400 Thermal Management Application Note • 14
COMPANY CONFIDENTIAL February 2010
9 Design Improvement Ideas
9.1 PCB Technology
Most CE customers prefer to use low-cost 4-layer PCB technology with 8-mil width and 8-mil spacing with
vias that pass through all layers. The designer can use 4-mil (0.1mm) line width and 4-mil (0.1mm) spacing
under the INT6400 were necessary for interconnect. See Figure 3. The use of other PCB techniques may be
considered to maximize heat flow and dissipation while maintaining the low PCB cost. Possible
improvements include:
Place thermal vias directly in the solder ball contact lands. This improves heat flow and minimizes
the disruption of the bottom-side copper.
Fill thermal vias with metal (copper or solder). This lowers the thermal resistance between the
device and the bottom-side copper.

9.2 Enclosure Design

The design of the enclosure has a large affect on the way air flows around the circuitry under conditions of

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natural convection. The design should optimize the flow of cooling air past the hottest components and out

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of the enclosure to transport away the most heat. Vertical enclosure designs appear to enhance the
convection and result in lower die temperatures. Air vents are likely to be required on all but the largest

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enclosures.

10 Revision History
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Revision Modifications
1 Initial release. 12/30/08 JDB
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2 Industrial notice added 5/29/09 JDB

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The information in this document has been carefully reviewed and is believed to be accurate. Nonetheless, this document is subject to
change without notice. Atheros assumes no responsibility for any inaccuracies that may be contained in this document, and makes no
commitment to update or to keep current the contained information, or to notify a person or organization of any updates. Atheros reserves
the right to make changes, at any time, to improve reliability, function or design and to attempt to supply the best product possible.

Document Number: APP-0010 Rev. 1

Atheros Communications, Incorporated

5480 Great America Parkway
Santa Clara, CA 95054
tel: 408.773.5200
fax: 408.773.9940
www.atheros.com

COMPANY CONFIDENTIAL
Subject to Change without Notice