See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/309639287

Method for balancing capacitors voltages on split DC-links

Conference Paper · September 2016

DOI: 10.1109/EPE.2016.7695618

CITATIONS READS

3 444

3 authors:

Douglas Pappis Eduardo Facanha de Oliveira

Leopold kostal GmbH & co. kg Huawei Technologies Duesseldorf GmbH
21 PUBLICATIONS 209 CITATIONS 19 PUBLICATIONS 55 CITATIONS

SEE PROFILE SEE PROFILE

Peter Zacharias
Universität Kassel
112 PUBLICATIONS 2,140 CITATIONS

SEE PROFILE

All content following this page was uploaded by Eduardo Facanha de Oliveira on 31 October 2020.

The user has requested enhancement of the downloaded file.

 Method for balancing capacitors voltages on split DC-links

Douglas Pappis, Eduardo F. de Oliveira, Peter Zacharias

Centre of Competence for Distributed Electric Power Technology (KDEE)
University of Kassel
Wilhelmshöher Alle 71
Kassel, Germany
douglas.pappis@gmail.com
http://www.kdee.uni-kassel.de

Keywords
«Converter control», «High voltage power converters», «DC power supply», «Regulation»

Abstract
A technique to actively balance the voltages on series-connected capacitors designated to split DC
sources whose loads comprise power converters is presented. It performs such balancing dynamically,
enabling the voltage equalization even for small capacitors under wide power and voltages ranges.
Proposal consists on lightly controlling the power of one input capacitor for each pair, measuring their
voltage difference and, based upon that, generating a single control signal. Thereby, it then controls
the power drained individually from that capacitor, whilst the total load remains being supplied by the
whole pair. The performance of the proposed capacitor voltage balancing control loop has been
demonstrated by means of experimental results of a 300 V – 6 kW bipolar-buck (330 V – 1500 V
supply).

Introduction
Voltage levels of DC links in power electronic converters are key in some cases of high voltage
supplies, especially for medium power applications, being widely applied in multi-level converters [1].
Among other reasons, split voltage between capacitors is required as there are demands for high input
voltage (few kV range), and eventually output loads requirements, whilst most power semiconductors
are rated up to 1.2 kV with acceptable reliability and competitive performance, as it is the case for the
largely applied IGBTs.
Even for the new wide-band-gap Silicon Carbide based devices, which theoretically would enable
much higher voltages; reaching reasonable reliability is of great difficulty due to their relatively fragile
gate structure [2]. Short-circuit robustness is of importance as the temperature constraints of such
structure are more critical as higher the voltage, whereas it yields faster temperature rise on such
events [3].
Moreover, multilevel converters improve significantly EMI performance in comparison to single level
by reducing the noise emission (lower switched voltages, smaller steps). In this way, split of voltages
to supply power converters is a valid design strategy and shall remain even in a new semiconductors
scenario. Furthermore, the splitting of voltages provides an important option for power converter
designs feasibility even when there are proper power switches, as multi-level converters may present
other advantages regarding overall performance, reliability, and cost [4].
Some techniques have already been developed to perform such balancing, however mainly focusing
on multi-level converters [5], [6]. Other than that, approaches have been developed to equalize the
voltage of series capacitances used as a single DC-links with load connected to the ends of the string
[7], [8]. A similar approach to the balancing voltages topic has been proposed in [5], however on that
case a cross coupling among the control variables occurs, potentially leading to instability and
therefore requesting extra-attention on the control design. Main difference from the approach proposed
here is that direct changes in the switches duty-cycle are applied, assuming a slow output response,
which is in fact not always applicable. The proposal here presented relays on light and fast load power
control of one of each pair of capacitors instead, guarantying stability as each of the independent loops
is inherently stable.
A detailed stability analysis enables a safe and optimum design, rating minimum capacitances
according to load dynamics requirements. Besides stability, it is usually important for the voltage split
to be kept within a tight range due to the limits of components maximum ratings, which means that
transient performance is crucial. Despite peaks from switching events, the difference between the
maximum input voltage and the maximum allowed for the converters’ semiconductors is relatively
tight on most applications.
The proposed technique dynamically balances the voltages of series connected input capacitances
supplied from a DC voltage source, fixed or variable, and susceptive to diverse loading conditions in
the form of parallel sinking current from the capacitors, yet able to maintain the voltage balancing/
symmetry in the capacitors with inherently null steady state error. A 300 V – 6 kW output / 330 V-
1500 V variable input DC-DC bipolar-buck based power supply with output voltage regulation has
been implemented to verify the technique feasibility, whose core concept is nevertheless expandable to
multi-level converters and inverters, besides to other step-down and up converters. Descriptions of the
proposed method are provided along the paper referring specifically to such bipolar-buck DC-DC
converter.
The voltage balancing method is presented in the second section, which is followed by experimental
results in the third one. Afterwards, early conclusions about the work are drawn in the last section.

Voltage balancing control design method

The bipolar-buck step-down converter control design starts at an individual closed-loop for the top and
bottom buck converter, as represented on the block diagram of Fig. 1 (d). In the present analysis,
output voltage regulation has been performed using peak current-mode control, comparing the
inductor peak current to a reference that depends on the output voltage [9]. Either for the two
independent loops or even open-loop, there is an inherent instability on the balancing symmetry on the
capacitor voltages. Any miner difference of power flow from one input capacitor to another causes one
voltage to rise to the input voltage VIN and the other to fall to zero. In this way, a method to balance the
capacitors voltages VC1 and VC2 is essential on the design of such converter.
Each buck loop has been equally designed based upon [9], being only briefly described in this short
paper. Set requirements were switching frequency of 12 kHz, 60° of phase margin and 720 Hz of cut-
off frequency in order to compensate potential ripple at maximum AC frequency of an input DC rail
(2·3·60 Hz = 360 Hz). To achieve such requirements, a controller with a pole in the origin (null error)
and a positive phase shift in the cut-off frequency was required. Able to provide such features, a Type
II controller has been chosen. The Bode diagram for the compensated open-loop transfer function is
presented on Fig. 2. Transfer function of output voltage per control voltage (GVo/Vc), proportional to
the inductor peak current, as well as details regarding slope compensation and sampling gain are
described in [9].
The method for achieving voltage balancing by controlling the load power of one of the capacitors has
been implemented via slight changes on its output reference voltage. The individual inner loop of each
buck remains stable as its reference is shifted slower than its own dynamics, in other words,
decoupled. Such changes have to be, however, fast enough to prevent unbalances between the two
input capacitances voltages.
The control loop for the bottom buck is illustrated with the block diagram of Fig. 1 (c). The control
signal, consisting of the difference between the capacitor voltages, is subtracted from the null
reference and this error signal amplified by a proportional controller KP and subtracted from the
reference. Thereby, an increase on VC1 in comparison to VC2 results in a positive value of VS, which in
turn is multiplied by the sensing gain HVin(s) and becomes negative after being subtracted from null
reference. The negative value -VS∙HVin(s)∙KP is then subtracted from the output voltage reference,
whose value becomes slightly higher than the nominal one, in the same way causing an slight increase
of VO1 and therefore yielding an output power PO1 rise. If PO1 is higher than the practically constant
output power of the top buck PO2, the voltage at VC1 lowers and consequently VC2 increases.
 +
-

(c)
+
-

(a) (d)

(b) (e)

Fig. 1: Overview of the proposed method: (a) Basic circuit to expand for n input capacitors; (b)
Simplified topology circuit used in theoretical analysis;(c) Block diagram of the extended closed-loop
output voltage regulation with symmetry control of the input capacitors voltage; (d) Block diagram of
a standard closed-loop output voltage regulation; (e) Complete circuit overview of the input step-down
stage control concept

Following the reasoning of the analysis presented in [5] and the design guide [9], it is possible to
define the transfer functions of the input capacitors voltage difference per duty cycle GVs/d(s) and of the
duty cycle per control voltage Gd/Vc(s). The product of these two equations results in the transfer
function of the input capacitors voltage difference per control voltage GVs/Vc(s), shown in Fig. 1 (c).
The analysis of the capacitor voltage balancing mechanism is performed considering a constant
current source in converter output, as shown in Fig. 1 (b). The instantaneous current of the central
branch is can be expressed by (1) and (2).

in (t ) = iC2 (t ) − iC1 (t ) (1)

in (t ) = iS1 (t ) − iS2 (t ) (2)

The generic switch instantaneous current can be described as shown in (3).

iS x (t ) = d S x (t ) ⋅ I L (3)

As already stated, the method for achieving voltage balancing consists of controlling the load of the
lower capacitor via slight changes on its output reference voltage. Therefore, the duty-cycle of the
switch S1 is composed by the effective duty cycle D and the perturbation ΔdS1, whereas the duty-cycle
of the S2 is composed only by the effective duty cycle D.

d S1 (t ) = D + Δd S1 (t ) (4)
d S2 (t ) = D (5)

From (1), the central branch current can be described as:

dvC2 (t ) dvC1 (t )
in (t ) = C2 ⋅ − C1 ⋅ (6)
dt dt

Being Vin a constant voltage source, one obtains that:

dVin dvC1 (t ) dvC2 (t )

= + =0
dt dt dt
dvC1 (t ) dvC (t )
=− 2 (7)
dt dt

Considering C1 = C2, and replacing (7) in (1), it is obtained the relationship among in, VC1 and VC2.

dvC1 (t )
in (t ) = −2 ⋅ C1 ⋅ (8)
dt
dvC2 (t )
in (t ) = 2 ⋅ C1 ⋅ (9)
dt

Replacing (3) in (2), the following equation can be derived:

[ ]
in (t ) = d S1 (t ) − d S 2 (t ) ⋅ I L (10)

Replacing the equations (8) and (9) in (10) and isolating the derivative capacitor voltages, the
following equations are found.

dvC1 (t )
dt
[
= d S2 (t ) − d S1 (t ) ⋅ ] 2I⋅ C
L
(11)
1

dvC2 (t )
dt
[
= d S1 (t ) − d S2 (t ) ⋅ ] 2I⋅ C
L
(12)
1

Perturbing, linearizing and applying the Laplace transformation in equations (11) and (12), the
dynamic equations (13) and (14) are obtained.

[
vC1 (s ) = d S2 (s ) − d S1 (s ) ⋅ ] 2 ⋅ sI ⋅ C
L
(13)
1

[
vC2 (s ) = d S1 (s ) − d S2 (s ) ⋅
IL
]
2 ⋅ s ⋅ C1
(14)

Finally, substituting (4) and (5) in equations (13) and (14), the transfer function of the input capacitor
voltages difference per duty cycle can be derived as follows:
 vC1 (s ) − vC2 (s ) I
= Gvs / d (s ) = − L (15)
d (s )
ˆ s ⋅ C1

An equivalent measurement with same reference potential of the input capacitors voltage subtraction
(control signal) sensing only the total input voltage and the voltage across C1 is given by:

Vs = VC1 − VC2 = 2 ⋅VC1 − Vin (16)

As already mentioned, the control of the step-down was performed applying peak current-mode
control. In this analysis, the output voltage regulation is employed by comparing the inductor peak
current to a reference that depends on the output voltage [9]. In order to calculate GVs/Vc(s) shown in
Fig. 1 (c) and described by (17), it is firstly necessary to find the duty cycle per control voltage
transfer function Gd/Vc(s).

GVs /Vc (s ) = GVs / d (s ) ⋅ Gd /Vc (s ) (17)

The duty cycle per control voltage transfer function can be found through the following reasoning.
The inductor peak current is given by:

D ⋅ (Vin − Vo ) Vo
I Lpk = + (18)
2⋅ L Ro

Multiplying all arguments by the current sensing gain Ri and being the control voltage Vc equal to ILpk∙
Ri, one obtains:

D⋅
(Vin − Vo ) ⋅ R + Vo ⋅ R − V =0
i i C (19)
2⋅ L Ro

Perturbing the duty cycle with d̂ will produce a small variation on the control voltage v̂c .

(D + dˆ )⋅ (V 2 −⋅ LV ) ⋅ R + VR ⋅ R − (V
in o
i
o
i C + vˆc ) = 0 (20)
o

Therefore, the duty cycle per control voltage transfer function can be described as in (21), where L =
L1 = L2, VO is the reference output voltage and Ri the current sensing gain.

dˆ (s ) 2⋅ L
= Gd /Vc (s ) = (21)
vˆc (s ) (Vin − Vo ) ⋅ Ri
Hence, GVs/Vc(s), indicated in the block diagram of Fig. 1 (c) can be described by (22).

2 ⋅ L1 I
GVs / Vc (s ) = GVs / d (s ) ⋅ Gd / Vc (s ) = − ⋅ L (22)
(Vin − Vo ) ⋅ Ri s ⋅ C1
Based on the obtained transfer functions and manipulating on the block diagram of Fig. 1 (c), the non-
compensated open-loop transfer function can be defined as in (23).
 − CTII (s )
OLTFVin (s ) = ⋅ GVs / Vc ⋅ HVin (23)
1 + GVo / Vc (s ) ⋅ HVo

With the compensated open-loop transfer function consisting on the introduction of a proportional
gain kp in the OLTF.

COLTFVin (s ) = K p ⋅ OLTFVin (s ) (24)

Bode diagram plotted on Fig. 3 (a) shows the OLTFVin(s). As its dynamic is too slow (fC Vin = 7 Hz) and
there must be voltage oscillations above such frequency because of both the fast single buck control
loop and the maximum input voltage ripple frequency (720 Hz and 360 Hz), a proportional gain of 33
has been added to the loop. The resulting bode diagram is shown in Fig. 3 (b).
A higher cut-off frequency would be preferable for the symmetry closed-loop (≥720 Hz), however a
proportional gain higher than 33 was not stable on the bench. Such behavior is nevertheless not
theoretical, but can be expected in real implementations because too high gains certainly amplify not
only the signal, but also noise from circuitry. Improvements on PCB layout besides other noise
reduction techniques could potentially enable higher gains. As proven to be successfully stable in the
entire input voltage and output loads range, Kp= 22 has been set as the adequate value.
Bode Diagram
Gm = 15.6 dB (at 3e+003 Hz) , Pm = 60 deg (at 720 Hz)
100

0
Magnitude (dB)

-100

-200

-300

-400
-90
New Design: fc= 720.0 Hz
Phase (deg)

-180

-270

-360
0 2 4 6 8
10 10 10 10 10
Frequency (Hz)

Fig. 2: Type II controller compensated open-loop transfer function for the single buck output voltage
regulation

Bode Diagram Bode Diagram

Gm = Inf , Pm = -173 deg (at 6.96 Hz) Gm = Inf , Pm = -137 deg (at 43.6 Hz)
50 100

0 50
M agnitude (dB)
Magnitude (dB)

-50 0

-100 -50

-150 -100
135 135
Non-compensated: fc= 7.0 Hz
Desgin: fc= 43.6 Hz
Phas e (deg)
Phas e (deg)

90 90

45 45

0 0
0 1 2 3 4 5 0 1 2 3 4 5
10 10 10 10 10 10 10 10 10 10 10 10
Frequency (Hz) Frequency (Hz)

(a) (b)
Fig. 3: Symmetry open-loop transfer function: (a) non-compensated (Kp=1); (b) compensated (Kp=22)
It is important to highlight that the critical point for stability of both bucks occurs for lower input
voltages In this case, a narrow asymmetry of the input voltage split may lead to one of the bucks to run
unstable (0V on the output), as its input voltage falls to value lower than the output voltage. In his
way, the proportional gain of Kp has to be set for the lowest operation input voltage within the
specified range.
On the other hand, for higher voltage inside the range a much larger stability margin is expected, as
well as similar voltage levels differences. Such characteristic is advantageous as the critical maximum
voltage on the semiconductors switches occurs exactly on higher voltages. Therefore, a very low
voltage difference is expected between the splits input voltages even at transient events, which has in
fact been observed in all experimental results.
Moreover, null steady-state error is expected for the voltage balancing control as the transfer function
of the GVs/Vc(s) presents a pole in the origin (s-1), which integrates the error signal even using only a
proportional gain in the loop.

Experimental results
In order to verify the feasibility, robustness and dynamic performance of the proposed control method,
experimental results were obtained by implementing the proposed controller in the circuit shown in
Fig. 1 (e). The control design was realized considering the parameters described in Table I below.
The tests were performed with the converter operating from its minimum up to its maximum input
voltage as well as at rated and light load. Experimental results showing the response of the close-loop
of the top buck converter for 50% to 100% load steps are shown in Fig. 4 and Fig. 5 for VIN = 1500 V
and 330 V, respectively. It can be observed a low overshoot value besides a fast response with a time
less than 1 ms to reach steady state.

Table I: Parameters of the constructed circuit

Output power Po 6 kW

Input voltage Vin 330 – 1500 V

Output voltage Vo 300 V

Input capacitor C1, C2 100 µF

Output capacitor C3, C4 330 µF

Buck inductor L1, L2 800 µH

Symmetry control proportional gain Kp 22

Current sensing gain Ri 15.25 mV/A

Output voltage sensing gain HVo 14.57∙10-3

Input capacitor voltages difference sensing gain HVin 1.75∙10-3

Switching frequency fsw 18 kHz

Output voltage loop cut-off frequency fc_vo 720 Hz

Symmetry loop cut-off frequency fc_vs 43.6 Hz

Fig. 6 shows waveforms of 5% to 70% at 450 V supply of nominal load steps. Stability can be clearly
observed for the output voltage regulation on all of the presented transient events. Voltages on the
input capacitors are so close that, in fact, differences are not noticeable, overlapping each other on the
waveforms of Fig. 6.

Fig. 4: Step-down bipolar buck response for VIN = 1500 V and 50% to 100% load step: output voltage
VO on top (Ch4, 50 V/div); input capacitor voltage VC1 in the middle (Ch2, 250 V/div); and buck
inductor current IL1 bellow (Ch3, 5 A/div); gate voltage on the bottom (Ch1, 25 V/div); time scale of 4
ms/div

Fig. 5: Step-down bipolar buck response for VIN = 330 V and 50% to 100% load step: gate voltage on
top (Ch1, 25 V/div); input capacitor voltage VC1 in the middle (Ch2, 50 V/div); output voltage VO
bellow (Ch4, 100 V/div); and buck inductor current IL1 on the bottom (Ch3, 5 A/div); time scale of 4
ms/div

VC1 = VC2

Fig. 6: Step-down bipolar buck response for VIN = 450 V and 5% to 70% load step: output voltage VO
on top (Ch4, 100 V/div); total input voltage VIN (Ch1, 50 V/div) and input capacitor voltage VC1 in the
middle (Ch2, 50 V/div); and buck inductor current IL1 on the bottom (Ch3, 5 A/div); time scale of 10
ms/div
 Conclusion
This paper presented a technique that provides active balancing on voltages of capacitors connected in
series to split the voltage of predominantly DC sources, whose load comprises power converters or
inverters. The method has proven to be effective to dynamically perform such balancing even on
critical cases as for relatively small capacitors with variables loads connected to them, besides large
ranges of input voltages. The proposal measures the voltage difference of each pair of series-
connected capacitors, achieving balancing voltage by lightly controlling the power of one of them.
An analysis of stability that enables a safe and optimum design, rating minimum capacitances
according to load dynamics requirements has been presented. Proposal’s main advantage is its
simplicity of implementation as each load can be independently regulated without any communication
neither interconnection. Such feature can be advantageous in the overall power converter design by
reducing or eliminating the amount isolated components such as opto-transistors, isolated rivers.
In order to confirm feasibility, a 6 kW DC-DC step-down prototype has been built, consisting of two
buck converters in bipolar connection supplied from a 330 V to 1500 V DC supply. The step-down
output is voltage regulated, whose control has been designed with inner peak current control. Voltage
balancing has been achieved via lightly changing its output voltage reference, consequently
controlling its power. The integral control plant prevents steady-state error in the output voltage,
keeping regulation within specifications. Full stability has been achieved, with equalized voltages in
the input capacitors even during extreme transients on several input voltages and load cases.
Differences on the capacitors voltages could not even be observed, which indicates that the maximum
ratings of the switches (both 1.2 kV IGBTs and diodes) have not been exceeded. It is important to
highlight though, that the proposed technique is not limited to the presented application. The
combination of a voltage or current supply predominantly DC and slight power control of one
capacitor load for each pair is in fact the single requirement to implement such technique. The method
itself allows for possibilities as variations on input voltage, even AC grid ripple, and other forms of
power control, such as current regulation (on cases of open loop or current regulated output).

References
[1] Rodriguez, J.; Jih-Sheng Lai; Fang Zheng Peng, "Multilevel inverters: a survey of topologies, controls, and
applications," in Industrial Electronics, IEEE Transactions on , vol.49, no.4, pp.724-738, Aug 2002.
[2] Singh, Ranbir; “Reliability and performance limitations in SiC power devices”, Microelectronics
Reliability Vol. 46, Issues 5-6, pp. 713-730, May-June 2006.
[3] Huang, Xing; Wang, Gangyao; Li, Yingshuang; Huang, Alex Q.; Baliga, B.Jayant, "Short-circuit capability
of 1200V SiC MOSFET and JFET for fault protection," in Applied Power Electronics Conference and
Exposition (APEC), 2013 Twenty-Eighth Annual IEEE , vol., no., pp.197-200, 17-21 March 2013.
[4] Rodriguez, J.; Jih-Sheng Lai; Fang Zheng Peng, "Multilevel inverters: a survey of topologies, controls, and
applications," in Industrial Electronics, IEEE Transactions on , vol.49, no.4, pp.724-738, Aug 2002.
[5] Costa, L.F.; Mussa, S.A.; Barbi, I., "Capacitor voltage balancing control of multilevel DC-DC converter," in
Power Electronics Conference (COBEP), 2013 Brazilian , vol., no., pp.332-338, 27-31 Oct. 2013.
[6] Khazraei, M.; Sepahvand, H.; Corzine, K.A.; Ferdowsi, M., "Active Capacitor Voltage Balancing in Single-
Phase Flying-Capacitor Multilevel Power Converters," in Industrial Electronics, IEEE Transactions on ,
vol.59, no.2, pp.769-778, Feb. 2012.
[7] Ertl, H.; Wiesinger, T.; Kolar, J.W.; “Active voltage balancing of DC-link electrolytic capacitors” IET
Power Electronics, pp. Dec. 2007.
[8] Lounila M.: ‘Balancing circuit for input voltage division between capacitors’. European Patent
EP1107438A2, June 2001.
[9] Texas Instruments Inc., “Understanding and Applying Current-mode Control Therory –Design Guide for
Fixed-Frequency, Continuous Conduction-Mode Operation”, Application Report SNVA555, 31st October
2007.

View publication stats