Simplified process:

Fabrication Process flow: Basic steps

Making of CMOS using N well
Twin well CMOS:
MOS Structure and operation:

The MOS transistor is a majority-carrier device in which the current in a conducting channel between the source
and drain is controlled by a voltage applied to the gate.
• The behavior of MOS transistors can be understood by first examining an
isolated MOS structure with a gate and body but no source or drain.
• The body is grounded and a voltage is applied to the gate. The gate oxide is a
good insulator so almost zero current flows from the gate to the body.
• A negative voltage is applied to the gate, so there is negative charge on the
gate. The mobile positively charged holes are attracted to the region
beneath the gate. This is called the accumulation mode.
• A small positive voltage is applied to the gate, resulting in some positive
charge on the gate. The holes in the body are repelled from the region
directly beneath the gate, resulting in a depletion region forming below the
gate.
• A higher positive potential exceeding a critical threshold voltage Vt is
applied, attracting more positive charge to the gate. The holes are repelled
further and some free electrons in the body are attracted to the region
beneath the gate. This conductive layer of electrons in the p-type body is
called the inversion layer.
The gate-to-source voltage Vgs is less than the threshold voltage. The source and drain
have free electrons. The body has free holes but no free electrons. Suppose the source is
grounded. The junctions between the body and the source or drain are zero-biased or
reverse-biased, so little or no current flows. We say the transistor is OFF, and this mode
of operation is called cutoff.
The gate voltage is greater than the threshold voltage.
Now an inversion region of electrons (majority carriers)
called the channel connects the source and drain,
creating a conductive path and turning the transistor
ON.

When a small positive potential Vds is applied to the

drain current Ids flows through the channel from drain to
source. This mode of operation is termed linear
If Vds becomes sufficiently large that Vgd < Vt , the channel is no longer inverted near the drain and
becomes pinched off.
• The nMOS transistor has three modes of operation.
• If Vgs < Vt, the transistor is cutoff (OFF). If Vgs > Vt, the transistor
turns ON.
• If Vds is small, the transistor acts as a linear resistor in which the
current flow is proportional to Vds.
• If Vgs > Vt and Vds is large, the transistor acts as a current source in
which the current flow becomes independent of Vds.
 • The pMOS transistor in Figure 2.4 operates in just the
opposite fashion.
• The n-type body is tied to a high potential so the junctions
with the p-type source and drain are normally reverse-
biased. When the gate is also at a high potential, no current
flows between drain and source.
• When the gate voltage is lowered by a threshold Vt , holes
are attracted to form a p-type channel immediately
beneath the gate, allowing current to flow between drain
and source.

• Although MOS transistors are symmetrical, by convention we say that majority carriers flow from their source to
their drain. Because electrons are negatively charged, the source of an nMOS transistor is the more negative of the
two terminals.
• Holes are positively charged so the source of a pMOS transistor is the more positive of the two terminals.
• In static CMOS gates, the source is the terminal closer to the supply rail and the drain is the terminal closer to the
output.
Current-Voltage (I-V) Characteristics:

• Here we are assuming that the channel length is long enough that
the lateral electric field (the field between source and drain) is
relatively low, which is no longer the case in nano meter devices. This
model is variously known as the long-channel, ideal, first-order, or
Shockley model.
• The long-channel model assumes that the current through an OFF
transistor is 0.When a transistor turns ON (Vgs > Vt), the gate attracts
carriers (electrons) to form a channel.
• The electrons drift from source to drain at a rate proportional to the
electric field between these regions. Thus, we can compute currents
if we know the amount of charge in the channel and the rate at
which it moves.
• We know that the charge on each plate of a capacitor is Q = CV. Thus,
the charge in the channel Qchannel is
• Qchannel = Cg (Vgc-Vt)
• Cg is the capacitance of the gate to the channel
• Vgc-Vt is the amount of voltage attracting charge to the channel
•
• The time required for carriers to cross the channel is the channel length divided by the
carrier velocity: L/v.
• Therefore, the current between source and drain is the total amount of charge in the
channel divided by the time required to cross
For Vgs > Vt, but Vds relatively small. It is called linear or resistive because when Vds <<
VGT, Ids increases almost linearly with Vds, just like an ideal resistor.
•
C-V Characteristics:
• Each terminal of the MOSFET has a capacitance with the other
terminals. These capacitances are non-linear and voltage
dependent.
 Gate capacitance:
• The gate capacitance has two components, the intrinsic capacitance
Cgin and the overlap capacitance Cgol.
• The intrinsic capacitance is the capacitance between the gate and the
channel whereas the overlap capacitance is caused by the
overlapped regions between the gate and source/drain.
• In ideal MOS transistors, there is no overlap between the source/
drain and the gate but due to imperfect manufacturing processes,
there is an overlap.
• The intrinsic capacitance is composed of three components
Cgs (Capacitance between gate and source) , Cgb (Capacitance
between gate and body) and Cgd (Capacitance between gate and
drain).
 • Cgin=Cgs+Cgb+Cgd = CoxWL = C0
• Cgin remains approximately constant across different voltages applied
on source, gate and drain. But depending upon the voltages on gate,
source and drain, the distribution of Cgin on Cgs, Cgb, Cgd change.
• Cut-off :
• In the cut off region, the transistor is off and there is no inversion
layer. The charges on the gate are matched by opposite charges in
the body.
• In accumulation region, Cgin=Cgb= C0 . Cgs and Cgd are zero because
there is no inversion layer.
• But as Vgs becomes positive and enters depletion region, the positive
charges are repelled down the body.
• This increases the distance between the “plates” of the capacitor
which decreases the capacitance Cgb. Look at the a) of the diagram
given above. There is a steady decline in Cgb from Vgs=0 to Vgs=Vt.
 Linear :
• When Vgs>Vt, an inversion layer is formed under the oxide layer.
• In linear region Vds is small hence the distribution of capacitance
between the source and the drain region is roughly equal
thus Cgs=Cgd=C0/2.
• Cgb is zero because the bottom plate of the gate capacitor is now the
n-channel and the n-channel cuts off connection between the gate
and the body.
• With increase in Vds, the channel near the drain region becomes less
inverted and hence a greater distribution of capacitance is attributed
to Cgs. Notice how Cgs and Cgd increase with increase in Vgs in diagram
a). Also notice how Cgs increases but Cgd decreases with increase in
Vds in diagram b).
• Saturation:
• When Vds>(Vgs-Vt) , the channel pinches off at the drain end. Thus the
entire intrinsic capacitance is attributed to the Vgs and due to the
pinch off at the drain end, the intrinsic capacitance reduces to 2/3 C0.
• In an non-ideal MOSFET, there are overlapping regions between the
gate and source/drain. Considering uniform overlap in both the
source and the drain regions, we can say the length of the
overlapped region is Lov.

• Cgs(overlap)=Cgd(overlap)=CLovW
• Cg = Cgin+ C(overlap) = Cgin+ Cgd(overlap) +Cgs(overlap)
• Diffusion Capacitance:
• The source and drain (In NMOS) are n-type regions surrounded by a P-type
substrate.
• When a n-type and a p-type region comes into contact, a PN junction
forms between them.
• As a virtue of this junction, there is capacitance between the n and p type
regions. In MOSFET’s , PN junctions form between source-body and drain-
body. This leads to formation of Csb and Cdb capacitances.
• The source (and drain) forms a cuboid structure inside a p-type substrate.
• A cuboid has 6 sides. One of the side walls of the source is seamlessly
merged with the n-channel and hence there is no PN junction formed on
that side wall.
• The top of the source doesn’t interact with any p-type substrate hence
there is no PN junction on the top either. The bottom plate, front ,back and
one side wall forms PN junctions with the P-type substrate.
• Bottom plate capacitance = Cbot = CjLsW
• where Cj is the diffusion capacitance per unit area
• Side wall capacitance = Csw = CjXjW
• Front and back capacitance = Cfb=2CjLsXj
• Csb = Cdb = Cbot+Csw+Cfb = CjLsW + CjXj (W+2Ls)
• Notice how the parasitic capacitance is almost proportional to the
width W of the transistor.
• With increase in W, parasitic capacitance increases. But remember
current is directly proportional to W (which mean resistance is
inversely proportional to W) .
• Hence with increase in W, resistance decreases but parasitic
capacitance increases.
 Channel Length Modulation:

•
•
Body Effect:
• So far, we have treated the threshold voltage as a constant. However,
Vt increases with the source voltage, decreases with the body
voltage, decreases with the drain voltage, and increases with channel
length.
• Until now, we have considered a transistor to be a three-terminal
device with gate, source, and drain.
• When a voltage Vsb is applied between the source and body, it
increases the amount of charge required to invert the channel, hence,
it increases the threshold voltage. The threshold voltage can be
modeled as
•
•
Layout Design Rules:
• The design rules are usually described in two ways:
• (i) Micron rules, in which the layout constraints such as minimum
feature sizes and minimum allowable feature separations are stated
in terms of absolute dimensions in micro meters, or,
• (ii) Lambda rules, which specify the layout constraints in terms of a
single parameter (λ) and thus allow linear, proportional scaling of all
geometrical constraints.
• Layout design is a schematic of the integrated circuits(IC) which describes the
exact placement of the components for fabrication.
• Layout design rules describe how small features can be & how closely they
can be packed in a manufacturing process.
• Industrial design rules are generally specified in microns.
• This makes migrating from one process to more advanced process difficult
because not all rules scale in the same way.
• In order to bring uniformity, Mead & Conway popularized lambda –based
design rules based on a single parameter
• Lambda, characterizes the resolution of the process & is generally the half the
minimum drawn transistor channel length.
• The channel length is the distance between drain & the source which is set by
a minimum width of a polysilicon wire.
• Fabrication process needs different masks, these masks are prepared from
layout.
• Layout is an Interface between circuit designer and fabrication engineer.
• Layout is made using a set of design rules.
• Design rules allow translation of circuit into actual geometry in silicon wafer.
• These rules usually specify the minimum allowable line widths for physical
objects on-chip.
• Example: metal, polysilicon, interconnects, diffusion areas, minimum
feature dimensions, and minimum allowable separations between two such
features.
 Need for Design Rules:
•Better area efficiency.
•Better yield.
•Better reliability.
•Increase the probability of fabricating a successful product on Si
wafer.
❑ If design rules are not followed:
• Functional or non-functional circuit.
• Design consuming larger Si area.
• The device can fail during or after simulation.
 Transistor rules:
• transistor is designed with at least four masks:
• active mask – defines where p- or n-diffusion type or gates will be placed;
• n-implant mask – defines areas where n-type diffusion is required; n-type
diffusion in p-wells define nMOS transistors; n-type diffusion in n-wells define
n-type contacts.;
• p-implant mask – defines areas where p-type diffusion is required; p-type
diffusion in n-wells defines pMOS transistors; p-type diffusion in p-wells
define p-well contacts
• polysilicon mask – crossing of polysilicon and diffusion mask defines the gates
of transistor.
• Polysilicon mask should cover active mask and extend beyond that area,
otherwise transistor will be shorted with the diffusion path between source
and drain. Polysilicon and active masks that does not form a transistor should
be kept separately.
 Contacts rules:
• Types of contacts:
• metal to p-active (p-diffusion)
• metal to n-active (n-diffusion)
• metal to polysilicon
• metal to well or substrate
• Contacts are normally of uniform size to allow for consistent etching of
very small features.
Vias(Vertical Interconnect Access) rules:
• Modern planarized processes permit stacked vias, which reduces the area
required to pass from a lower-level metal to a high-level metal.
• Vias are normally of uniform size within a layer.
• They may increase in size toward the top of a metal stack.
• For instance, large vias required on power busses are constructed from an
array of uniformly sized vias.
 Metal rules:
• Metal spacing can be different depending on the metal line. But
there is certain width applied to small and thick wires. So if there is a
need of wider wires, they can be made of several small wires
connected together. Spacing rules can be applied to a long parallel
wires.
Other Rules:
• Some additional rules that might be present in some processes are as
follows:
• Extension of polysilicon or metal beyond a contact or via
• Differing gate poly extensions depending on the device length
• Maximum width of a feature
• Minimum area of a feature (small pieces of photoresist can peel off
and float away)
• Minimum notch sizes (small notches are rarely beneficial and can
interfere with resolution enhancement techniques)
MOSFET Scaling:
• The reduction of the size, i.e., the dimensions of MOSFETs, is
commonly referred to as scaling.
• It is expected that the operational characteristics of the MOS
transistor will change with the reduction of its dimensions.
• There are two basic types of size-reduction strategies: full scaling
(also called constant-field scaling) and constant voltage scaling.
• Both types of scaling approaches will be shown to have unique
effects upon the operating characteristics of the MOS transistor.
• Scaling of MOS transistors is concerned with systematic reduction of
overall dimensions of the devices as allowed by the available technology,
while preserving the geometric ratios found in the larger devices.
• The proportional scaling of all devices in a circuit would certainly result in
a reduction of the total silicon area occupied by the circuit, thereby
increasing the overall functional density of the chip.
• To describe device scaling, we introduce a constant scaling factor S > 1.
• We consider the proportional scaling of all three dimensions by the same
scaling factor S. Figure 3.24 shows the reduction of key dimensions on a
typical MOSFET, together with the corresponding increase of the doping
densities.
Constant-field Scaling(Full Scaling):
• This scaling option attempts to preserve the magnitude of internal
electric fields in the MOSFET, while the dimensions are scaled down
by a factor of S.
• To achieve this goal, all potentials must be scaled down
proportionally, by the same scaling factor.
• Note that this potential scaling also affects the threshold voltage VT0
• Now consider the influence of full scaling described here upon the
current-voltage characteristics of the MOS transistor.

• The aspect ratio WIL of the MOSFET will remain unchanged under
scaling. Consequently, the trans conductance parameter kn will also
be scaled by a factor of S.
• Since all terminal voltages are scaled down by the factor S as well,
the linear-mode drain current of the scaled MOSFET can now be
found as:
• Similarly, the saturation-mode drain current is also reduced by the
same scaling factor.

• Now consider the power dissipation of the MOSFET.

• Notice that full scaling reduces both the drain current and the drain-
to-source voltage by a factor of S; hence, the power dissipation of
the transistor will be reduced by the factor S2 .
• The changes in key device characteristics as a result of full (constant-
field) scaling.
Constant – Voltage Scaling:
• In constant-voltage scaling, all dimensions of the MOSFET are
reduced by a factor of S, as in full scaling. The power supply voltage
and the terminal voltages, on the other hand, remain unchanged.
• The doping densities must be increased by a factor of S2 in order to
preserve the charge-field relations.
• Table 3.4 shows the constant-voltage scaling of key dimensions,
voltages, and densities.
• Under constant-voltage scaling, the changes in device characteristics
are significantly different compared to those in full scaling
• The gate oxide capacitance per unit area Cox is increased by a factor of S,
which means that the trans conductance parameter is also increased by S.

• Since the terminal voltages remain unchanged, the linear mode drain current
of the scaled MOSFET can be written as:

• Also, the saturation-mode drain current will be increased by a factor of S after

constant voltage scaling.
• Next, consider the power dissipation. Since the drain current is
increased by a factor of S while the drain-to-source voltage remains
unchanged, the power dissipation of the MOSFET increases by a
factor of S.

• To summarize, constant-voltage scaling may be preferred over full

(constant-field) scaling in many practical cases because of the
external voltage-level constraints.
• It must be recognized, however, that constant-voltage scaling
increases the drain current density and the power density by a factor
of S3.
• This large increase in current and power densities may eventually
cause serious reliability problems for the scaled transistor, such as
electromigration, hot-carrier degradation, oxide breakdown, and
electrical over-stress
• Results of constant field scaling:
• Current capability of transistors drops by a factor of S.
• Capacitances decrease by a factor of S.
• Delay times decreases by a factor of S.
• Power dissipation drops by a factor of S3
• Power density remains unchanged.

• However, constant field scaling leads to

• reduction of supply voltage reduces dynamic range (of analog circuitry)
• lower end of dynamic range is limited by thermal noise
• problems caused by short-channel effects
• Results of constant-voltage scaling
• current capability of transistors drops by a factor of 1 or α
• capacitances decrease by a factor of α
• delay times decrease by a factor of α or α2
• power dissipation drops by a factor of 1 or α
• power density increases by a factor of α2 or α3 (!)
• field increases by a factor of α

• However, constant voltage scaling leads to

• drastically increased power density
• hot-electron & oxide reliability problems
• mobility degradation
Short Channel Effect:

• A MOSFET can be defined as a short-channel device if the effective

channel length Leff is approximately equal to the source and drain
junction depth xj.
• The short-channel effects that arise in this case are attributed to two
physical phenomena:
• (i) the limitations imposed on electron drift characteristics in the
channel, and
• (ii) the modification of the threshold voltage due to the shortening
channel length.
 Drain-Induced Barrier Lowering:
• The drain voltage Vds creates an electric field that affects the
threshold voltage.
• This drain-induced barrier lowering (DIBL) effect is especially
pronounced in short-channel transistors. It can be modelled as

• Where η is the DIBL coefficient

• Drain-induced barrier lowering causes Ids to increase with Vds in
saturation, in much the same way as channel length modulation does.

• This effect can be lumped into a smaller Early voltage VA used in

channel length modulation. Again, this is a bane for analog design
but insignificant for most digital circuits.
 Short channel effect:
• The threshold voltage typically increases with channel length.
• This phenomenon is especially pronounced for small L where the
source and drain depletion regions extend into a significant portion
of the channel, and hence is called the short channel effect or Vt
rolloff .
• In some processes, a reverse short channel effect causes Vt to
decrease with length.
• There is also a narrow channel effect in which Vt varies with channel
width; this effect tends to be less significant because the minimum
width is greater than the minimum length.