1. Most components in our computer are in fact, a memory.

From CPU registers, RAM, and our

main storage are all memories, due to the fact that they store bits, i.e. 1 and 0. There are lot of
ways to store the bits informa on. It could be simple mechanical device which open and close,
could also be electric voltage, etc. It is due to the fact that among many op ons available that
drives the choice of memory system to be used. The main tradeo is whether to choose speed,
or to choose lower price. Mo vated by this fact, the memory hierarchy explains the available
choices of memory to build our computer.
Overall, we can dis nguish two categories of memory, vola le and non-vola le. They di er by
their ability to keep the informa on stored once the system is turned o . It is then
understandable that vola le memory loses the informa on while non-vola le keeps them. The
ability of non-vola le memory to keep informa on albeit power is turned o comes to a price
that it o en performs slower.
Vola le memory usually comes at the top of the hierarchy, comprising of CPU and registers
which are ultrafast, followed by cache memories and/or SRAM which is a bit slower, then DRAM,
respec vely. SRAM (or cache) is used to bridge the speed di erence between registers and
DRAM by u lizing temporal and space locality. Anyway, even though DRAM is far slower than
CPU or SRAM, it is in fact s ll much faster than the fastest non-vola le memory.
NAND-Flash and HDD falls into non-vola le category. They are far slower than vola le memories,
but they have the ability to store the data even a er the power is completely o . They are also
much cheaper per bits stored, thus usually comes with a huge storage. From this fact, they are
mainly used to store OS and another data such as movies, music, etc. In terms of speed, NAND-
Flash is normally 10 mes faster than HDD as they completely di er in opera ng mechanisms.
NAND-Flash is also more robust due to the fact that they do not use spinning disks, as what HDD
does.
So to summarize, normally in memory hierarchy, from top to bo om, we have CPU, SRAM,
DRAM, NAND-Flash, and nally HDD.

2. The e ect of scaling down might degrade the transistor performance. Up to this point, it is
thought that the MOSFET technology has reached its end in terms of scaling down, i.e. up un l
to 14 nm size. Further scaling down might seems impossible, or at least very prone to unpleasant
e ects, including leakage and wide variability.

To make it clear, in planar MOSFET, a single gate controls the source-drain channel. It is intui ve
that a single gate does not have good electrosta c eld control, leading to leakage between
source and drain even though the gate is under closed posi on. To alleviate this, a new
technology called FinFET was proposed. In principle, the FinFet replaces the source-drain
channel with a ver cal n, penetra ng to the gate, as if the gate is wrapped around the source-
drain channel. This enables a be er control on electric eld, thus leading to a more robust gate
which is not prone to a leakage. This ability of FinFET is the main reason why it can alleviate the
scaling down problem of planar MOSFET.
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 There are other advantages of FinFET compared to planar MOSFET. This includes the high
integra on density due to its natural 3D shape. FinFET also o ers smaller variability, mainly
variability due to random dopant uctua on. It is due to all of these advantages that FinFET
enables scaling down further, even up to 7 nm.

3. The average instruc on cycle number de nes how many clock cycles required to perform one
instruc on. It is thus intui ve that it comprises of register cycle plus memory access cycle. In
terms of memory access cycle itself, due to the cache memory technology, o en the register
nds the required data from cache memory instead of main memory, thus enable faster
instruc on cycle.
For case 1, since only level 1 cache is applied, we have,

Case 1:
Tam (DRAM) = 60 ns
Tac (cache) = 0.8 ns
Clock freq = 2.5 GHz
Clock freq = 2.5 GHz
H1 = 95%
H2 = 97%

Ｔ＝１＋０.３×ｈ1×Ｔc1＋０.３×（１−ｈ1）× (h2 x Tc2 + (1-h2) x Tm)

Ｔ＝１＋０.３×0.95 × (0.4 x 10^(-9) 2.5 x 10^9)＋０.３×（0.05）× (0.97 x (6 x 10^(-9) 2.5 x

10^9) + (0.03) x (60 x 10^(-9) 2.5 x 10^9))
T = 1 + 0.285 + 0.28575
T = 1.57075 cycles
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