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Total No. of Questions—8] [Total No. of Printed Pages—2

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S.E. (Computer) (I Sem.) EXAMINATION, 2019
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COMPUTER ORGANIZATION AND ARCHITECTURE
.23 G
CE

(2015 PATTERN)

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Time : Two Hours Maximum Marks : 50

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N.B. :— (i) Neat diagrams must be drawn wherever necessary.

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(ii) Figures to the right indicate full marks.
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(iii) Use of logarithmic tables, slide rule, Mollier charts, electronic
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pocket calculator and steam tables is allowed.

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(iv) Assume suitable data, if necessary.

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1. (a) Explain the following cache updating policies : [6]

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(i) Write through
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(ii) Write back.
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(b) Apply Booth’s algorithm to multiply the following numbers. Show

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every step clearly (+12) * (–7). [6]

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Or
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2. (a) What is cache coherenee ? What are the solutions to cache

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coherence problem ? Explain any one in detail. [6]

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(b) Explain the following : [6]

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(i) Direct Mapping

(ii) Associate Mapping.
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3. (a) What are the major functions of I/O module ? [6]

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(b) Explain types of instructions according to operations and

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number of address. Give examples. [6]

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4. (a) Explain the following addressing modes with example of each : [6]

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(i) Immediate addressing
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(ii) Register addressing
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(iii) Auto decrement.

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(b) List DMA data transfer modes and explain any one in

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detail. [6]
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5. (a) Compare superscalar and superpipelined approaches in

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superscalar processor. [6]
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(b) Draw and explain instruction cycle in detail. [7]
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6. (a) List and explain various ways in which an instruction pipeline

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can deal with conditional branch instructions. [7]

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(b) Draw and explain the functional block diagram of 8086. [6]

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7. (a) Write a control sequence for the following instructions for

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single bus organization. ADD (R3), R1. Assuming R1 as

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destination. [7]
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(b) Draw and explain micro-programmed control unit design. [6]

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8. (a) Differentiate in between Hardwired control and Micro-

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programmed control. [6]

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(b) Draw and explain single bus organization of CPU. [7]

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