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SE (Computer) (I Sem.) EXAMINATION, 2017

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DIGITAL ELECTRONICS AND LOGIC DESIGN
8.2 G

(2012 PATTERN)
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.24 CE

Time : Two Hours Maximum Marks : 50

N.B. :— (i ) Solve Q. No. 1 or Q. No. 2 , Q. No. 3 or Q. No. 4 ,

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Q. No. 5 or Q. No. 6 and Q. No. 7 or Q. No. 8 .
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(ii ) Neat diagrams must be drawn wherever necessary.

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Figures to the right indicate full marks.
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(iv) Use of Mollier charts, electronic pocket calculator and steam
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tables are allowed.
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(v ) Assume suitable data, if necessary.

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1. (a) Minimize the following function using K-map and realize using
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logic gates : [4]

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F(A, B, C, D) = m(1, 5, 7, 13, 15) + d(0, 6, 12, 14).
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(b) Convert the following : [2]
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(175)10 = (?)8
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(c ) List the differences between CMOS and TTL. [6]

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2. (a) Convert the following numbers into binary numbers : [4]

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(i ) (37)8
1

(ii ) (25.5)10
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(b) Explain the standard TTL characteristics in detail. [6]

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 (c ) Represent the following signed number in 2’s complement

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method : [2]

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(i ) +17

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(ii ) –17.

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3. (a) Explain rules for BCD addition with suitable example and design

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a single digit BCD adder using IC 7483. [6]
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(b) Design a MOD-6 synchronous counter using J-K flip-flops. [6]

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Or

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4. (a) Design a sequence generator using J-K flip-flop sequence

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is : [6]

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1 3 5 6 7 1.

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(b) Design a circuit to convert 4-bit binary to its equivalent
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gray code. [6]
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5. (a) What is ASM chart ? Give its application and explain the
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MUX controller method with suitable example. [7]

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(b) Write VHDL code for 4-bit adder using structural modelling
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style. [6]
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6. (a) Draw the ASM chart for the following state machine.
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A 2-bit up counter is to be designed with output QAQ B

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and enable signal ‘X’. If X = 0, then counter changes the

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state as 00-01-10-11-00. If ‘X’ = 1, then counter should remain

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in current state. Design the circuit using J-K flip-flop and

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suitable MUX. [7]

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(b) Write a VHDL code for 8 : 1 MUX using Behavioural

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modeling. [6]
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7. (a) Draw and explain basic architecture of FPGA in detail. [6]

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(b) A combinational circuit is defined by the functions : [7]

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f1(A, B, C) = m(3, 5, 7)

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f2(A, B, C) = m(4, 5, 7)

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Implement the circuit with PLA having 3 input and 3 product
term with 2 output.

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Or
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8. (a) Implement 4 : 1 MUX using PAL. [6]

(b) Implement the following functions using PLA : [7]
f1(A, B, C) =

0
m(0, 3, 4, 7)

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f2(A, B, C) = m(1, 2, 5, 7).

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