Asynchronous sequential circuit:

 Do not use clock pulses. The change of internal state occurs when there is a change in
the input variable.
 Their memory elements are either unclocked flip-flops or time-delay elements.
 They often resemble combinational circuits with feedback.
 their synthesis is much more difficult than the synthesis of clocked synchronous
sequential circuits.
 They are used when speed of operation is important. The communication of two units
with each unit having its own independent clock, must be done with asynchronous
circuits.
The general structure of an asynchronous sequential circuit is as follows:

There are n input variables, m output variables, k internal states. The presents state variables
(y1 to yk) are called secondary variables. the next state variables (Y1 to Yk) are called
excitation variables. Fundamental mode operation assumes that the input signals change one
at a time and only when the circuit is in a stable condition.
Stability: For a given set of inputs (i.e., values), the system is STABLE if the circuit
eventually reaches steady state and the excitation variables and secondary variables are equal
and unchanging (little y = capital Y), otherwise the circuit is UNSTABLE.
Types of Asynchronous sequential circuit:
Asynchronous sequential circuit is classified into two types.
1. Fundamental mode
2. Pulse mode.
Fundamental Mode Asynchronous sequential circuit
A circuit is operating in fundamental mode if we assume/force the following restrictions on
how the inputs can change:
1. Only ONE input is allowed to change at a time,
2. The input changes only after the circuit is STABLE.
Analysis of Asynchronous sequential circuit:
The analysis of Asynchronous sequential circuit proceeds in much the same way as that
clocked sequential circuit. From a logic diagram, Boolean expressions are written and then
transferred into tabular form.
An example of asynchronous sequential circuit is shown below:

The analysis of the circuit starts by considering the excitation variables (Y1 and Y2) as
outputs and the secondary variables (y1 and y2) as inputs.
The boolean expressions are:
Y1 = xy1 + x'y2 and Y2 = xy1'+x'y2
The next step is to plot the Y1 and Y2 functions in a map:
Map for Y1 = xy1 + x'y2
y1y2 x=0 x=1 Map for Y2 = xy1'+x'y2
00 0 0 y1y2 x=0 x=1
01 1 0 00 0 1
11 1 1 01 1 1
10 0 1 11 1 0
10 0 0

combining the binary values in corresponding squares the following transition table is
obtained:
y1y2 x=0 x=1

00 00 01

01 11 01

11 11 10

10 00 10
The transition table shows the values of Y = Y1Y2 inside each square. Those entries where
Y = y are circled to indicate a stable condition.
The circuit has four stable total states - y1y2x = 000, 011, 110 and 101 - and four unstable
total states - 001, 010, 111 and 100.
The state table of the circuit is shown below:
Present Next State
State x=0 x= 1
00 0 0 01
01 11 01
11 00 10
10 11 10
This table provides the same information as the transition table.
Flow table: In a flow table the states are named by letter symbols. Example of flow tables are
as follows:
y1y2 x=0 x=1

a a b

b c b

c c d

d a d

Analysis Summary:
Procedure to determine transition table and/or flow table from a circuit with combinatorial
feedback paths:
 Determine feedback paths.
 Label Y (excitation variables) at output and y (secondary variables at input).
 Derive logic expressions for Y (excitation variables) in terms of circuit inputs and
secondary variables. Do the same for circuit outputs.
 Create a transition table and flow table.
 Circle stable states where Y (excitation variables) are equal to y (secondary
variables).
Race Conditions:
A race condition exists in an asynchronous circuit when two or more binary state variables
change value in response to a change in an input variable. when unequal delays are
encountered, race condition may cause the state variable to change in an unpredictable
manner.
there are two types of races. Noncritical races and Critical races.
Noncritical Races:
if the final stable state that the circuit reaches does not depend on the order in which the state
variables change, the race is called a noncritical race. Examples of noncritical races are
illustrated in the transition tables below:
y1y2 x=0 x=1 y1y2 x=0 x=1

00 00 11 00 00 11

01 11 01 01

11 11 11 01

10 11 10 11
Possible transitions: Possible transitions:
00 -> 11 00 -> 11->01
00->01->11 00->01
00->10->11 00->10->11->01
Critical Races:
The transition tables below illustrate critical races:
y1y2 x=0 x=1 y1y2 x=0 x=1

00 00 11 00 00 11

01 01 01 11

11 11 11 11

10 10 10 10
Possible transitions: Possible transitions:
00 ->11 00 ->11
00->01 00->01->11
00->10 00->10
Critical races should be avoided.
Races can be avoided by directing the circuit through a unique sequence of intermediate
unstable states. when a circuit does that, it is said to have a cycle. Example of cycles are:

y1y2 x=0 x=1 y1y2 x=0 x=1 y1y2 x=0 x=1

00 00 01 00 00 01 00 00 01

01 11 01 11 01 11

11 10 11 11 11 10

10 10 10 10 10 01
State transitions: State transitions: Unstable
00 ->01->11->10 00->01->11 01->11->10--->01

Stability Check:
Asynchronous sequential circuits may oscillate between unstable states due to the feedback
 Must check for stability to ensure proper operations.
 Can be easily checked from the transition table.
 Any column has no stable states -> unstable
 Example:

Transition Table:
x1x2
y
00 01 11 10
0 0 1 1 0
1 0 1 0 0
Design of Asynchronous Sequential Circuit:
1. Obtain a primitive flow table from the given design specifications
2. Reduce the flow table by merging rows in the primitive flow table. This is also called as State
reduction technique.
3. Assign binary state variables to each row of the reduced flow to obtain the transition table.
This is also called as state assignment.
4. Assign output values to the dashes associated with the unstable states to obtain the output map
5. Simplify the Boolean functions of the excitation and output variables and draw the logic
diagram.
State Reduction Techniques:
„Two states are equivalent if they have the same output and go to the same (equivalent) next states
for each possible input.
Present Next State Output
State x=0 x=1 x=0 x=1
a c b 0 1
b d a 0 1
c a d 1 0
d b d 1 0
Ex: (a,b) are equivalent (c,d) are equivalent.
State reduction procedure is similar in both sync. & async. sequential circuits.
For completely specified state tables: -> use implication table „
For incompletely specified state tables:-> use compatible pairs
Implication table method:
„ Step 1: build the implication chart

Step 2: delete the node with unsatisfied conditions „

Step 3: repeat Step 2 until equivalent states found
Merge the Flow Table
The state table may be incompletely specified. Some next states and outputs are don’t care.
Primitive flow tables are always incompletely specified. Several synchronous circuits also have
this property. Incompletely specified states are not “equivalent”. Instead, we are going to find
“compatible” states. Two states are compatible if they have the same output and compatible next
states whenever specified.
Three procedural steps:
 Determine all compatible pairs „
 Find the maximal compatibles „
 Find a minimal closed collection of compatibles.
Compatible Pairs
Implication tables are used to find compatible states. We can adjust the dashes to fit any desired
condition. Must have no conflict in the output values to be merged

Maximal Compatibles „
A group of compatibles that contains all the possible combinations of compatible states
 Obtained from a merger diagram
 A line in the diagram represents that two states are compatible
n-state compatible -> n-sided fully connected polygon „
 All its diagonals connected „
Not all maximal compatibles are necessary

Closed Covering Condition „

The set of chosen compatibles must cover all the states and must be closed „
Closed covering „
The closure condition is satisfied if „
 There are no implied states „
 The implied states are included within the set „
Ex: if remove (a,b) in the right „
 (a,c,d) (b,e,f) are left in the set „
 All six states are still included „
  No implied states according to its implication table

Hence, Maximum compatible pairs are: (a,b), (a,c,d) and (b,e,f)

Race-Free State Assignment:
 Objective: choose a proper binary state assignment to prevent critical races
 Only one variable can change at any given time when a state transition occurs „
 States between which transitions occur will be given adjacent assignments „
 Two binary values are said to be adjacent if they differ in only one variable
 To ensure that a transition table has no critical races, every possible state transition
should be checked „
 A tedious work when the flow table is large „
 Only 3-row and 4-row examples are demonstrated
3-Row Flow Table Example
 Three states require two binary variables „
 Outputs are omitted for simplicity „
 Adjacent info. are represented by a transition diagram „
 a and c are still not adjacent in such an assignment !! „
Impossible to make all states adjacent if only 3 states are used

A race-free assignment can be obtained if we add an extra row to the flow table „
Only provide a race-free transition between the stable states „
The transition from a to c must now go through d „
00 -> 10 -> 11 (no race condition)
4-Row Flow Table Example
Sometimes, just one extra row may not be sufficient to prevent critical races „
More binary state variables may also required „
With one or two diagonal transitions, there is no way of using two binary variables that satisfy all
adjacency

Multiple-Row Method „
Multiple-row method is easier „
May not as efficient as in above shared-row method „
Each stable state is duplicated with exactly the same output „
Behaviors are still the same „
While choosing the next states, choose the adjacent one

Hazard:
A hazard in a system is an undesirable effect caused by either a deficiency in the system or
external influences. Logic hazards are manifestations of a problem in which changes in the input
variables do not change the output correctly due to some form of delay caused by logic elements
(NOT, AND, OR gates, etc.) This results in the logic not performing its function properly. The
three different most common kinds of hazards are usually referred to as static, dynamic and
function hazards.
Hazards are a temporary problem, as the logic circuit will eventually settle to the desired
function. Therefore, in synchronous designs, it is standard practice to register the output of a
circuit before it is being used in a different clock domain or routed out of the system, so that
hazards do not cause any problems. If that is not the case, however, it is imperative that hazards be
eliminated as they can have an effect on other connected systems.
Static Hazard
A static hazard is the situation where, when one input variable changes, the output changes
momentarily before stabilizing to the correct value. There are two types of static hazards:

 Static-1 Hazard: the output is currently 1 and after the inputs change, the output momentarily
changes to 0,1 before settling on 1
 Static-0 Hazard: the output is currently 0 and after the inputs change, the output momentarily
changes to 1,0 before settling on 0

In properly formed two-level AND-OR logic based on a Sum Of Products expression, there will
be no static-0 hazards. Conversely, there will be no static-1 hazards in an OR-AND
implementation of a Product Of Sums expression.
most commonly used method to eliminate static hazards is to add redundant logic (con
sensus terms in the logic expression).
Example of a static hazard
Let us consider an imperfect circuit that suffers from a delay in the physical logic elements i.e.
AND gates etc. The simple circuit performs the function noting:
f = X1 * X2 + X1' * X3
If we first look at the starting diagram, it is clear that if no delays were to occur, then the circuit
would function normally. However, no two gates are ever manufactured exactly the same. Due to
this imperfection, the delay for the first AND gate will be slightly different than its counterpart.
Thus an error occurs when the input changes from 111 to 011. i.e. when X1 changes state.
Now we know roughly how the hazard is occurring, for a clearer picture and the solution on how
to solve this problem, we would look to the Karnaugh map. The two gates are shown by solid
rings, and the hazard can be seen under the dashed ring. A theorem proved by Huffman[1] tells us
that by adding a redundant loop 'X2X3' this will eliminate the hazard.
So our original function is now: f = X1 * X2 + X1' * X3 + X2 * X3
Now we can see that even with imperfect logic elements, our example will not show signs of
hazards when X1 changes state. This theory can be applied to any logic system. Computer
programs deal with most of this work now, but for simple examples it is quicker to do the
debugging by hand. When there are many input variables (say 6 or more) it will become quite
difficult to 'see' the errors on a Karnaugh map.
Dynamic hazards
A dynamic hazard is the possibility of an output changing more than once as a result of a
single input change. Dynamic hazards often occur in larger logic circuits where there are different
routes to the output (from the input). If each route has a different delay, then it quickly becomes
clear that there is the potential for changing output values that differ from the required / expected
output. e.g. A logic circuit is meant to change output state from 1 to 0, but instead changes
from 1 to 0 then 1 and finally rests at the correct value 0. This is a dynamic hazard.
As a rule, dynamic hazards are more complex to resolve, but note that if all static hazards have
been eliminated from a circuit, then dynamic hazards cannot occur.
Functional hazards
In contrast with static and dynamic hazards, functional hazards are ones occurred by a
change applied to more than one input. There is no specific logical solution to eliminate them.
One really reliable method is preventing inputs from changing simultaneously, which is not
applicable in some cases. So, circuits should be carefully designed to have equal delays in each
path.
Circuits with Hazard:
Static hazard: a momentary output change when no
output change should occur
 If implemented in sum of products:
 no static 1-hazard -> no static 0-hazard or dynamic hazard
 Two examples for static 1-hazard:

Hazard Free Circuit

Hazard can be detected by inspecting the map
The change of input results in a change of covered product term Hazard exists
Ex: 111 ->101 in (a)
 To eliminate the hazard, enclose the two minterms in another product term
 Results in redundant gates

Remove Hazard with Latches

Implement the asynchronous circuit with SR latches can also remove static hazards
 A momentary 0 has no effects to the S and R inputs of a NOR latch
 A momentary 1 has no effects to the S and R inputs of a NAND latch
Essential Hazards
Besides static and dynamic hazards, another type of hazard in asynchronous circuits is called
essential hazard.
Caused by unequal delays along two or more paths that originate from the same input
Cannot be corrected by adding redundant gates
Can only be corrected by adjusting the amount of delay in the affected path
Design of Asynchronous Sequential Circuit:
Recommended Design Procedure:
1. State the design specifications
2. Derive a primitive flow table
3. Reduce the flow table by merging the rows
4. Make a race-free binary state assignment
5. Obtain the transition table and output map
6. Obtain the logic diagram using SR latches
Example:
Design a negative edge triggered T Flip flop.
Sol:
Two inputs. T(Toggle) and C(Clock). When T = 1, output toggles. Otherwise No change occurs at
the output.
One output. Q.
Primitive flow Table:
Input Output
State Comments
T C Q
a 1 1 0 Initial output is 0
b 1 0 1 After state a
c 1 1 1 Initial output is 1
d 1 0 0 After state c
e 0 0 0 After states d or f
f 0 1 0 After states e or a
g 0 0 1 After states b or h
h 0 1 1 After states g or c
Merging the Flow table Merger Diagram

Compatible pairs:
(a,f), (b,g), (b,h), (c,h), (d,e), (d,f), (e,f), (g,h)
Maximal Compatible Set:
(a,f), (b,g,h), (c,h), (d,e,f) -> state a,b,c,d.
Reduced Flow Table

State Assignment

Logic Diagram
Pulse mode Asynchronous Sequential Circuits:
In this circuits, the inputs are pulses. Here it is assumed that no two pulses will arrive at the same
time. Also it is assumed that the duration of the pulses is long enough to cause state transition and
is short enough so that there will not be more than one state transition for a single pulse.
Pulse mode:
The input variables are pulse instead of levels.
the width of the pulses is long enough for the circuit to respond to the input.
the pulse width must not be so long that it is still present after the new state is reached.
Note: The design procedure employed for fundamental mode circuits are also applicable for pulse
mode circuit.