Professional Documents
Culture Documents
Connectivity IPs
Vitis Tools
(Compiler, Analyzer, Debugger)
2 © Copyright 2022 Xilinx
For XUP teaching use only. Not for republication or redistribution.
Steps to Accelerate Applications with Vitis
Profile Applications and Identify Design Accelerated Kernels
1 2
Performance-critical Functions
Executable
Runtime
Accelerated
Libraries
Custom
Accelerators
Vision & Finance Data Analytics & Data Compression Data Security
Image Database
Common Libraries
https://github.com/Xilinx/Vitis_Libraries
5 © Copyright 2022 Xilinx
For XUP teaching use only. Not for republication or redistribution.
Develop in Familiar Programming Languages
User Application
Abstraction
Hardware Shell & • Performance-optimized Kernels, with
Library Primitives (L1) Configuration required interfaces and compiler
directives
• Basic algorithmic functions (HLS L1 L1
functions) for designing Kernels L2 • Customize, if needed, and build
L1 L1 accelerator image with Vitis tools
• Customize or Combine with other
Primitives and Kernels
• Initialization, Data Transfers managed
L3 Overlay via integration with Xilinx Runtime
• Requires compile and built and
Library (XRT)
compiled with Vitis tools
8 © Copyright 2022 Xilinx
For XUP teaching use only. Not for republication or redistribution.
Vitis Accelerated Libraries Structure
User can interact with the libraries at all three levels
L2
Comprehensive
Documentation & User Guide
Organized by Level of Abstraction
as Primitives (L1), Kernels (L2)
and Software APIs (L3)
Source Code
Performance Benchmarks
& Steps to Reproduce
L2 kernels typical work with DDR input, so they often have pointer interface.
DDR
Kernel
buffer
GCC/G++
Level 3 Level 1/2
XRT XCLBIN
Accelerated Design
SHELL
12 © Copyright 2022 Xilinx
For XUP teaching use only. Not for republication or redistribution.
Libraries Description
B B
Write Table
Write Table
Scan Table
Scan Table
Dyn-Filter
Dyn-Filter
Dyn-Evaluation
Dyn-Evaluation
A C A C
Aggregate
Aggregate
Hash Join
Hash Join
Library APIs can be called directly in your C, C++, and Python host
applications.
Multiple examples available
Heston Finite Difference
Monte Carlo Black Scholes American and European models
DataFrame (2020.2)
Dtore and load multiple types of fixed and variable data length
B
Write Table
Scan Table
Dyn-Filter
Write Table
Scan Table
Dyn-Filter
Dyn-Evaluation
A C
Dyn-Evaluation
Aggregate
A C
Hash Join
Aggregate
Hash Join
22 © Copyright 2022 Xilinx
For XUP teaching use only. Not for republication or redistribution.
Other Vitis Libraries
Sparse
DSP
Graph
Codec
HPC
The landing page of document and sub-repo top README usually answers
“what is in here”
The HTML doc provide for each level
API list: the brief doc on parameters and arguments
Design info: usually contains block diagram, resource/performance info
L3 Overlay API
28 L1 Primitive
© Copyright 2022 Xilinx
For XUP teaching use only. Not for republication or redistribution.
License