DE LAB ManualC-21 Final

Dr.B.R.
Ambedkar GMR Polytechnic for Women

(S.C), KARIMNAGAR
(Affiliated to SBTET, Hyderabad, TS & Approved by AICTE, New Delhi)
Department of Electronics & Communication Engineering
C-21
18EC-308P
Digital Electronics Lab Manual
Prepared by
MD ASIF ALI
MTech.
Lecturer in ECE
1
Index Page
( Max Marks: 10)
( Max Marks: 10)

Record Marks
Observation
S.No Name of the Experiment Page No.
Identify Digital ICs and noting down pin details from data sheets
a)Identify the given digital ICs and draw the pin diagrams. (Use TTL
and CMOS ICs of
1 AND, OR,NOT, NAND, NOR and XOR gates with two and three
inputs)
b)Realize basic gate functions using toggle switches and a bulb.
Verify the truth tables of basic gates using universal gates

a)Verify the truth table of 7403 IC (open collector quad 2input
NAND gate).
2
b)Verify the Truth table of 4073 IC.
a) Implement OR gate using NAND gates only and verify the Truth
Table
3 b) Implement NOT gate using using NOR gates only and verify the
Truth Table
a) Verify the truth table of AND gate using NOR gates only.
4
b) From the data sheets find out CMOS equivalent of above ICs
a). Verify the truth table of XOR using TTL NAND gates only.
5 b) Verify the truth table of XOR using CMOS NOR gates only
c) From the data sheets find out CMOS Equivalent of XOR ICs.
a) Implement a given Boolean function using basic gates and verify
the truth table.
6 b) Implement a given Boolean function using NAND gates only and
verify the truth table.
a) Verify the truth table of half adder using basic gates only.
7 b) Verify the truth table of half adder using NAND gates only.
.
a) Verify the truth table of full adder using 2 half adders.
8
b) Implement a full adder using NOR gates only.
a) Verify the truth table of IC 74153MUX.
9 b)Verify the truth table of IC 74154 DE-MUX.
a) Verify the function of 74148 Encoder and write the truth table
10 b)Verify the function of 74138 Decoder and write the truth table
11 a) Verify the to decimal decoder and write function of BCD its truth
table.
2
b) Verify the function of decimal BCD to encoder and write its truth
table.
a) Construct clocked RS FF using NAND gates and Verify its truth

table.
12
b) Verify the truth table of CD 4013 Dual D flip Flop
a) Verify the functionality and truth table of 74L71 RS flip flop with
13 Preset and Clear
b)Verify the Truth table of JK FF using 7476 IC
a) Construct and verify the function of decade counter using 7490
ICs.
14
b) Verify the function of up/down counter using 74190, 74193
a) Verify the function of CD 4029 up/down counter.

b) Verify the function of shift register (ICs like 7495or 74194 etc.)
15
c) Verify the function of Johnson counter using CD 4017 IC
3
EXPERIMENT: 1
IDENTIFY DIGITAL ICS AND NOTING DOWN PIN DETAILS FROM DATA SHEETS
A) IDENTIFY THE GIVEN DIGITAL ICS AND DRAW THE PIN DIAGRAMS
AIM: To identify the Digital Ics, Specifications and draw the pin diagrams of Logic Gates using
TTL Ics.
APPARATUS REQUIRED:
Power Supply, Digital Trainer Kit., Connecting Leads, IC’s (7400, 7402, 7404, 7408, 7432, and 7486)
THEORY:
AND Gate: The AND operation is defined as the output as (1) one if and only if all the inputs are (1)
one. 7408 is the two Inputs AND gate IC.A&B are the Input terminals &Y is the Output terminal.
Y = A.B
OR Gate: The OR operation is defined as the output as (1) one if one or more than 0 inputs are (1)
one. 7432 is the two Input OR gate IC. A&B are the input terminals & Y is the Output terminal.
Y=A+B
NOT GATE: The NOT gate is also known as Inverter. It has one input (A) & one output (Y). IC No.
is 7404. Its logical equation is,
Y = A NOT B, Y = A’
NAND GATE: The IC no. for NAND gate is 7400. The NOT-AND operation is known as NAND
operation. If all inputs are 1 then output produced is 0. NAND gate is inverted AND gate.
Y = (A. B)’
NOR GATE: The NOR gate has two or more input signals but only one output signal. IC 7402 is two
I/P IC. The NOT- OR operation is known as NOR operation. If all the inputs are 0 then the O/P is 1.
NOR gate is inverted OR gate.
Y = (A+B)’
EX-OR GATE: The EX-OR gate can have two or more inputs but produce one output. 7486 is two
inputs IC. When two inputs are not equal output goes high else low.
PIN DIAGRAMS
IC 7404 PIN Diagram
4
Description: 7404 IC is a HEX 1-Input NOT GATE and contains six independent gates each of which
performs the logic NOT function.
IC 7408 PIN Diagram
Description: 7408 IC is a QUAD 2-Input AND GATES and contains four independent gates each of
which performs the logic AND function.
IC 7432 PIN Diagram:
Description: OR gates are basic logic gates, and are available in TTL and CMOS ICs logic families. The
standard 4000 series CMOS IC is the 4071, which includes four independent two-input OR gates. The TTL
device is the 7432.
Features:
 Four 2-Input Logic OR Gates in a 14-Pin DIP Package.
 Outputs Directly Interface to CMOS, NMOS and TTL.
 Large Operating Voltage Range.
 Wide Operating Conditions.
 Not Recommended for New Designs Use 74LS32 or 74HC32.
5
Applications:
 IC 7432: It is a quad two input OR gate.
 All four OR gates may be used independently. On any gate if either of the input is 'High' then the
Output is 'High'.
Description: IC 7400, NAND gate. 7400 IC is the most widely used TTL (Transistor-Transistor
Logic) device in the world. It contains four independent two-input NAND gates. Its popularity is
based on the fact that any logic gate function can be created using only NAND gates.
Feature
 The first part number in the series, the 7400, is a 14-pin IC
 IC7400 containing four two-input NAND gates.
 Each gate uses two input pins and one output pin, with the remaining two pins being
power (+5 V) and ground.
Applications:
 IC 7400, NAND gate. 7400 IC is the most widely used TTL (Transistor-Transistor
Logic) device in the world.
 It contains four independent two-input NAND gates.
 Its popularity is based on the fact that any logic gate function can be created using only
NAND gates
6
Description: IC 7402, NOR gate. 7402 IC is the most widely used TTL (Transistor-Transistor
Logic) device in the world. It contains four independent two-input NOR gates. Its popularity is
based on the fact that any logic gate function can be created using only NOR gates.
Feature
 The first part number in the series, the 7402, is a 14-pin IC
 IC7402 containing four two-input NOR gates.
 Each gate uses two input pins and one output pin, with the remaining two pins being
power (+5 V) and ground.
Description: IC 7486: It is a quad two input Ex-OR gate. All four Exclusive-OR gates may be
used independently. On any gate when one input(Not Both) is 'High' then the Output is High.
Features:
 7486 Quad EXCLUSIVE-OR Gate Datasheet.
 Four 2-Input Exclusive OR Gates in a 14 Pin DIP Package.
 Outputs Directly Interface to CMOS, NMOS and TTL.
7
 Large Operating Voltage Range. Wide Operating Conditions. Not Recommended for New
Designs Use 74LS86 or 74HC86.
Applications:
 An XOR gate (sometimes referred to by its extended name, Exclusive OR gate) is a
digital logic gate with two or more inputs and one output that performs exclusive
disjunction. ... If both of an XOR gate's inputs are false, or if both of its inputs are true,
then the output of the XOR gate is false.
RESULT: Hence identified all digital IC’S pin diagrams
8
EXPERIMENT 1
B) REALIZE BASIC GATE FUNCTIONS USING TOGGLE SWITCHES AND A BULB
AIM: To realize basic gate functions using toggle switches and a bulb.
APPARATUS REQUIRED:
S.NO APPARATUS REQUIRED QUANTITY

1 Digital IC trainer kit 1
2 IC’S 7404,7408,7432 1
4 Bread board 1
5 Connecting wires As required
6 Bulb 1
7 Toggle switches 2
THEORY:
AND Gate: The AND operation is defined as the output as (1) one if and only if all the inputs are (1)
one. 7408 is the two Inputs AND gate IC.A&B are the Input terminals &Y is the Output terminal.
Y = A.B
OR Gate: The OR operation is defined as the output as (1) one if one or more than 0 inputs are (1)
one. 7432 is the two Input OR gate IC. A&B are the input terminals & Y is the Output terminal.
Y=A+B
NOT GATE: The NOT gate is also known as Inverter. It has one input (A) & one output (Y). IC No.
is 7404. Its logical equation is,
Y = A NOT B, Y = A’
Procedure:
OR GATE
• Initially connect the toggle switches in parallel with the help of connecting
wires.
• Connect one end of the wire to the battery and another end to the bulb.
• Check the output of the bulb.
• Compare the output of the bulb with functionality of the OR gate and verify
the truth table.
9
AND GATE
• Connect the toggle switches in series with each other.
• Connect one end of the wire to battery and another to bulb.
• Check the output of the bulb.
• Compare the output of the bulb with functionality of the AND gate and
verify the truth table
10
• NOT GATE
• Connect the battery in parallel with toggle switch by the help of connecting
wires and connect it to the bulb as output.
• Compare the output of the bulb with functionality of the NOT gate and
verify the truth table
RESULT: Hence realized basic gate functions using toggle switches and a bulb.
11
EXPERIMENT: 2
VERIFY THE TRUTH TABLES OF BASIC GATES USING UNIVERSAL GATES.
AIM: To implement basic logic gates using NAND and NOR gates and verify its truth tables.
APPARATUS REQUIRED:
1 Digital IC trainer kit 1 No
2 IC 7400 1No
3 IC 7402 1No
4 Bread board 1No
THEORY:
Logic gates are electronic circuits which perform logical functions on one or more inputs
to produce one output. There are seven logic gates. When all the input combinations of a logic
gate are written in a series and their corresponding outputs written along them, then this input/
output combination is called Truth Table. Various gates and their working is explained here.
AND Gate:
AND gate produces an output as 1, when all its inputs are 1; otherwise the output is 0. This
gate can have minimum 2 inputs but output is always one. Its output is 0 when any input is 0.
IC 7408
OR Gate:
OR gate produces an output as 1, when any or all its inputs are 1; otherwise the output is 0.
This gate can have minimum 2 inputs but output is always one. Its output is 0 when all input are 0.
12
IC 7432
NOT Gate:
NOT gate produces the complement of its input. This gate is also called an INVERTER. It
always has one input and one output. Its output is 0 when input is 1 and output is 1 when input is
0.
IC 7404
NAND Gate:
NAND gate is actually a series of AND gate with NOT gate. If we connect the output of
an AND gate to the input of a NOT gate, this combination will work as NOT-AND or NAND
gate. Its output is 1 when any or all inputs are 0, otherwise output is 1.
IC 7400
13
NOR Gate:
NOR gate is actually a series of OR gate with NOT gate. If we connect the output of an
OR gate to the input of a NOT gate, this combination will work as NOT-OR or NOR gate. Its
output is 0 when any or all inputs are 1, otherwise output is 1.
IC 7402
I. Implementation of logic gates using NAND gates:
i. NAND gates as NOT gate:
A NOT produces complement of the input. It can have only one input, tie the inputs of a
NAND gate together. Now it will work as a NOT gate. Its output is
Y = (A.A)’
Y = (A)’
ii. NAND gates as AND gate:
A NAND produces complement of AND gate. So, if the output of a NAND gate is
inverted, overall output will be that of an AND gate.
Y = ((A.B)’)’ = Y = (A.B)
iii. NAND gates as OR gate:

From DeMorgan’s theorems: (A.B)’ = A’ + B’
(A’.B’)’ = A’’ + B’’ = A + B
14
So, give the inverted inputs to a NAND gate, obtain OR operation at output. From DeMorgan’s
theorems: (A.B)’ = A’ + B’
(A’.B’)’ = A’’ + B’’ = A + B
So, give the inverted inputs to a NAND gate, obtain OR operation at output.
II. Implementation of logic gates using NOR gates:

i. NOR gates as NOT gate:
NOR gate together. Now it will work as a NOT gate. Its output is
Y = (A+A)’
Y = (A)’
ii. NOR gates as OR gate:

A NOR produces complement of OR gate. So, if the output of a NOR gate is inverted,
overall output will be that of an OR gate.
Y = ((A+B)’)’
Y = (A+B)
iii .NOR gates as AND gate:

From DeMorgan’s theorems: (A+B)’ = A’B’
(A’+B’)’ = A’’B’’ = AB
So, give the inverted inputs to a NOR gate, obtain AND operation at output.
15
PROCEDURE:
1. Connect the trainer kit to power supply.
2. Connect the inputs to the logic switches and its output to the logic indicator.
3. Apply various input combinations and observe output for each one.
4. Verify the truth table for each input/ output combination.
5. Repeat the process for all other logic gates.
6. Switch off the power supply.
.
OBSERVATIO N TABLE:
INP UTS OUTP UTS

A’ A+B (A+B)’ (A *B) (A*B )’ (A B)
A B
NOT OR NOR A ND NAND Ex-OR
0 0 1 0 1 0 1 0
0 1 1 1 0 0 1 1
1 0 0 1 0 0 1 1
1 1 0 1 0 1 0 0
PRECAUTIONS:
1. Make the connection s according to the IC pin diagram.

2. The connections should be tight.
3. The Vcc and ground should be applied carefully at the specified pin only.
RESULT: We have implemented all the gates using universal gates
16
2A) VERIFY THE TRUTH TABLE OF 7403 IC (OPEN COLLECTOR QUAD 2INPUT
NAND GATE).
AIM: To Verify the Truth Table of 7403 IC (Open Collector Quad 2input NAND Gate).
APPARATUS REQUIRED

2 IC 7403 1No
4 Bread board 1No
THEORY :
NAND GATE: The IC no. for NAND gate is 7400. The NOT-AND operation is known as
NAND operation. If all inputs are 1 then output produced is 0. NAND gate is inverted AND
gate.
Y = (A. B)’
Ic 7403 is an open collector NAND gate.
PIN DIAGRAM:
TRUTH TABLE:
Inputs output
A B C
0 0 1
0 1 1
1 0 1
1 1 0
INTERNAL DIAGRAM:
17
PROCEDURE:
PRECAUTIONS
3. The Vcc and ground should be applied carefully at the specified
pin only.
RESULT: Thus we have verified the Truth Table of 7403 IC (Open Collector Quad 2input NAND
Gate).
2B) VERIFY THE TRUTH TABLE OF 4073 IC

18
AIM: To Verify the Truth Table of 4073
APPARATUS REQUIRED:

2 IC 4073 1No
4 Bread board 1No
THEORY:
3-input AND Gate: The AND operation is defined as the output as (1) one if and only if all the
inputs are (1) one.
4073 is the three Input AND gate IC. Let A,B & C are the Input terminals &Y is the Output
terminal.
Y = A.B.C
Logic Diagram Pin Diagram
TRUTH TABLE:
Inputs Output
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
PROCEDURE:
19
1) Connect the trainer kit to power supply.
2) Connect the inputs to the logic switches and its output to the logic indicator.
3) Apply various input combinations and observe output for each one.
4) Verify the truth table for each input/ output combination.
5) Switch off the power supply.
PRECAUTIONS
1) Make the connection s according to the IC pin diagram.
2) The connections should be tight.
3) The Vcc and ground should be applied carefully at the specified pin
only.
RESULT: Thus we have verified the Truth Table of 4073 IC (Quad 3 input AND Gate).
EXPERIMENT 3
20
A) IMPLEMENT OR GATE USING NAND GATES ONLY AND VERIFY THE TRUTH
TABLE
AIM: To implement OR gate using NAND gates only and verify the truth table
APPARATUS REQUIRED:

2 IC 7400 1No
4 Bread board 1No
THEORY:
OR Gate:
OR gate produces an output as 1, when any or all its inputs are 1; otherwise the output is 0.
This gate can have minimum 2 inputs but output is always one. Its output is 0 when all input are 0.
NAND gates as OR gate:
From DeMorgan’s theorems: (A.B)’ = A’ + B’
(A’.B’)’ = A’’ + B’’ = A + B
So, give the inverted inputs to a NAND gate, obtain OR operation at output. From DeMorgan’s
theorems: (A.B)’ = A’ + B’
(A’.B’)’ = A’’ + B’’ = A + B
So, give the inverted inputs to a NAND gate, obtain OR operation at output.
LOGIC CIRCUIT:
TRUTH TABLE:
21
A B C
0 0 0
0 1 1
1 0 1
1 1 1
PROCEDURE:
PRECAUTIONS
RESULT:
Hence implemented OR gate using NAND gates only and verified the truth table
22
EXPERIMENT 3
B) IMPLEMENT NOT GATE USING NOR GATES ONLY AND VERIFY THE TRUTH
TABLE
AIM: To implement NOT gate using NOR gates only and verify the truth table
APPARATUS REQUIRED:

2 IC 7402 1No
4 Bread board 1No
THEORY:
NOT Gate:
NOT gate produces the complement of its input. This gate is also called an INVERTER. It
always has one input and one output. Its output is 0 when input is 1 and output is 1 when input is
0.
NOR gate as NOT gate:
NOR gate together. Now it will work as a NOT gate. Its output is
Y = (A+A)’
Y = (A)’
LOGIC CIRCUIT:
TRUTH TABLE:
INPUT OUTPUT
A A’
0 1
1 0
23
PROCEDURE:
PRECAUTIONS

RESULT:
Hence implemented NOT gate using NOR gates only and verified the truth table
EXPERIMENT 4
24
A) VERIFY THE TRUTH TABLE OF AND GATE USING NOR GATES ONLY
AIM: To implement AND gate using NOR gates only and verify the truth table
APPARATUS REQUIRED:

2 IC 7402 1No
4 Bread board 1No
THEORY:
AND Gate:
NOR gates as AND gate:
From DeMorgan’s theorems: (A+B)’ = A’B’
(A’+B’)’ = A’’B’’ = AB
So, give the inverted inputs to a NOR gate, obtain AND operation at output.
LOGIC CIRCUIT:
TRUTH TABLE
A B C
0 0 0
0 1 0
1 0 0
1 1 1
PROCEDURE:
25
PRECAUTIONS

RESULT:
Hence implemented AND gate using NOR gates only and verified the truth table.
EXPERIMENT 4
B) FROM THE DATA SHEETS FIND OUT CMOS EQUIVALENT OF ABOVE
(NAND, NOR) IC’S
26
AIM: To find out CMOS equivalent of NAND, NOR IC’s
APPARATUS REQUIRED:

1 Data sheet 1 No
2 IC 4001,4011 1No
Theory:
An AND gate performs logical multiplication, more commonly known as the AND
function. It has two and the output or more inputs and one output. The standard
logic symbol for a AND gate with two inputs A and B, Y is the output. The Boolean
expression for AND function is Y=A *B.
Circuit Diagram:
Truth table:
Inputs Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
PIN DIAGRAM OF 4001(2 INPUT NAND

27
RESULT: Hence found out the CMOS equivalent of NAND, NOR IC’s
EXPERIMENT 5
A) VERIFY THE TRUTH TABLE OF XOR USING TTL NAND GATES ONLY.
AIM: To verify the truth table of XOR using TTL NAND gates only.
28
APPARATUS REQUIRED:

2 IC 7400 1No
4 Bread board 1No
THEORY:
The NAND and NOR gates are universal gates. In practice, this is advantageous since
NAND and NOR gates are economical and easier to fabricate and are the basic gates used in all
IC digital logic families.
EX-OR GATE:
Exclusive disjunction essentially means 'either one, but not both or none'. In other words,
the statement is true if and only if one is true and the other is false.
Output equation is given by AB’+A’B
NAND gates as X-OR gate:
The output of a 2 input X-OR gate is shown by: Y = A’B + AB’.
Four NAND gates are required to built an EX-OR gate
LOGIC CIRCUIT:
EX-OR EQUATION REDUCTION:

Gate No. Inputs Output
1 A, B (AB)’
2 A, (AB)’ (A (AB)’)’
29
3 (AB)’, B (B (AB)’)’
4 (A (AB)’)’, (B (AB)’)’ A’B + AB’
Now the ouput from gate no. 4 is the overall output of the configuration.
Y = ((A (AB)’)’ (B (AB)’)’)’
= (A(AB)’)’’ + (B(AB)’)’’
= (A(AB)’) + (B(AB)’)
= (A(A’ + B)’) + (B(A’ + B’))
= (AA’ + AB’) + (BA’ + BB’)
= ( 0 + AB’ + BA’ + 0 )
= AB’ + BA’
=> Y = AB’ + A’B
TRUTH TABLE:
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
PROCEDURE:
RESULT:
Hence implemented EX-OR gate using NAND gates only and verified the truth table.
EXPERIMENT 5
B) VERIFY THE TRUTH TABLE OF XOR USING CMOS NOR GATES ONLY.
AIM: To Verify the truth table of XOR using CMOS NOR gates only.
30
APPARATUS REQUIRED:

2 IC 4001 2 No
4 Bread board 1No
THEORY:
The NAND and NOR gates are universal gates. In practice, this is advantageous since
NAND and NOR gates are economical and easier to fabricate and are the basic gates used in all
IC digital logic families.
EX-OR GATE:
Exclusive disjunction essentially means 'either one, but not both or none'. In other words,
the statement is true if and only if one is true and the other is false.
Output equation is given by AB’+A’B
NOR gates as X-OR gate:
The output of a 2 input X-OR gate is shown by: Y = A’B + AB’.
Five NOR gates are required to built an EX-OR gate
LOGIC CIRCUIT:
Gate No. Inputs Output

1 A, B (A + B)’
2 A, (A + B)’ (A + (A+B)’)’
3 (A + B)’, B (B + (A+B)’)’
31
4 (A + (A + B)’)’, (B + (A+B)’)’ AB + A’B’
5 ((AB + A’B’))’ AB’+A’B
Now the ouput from gate no. 5 is the overall output of the configuration.
Y = ((A + (A+B)’)’ (B +( A+B)’)’)’
= (A+(A+B)’)’’.(B+(A+B)’)’’
= (A+(A+B)’).(B+(A+B)’)
= (A+A’B’).(B+A’B’)
= (A + A’).(A + B’).(B+A’)(B+B’)
= 1.(A+B’).(B+A’).1
= (A+B’).(B+A’)
= A.(B + A’) +B’.(B+A’)
= AB + AA’ +B’B+B’A’
= AB + 0 + 0 + B’A’
= AB + B’A’
= (( AB + A’B’))’
Y = AB’+A’B
TRUTH TABLE:
Inputs Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
PROCEDURE:
2. Connect the circuit as per logic diagram/circuit.
RESULT:
Hence implemented EX-OR gate using CMOS NOR gates only and verified the truth table.
5c) From the data sheets find out CMOS Equivalent of XOR ICs.
Aim: To find out CMOS Equivalent of XOR IC ’ s.
Theory: XOR gate is used extensively in error detection circuits,
computational logic comparators and arithmetic logic circuits. The Exclusive
OR gate gives an output only if its two inputs are dissimilar, namely if one of them
is high (one) and the other is low (zero).
32
Circuit Diagram:
Truth table:
Result: The CMOS Equivalent of XOR IC ’s is found
EXPERIMENT 6
A) IMPLEMENT A GIVEN BOOLEAN FUNCTION USING BASIC GATES AND
VERIFY THE TRUTH TABLE.
33
AIM: To implement a given Boolean function F= (A+B)*(A+B’) using basic gates and verify the
Truth table.
APPARATUS REQUIRED:

2 IC 7404,7432,7408 1No
3 Bread board 1No
THEORY:
Logic gates implementation or logic representation of Boolean functions is very simple
and easy form. The implementation of Boolean functions by using logic gates involves in
connecting one logic gate's output to another gate's input and involves in using NOT,AND,
OR, NAND and NOR gates
LOGIC DIAGRAM:
Truth Table
A B B’ A+B A+B’ F
0 0 1 0 1 0
0 1 0 1 0 1
1 0 1 1 1 1
1 1 0 1 1 1
34
PROCEDURE:
RESULT:
Hence we have implemented an equation using basic gates and verified the truth table.
EXPERIMENT 6
B) IMPLEMENT A GIVEN BOOLEAN FUNCTION USING NAND GATES ONLY
AND VERIFY THE TRUTH TABLE.
35
AIM: To implement a given 3-variable logic function using two input NAND gate
Q= AB+A’B’
APPARATUS REQUIRED:

2 IC 7400 1No
3 Bread board 1No
THEORY:
•The most basic operation, is the addition of two binary digits

•The simple addition consists of four possible elementary operations, namely,
0 + 0 =0
0 + 1 =1
1 + 0 =1
1 + 1 = 102
• The first three operations produce a sum whose length
is one digit, but when the last operation is performed
sum is two digits. The higher significant bit of this
result is called a carry, and lower significant bit is
called sum.
• The logic circuit which performs this operation is
called a halfadder.
• The half adder operation needs two binary inputs
and add end bits; and two binary outputs: sum and
carry.
• In multi digit addition we have to add two bits, along
with the carry of previous digit addition. Effectively
such addition requires addition of three bits. This is
not possible with half adder. Hence half adders are not
used in practice.
• The circuit which performs addition of three bits (two
significant bits and a previous carry) is a full adder.
Circuit Diagram:
36
Truth Table:
PROCEDURE:
RESULT: Boolean function using NAND gates is implemented and the truth table is
verified.
EXPERIMENT 7
37
A) VERIFY THE TRUTH TABLE OF HALF ADDER USING BASIC GATES ONLY.
AIM: To Design &Verify Operation of Half Adder using basic gates only.
APPARATUS REQUIRED:

2 IC 7486 1No
3 IC 7408 1No
4 Bread board 1 No
BRIEF THEORY:
EX-OR GATE: The EX-OR gate can have two or more inputs but produce one output. 7486
is two inputs IC. EX-OR gate is not a basic operation & can be performed using basic gates.
Y=A B
AND Gate:
C=A.B
HALF ADDER: It is a logic circuit that adds two bits. It produces the O/P, sum & carry.
The Boolean equation for sum & carry are:
SUM = A + B
CARRY = A. B
Therefore, sum produces 1 when A&B are different and carry is 1when A&B are 1.
Application of Half adder is limited.
LOGIC DAIGRAM:
Half Adder
TRUTH TABLE:
38
HALF ADDER:
INPUTS OUTPUT
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
PROCEDURE:
2. Connect the circuit as per logic diagram /circuit.
RESULT:
Hence we have verified Operation of Half Adder using basic gates only.
EXPERIMENT 7
39
B) VERIFY THE TRUTH TABLE OF HALF ADDER USING NAND GATES ONLY.
AIM: To verify the truth table of half adder using NAND gates only.
APPARATUS REQUIRED:

2 IC 7400 1No
3 Bread board 1 No
THEORY:
HALF ADDER: It is a logic circuit that adds two bits. It produces the O/P, sum & carry.
The Boolean equation for sum & carry are:
SUM = A + B
CARRY = A. B
Therefore, sum produces 1 when A&B are different and carry is 1when A&B are 1.
Application of Half adder is limited.
It can be implemented using universal gates (NAND, NOR) also.
BLOCK DIAGRAM:
LOGIC CIRCUIT:
TRUTH TABLE:
40
HALF ADDER:
INPUTS OUTPUT
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
PROCEDURE:
RESULT:
Hence we have verified Operation of Half Adder using NAND only.
EXPERIMENT 8
41
A) VERIFY THE TRUTH TABLE OF FULL ADDER USING 2 HALF ADDERS.
AIM: To verify the truth table of full adder using 2 half adders.
APPARATUS REQUIRED:

2 IC 7486,7408,7432 1No
3 Bread board 1 No
THEORY:
Full Adder is the adder which adds three inputs and produces two outputs. The first
two inputs are A and B and the third input is an input carry as C-IN. The output carry is
designated as C-OUT and the normal output is designated as S which is SUM.
A full adder logic is designed in such a manner that can take eight inputs together to create
a byte-wide adder and cascade the carry bit from one adder to the another.
BLOCK DIAGRAM:
LOGIC CIRCUIT:
TRUTH TABLE:
INPUTS OUTPUTS
42
A B C S CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
PROCEDURE:
RESULT:
Hence verified the truth table of full adder using 2 half adders.
EXPERIMENT 8
B) IMPLEMENT A FULL ADDER USING NOR GATES ONLY.
43
AIM: To verify the truth table of full adder using NOR gates only
APPARATUS REQUIRED:

2 IC 7402 3No
3 Bread board 1 No
THEORY:
Full Adder is the adder which adds three inputs and produces two outputs. The first
two inputs are A and B and the third input is an input carry as C-IN. The output carry is
designated as C-OUT and the normal output is designated as S which is SUM.
A full adder logic is designed in such a manner that can take eight inputs together to create
a byte-wide adder and cascade the carry bit from one adder to the another.
LOGIC DIAGRAM:
Circuit diagram:
TRUTH TABLE:
INPUTS OUTPUTS
A B C S CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
44
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
PROCEDURE:
RESULT:
Hence verified the truth table of full adder using NOR gates only.
EXPERIMENT 9
A) VERIFY THE TRUTH TABLE OF IC 74153MUX.
AIM: Verify the truth table and function of multiplexer using 74153.
APPARATUS REQUIRED:

2 IC 74153 1No
3 Bread board 1No
THEORY:
MULTIPLEXER:
Multiplexer generally means many into one. A multiplexer is a circuit with many Inputs
but only one output. By applying control signals we can steer any input to the output .The fig. (1)
Shows the general idea. The circuit has n-input signal, control signal & one output signal. Where
2n = m. One of the popular multiplexer is the 16 to 1 multiplexer, which has 16 input bits, 4
control bits & 1 output bit.
IC 74153 (4x1 multiplexer):
The truth table of a 4-to-1 multiplexer is shown below in which four input combinations
00, 10, 01 and 11 on the select lines respectively switches the inputs D0, D2, D1 and D3 to the
output. That means when S1=0 and S0 =0, the output at Y is D0, similarly Y is D1 if the select
inputs S1=0 and S0= 1 and so on.
PIN CONFIGURATION
45
IC 74153 (4x1 multiplexer)
LOGIC DIAGRAM:
Multiplexer (4x1) IC 74153
PROCEDURE:
1. Fix the IC's on the bread board &give the input supply.
2. Make connection according to the circuit.
3. Give select signal and strobe signal at respective pins.
4. Connect +5 v Vcc supply at pin no 16 & GND at pin no 8.
5. Verify the truth table for various inputs.
OBSERVATION TABLE:
46
Truth Table of multiplexer (4x1) IC 74153
Channel - A Channel - A
Inputs Select O/P Inputs Select O/P
lines lines
Ea Ioa I1a I2a I3a S1 S2 Za(v) Ea Ioa I1a I2a I3a S1 S2
1       0 1      
0 0    0 0 0 0 0    0 0
0 1    0 0 1 0 1    0 0
0  0  0 0 1 0 0  0  0 0 1
0  1  1 0 1 1 0  1  1 0 1
0   0  1 0 0 0   0  1 0
0   1  1 0 1 0   1  1 0
0    0 1 1 0 0    0 1 1
0    1 1 1 1 0    1 1 1
8:1 MUX
PRECAUTIONS:
a. Make the connections according to the IC pin diagram.
The connections should be tight.
b. The Vcc and ground should be applied carefully at the specified pin only.
RESULT: Verified the truth table of 4:1multiplexer using IC 74153
47
EXPERIMENT 9
B) VERIFY THE TRUTH TABLE OF IC 74154 DE-MUX.
AIM: To Design & Verify the Operation of DE-MULTIPLEXER

APPARATUS REQUIRED:
48
2 IC 74154 1No
3 Bread board 1No
THEORY:
A demultiplexer (or demux) is a device that takes a single input line and routes it to
one of several digital output lines. A demultiplexer of 2n outputs has n select lines, which
are used to select which output line to send the input.
PIN DIAGRAM:
(a)Circuit diagram:
49
TRUTH TABLE:
CHANNEL-A
Inputs Outputs
Ea Sla S0a Y1a Y2a Y3a Y4a
1   1 1 1 1
0 0 0 0 1 1 1
0 0 0 1 0 1 1
0 1 1 1 1 0 1
0 1 1 1 1 1 0
(c)Observations
50
CHANNEL-A
Inputs Outputs
Ea Sla S0a Y1a Y2a Y3a Y4a
1   1 1 1 1
0 0 0 0 1 1 1
0 0 0 1 0 1 1
0 1 1 1 1 0 1
0 1 1 1 1 1 0
PROCEDURE:
2. Connect the connections as per logic circuits.
RESULT:
Hence we have verifed the function of de-multiplexer
EXPERIMENT 10
51
A) VERIFY THE FUNCTION OF 74148 ENCODER AND WRITE THE TRUTH
TABLE
AIM: To Implement and Verification of Encoder using IC 74148
APPARATUS REQUIRED:

2 IC 74148 1No
3 Bread board 1No
THEORY:
Unlike a multiplexer that selects one individual data input line and then sends that data to a
single output line or switch, Digital Encoder more commonly called a Binary Encoder takes
ALL its data inputs one at a time and then converts them into a single encoded output. So we can
say that a binary encoder, is a multi-input combinational logic circuit that converts the logic level
“1” data at its inputs into an equivalent binary code at its output.
Features:
 For Encoding 8 Data Lines to 3-Line Binary

 Applications Include n-bit Encoding and Code Converters
 Units Can be Cascaded for Larger Encoding Applications
 Standard TTL Voltages
 Superseded, Not Recommended for New Designs
52
TRUTH TABLE:
PROCEDURE:
PRECAUTIONS
pin only.
RESULT: Thus we have implemented 8*3 ENCODER and observed the truth table
EXPERIMENT 10
53
b) VERIFY THE FUNCTION OF 3 TO 8 DECODER (IC 74138)
AIM: To Implement and Verify the function of 3x8 Decoder.
APPARATUS REQUIRED:

2 IC 74138 1No
3 Bread board 1No
THEORY:
DECODER: A decoder is a device which does the reverse operation of an encoder, undoing the
encoding so that the original information can be retrieved. The same method used to encode is
usually just reversed in order to decode. It is a combinational circuit that converts binary
information from n input lines to a maximum of 2 n unique output lines. In digital electronics, a
decoder can take the form of a multiple- input, multiple-output logic circuit that converts coded
inputs into coded outputs, where the input and output codes are different. e.g. n-to-2 n , binary-
coded decimal decoders. Enable inputs must be on for the decoder to function, otherwise its
outputs assume a single "disabled" output code word. In case of decoding all combinations of
three bits eight (23=8) decoding gates are required. This type of decoder is called 3-8 decoder
because 3 inputs and 8 outputs. For any input combination decoder outputs are 1.
BLOCK DIAGRAM:
PIN DIAGRAM:
54
Circuit Diagram:
PROCEDURE:
1) Connect the circuit as shown in figure.
2) Apply Vcc & ground signal to every IC.
3) Observe the input & output according to the truth table.
OBSERVATION TABLE:
Truth table for Decoder
PRECAUTIONS:
55
1) Make the connections according to the IC pin diagram.
The connections should be tight.
2) The Vcc and ground should be applied carefully at the specified pin only.
RESULT: Thus We implemented the decoder using ic 74138and verified its truth table.
EXPERIMENT 11
56
A) VERIFY THE DECIMAL DECODER AND WRITE FUNCTION OF BCD WITH ITS
TRUTH TABLE.
AIM: To verify the decimal decoder and write function of BCD with its truth table.
APPARATUS REQUIRED:

2 IC 7447 1No
3 Bread board 1No
THEORY:
DECODER: A decoder is a device which does the reverse operation of an encoder, undoing
the encoding so that the original information can be retrieved. The same method used to encode
is usually just reversed in order to decode. It is a combinational circuit that converts binary
information from n input lines to a maximum of 2 n unique output lines. In digital electronics, a
decoder can take the form of a multiple- input, multiple-output logic circuit that converts coded
inputs into coded outputs, where the input and output codes are different. e.g. n-to-2 n , binary-
coded decimal decoders. Enable inputs must be on for the decoder to function, otherwise its
outputs assume a single "disabled" output code word. In case of decoding all combinations of
three bits eight (23=8) decoding gates are required. This type of decoder is called 3-8 decoder
because 3 inputs and 8 outputs. For any input combination decoder outputs are 1.
PIN DIAGRAM:
LOGIC CIRCUIT:
57
Circuit Diagram:
TRUTH TABLE:
58
PROCEDURE:
RESULT: Thus we have implemented BCD TO decimal decoder with its truth table
59
EXPERIMENT 11
B) VERIFY THE FUNCTION OF DECIMAL TO BCD ENCODER AND WRITE ITS
TRUTH TABLE.
AIM: To Verify the function of decimal TO BCD encoder and write its truth table.
APPARATUS REQUIRED:

2 IC 74147 1No
3 Bread board 1No
THEORY: Decimal-to-BCD encoder is a digital circuit that has 10 input lines and 4
output lines. The inputs represent the 10 decimal numbers from 0 to 9, where only one
input can be active. The outputs indicate the BCD code that represents the active input.
BLOCK DIAGRAM:
LOGIC SYMBOL:
60
IC DIAGRAM:
Circuit Diagram:
TRUTH TABLE:
PROCEDURE:
61
PRECAUTIONS
pin only.
RESULT: Thus we have implemented the function of decimal TO BCD encoder.
62
EXPERIMENT 12
A) CONSTRUCT CLOCKED RS FF USING NAND GATES AND VERIFY ITS TRUTH
TABLE.
AIM: To construct clocked RS ff using NAND gates and verify its truth table.
APPARATUS REQUIRED:

2 IC 7400 1No
3 Bread board 1No
THEORY:
The RS Flip Flop is considered as one of the most basic sequential logic circuits. The Flip
Flop is a one-bit memory bi-stable device. It has two inputs, one is called “SET” which will set
the device (output = 1) and is labeled S and another is known as “RESET” which will reset the
device (output = 0) labeled as R. The RS stands for SET/RESET.
The flip-flop is reset back to its original state with the help of RESET input and the output
is Q that will be either at logic level “1” or logic”0”. It depends upon the set/reset condition of the
flip-flop. Flip flop word means that it can be “FLIPPED” into one logic state
or “FLOPPED” back into another.
The basic NAND gate RS Flip Flop circuit is used to store the data and thus provides
feedback from both of its outputs again back to its inputs. The RS Flip Flop actually has three
inputs, SET, RESET and its current output Q relating to its current state.
CIRCUIT DIAGRAM:
RS FLIP-FLOP
63
TRUTH TABLE:
Qn Qn’ R S Qn+1 Qn+1’
0 1 0 0 0 1
1 0 0 0 1 0
0 1 0 1 1 0
1 0 0 1 1 0
0 1 1 0 0 1
1 0 1 0 0 1
0 1 1 1 X X
1 0 1 1 X X
PROCEDURE:
PRECAUTIONS
pin only.
RESULT: Thus we have constructed clocked RS ff using NAND gates and verify its
truth table.
64
EXPERIMENT 12
B) VERIFY THE TRUTH TABLE OF CD 4013 DUAL D FLIP FLOP
AIM: To verify the truth table of CD 4013 Dual D flip Flop
APPARATUS REQUIRED:

2 IC 4013 1No
3 Bread board 1No
THEORY: The D flip-flop tracks the input, making transitions with match those of the input D.
The D stands for "data"; this flip-flop stores the value that is on the data line. It can be thought of
as a basic memory cell. A D flip-flop can be made from a set/reset flip-flop by tying the set to the
reset through an inverter.
BLOCK DIAGRAM:
INTERNAL PIN DIAGRAM:
65
TRUTH TABLE:
PROCEDURE:
PRECAUTIONS
pin only.
RESULT: Thus we have verified the truth table of CD 4013 Dual D flip Flop
66
EXPERIMENT 13
A) VERIFY THE FUNCTIONALITY AND TRUTH TABLE OF 74L71 RS FLIP FLOP
WITH PRESET AND CLEAR
AIM: To verify the functionality and truth table of 7471 RS flip flop with Preset and Clear
APPARATUS REQUIRED:

2 IC 74H71 1No
3 Bread board 1No
THEORY:
The RS Flip Flop is considered as one of the most basic sequential logic circuits. The Flip
Flop is a one-bit memory bi-stable device. It has two inputs, one is called “SET” which will set
the device (output = 1) and is labeled S and another is known as “RESET” which will reset the
device (output = 0) labeled as R. The RS stands for SET/RESET.
The flip-flop is reset back to its original state with the help of RESET input and the output
is Q that will be either at logic level “1” or logic”0”. It depends upon the set/reset condition of the
flip-flop. Flip flop word means that it can be “FLIPPED” into one logic state
or “FLOPPED” back into another.
The basic NAND gate RS Flip Flop circuit is used to store the data and thus provides
feedback from both of its outputs again back to its inputs. The RS Flip Flop actually has three
inputs, SET, RESET and its current output Q relating to its current state.
PIN DIAGRAM:
67
TRUTH TABLE:
PROCEDURE:
2. Connect the connections as per Pin diagram.
5. Switch off the power supply
RESULT: Thus we have verified the truth table of 74L71 RS flip flop with Preset and Clear.
68
EXPERIMENT 13
B) VERIFY THE TRUTH TABLE OF JK FF USING 7476 IC.
AIM: To verify the Truth table of JK FF using 7476 IC
APPARATUS REQUIRED:

2 IC 7476 1No
3 Bread board 1No
THEORY:
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input
circuitry that prevents the illegal or invalid output condition that can occur when both inputs S
and R are equal to logic level “1”.
The JK flip-flop augments the behavior of the SR flip-flop (J: Set, K: Reset) by
interpreting the J = K = 1 condition as a "flip" or toggle command. Specifically, the combination J
= 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset
the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its
output to the logical complement of its current value. Setting J = K = 0 maintains the current state.
To synthesize a D flip-flop, simply set K equal to the complement of J (input J will act as input
D). Similarly, to synthesize a T flip-flop, set K equal to J. The JK flip-flop is therefore a universal
flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop.
PIN DIAGARM:
69
INTERNAL PIN DIAGRAM:
BLOCK DIAGRAM OF JK FILP FLOP:
TRUTH TABLE:
70
JK TRUTH TABLE:
PROCEDURE:

2. Connect the connections as per Pin diagram.
PRECAUTIONS
pin only.
RESULT: Thus we have verified the truth table of JK FF using 7476 IC
71
EXPERIMENT 14
A) CONSTRUCT AND VERIFY THE FUNCTION OF DECADE COUNTER USING
7490 IC.
AIM: To construct & verify the function of decade counter using IC 7490.
APPARATUS REQUIRED:

2 IC 7490 1No
3 Bread board 1No
THEORY:
A decade counter is one that counts in decimal digits, rather than binary. A decade
counter may have each (that is, it may count in binary-coded decimal, as the 7490 integrated
circuit did) or other binary encodings. "A decade counter is a binary counter that is designed
to count to 1010 (decimal 10).
A binary coded decimal (BCD) is a serial digital counter that counts ten digits .And it
resets for every new clock input. As it can go through 10 unique combinations of output, it is also
called as “Decade counter”. A BCD counter can count 0000, 0001, 0010, 1000, 1001, 1010, 1011,
1110, 1111, 0000, and 0001 and so on.
A 4 bit binary counter will act as decade counter by skipping any six outputs out of the
16 (24) outputs. There are some available ICs for decade counters which we can readily use in
our circuit, like 74LS90. It is an asynchronous decade counter.
BLOCK DIAGRAM:
72
PIN DIAGRAM OF 74LS90
DECADE COUNTER OPERATION:
When the Decade counter is at REST, the count is equal to 0000. This is first stage of the
counter cycle. When we connect a clock signal input to the counter circuit, then the circuit will
count the binary sequence. The first clock pulse can make the circuit to count up to 9 (1001). The
next clock pulse advances to count 10 (1010).
Then the ports X1 and X3 will be high. As we know that for high inputs, the NAND gate
output will be low. The NAND gate output is connected to clear input, so it resets all the flip flop
stages in decade counter. This means the pulse after count 9 will again start the count from count
0.
TRUTH TABLE:
The above table describes the counting operation of Decade counter. It represents the
count of circuit for decimal count of input pulses. The NAND gate output is zero when the count
73
reaches 10 (1010) .After counts 10, the logic gate NAND will trigger its output from 1 to 0, and it
resets all flip flops.
EXPLANATION:
It is a simple counter which can count from 0 – 9. As it is a 4 bit binary decade counter, it
has 4 output ports QA, QB, QC and QD. When the count reaches 10, the binary output is reset to 0
(0000), every time and another pulse starts at pin number 9. The Mod of the IC 7490 is set by
changing the RESET pins R1, R2, R3, R4.
If any one of R1 & R2 is at high or R3 & R4 are at ground, the counter will reset all the outputs
QA, QB, QC and QD to 0. If the pins R3 & R4 are high, then the count on QA, QB, QC and QD is
1001.
TIMING DIAGRAM OF MOD10:
CLK
0 0 0 1 0 1 0 0
1 1 1
QA
0 0 0 0 0 0 0
1 1 1 1
QB
0 0 0 0 1 1 0 0 0
QC 1 1
0 0 0 0 0 0 0 0 0
1 1
QD
PROCEDURE:
2. Connect the connections as per logic circuits
RESULT:
Thus, we implemented decade counter,Using IC7490.
74
EXPERIMENT 14
B) VERIFY THE FUNCTION OF UP/DOWN COUNTER USING 74190/74193
AIM: To verify the function of up/down counter using 74190/74193
APPARATUS REQUIRED:

2 IC 74190/74193 1No
3 Bread board 1No
THEORY:
Counters: counters are logical device or registers capable of counting the no of states or no
of clock pulse arriving at its clock input where clock is a timing parameter arriving at regular
intervals of time, so counters can be also used to measure time & frequencies. They are made up
of flip flops. Where the pulse are counted to be made of it goes up step by step & the o/p of
counter in the flip flop is decoded to read the count to its starting step after counting n pulse
incase of module & counters.
 Synchronous Counter:
In this counter, all the flip flops receive the external clock pulse simultaneously.
Ex:- Ring counter & Johnson counter
The gates propagation delay at reset time will not be present or we may
say will not occur.
 Classification of synchronous counter:
Depending on the way in which counting processes, the synchronous
counter is classified is :-
1) Up counter.
2) Down counter.
3) Up down counter.
 Up Counter:
The up counter counts binary form 0 to7 i.e.(000 to 111).It counts from small to
large number. It’s O/P goes on increasing as they receive clock pulse
 Down Counter:
This down counter counts binary from 7-0 i.e.(111-000).It counts from large to
small number. Its O/P goes on increasing as they receive clock pulse
75
PIN DIAGRAMS:
INTERNAL DIAGRAM:
TRUTH TABLE:
PROCEDURE:
76
RESULT: Up and down counters are successfully implemented, the counters are studied & o/p
are checked. The truth table is verified.
Enhancements/modifications:
As the design part is done for the 3 bit Counter, we can implement the same for 4 bit counter.
FAQ’s with answers:

 What do you mean by Counter?
A Counter is a register capable of counting the no. of clock pulses arriving at its
clock inputs. Count represents the no. of clock pulses arrived. A specified sequence
of states appears as the counter output.
 What are the types of Counters? Explain each.
There are two types of counters as Asynchronous Counter and Synchronous Counter.
Asynchronous Counter: In this counter, the first flip-flop is clocked by the external
clock pulse and then each successive flip-flop is clocked by the Q or Q’ o/p of the
previous flip-flop. Hence in Asynchronous Counter flip-flops are not clocked
simultaneously and hence called as Ripple Counter.
Synchronous Counter: In this counter, the common clock input is connected to all
the flip-flops simultaneously.
 What do you mean by pre-settable counters?
A counter in which starting state is not zero can be designed by making use of the
preset inputs of the flip flops. This is referred to as loading the counter asynchronously.
This is referred to as pre-settable counter.
 What are the applications of synchronous counters?
Digital clock
Frequency divider circuits
Frequency counters
Used in analog to digital converters
 What are the advantages of synchronous counters over asynchronous counters?
77
Propagation delay time is reduced
Can operate at a much higher frequency than the asynchronous counters.
 Ring counter is an example of synchronous counters or asynchronous counter?
Synchronous counter. Since all the flip flops are clocked simultaneously.
 Twisted Ring (Johnson’s) counter is an example of synchronous counters or
asynchronous counter?
Synchronous counter. Since all the flip flops are clocked simultaneously.
 What is the difference between ring counter and twisted ring counter?
In ring counter pulses to be counted are applied to a counter , it goes from state to state and the
output of the flip flop s in the counter is decoded to read the count. Here the uncomplimentary
output (Q) of last flip flop is fed back as an input to first flip flop. Ring counters are referred
as MOD ‘N’ counters.
But in Twisted ring counter the complimentary output (Q bar) of last flip flop is fed back as an
input to first flip flop. Twisted Ring counters are referred as MOD ‘2N’ counters.
 What are the applications of ring counters?

Ring counter outputs are sequential non-overlapping pulses which are useful for control state
counters,
Used in stepper motor, which requires pulses to rotate it from one position to the next.
Used as divide by ‘N’ ((MOD ‘N’) counters.
 What are the applications of ring counter twisted ring counters?
Used as divide by ‘2N’ ((MOD ‘2N’) counters.
Used for control state counters.
Used for generation of multiphase clock.
 List the Synchronous Counter ICs.
IC 74162 : Decade Up Counter
IC 74163 : 4 bit binary Up Counter
IC 74168 : Decade Up/Down Counter
IC 74169 : 4 bit Binary Up/Down Counter
IC 74191 : 4 bit Binary Up/Down Counter
78
EXPERIMENT 15
A) VERIFY THE FUNCTION OF CD 4029 UP/DOWN COUNTER.
AIM: To verify the function of up/down counter using CD 4029.
APPARATUS REQUIRED:

2 IC 4029 1No
3 Bread board 1No
THEORY:
The CD4029 is a presettable up/down counter which counts in either binary or decade
mode depending on the voltage level applied at binary/decade input. When binary/decade is at
logical ``1'', the counter counts in binary, otherwise it counts in decade. Similarly, the
counter counts up when the up/down input is at logical ``1'' and vice versa.
A logical ``1'' preset enable signal allows information at the ``jam'' inputs to preset the
counter to any state asynchronously with the clock. The counter is advanced one count at the
positive-going edge of the clock if the carry in and preset enable inputs are at logical ``0''.
Advancement is inhibited when either or both of these two inputs is at logical ``1''. The carry out
signal is normally at logical ``1'' state and goes to logical ``0'' state when the counter reaches its
maximum count in the ``up'' mode or the minimum count in the ``down'' mode provided the carry
input is at logical ``0'' state.
BLOCK DIAGRAM:
79
PIN DIAGRAM:
TRUTH TABLE:
PROCEDURE:

RESULT: Hence verified the function of up/down counter using CD 4029.
80
EXPERIMENT: 15
B) VERIFY THE FUNCTION OF SHIFT REGISTER (ICS LIKE 7495 OR 74194 ETC.)
AIM: To study shift register using IC 7495 in all its modes i.e.
SIPO/SISO, PISO/PIPO.
APPARATUS REQUIRED:
2 IC 7495 1No
3 Bread board 1No
THEORY:
Shift Register is a group of flip flops used to store multiple bits of data. The bits stored in
such registers can be made to move within the registers and in/out of the registers by applying
clock pulses.
Shift registers can have both parallel and serial inputs and outputs. These are often
configured as "serial-in, parallel-out" (SIPO) or as "parallel-in, serial-out" (PISO). There are also
types that have both serial and parallel input and types with serial and parallel output. There are
also "bidirectional" shift registers which allow shifting in both directions: L→R or R→L. The
serial input and last output of a shift register can also be connected to create a "circular shift
register". A PIPO register (parallel in, parallel out) is very fast – an output is given within a single
clock pulse.
PIN DIAGRAMS:
SIPO:
81
SISO:
PISO:
PIPO:
82
PROCEDURE:
Serial In Parallel Out (SIPO):
1. Connections are made as per Pin Diagram.

2. Apply the data at serial input.
3. Apply one clock pulse at clock 1 (Right Shift) observe this data at QA.
4. Apply the next data at serial input.
5. Apply one clock pulse at clock 2, observe that the data on QA will shift to
QB and the new data applied will appear at QA.
6. Repeat steps 2 and 3 till all the 4 bits data are entered one by one into the
shift register.
Serial In Serial Out (SISO):
2. Load the shift register with 4 bits of data one by one serially.
3. At the end of 4th clock pulse the first data ‘d0’ appears at QD.
4. Apply another clock pulse; the second data ‘d1’ appears at QD.
5. Apply another clock pulse; the third data appears at QD.
6. Application of next clock pulse will enable the 4th data ‘d3’ to appear at
QD. Thus the data applied serially at the input comes out serially at QD
Parallel In Serial out (PISO):
2. Apply the desired 4 bit data at A, B, C and D.
3. Keeping the mode control M=1 apply one clock pulse. The data applied at
A, B, C and D will appear at QA, QB, QC and QD respectively.
4. Now mode control M=0. Apply clock pulses one by one and observe the
Data coming out serially at QD
Parallel In Parallel Out (PIPO):
2. Apply the 4 bit data at A, B, C and D.
3. Apply one clock pulse at Clock 2 (Note: Mode control M=1).
4. The 4 bit data at A, B, C and D appears at QA, QB, QC and QD Respectively.
RESULT: Thus we implemented the shift register and verified its truth tables.
EXPERIMENT: 15
83
C. VERIFY THE FUNCTION OF JOHNSON COUNTER USING CD 4017 IC
AIM: To verify the function of Johnson counter using CD 4017 IC
APPARATUS REQUIRED:
2 CD 4017 1No
3 Bread board 1No
THEORY:
Johnson counter also known as creeping counter, is an example of synchronous counter.
In Johnson counter, the complemented output of last flip flop is connected to input of first flip
flop and to implement n-bit Johnson counter we require n flip-flop.It is one of the most
important type of shift register counter.
A straight ring counter, also known as a one-hot counter, connects the output of the last
shift register to the first shift register input and circulates a single one (or zero) bit around the ring.
A twisted ring counter, also called switch-tail ring counter, walking ring counter, Johnson
counter, or Möbiuscounter, connects the complement of the output of the last shift register to the
input of the first register and circulates a stream of ones followed by zeros around the ring.
A Johnson counter (or switch-tail ring counter, twisted ring counter, walking ring counter,
or Möbius counter) is a modified ring counter, where the output from the last stage is inverted and
fed back as input to the first stage. The register cycles through a sequence of bit-patterns, whose
length is equal to twice the length of the shift register, continuing indefinitely. These counters find
specialist applications, including those similar to the decade counter, digital-to-analog conversion,
etc. They can be implemented easily using D- or JK-type flip-flops.
PIN DIAGRAM:
TRUTH TABLE:
84
PROCEDURE:
2. Connect the connections as per pin diagram.
RESULT: Hence verified the function of Johnson counter using CD 4017 IC
85

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Dr.B.R.

Ambedkar GMR Polytechnic for Women

Department of Electronics & Communication Engineering

Digital Electronics Lab Manual

( Max Marks: 10)

( Max Marks: 10)

Verify the truth tables of basic gates using universal gates

b)Verify the Truth table of 4073 IC.

a) Construct clocked RS FF using NAND gates and Verify its truth

a) Verify the function of CD 4029 up/down counter.

IC 7404 PIN Diagram

IC 7408 PIN Diagram

IC 7432 PIN Diagram:

IC 7400 PIN Diagram:

IC 7486 PIN Diagram:

RESULT: Hence identified all digital IC’S pin diagrams

S.NO APPARATUS REQUIRED QUANTITY

ii. NAND gates as AND gate:

iii. NAND gates as OR gate:

II. Implementation of logic gates using NOR gates:

ii. NOR gates as OR gate:

iii .NOR gates as AND gate:

INP UTS OUTP UTS

1. Make the connection s according to the IC pin diagram.

RESULT: We have implemented all the gates using universal gates

S.NO APPARATUS REQUIRED QUANTITY

2B) VERIFY THE TRUTH TABLE OF 4073 IC

S.NO APPARATUS REQUIRED QUANTITY

S.NO APPARATUS REQUIRED QUANTITY

S.NO APPARATUS REQUIRED QUANTITY

1. Make the connection s according to the IC pin diagram.

S.NO APPARATUS REQUIRED QUANTITY

1. Make the connection s according to the IC pin diagram.

S.NO APPARATUS REQUIRED QUANTITY

PIN DIAGRAM OF 4001(2 INPUT NAND

S.NO APPARATUS REQUIRED QUANTITY

EX-OR EQUATION REDUCTION:

S.NO APPARATUS REQUIRED QUANTITY

Gate No. Inputs Output

Result: The CMOS Equivalent of XOR IC ’s is found

S.NO APPARATUS REQUIRED QUANTITY

S.NO APPARATUS REQUIRED QUANTITY

•The most basic operation, is the addition of two binary digits

S.NO APPARATUS REQUIRED QUANTITY

S.NO APPARATUS REQUIRED QUANTITY

Hence we have verified Operation of Half Adder using NAND only.

S.NO APPARATUS REQUIRED QUANTITY

S.NO APPARATUS REQUIRED QUANTITY

S.NO APPARATUS REQUIRED QUANTITY

Multiplexer (4x1) IC 74153

RESULT: Verified the truth table of 4:1multiplexer using IC 74153

AIM: To Design & Verify the Operation of DE-MULTIPLEXER

Ea Sla S0a Y1a Y2a Y3a Y4a

Ea Sla S0a Y1a Y2a Y3a Y4a

AIM: To Implement and Verification of Encoder using IC 74148

S.NO APPARATUS REQUIRED QUANTITY

IC 74148 PIN Diagram:

 For Encoding 8 Data Lines to 3-Line Binary

AIM: To Implement and Verify the function of 3x8 Decoder.

S.NO APPARATUS REQUIRED QUANTITY

Truth table for Decoder

S.NO APPARATUS REQUIRED QUANTITY

S.NO APPARATUS REQUIRED QUANTITY