Analog & Mixed Signal Circuits: Adc and Dac

ANALOG & MIXED SIGNAL
CIRCUITS
ADC and DAC

Burak Kelleci
© Burak Kelleci - 2023
INTRODUCTION TO DAC AND ADC
○Digital to Analog Converter (DAC) is used to convert digital

signals to analog signals.
○Analog to Digital Converter (ADC) is used to convert analog
signals to quantized, discrete-time (digital) signals.
○Converters are classified as two main types
● Nyquist-Rate Converters
● Oversampling Converters
© Burak Kelleci - 2023 ADC and DAC 2

Nyquist-Rate Converters
○Nyquist-Rate converters operate ideally at the twice of the

signal bandwidth (Nyquist Bandwidth).
○Conversion is performed between B-bit digital code and
analog signal.
○Ideal Nyquist-rate converter is usually used 1.5 to 10 times
higher than Nyquist-Rate in order to simplify realization of
anti-alias filter placed before ADC and smoothing filter
placed after DAC.

OVERSAMPLING CONVERTERS
○Oversampling converters operate at much higher rate than

Nyquist-Rate. (Typically, 20 to 512 times)
○Improvement on Signal-to-Noise Ratio (SNR) is obtained by
filtering the quantization noise which is not on the signal
bandwidth.
○In oversampling ADC filtering is performed using digital
filters.
○In oversampling DAC filtering is performed using analog
filters.
○Most often oversampling converters use noise shaping to
place maximum amount of quantization noise outside the
signal bandwidth.

DAC TYPES
DAC
Nyquist
Oversampling
Rate
String Binary Interpolating Delta Sigma

Thermometer
DAC Weighted (No Noise Shaping) (Noise Shaping)

IDEAL DAC
○Bin is the N-bit digital signal (word)

−1 −2
Bin = b1 2 + b2 2 ++ bN 2 −N Bin DAC Vout
○The output signal is related to the Vref

digital signal through an analog V out
V ref
reference signal Vref. 1
( −1 −2
Vo u t = Vref b1 2 + b2 2 +  + bN 2 −N
)=V ref Bin
3/4
1/2
○VLSB is the voltage change when one

1/4
0
LSB changes 00 01 10 11 100
Vref
VLS B = N
2
Note that maximum -N
© Burak Kelleci - 2023 ADC and DAC value of Vout is Vref(1-2 ) 6
IDEAL DAC
○Following input is applied to a 4-bit DAC with 5V Vref.

Bin=1011
○Determine also VLSB
○Bin=2-1+2-3+2-4=0.6875
○Vout=VrefBin= 3.4375V
○VLSB=Vref/2N= Vref/24= 0.3125V

ADC TYPES
ADC
Nyquist
Oversampling
Rate
Interpolating Delta Sigma

Integrating Converter
(No Noise Shaping) (Noise Shaping)
Successive Approximation Converter First-Order Low-Pass

(SAR) Single-Bit Modulator
Algorithmic Second-Order Low-Pass

(Cyclic) ADC Single-Bit Modulator
Higher-Order Low-Pass
Flash ADC
Single-Bit Modulator
First-Order Low-Pass
Two-Step ADC
Multi-Bit Modulator
Second-Order Low-Pass
Interpolating ADC
Multi-Bit Modulator
Higher-Order Low-Pass
Folding ADC
Multi-Bit Modulator
Pipelined ADC Band-Pass Modulator
Time-Interleaved
ADC

IDEAL ADC
○Bin is the N-bit digital signal (word)

Vin ADC Bin
Bin = b1 2−1 + b2 2−2 ++ bN 2− N
Vref
○The output signal is related to the
digital signal through an analog Overloaded
reference signal Vref.
( )
11
Vin  Vq = Vref b1 2−1 + b2 2−2 +  + bN 2− N = Vref Bin 10
01
○Vq is the quantization error 00

0 1/4 1/2 3/4 1 Vin
Vref
1 1 Note that maximum value

− VLSB  Vq  VLSB of Vout is Vref(1-2-N)
2 2
QUANTIZATION NOISE
○Quantization error occurs even in ideal ADC.

○This error is modeled as additive noise source and
uncorrelated to the analog signal.
○The average of quantization noise is zero and its RMS is equal
to VLSB/sqrt(12)
○For a sinusoidal input signal between 0 and Vref, signal-to-
noise ratio is
SNR = 6.02 N + 1.76dB
○where N is the number of bits.
○Note that maximum SNR level is achieved when the input
signal is at its best maximum value.
○Reducing signal level also decreases SNR level.
QUANTIZATION NOISE
○Example: A sinusoidal signal with an amplitude of 100mV is

applied to a 12-bit ADC with Vref equals to 5V.
○Determine the SNR of digitized signal.
○Maximum SNR is achieved when the input signal amplitude is
2.5V.
○Maximum SNR = 6.02 x 12 +1.76 = 74 dB
○Since the input amplitude is 100mV, the SNR is
20log10(2.5/0.1) = 28 dB below the Full Scale.
○Therefore, the SNR of digitized signal is
74 dB – 28 dB = 46 dB

INTERFACES
○ Digitized data needs to be sent from ADC to digital system or from digital
system to DAC.
○ Depending on the data rate requirement, there are various data
communication standards
○ SPI (Serial Peripheral Interface Bus):
● SPI does not have a formal standard, so each device defines its own
protocol.
● Full Duplex communication
● Faster than I2C
● Usually clock frequencies are below 20MHz.
● Since it is a serial communication, increasing number of bits slows
down sample rate.
● For example, 20 MHz clock and 16-bit data limits sample rate to
1.25MSamples

INTERFACES
○I2C/Serial 2-Wire
● Also called Inter-Integrated Circuit is invented by Philips and used
to communicate with peripherals at low speed.
● Speed
○ 10 kbit/s: Low-speed mode
○ 100kbit/s: Standard mode
○ 400 kbit/s: Fast mode
○ 1Mbit/s: Fast mode plus
○ 3.4 Mbit/s: High Speed mode (Defined in version 3.0)
● Since it is a serial communication, increasing number of bits slows

down sample rate.
● For example, 3.4 Mbit/s mode and 16-bit data limits sample rate to
212.5KSamples

INTERFACES
○CMOS (Parallel)
● Data is sent in parallel.
● Number of data outputs is equal to number of bits used in ADC or
DAC.
● For example, a 16-bit ADC requires 16 outputs.
● This parallel interface is used below 200MSample/s rates.
● Since digital data is sent in parallel, timing closure on the PCB is
important.

INTERFACES
○LVDS (Low Voltage Differential Signaling)

● The information is transmitted as the difference between voltages
on a pair of wires.
● The voltage levels are kept within ±200mV in order to reduce
power consumption and increase the speed.
● LVDS is the only choice above 200MSample/s rate.
● Even some ADCs use LVDS for data rates above 50MSample.
● The main disadvantage of LVDS is it requires two wires for a single
bit. Therefore, a 16-bit ADC requires 32 output pins, which makes
PCB design complicated.
● Since digital data is sent in parallel, timing closure on the PCB is
important.

INTERFACES
○In some applications, data is sent in parallel as nibbles (4-bits).

○For example, 16-bit data is sent as 4 nibbles.
○Some manufactures prefer use LVDS to send this 4-bit data.

PERFORMANCE LIMITATIONS
○ The response of a DAC is defined as the level of analog output for each
digital input signal.
○ Similarly, the response of an ADC is defined as the midpoints of the
quantization intervals for each digital word output.
○ Resolution
● Defined as the number of distinct levels.
● N-bit resolution means that there are 2N distinct analog levels.
● Resolution is not an indication of accuracy, but it is used to refer the
number of bits of the digital word.
● For example, a 16-bit ADC may be accurate only the same as the 12-
bit ideal ADC. This means, although the output is 16-bit, first 12-bits
are meaningful, last 4-bits are buried under noise and other errors.

OFFSET AND GAIN ERROR
○Offset Error:
● In DAC, offset error Eoff is defined as the output that produces
zero output.
Vo u t
Eo ff ( D / A ) =
VLS B 00
● In ADC, offset error is defined as the deviation of V0…01 from ½

LSB.
V00 1 1
Eo ff ( A / D ) = − LSB
VLS B 2

○The gain error is defined to be the difference at the full-scale

value between the ideal and actual curves when the offset
error is reduced to zero.
○In DAC, the gain error is defined in LSBs
 Vo u t 
Eg a in( D / A) = 
 VLS B
−
V
V
o u t  − 2N −1

( )
 11 LS B 00 
○In ADC, the equivalent gain error is defined in LSBs
 V11 V00 
E g a in( A / D ) =  − (
 − 2 N − 2 )
 VLS B VLS B 

○Offset and Gain Error in DAC

V out
V ref Ideal Curve
1
3/4
1/2 Gain Error
1/4
Offset Error
0
00 01 10 11
○Example
● In a 3-bit DAC with Vref=5V, following voltages are measured
● 0.02 : 0.626 : 1.26 : 1.875 : 2.45 : 3.13 : 3.85 : 4.374
● Find the offset and gain errors
○Solution:
● 1 LSB = 5V / 23 = 0.625
● Offset Error Vo u t 0.02
Eo ff ( D / A) = = = 0.032 LSB
VLS B 00 0.625
● Gain Error
 Vo u t 
Eg a in( D / A) =  −
Vo u t
( − 2 N − 1 =  4.374 − 0.02  − 23 − 1 = −0.0336 LSB
) ( )
 VLS B VLS B 00   0.625 
 11

○Offset and Gain Error in ADC
Ideal Curve
Gain Error
11
10
01
00 Vin
0 1/4 1/2 3/4 1
Vref
Offset Error
○Example
● In a 3-bit ADC with Vref=5V, at the following voltages the output
word is changed
● 0.34 : 0.94 : 1.58 : 2.2 : 2.85 : 3.55 : 4.25
● Find the offset and gain errors
○Solution:
● 1 LSB = 5V / 23 = 0.625
● Offset Error V00 1 1 0.34 1
Eo ff ( A/ D ) = − LSB = − = 0.044 LSB
VLS B 2 0.625 2
● Gain Error
V V 
( )  4.25 0.34 
E g a in( A / D ) =  11 − 00  − 2 N − 2 =  − ( )
 − 2 − 2 = 0.256 LSB
3
 VLS B VLS B   0.625 0.625 

INTEGRAL NONLINEARITY (INL)
○INL is defined as the deviation of transfer response from

straight line when offset and gain errors are removed.
○There are two different methods to define the straight line
● The straight line is defined using the endpoints of the transfer
response
● The other method is finding a best-fit straight line which minimizes
the mean squared error.

INTEGRAL NONLINEARITY (INL)
○INL for DAC and ADC
V out
Ideal Straight
V ref
Ideal Straight Line
1 Line Ideal
Response
3/4 Actual 11
Response
1/2 10
Actual
1/4 01 Response
0 00
00 01 10 11 100 0 1/4 1/2 3/4 1 Vin
Vref

DIFFERENTIAL NONLINEARITY (DNL)
○In an ideal data converter, each step size corresponds 1 LSB.

● In an ideal DAC, each output level is exactly 1 LSB apart from
neighbor levels.
● In an ideal ADC, each transition level is exactly 1 LSB apart from
neighbor transition levels.
○DNL is defined as the variation of step sizes from 1 LSB once
offset and gain errors are removed.

INL AND DNL
○Example
● 0.02 : 0.626 : 1.26 : 1.875 : 2.45 : 3.13 : 3.85 : 4.374
● Determine INL and DNL errors (in units of LSBs)
○To calculate INL and DNL errors, offset and gain errors
should be removed.
● The offset error is calculated as 0.032 LSB
● The gain error is calculated as -0.0336 LSB
● The offset error is removed by subtracting 0.032LSB from each
value and the gain error is removed by scaling the values.
ith value  i 
− offset error −  gain error
LSB Level  Numberof Levels- 1 

INL AND DNL
○For example, the scaled value of 0.626 is

0.626 1
− 0.032 +  0.0336 = 0.9744
0.625 7
○The scaled values are

● 0 : 0.9744 : 1.9936 : 2.9824 : 3.9072 : 5 : 6.1568 : 7
○INL is defined as the difference between these values and
ideal values
● 0 : -0.0256 : -0.0064 : -0.0176 : -0.0928 : 0 : 0.1568 : 0
○For DNL, the difference between adjacent scaled values
● -0.0256 : 0.0192 : -0.0112 : -0.0752 : 0.0928 : 0.1568 : -0.1568

INL AND DNL
○Although it is easy to give all INL and DNL values for data
converters with low number of bits, it is not practical for high
number of levels.
○For example an 8-bit data converter has 256 levels.
○Therefore, INL and DNL is given either given as the maximum
value or a graphic which shows all possible cases.

INL AND DNL
○Let’s show INL and DNL of previous example.
0.2 0.25
0.15 0.2
0.1 0.15
0.05
0.1
INL
DNL
0
0.05
-0.05
0
-0.1
-0.05
-0.15
-0.1
-0.2 0 2 4 6 8
0 1 2 3 4 5 6 Code
Code
Max DNL: 0.1568 Max INL: 0.1568

ACCURACY
○ Absolute accuracy
● Difference between expected and actual responses
● Includes effect of offset, gain and linearity errors
○ Relative accuracy
● Accuracy after offset and gain errors are removed.
○ Accuracy is expressed as a percentage error of full-scale value as
effective number of bits or fraction of an LSB.
○ For example, 12-bit accuracy indicates that the error is less than full scale
value divided by 212.
○ For example, a data converter may have 10-bit resolution with only 8-bit
accuracy. Another converter may have 8-bit resolution but 10-bit
accurate. First data converter’s last 2-bit is buried under noise and is not
reliable. On the other hand, second data converter’s response is close to
ideal 8-bit converter response due to 10-bit accuracy.

ACCURACY
○Example
● 0.02 : 0.626 : 1.26 : 1.875 : 2.45 : 3.13 : 3.85 : 4.374
● Calculate absolute and relative accuracy.
○Absolute accuracy is calculated using the largest deviation

between the measured values and ideal values.
● The largest deviation is 0.1V.
● The effective number of bits (ENOB) is calculated when this value
corresponds to 1 LSB
5V 0.1V
N eff
= 0.1V  N eff = 5.64 bits = 16% LSB
2 0.625V

ACCURACY
○For relative accuracy, INL data can be used.

○Maximum INL is 0.1568 LSB, which corresponds to 98mV
○Calculating effective number of bits using relative accuracy
gives
5V
N eff
= 0.098V  N eff = 5.67 bits
2

INL, DNL AND ACCURACY
○Example
● In a 3-bit ADC with Vref=5V, at the following voltages the output
word is changed
● 0.34 : 0.94 : 1.58 : 2.2 : 2.85 : 3.55 : 4.25
● Find the INL, DNL and ENOB using absolute and relative accuracy.
○Solution:
● The offset error is calculated as 0.044 LSB
● The gain error is calculated as 0.256 LSB
● Offset and gain error is removed in a similar way like removing
from DAC response
0.94 1
− 0.044 −  0.256 = 1.4173
0.625 6

○The scaled values are

● 0.5 : 1.4173 : 2.3987 : 3.3480 : 4.3453 : 5.4227 : 6.5
○INL is defined as the difference between these values and
ideal values
● 0 : -0.0827 : -0.1013 : -0.1520 : -0.1547 : -0.0773 : 0
○For DNL, the difference between adjacent scaled values
● -0.0827 : -0.0187 : -0.0507 : -0.0027 : 0.0773 : 0.0773
○The largest deviation from ideal value is 0.1875.
○The ENOB based on absolute accuracy is
5V
N
= 0.1875V  N eff = 4.737 bits
2 eff

○The ENOB based on relative accuracy is calculated using

maximum INL.
○Maximum INL for this 3-bit ADC is 0.1547 LSB, which
corresponds to 96.7mV
5V
N
= 0.0967V  N eff = 5.69 bits
2 eff
0 0.08
0.06
-0.02
0.04
-0.04
0.02
-0.06
0
DNL
INL
-0.08
-0.02
-0.1
-0.04
-0.12 -0.06
-0.14 -0.08
-0.16 -0.1
0 1 2 3 4 5 6 0 1 2 3 4 5
Code Code

MONOTONICITY AND MISSING CODES
○Monotonicity
● In a monotonic DAC, the output always increases as the input
increases.
● If maximum INL error of a DAC is less than 0.5 LSB, it is
guaranteed to be monotonic.
○Missing Code
● In an ADC, it is guaranteed not to have any missing codes if the
maximum DNL error is less than 1 LSB or the maximum INL error is
less than 0.5 LSB.

SAMPLING TIME UNCERTAINTY
○ADC and DAC are clocked circuits and actual clock signal has
also noise and uncertainty.
○Clock edges, at where the sampling occurs, is not precisely
defined as in an ideal clock source. This uncertainty creates
noise at the output of ADC or DAC.
○The sampling time uncertainty also knows as aperture jitter is
usually characterized for full scale sinusoidal signal.
Vref
Vin = sin (2f in t )
2

SAMPLING TIME UNCERTAINTY
○The rate of a sinusoidal signal is maximum at zero crossings,

which is found by differentiating Vin with respect to time and
setting t=0.
V
= f inVref
t max
○Assuming Δt is the sampling uncertainty, and ΔV is the

voltage error which is wanted to be less than 1 LSB.
VLS B 1
t  = N
f inVref 2 f in
○For example, an 8-bit converter with 250MHz sinusoidal

signal, must have less than 5ps of sampling uncertainty

ADC CONVERSION TIME AND
SAMPLING RATE
○ADC Conversion Time
● The time taken for the converter to complete one single
conversion of the input signal.
● This time includes time required for acquisition.
● Sampling rate is the inverse of conversion time.
○Latency
● Time required the signal at the input changes the output signal.
● High sampling rate does not always mean low latency.
● For example, a pipelined ADC may have 2µs conversion time but
24µs latency.

DAC SETTLING TIME AND
SAMPLING RATE
○DAC Settling Time
● Time for the converter to settle to within some specified value of
the final value.
● This value is usually 0.5 LSB
○Sampling Rate
● The rate at which samples can be continuously converted.
● Sampling rate is equal or lower than the inverse of settling time,

SIGNAL-TO-NOISE RATIO (SNR)
○In ideal ADC and DAC, the only noise is quantization noise.
○However, actual converters have also various analog circuits
which generate noise, such as thermal, flicker
○To quantify all noise sources together, a sinusoidal signal is
applied to the converter and signal power and noise power is
determined at its output.
○Usually, due to the nonlinearity of circuits elements, there is
also harmonics of the input signal. To determine the noise
power, these harmonics should also be removed.

○If the all noise power except quantization is below

quantization noise, then the SNR is related to number of bits
by the following formula
SNR = 6.02 N + 1.76dB
○However, if the other noise sources are above or at
comparable levels to quantization noise, this relation does
not hold.
○This SNR formula is reevaluated, to find number of bits when
SNR is known. This N is defined as Effective Number of Bits
(ENOB)
○For example, the SNR at the output of 10-bit ADC may be
55dB instead of 61.96dB. Therefore, its ENOB is 8.84-bits

-20 Signal
-40
Amplitude (dB)
-60
Noise
-80
-100
-120
0 100 200 300 400 500
Frequency (KHz)

TOTAL HARMONIC DISTORTION
○Nonlinear behavior of circuits also create harmonics of the

input signal.
○Harmonic frequencies at integer multiple of input signal
frequency and their amplitude depend on the input signal
level and nonlinearity of the circuit.
○Total Harmonic Distortion (THD) is the ratio of harmonic
power to signal power
P2 + P3 +  + PN V22 + V32 +  + VN2

THD = =
P1 V1
○THD is usually expressed in dB or percentage

TOTAL HARMONIC DISTORTION
Fundamental
-20
Second Third
Harmonic Harmonic
Amplitude (dB)
-40
Noise
-60
-80
-100
-120
0 100 200 300 400 500
Frequency (KHz)

INTERMODULATION DISTORTION
○Harmonics of signals are as apart as the signal frequency.

This causes underestimate of nonlinearity performance if
harmonic levels are reduced due to the frequency response
of the circuit.
○To overcome this problem, two sinusoidal signal with
frequencies close to each other is applied.
○The 3rd order nonlinearity creates intermodulation products
close to these tones.
○The ratio of the intermodulation product to the fundamental
signal is expressed intermodulation distortion.

INTERMODULATION DISTORTION
0
f1 f2
Fundamental
Intermodulation
-20 Product
Second
Third
Harmonic
-40 Harmonic
f2-f1 f1+f2
Noise
Amplitude (dB)
2f1-f2 2f1+f2
2f2+f1
2f2-f1
-60 2f1 2f2

3f1 3f2
-80
-100
-120
0 100 200 300 400 500
Frequency (KHz)

Dynamic Range
○ Dynamic range is the ratio of the maximum allowable signal level to

minimum signal level that is above the noise level.
○ If the noise level does not change with signal level, dynamic range is equal
to SNR at the output for the full scale sinusoidal signal.
○ Noise at the output of some data converters is also function of signal
level. In this case the dynamic range is different than SNR for the full
scale case.
○ Dynamic range is also function of input signal frequency.
● For example, a data converter may show 8-bit performance for the
low frequency input signal, but show 6-bit performance when the
input signal frequency is close to Nyquist rate.

NYQUIST-RATE DAC
○Decoder-Based Converter
● A N-bit DAC can be realized by creating 2N reference signals and
connecting appropriate signal to the output.
● 2N reference signals can be generated by resistor string network.
● The generated voltage is connected in a tree-like decoder.
● In order to prevent any loading of the DAC due to the output
capacitance a buffer is utilized.

DECODER-BASED CONVERTER
Vref
R b3
b3 b2
R
R b3
R b3 b2 b1
2N Vout
Resistors
R b3
Analog
b3 b2
Buffer
R
R b3
R b3 b2 b1

○Advantages
● Simple to build.
● Does not require extra logic for decoding
● No DC current flowing through switches, so small size switches
can be used
○Disadvantages
● Even there is no digital activity, there is static current through
resistors
● Since each switch brings an extra node, which introduces extra
parasitic capacitance.
● These capacitances are charged and discharged through switches
and resistors on the resistor string
● Increasing switch sizes reduces switches on resistance but
increases parasitic capacitance
Vref
R b3
Cpar b3 b2
R
Cpar b3 Cpar
R
Cpar b3 b2 b1
R
2N Vout
Resistors Cpar b3 Cpar Cpar
R
Analog
Cpar b3 b2
Buffer
R
Cpar b3 Cpar
R
Cpar b3 b2 b1
R
Cpar Cpar Cpar Cpar

○Example:
● How many switches are required for N-bit decoded based DAC?
○Solution:
● 2N+2N-1+…+22+21= 2N+1-2

Vref
○To reduce the capacitance R
due to internal nodes R

Cpar
generated by switches, a Cpar

decoder circuit is utilized. R b3
○The amount of parasitic
Decoder
Cpar
R
2N b2
capacitance is reduced in Resistors Cpar
R
the expense of increased
b1
digital circuit complexity. R
Cpar
Cpar
R
Note that the node connected to analog Cpar

buffer input is also connected to drains of R
Vout
2N switches, which will introduce Cpar Cpar
significant amount of capacitance Analog
Buffer

FOLDED RESISTOR-STRING CONVERTER
Vref
○To reduce the decoding
area and large capacitive
loading at the analog b1
buffer input, a folded
Decoder
2N
Resistors with
structure is introduced. b2
equal sizes
○Total number of
transistor junctions at
the output is 2sqrt(2N)
Vout
Analog
Decoder Buffer
b3 b4

MULTIPLE R-STRING CONVERTER
○ First resistor string is used to determine MSB bits.

○ The intermediate voltages are connected to second resistor string to realize LSBs
○ This approach requires only 2x2N/2 resistor.
○ Analog buffers must be matched and have low noise and low offset.
Analog
Vref
Buffer R b1
Decoder
R
b3
Decoder
R b0
R
b2
R
R
R
Vout
Analog Analog
Buffer Buffer
BINARY SCALED CONVERTERS
○Combining a set of signal in a binary fashion is used to realize

DAC.
○Signal sets are realized as binary weighted.
 b b b b  R V 
Vo u t = − RF VREF  − 1 − 2 − 3 − 4  =  F REF  Bin
 2 R 4 R 8R 16 R   R 
The resistor and
Bin = b1 2 −1 + b2 2 − 2 + b3 2 −3 + b4 2 − 4
current ratios are on
RF the order of 2N, which
results in large switch
sizes in order to equal
Vout
the voltage drop on
the resistors.
2R 4R 8R 16R
-Vref

REDUCES RESISTANCE RATIO DAC
○To reduce the resistor ratios a portion of the array may be

scaled.
○This converter has the same relationship to the binary signal
as the previous binary weighted approach but reduced
resistor ratio.
RF
Vout
2R 4R 2R 4R
-Vref/4
3R
-Vref R 4R

R-2R BASED CONVERTERS
○A popular architecture is R-2R resistor ladder.

○The resistor ratio is only 2 and independent of the number of
bits.
○Usually 2R resistor are constructed by series connection of
two R valued resistors to improve matching performance.
R1 R2 R3 R4 R4 = 2 R || 2 R = R
Vref R R R 2R
R3 = 2 R || (R + R4 ) = R
2R 2R 2R 2R R2 = 2 R || (R + R3 ) = R
R1 = 2 R || (R + R2 ) = R

○The current ratio through switches is still large which results

in larger switch sizes for MSBs.
RF
Vout
2R 2R 2R 2R
-Vref R R R 2R

○To reduce current ratio on switches current mirrors are used

to equal the current.
RF
R 2R 2R
R R R
Vout
I I I I

CURRENT MODE CONVERTERS
○Similar to resistor based converters, but can be used at higher

speed.
○Binary weighted currents are switched either to ground or to
the output. R F
Vout
I I/2 I/4 I/8

SWITCHED-CAPACITOR BASED CONVERTERS
○ The resistor array is replaced by capacitor array.

○ By arranging clocking scheme opamp input offset, 1/f noise and finite
amplifier gain effects can be mitigated.
○ Maximum gain is (8C+4C+2C+C)/16C
○ 1 and 2 are non-overlapping clocks
○ 1a and 2a are slightly advanced clocks with respect to 1 and 2
16C 1
1
2
8C 4C 2C C 1a Vout
2
1 C2
Vref 2a
2

WHY DO WE WANT REDUCE
THE RESISTOR RATIO?
○Let’s consider a binary scaled resistor-based DAC.

○The largest resistor value is 2NR whereas the smallest resistor
value is R.
○If the resistor values are within 5% of desired value, in order
to have error less than 1 LSB when largest resistor is selected
the number of bits is limited to
1
N
 0.05  N  4.3
2
○5% is typical matching parameter for integrated resistors.
Some processes allow 1% matching performance which
yields to 6.6 bits
○With laser trimming 0.1% matching yields 10bits.

NYQUIST-RATE DAC
○Thermometer-Code Converter
● Another method is to recode the digital input value to a
thermometer code.
● Thermometer code has 2N-1 digital inputs to represent 2N different
digital values.
Decimal Binary Thermometer Code
b1 b2 b3 d1 d2 d3 d4 d5 d6 d7
0 0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 0 0 0 1
2 0 1 0 0 0 0 0 0 1 1
3 0 1 1 0 0 0 0 1 1 1
4 1 0 0 0 0 0 1 1 1 1
5 1 0 1 0 0 1 1 1 1 1
6 1 1 0 0 1 1 1 1 1 1
7 1 1 1 1 1 1 1 1 1 1

NYQUIST-RATE DAC
○Thermometer-Code Converter
● Thermometer code based converters’ circuit complexity is higher
than binary code based converter.
● It has advantages over its binary counterpart
○ Low DNL errors
○ Guaranteed monotonicity
○ Reduced glitching noise.
● These advantages makes thermometer based converters attractive

for small number of bits.

NYQUIST-RATE DAC
○Resistor based thermometer-coded converter RF
d1 d2 d3 d4 d5 d6 d7
Vout
R R R R R R R
-Vref
○If resistor areas are larger than switch areas, the size of
resistor based thermometer coded DAC is not increased
compared to binary-weighted DAC.
○To built R, 2R and 4R, 7R resistors are needed.

NYQUIST-RATE DAC
○Current mode thermometer-coded converter

● Resistors are not scaled well with advanced process technologies
as MOSFET.
● A current mode approach yields better area shrinkage compared to
resistor based approach.
Iout M1 generates the current that will
be routed to the output
M2 M3
di di Depending on the digital inputs,

current generated by M1 flows
through M2 or M3
M1
Not turning off M1 totally,
Vbias improves the switching timing.

NYQUIST-RATE DAC

● Bias voltage required by M1 is usually generated by a diode
connected transistor.
● Matching of currents on M1 and diode connected transistor
depends on distance between them, process matching
performance and matching of VDS and VGS of transistors.
● Since gate current of MOSFET is zero, their gate-source voltage
will be the same. The zero gate current assumption is not valid for
advanced technologies where gate leakage current is significant.

NYQUIST-RATE DAC

● Mismatch on drain-source voltages will generate current mismatch
due to the channel length modulation.
● To minimize this effect, a cascode structure is usually used.
● Mismatch due to the process still limits the performance.
● To obtain well matched current sources dynamic techniques with
current switching is used. With this technique up to 16-bit
accuracy is obtained for audio frequency DAC.

NYQUIST-RATE DAC
○Current mode thermometer-coded converter RF
d1 d2 d3 d4 d5 d6 d7
Vout
I I I I I I I
RF
Iref d1 d2 d3 d4 d5 d6 d7
Vout
VDD/2

NYQUIST-RATE DAC
○Instead of using and amplifier, current sources drive directly

the load
I I I I I I I
d1 d2 d3 d4 d5 d6 d7
VOUT
RL

NYQUIST-RATE DAC
○Practical current sources have finite output impedance.

Moreover, switches have also finite on resistance.
I ROUT
B IEQ
RON
dN
REQ = ROUT + RON
REQ/B RL
RL

NYQUIST-RATE DAC
○The equivalent output current is

I  ROUT + VDD
I EQ =
ROUT + RON
○Assuming k is the number of cells that are switched on,
output voltage becomes
RL  REQ / k k RL
VO U T = k  I EQ = I EQ  RL =
RL + REQ / k 1 + k REQ
○This equation indicates that there is gain error and

nonlinearity in terms of INL

NYQUIST-RATE DAC
○INL is in LSBs
INL(k ) =
 
k 1 +  (2n − 1)
−k k = 0,,2n − 1
1 + k
○The maximum of INL occurs at the mid-code and

approximately equals to
INLMAX =   2n−2
○In order to obtain less than 1LSB INL error, equivalent output
resistance must be greater than
REQ  RL  2n −2

NYQUIST-RATE DAC
○For example, to get 12-bit performance for 25Ohm load

resistance, equivalent resistance must be greater
100MegaOhm.
○In modern CMOS processes this level of output resistance
can be achieved using cascode structures.

NYQUIST-RATE DAC
○Mismatch between current sources limits the performance.

○To obtain 99.9% yield, current mismatch must
I
 0.3  2−n / 2
I
○For example, to obtain 12-bit performance mismatch must be
lower than 0.5%.
○This level is not possible unless special processing steps or
digital signal processing techniques are used.
○Note that, 5% mismatch will results in 5-bit resolution.

NYQUIST-RATE DAC
○Dynamically matched current source

● In this method, a current source is first calibrated by connecting it
to a reference current.
● Opening S1 switch the gate source voltage remains constant since
there is no current flow through MOSFET gate.
Iref
Iref
Calibration Iout Iout
Current Source
Phase
Mode
S2 S2
S1 M1
S1 M1
CGS CGS

NYQUIST-RATE DAC
○Hybrid Converters (Segmented Converters)

● Combining binary approach with thermometer technique yields to
Hybrid converters.
● Top few MSBs are realized using thermometer coded approach
and binary approach is used for lower LSBs.
● Since LSBs require less accuracy and have less glitch energy, area
saving is performed by using binary approach for LSBs.
b3 b2 b1
Binary-to-Thermometer Decoder RF
d1 d2 d3 d4 d5 d6 d7
d1 d2 d3 d4 d5 d6 d7 b4 b5 b6
Vout
I I I I I I I I/2 I/4 I/8

RAMP CONVERTER
○At the beginning of conversion reset switch discharges the

capacitance C.
○Then the counter starts to count from zero.
○Comparator closes the switch till count number reaches the
input level.
○2N clock cycles are required to reach Full Scale.
Reset
Vout
S&H
kI C
VOUT = Input Comp Clk/2n
C  fS I
Count
k is the digital code
Clk
RAMP CONVERTER
○Ramp converter requires 2N clock cycles to reach Full Scale.

○If two current sources are used to charge the number of
clock cycles are reduced.
Reset
Vout
S&H
C
InputMSB-M Comp IM
InputREST Comp I
Clk/2n-M
Count Count
Clk Clk

DUTY-CYCLE CONVERTER
○The duty-cycle converter converts input signal into series of

pulses.
○Counter connects low-pass filter input to Vref is counter
value is less than input value, otherwise to zero. Filter
removes high frequency content.
○2N clock period is required for conversion.
Vref
Vout
Filter
Input Comp
Count
Clk

NYQUIST-RATE ADC

INTEGRATING CONVERTER
○Suitable for
● High accuracy
● Very slow moving signals
● Measurement of low frequency close to DC voltage or current
○Advantages
● Very low offset and gain errors
● Highly Linear
● Low area requirement

○In dual-slope integrating converter conversion is performed

in two phases.
S2
C1
S1
S2
-Vin S1 R1 Comparator
Vref Vx
Control Bout
Counter
logic
Clock
fclk=1/Tclk

○Phase I
● fixed time interval of length T1 and determined by running counter
2N clock cycles
T1 = 2 Tclk
N
● S1 is connected to –Vin, Vx ramps up proportional to the magnitude

of Vin.
● Assuming initially Vx is zero, Vx and Vin has the following
relationship t
− Vin Vin
Vx (t ) = −  d = t
0
R1C1 R1C1
● At the end of phase I the value of Vx is equal to
Vin T1
Vx =
R1C1
○Phase II
● Occurs for variable of time.
● At the beginning of this phase counter is reset and S1 is connected
to Vref, resulting in constant slope for decaying voltage at Vx.
● To obtain a digital value, counter counts until Vx is below zero, at
which point that count value is the digitized value of the input
signal Vin.
● Assuming that the digital output count is normalized so that largest
count is unity, Bout is defined as
Bout = b1 2−1 + b2 2−2 + + bN −112−(N −1) + bN 2− N

○Phase II
● Therefore T2 is equal to
( )
T2 = 2N BoutTclk = b1 2N −1 + b2 2N −2 + + bN −112 + bN Tclk
● Let’s calculate value of Vx during phase II
t
Vref
Vx (t ) = −  d + Vx (T1 )
T1
R1C1
− Vref Vin T1
= (t − T1 ) +
R1C1 R1C1

○Phase II
● Since Vx equals to zero when t=T1+T2
− Vref T2 Vin T1
0= +
R1C1 R1C1
● Therefore the relationship between T2 and T1 is
 Vin 
T2 = T1  
V 
 ref 
 Vin 
N
2 Bo u tTclk = 2 Tclk 
N   Bo u t = Vin
V  Vref
 ref 

○The relationship between analog input and digital output

does not depend on clock frequency and RC time constant.
○Since RC time constant determines peak voltage at Vx node,
RC time constant should be chosen so that signal at Vx node
does not clip and is as large as possible.
○The conversion speed is at the worst case when Vin equals to
Vref is
2 N +1 Tclk
○For example, for a 16-bit converter with a clock frequency of
1MHz worst-case conversion rate is 7.6Hz.

○By carefully choosing T1, certain frequency components on

the input signal can be attenuated.
○Let’s assume that input signal has also 50Hz noise
Vin = Vin (id ea l) + Vn o ise(5 0H z)

= Vin (id ea l) + A sin (2 50t +  )
○Let’s calculate Vx at the end of T1.
− Vin − Vin (id ea l) − A sin (2 50t +  )

t t t
V x (t ) = −  d = −  d −  d
0
R1C1 0
R1C1 0
R1C1

○Since T1 is equal to the period 50Hz sinusoidal signal, the

second integral yields to zero.
○Note that this T1 value also attenuates harmonics of 50Hz
(100Hz, 150Hz, …)
○Since this converter effectively performs integrate and
dumps the input signal, its impulse response corresponds a
square pulse of length T1.
○The Fourier transform of square pulse is
sin (fT1 )
H( f ) =
fT1

-5
-10
H (dB)
-15
-20
-25
-30
1 2 3
10 10 10
Frequency (Hz)

○Example:
○Design a 16-bit two-slope integrating ADC with the following
specifications
● Max Input Voltage = 3V
● Max Voltage at the integrator output = 4V
● Reject 50Hz supply noise
● Calculate the required RC time constant and clock rate
● Find the attenuation for noise signals at 220Hz.

○Example:
○Since 50Hz and harmonics will be rejected
1
= 20ms T1 =
50
○Therefore, the clock frequency is
1 21 6
f clk = = = 3.28MHz
Tclk T1
○At the end of phase I, the voltage at Vx is

Vin T1 Vin T1 3  20ms
Vx =  R1C1 = = = 15ms
R1C1 Vx 4

○Example:
○To find the attenuation at 220Hz, we need to evaluate
sin (fT1 )
H( f ) =
fT1
sin (  220  20ms)
H (220) = = −23dB
  220  20ms

SUCCESSIVE APPROXIMATION
CONVERTERS (SAR)
○SAR converters are one of the popular approaches due to
their quick conversion time and moderate circuit complexity.
○The operation of SAR is based on binary search algorithm.
○First MSB (b1) is detected followed by b2 and so on until all N
bits are determined.
○Therefore, SAR converter requires only N clock cycles to
determine the digital output word.

CONVERTERS (SAR)
○DAC based SAR
● Input signal is first sampled and hold its value during the
conversion time.
● By changing Bout value, DAC output voltage changes.
● The accuracy and speed of DAC determines the performance of
ADC
Sample
Vin SAR Register and
Hold
control logic
Bout
DAC Vref

CONVERTERS (SAR)
Start
○Flow graph for
SAR Converter Sample Vin, VDAC=VREF/2-VLSB/2, i=1
no
Vin > VDAC
yes
bi=1 bi=0
VDAC=VDAC + Vref/2i+1 VDAC=VDAC - Vref/2i+1
İ=i+1
no
İ > N-1
yes
Stop

CONVERTERS (SAR)
○Determine DAC values for Vref=8V, Vin=2.831V and a 3-bit
conversion and the final digital output.
○Solution:
● VLSB=Vref/2N=1V
● In cycle 1 Bout = 100 and VDAC = 3.5V
○ Since Vin < VDAC b1 is set to 0
○ Since Vin > VDAC b2 is set to 1
○ Since Vin > VDAC b3 is set to 1
● Therefore the resulting Bout = 011
● Since VLSB/2=0.5, the quantization error is 2.831V-2.5V=0.331V
which is less when VLSB/2

CONVERTERS (SAR)
○Unipolar Charge Start
Redistribution ADC Sample V=Vin-(VREF/2-VLSB/2), i=1

● Instead of using a separate
DAC, the sampled voltage is V>0
no
modified and compared to

ground. bi=1
yes
bi=0
● This structure is easy to
implement with switched- V = V - Vref/2i+1 V = V + Vref/2i+1
cap circuits
● Since this algorithm requires
İ=i+1
signed input, Vin should be no

converted to signed İ>N
representation by yes
subtracting (Vref/2-VLSB/2) Stop

CONVERTERS (SAR)
○Sample Mode
● All capacitors are charged to Vin while the comparator is being
reset using S2.
● In this mode the capacitor array is performing sampling operation
S2
Vx=0
16C 8C 4C 2C C C SAR
b1 b2 b3 b4 b5
S3
S1
Vin Vref

CONVERTERS (SAR)
○Hold Mode
● By opening S2, the comparator is now in normal operation
● Then all capacitors are switched to ground and Vx goes to –Vin.
S2
Vx=-Vin
b1 b2 b3 b4 b5
S3
S1
Vin Vref

CONVERTERS (SAR)
○Bit Cycling
● First largest capacitor is switched to Vref, so Vx goes to –Vin+Vref/2
● If Vx is negative then ground then MSB capacitor is left connected
to Vref.
● This is also performed for remaining bits to obtain the digital
output word. S2
Vx=-Vin+Vref/2
b1 b2 b3 b4 b5
S3
S1
Vin Vref

CONVERTERS (SAR)
○To get an exact division by two an additional unit capacitor is
added.
○Therefore, total capacitance is 2NC.
○The bottom plates of the capacitors should be connected to
Vref in order to minimize the parasitic capacitance at node Vx.

CONVERTERS (SAR)
○Example
● Determine intermediate node voltages at Vx for the 5-bit charge
redistribution converter shown in previous slide when Vin=1.23V
and Vref=5V. Assume that there is 8C parasitic capacitance at Vx
node.
○Solution
● During the sample mode Vx=0
● During the hold mode all capacitors are switched and the charge
on Vx is shared between 32C total converter capacitance and the
parasitic 8C
 (− Vin ) = −0.984V
32
Vx =
32 + 8

CONVERTERS (SAR)
○Solution (cont.)
● During the first bit cycling, b1 is switched
16
Vx = −0.984V +  5 = 1.016V
40
● Since Vx is greater than 0, b1 is switched back to ground. Then b2 is
switched.
8
Vx = −0.984V +  5 = 0.016V
40
● Since Vx is greater than 0, b2 is switched back to ground. Then b3 is
switched.
4
Vx = −0.984V +  5 = −0.484V
40

CONVERTERS (SAR)
○Solution (cont.)
● Since Vx is less than 0, b3 is left connected. Then b4 is switched.
2
Vx = −0.484V +  5 = −0.234V
40
● Since Vx is less than 0, b4 is left connected. Then b5 is switched.
1
Vx = −0.234V +  5 = −0.109V
40
● Since Vx is less than 0, b5 is left connected.
● Therefore, the output Bout is 00111.
● The voltage at Vx is within a LSB/2 of ground
(VLSB=5/32=0.15625V)

ALGORITHMIC (CYCLIC) ADC
○ Algorithmic ADC operates in the

Start
same way as the SAR ADC. Sample V=Vin-(VREF/2-VLSB/2), i=1
○ Although in SAR the reference

voltage is halved at every cycle, V>0
no
an algorithmic converter doubles

the error voltage while leaving
yes
bi=1 bi=0
the reference voltage unchanged.
 Since this algorithm requires V = 2(V - Vref/4) V = 2(V + Vref/4)
signed input, Vin should be

converted to signed İ=i+1
representation by subtracting
(Vref/2-VLSB/2) no
İ>N
yes
Stop

○This converter requires a small amount of analog circuitry,

since it uses the same circuit for conversion.
○One of the difficulty is to obtain X2 gain opamp without
offset. B out
Vin Sample Shift

Comparator
Hold Register
Vref/4
Sample
X2
Hold
-Vref/4

○Multiply-by-two Circuit
● The basic idea of this gain circuit is to sample the input signal twice
using the same capacitor.
● Phase I: Sample error voltage on C1 and remove any charge on C2.
C2
C1
Verr
Comparator
Q1

● Phase II: Transfer the charge of C1 to C2.
C2
Q1
C1
Verr
Comparator
Q1

● Phase III: Resample error voltage on C1.
● Keep the charge on C2.
C2
Q1
C1
Verr
Comparator
Q2

● Phase IV: Sum the charge on C2 with the charge on C1.
C2
C1
Verr
Comparator
Q1+Q2
Vout=2Verr

○Example
● Consider the multiply-by-two circuit in the previous slide.
● Assume opamp has an input offset designated by Voff.
● Find the values of VC1, VC2 and Vout
○Solution
● Phase I: The opamp output is connected to the negative opamp
input
Vo u t = Vo ff
VC1 = Verr − Vo ff
VC 2 = 0 − Vo ff = −Vo ff

○Solution (cont.)
● Phase II: At the end of this phase
 C1 
Vo u t =  Verr
 C2 
VC1 = 0 − Vo ff = −Vo ff
 C1 
VC 2 = −Vo ff +  Verr
 C2 
QC1 = C1 (Verr − Vo ff − (− Vo ff )) = C1Verr

○Solution (cont.)
● Phase III: At the end of this phase, VC2 is unchanged since one side
of C2 is open.
Vo u t = Vo ff
VC1 = Verr − Vo ff
 C1 
VC 2 = −Vo ff +  Verr
 C2 

○Solution (cont.)
● Phase IV: At the end of this C2 is discharged to the same value in
phase I.
Vo u t = 2Verr
VC1 = 2Verr − Vo ff
VC 2 = −Vo ff
 C1 
QC 2 = C 2  Verr = C1Verr
 C2 
● Note that the final value of Vout is independent of sizes of C1 and

C2 and the offset value Voff.

FLASH CONVERTER
○Main advantage is high speed operation

○The input signal is fed to 2N comparators and each
comparator is connected to a different node of a resistor
string.
○If voltage is at the resistor string is higher than the voltage at
the input, the comparator output becomes one.
○Since the output of comparator is thermometer coded, an
encoder is needed to convert thermometer code to digital
word.

FLASH CONVERTER
Vref Vin
○Top and bottom resistors R/2
are used to create the R

0.5LSB offset in an ADC.
○Flash ADCs are fast but
R
power and area hungry due R
Encoder
to the number of R
Digital
Outputs
comparators.
R
○Due to the mismatch
among resistors, maximum R
number of bits are limited R
to 8-10 bits.
R/2

FLASH CONVERTER
○There are some design issues that should be addressed when

designing Flash ADCs.
○Input Capacitive Loading
● The large number of comparators connected to Vin node results in
large capacitive load at the input node.
● To drive this large capacitive load, a buffer is needed.
● Usually this capacitive load limits speed and increases power
consumption.
○Resistor String Bowing
● If input current of comparators is non-zero, this bias current
disturbs the voltages on the resistor string and causes error.

FLASH CONVERTER
○Signal and/or Clock Delay

● Differences in the arrival of clock or input signal at different
comparators causes error.
● For example, consider a 250MHz, 1V sinusoidal signal. This signal
has its maximum slope of 1570V/ms at zero crossings.
● If this signal is converted using 8-bit ADC with Vref=2V, it will take
only 5ps to change through 1LSB. This time is approximately the
same time as the propagation time of a signal through 500mm
metal interconnect.

FLASH CONVERTER
○Bubble Error Removal

● In ideal operation, the output of comparators are thermometer
coded.
● However, sometimes a lone 1 will occur within the string of 0s (or
a 0 within the string of 1s) due to the comparator metastability,
noise, cross talk, etc.
● These bubbles usually occur near the transition point of the
thermometer code.
● These bubbles can be removed using two-input NAND gates.

FLASH CONVERTER
Vref Vin
○Bubble error can be
removed by using three
R/2
input NANDs. R
○For transition, there must R
be two ones immediately R
above a 0 in order to decide
Encoder
Digital
transition point. R
Outputs
R
R/2

FLASH CONVERTER
○Flashback
● When the comparator is clocked, there is a glitch at the inputs to
the latch.
● If positive and negative side impedances of the comparator is not
matched, this glitch creates voltage difference and causes errors.

TWO-STEP ADC
○Two-step or subranging converters are used for high-speed

medium accuracy ADCs,
○Two step ADCs require less area, have less capacitive
loading, dissipate less power than flash converters.
○However, they have larger latency than flash converters,

TWO-STEP ADC
4-bit 4-bit 4-bit

Vin MSB MSB 16 LSB
ADC DAC ADC
First 4 Bits Lower 4 Bits

b1, b2, b3, b4 b5, b6, b7, b8
○First 4 MSB bits are determined using a Flash ADC.

○To determine the remaining LSBs, the 4-bit MSB is
converted to analog and subtracted from input signal.
○The subtraction result is multiplied by 24(16) and lower 4
LSB bits are determined using another Flash ADC.

TWO-STEP ADC
○For example, 8-bit two-step ADC requires 32 comparators.

○If 8-bit Flash architecture is used 256 comparator will be
required.
○The ease the linearity requirement of MSB ADC usually
digital error correction is used.
○Without error correction first MSB ADC must be N-bit
accurate.

TWO-STEP ADC
○ Consider 8-bit Two-Step ADC with VLSB=Vref/28

○ For an ideal 8-bit ADC the absolute accuracy is 0.5LSB
○ If the MSB ADC is 8-bit accurate, the quantization noise at the MSB ADC
output is ±8.5LSB
○ If it is 4-bit accurate, the quantization noise is within ±16LSB
○ Since the quantization noise is ±16LSB, 5-bit ADC is required to
determine lower bits.
4-bit accurate 8-bit accurate 5-bit accurate 5-bit accurate
4-bit 4-bit 5-bit
Vin MSB MSB 8 LSB
ADC DAC ADC
Error Correction
8 Bits

INTERPOLATING ADC
○Interpolating converters utilize comparators as amplifiers.

○Comparators operate as linear amplifiers near their threshold
voltages but are saturated once the differential inputs are
large.
○Since the difference between reference voltage and input
signal is amplified, only simple latch is required to detect the
sign changes at the amplifier output.
○Another advantage of this technique is reduced number of
comparators results in lower parasitic capacitive load at the
input node.

INTERPOLATING ADC
○For a good linearity the

Vref Vin
interpolated signals need to

Latch
R
Latch
cross latch thresholds at R

R
R
Latch
correct points. R
Latch
Latch
○For fast operations the signal R

Latch
delays to each of latch needs

R
Latch Digital
R
R Outputs
Encoder
to be made equal
Latch
R
Latch
R
Latch
R
Input Amplifier Output
Latch
R
R
V2 Latch
R
V1
Latch
Latch Threshold R
R Input Latch
Amplifiers R
V2a V2c Latch
R
V2b Latch
R
Latch
Comparators
Vin

INTERPOLATING ADC
○Since the comparators are

identical, they have similar R
R
input capacitances and Latch
adding extra resistors R R/4

Latch
makes the delay nearly R
equal. Latch
R R/4
○The impedance seen by Latch
latches are almost the same R
R
Latch
if the amplifiers output
R
impedance is low.

INTERPOLATING ADC
○Circuit techniques other than resistor

2 1
string can also be used to generate I 2a = I1 + I 2
interpolating architecture. 3 3
○For example, current mirrors can be used 1 2
I 2b = I1 + I 2
to generate interpolated currents. 3 3
I1 I2a I2b I2
9 3 3 3 3 3 3 9

FOLDING ADC
○Interpolating architecture reduces the number of input

amplifiers but the number of latches are 2N.
○This large number of latches can be reduced by the use of
folding architecture.
○In the folding structure, the input amplifier has more than
one threshold point.
Folding rate is the number of output
transitions
Input Amplifier Output
Folding Rate : 4
Latch Threshold
Vin
FOLDING ADC

FOLDING ADC
○The MSB converter determines whether the input signal is

within one of four voltage regions.
○Usually the MSB signals are determined by combining
appropriate signals in the folding blocks.
○Four latches are used for different MSB regions and the
thermometer code is inverted when Vin is between either ¼ and
½ or ¾ and 1.
○For example, when Vin is increased from 0 to ¼ the
thermometer code changes as 0000, 0001, 0011, 0111, 1111.
○Increasing from ¼ to ½ changes the code 1110, 1100, 1000,
0000.

FOLDING ADC
○Folding blocks can be realized using cross-coupled

differential pairs.

FOLDING ADC
○Although the number of latch comparators are reduced, the

input capacitance is not reduced.
○Actually, folding architecture has the same amount of input
capacitance as the flash converter due to the increase of the
number differential pairs in folding structure.
○Therefore, the folding architecture is usually used using
interpolation architecture.

FOLDING ADC
○MSB bits are easily determined by using internal signals of

top folding pair which generates V1.
○MSB bit b1 depends only whether the input signal is above or
below Vref/2.
○Comparing the input signal with (8/16)Vref, b1 can be
obtained.
○Similarly to determine b2 bit, references 4/16 and 12/16 are
needed. These references are also present in the top folding
block.

FOLDING ADC
○Top folding block which also determines b1 and b2.

PIPELINED ADC
○The two-stage architecture can be generalized to multiple

stages, where each stage determines single bit.
○A straightforward implementation will be too slow, because
each stage will wait other stages to be completed.
○For fast operation pipelining is incorporated. Once a stage
completes its operation it passes the result to next stage and
immediately starts processing the other bit.
○The sampling rate is the same as the clock frequency but
latency will be product of sampling period and the number
pipeline stages.

PIPELINED ADC
○ Each sub block contains a sample and hold circuit in order to store
the analog waveform coming from previous stage.
○ The analog signal at the output of sample and hold is compared to
reference voltage and the bit value is determined.
○ Depending on the comparator result, Vref/4 is added or subtracted
from input voltage and the result is multiplied by two and passed
to
preceding stage.

PIPELINED ADC

TIME-INTERLEAVED ADC
○Very high speed ADCs can be realized by combining them in

parallel.

OVERSAMPLING
○Oversampling become popular for high resolution medium-

to-low speed applications, such as audio
○Main advantage of oversampling it relaxes analog circuit
requirements in the expense of more complicated digital
circuits.
○At submicron technologies, digital circuits are cheap but high
quality analog components are expensive.
○Therefore, relaxing analog requirements in the expense of
digital is desired at new technologies.

OVERSAMPLING WITHOUT
NOISE SHAPING
○The quantization noise power is equal to VLSB2/12 and
independent of the sampling frequency.
○The spectral density of quantization noise is white and all its
power is within ±fs/2.
○The spectral density height is
2 
fs / 2
S (f )=  Se ( f ) =
1
 
2
e
− fs / 2
12 12 fs

NOISE SHAPING
○The advantage of oversampling occurs when the signals of
interest are bandlimited to f0 and the sampling rate is greater
than 2f0.
○The oversampling ratio
fs
OSR =
2 f0
○After quantization the output is filtered and all signals above

f0 is filtered out.
○Therefore the quantization noise is reduced to
 
f0 2 2
2 f
( ) 1
− f S e f = 12 f s = 12 OSR
2 0

NOISE SHAPING
○Doubling OSR decreases the quantization noise power by
3dB or equivalently 0.5bits.
○Maximum SNR for sinusoidal input is
SNR = 6.02N + 1.76 + 10 log1 0 (OSR)
○The first term is due to N-bit quantizer and the last term is
due to SNR improvement due to oversampling.

NOISE SHAPING
○Example
○96dB SNR needs to be obtained for f0=25KHZ using 1-bit
ADC. What is the required oversampling ratio (OSR)
○Assuming 1-bit ADC has 6dB SNR, 90dB SNR needs to be
obtained by oversampling.
○Since OSR improvement is 3dB per octave, sampling rate
must be 30 octave above 2f0.
f s = 230  2 f 0 = 54000GHz
○Without noise shaping it will be impractical to obtain 96dB

SNR from 1-bit quantizer.

NOISE SHAPING
○1-bit DAC
○Although oversampling improves the SNR, it does not
improve linearity.
○For example, if 16-bit converter is desired using
oversampling of 12-bit converter, the 12-bit converter must
be 16-bit accurate.
○On the other hand, 1-bit converter is inherently linear, since
it has only two output values.
○However, 1-bit converter is sensitive to clock jitter. The error
at the clock edge will be multiplied with Vref, since LSB
equals to VREF.
○For multi-bit converters the error due to jitter will be
multiplied by Vref/2N.
OVERSAMPLING WITH NOISE SHAPING
○Using a feedback system, the quantization noise within

desired band can be pushed to outside the desired band.
○This will results in dramatic improvement of SNR.
○The oversampling converters with noise shaping is also called
delta-sigma (Δ) or sigma-delta (Δ) converters.
○The general model of delta-sigma converter is

○Assuming the linear model has two independent inputs,

signal transfer function (STF) and noise transfer function (NTF)
can be developed.
Y (z ) H (z )
S TF (z ) = =
U (z ) 1 + H (z )
Y (z )
N TF (z ) =
1
=
E (z ) 1 + H (z )
Y (z ) = S TF (z )U (z ) + N TF (z )E (z )

○To shape the quantization noise, the magnitude of H(z) is

chosen large from 0 to f0 (in the band of interest).
○Therefore, STF(z) will be approximately unity and NTF(z) will be
approximately zero within the band of interest.
○However, the noise outside the band of interest is not
reduced since the loop gain at high frequencies is lower than
the loop gain at low frequencies.
○This out-of-band noise is removed by post-filtering.

○To realize first order noise shaping, NTF should have zero at
DC, so than quantization noise is high-pass filtered.
○Since the zeros of NTF is equal to poles of H(z), first order
noise shaping can be obtained using discrete-time integrator.
z −1
H (z ) =
1
=
z − 1 1 − z −1

○The signal transfer function and noise transfer function
Y (z ) 1 / ( z − 1)
S TF ( z ) = = = z −1
U ( z ) 1 + 1 / ( z − 1)
Y (z )
N TF ( z ) = =
1
E ( z ) 1 + 1 / ( z − 1)
(
= 1 − z −1 )
○To find the magnitude of the noise transfer function, let
z=ejwT.

e jf / f s − e − jf / f s
N TF ( f ) = 1 − e − j 2f / f s =  2 j  e − jf / f s
2j
 f 
= sin    2 j  e − jf / f s
 fs 
○Therefore the magnitude becomes
 f 
N TF ( f ) = 2 sin  
 fs 

○The quantization noise power over the band of the interest is

2
f0
 1 2 f0
  f 
Pe =  S (f )N (f ) df = − f 2 sin  f s  df
2 2
e TF
− f0
12 f s 0  
○Assuming fs>>f0, sin((f)/fs) is approximated as (f)/fs.
3
  2 2
 2 f0 
Pe =  
12 3  fs 

○Maximum SNR for sinusoidal signal is
 Ps  3   3 3
SNR = 10log10   = 10log10  22 N  + 10log10  2 ( OSR ) 
 Pe  2   
= 6.02 N + 1.76 − 5.17 + 30log10 ( OSR )
○Doubling the OSR improves SNR by 9dB or equivalently
1.5bits.
○Compared to oversampling without noise shaping an extra
1bit/octave improvement is achieved using noise shaping.

○Example
ADC and first order noise shaping. What is the required
oversampling ratio (OSR)
○96dB SNR needs to be obtained by oversampling.
must be at least 11 octave above 2f0.
f s = 211  2 f 0 = 102.4MHz
○102MHz sampling rate is practical with current technology.

○A second order delta sigma modulator is used to put more

noise out of the band of interest.
S TF (z ) = z −1
(
N TF (z ) = 1 − z )
−1 2
2
  f 
N TF (z ) = 2 sin  
  fs 

○The quantization noise power over the band of interest

becomes
2 4  1 
5
Pe =  
60  OSR 
○SNR for sinusoidal signal is
 Ps   3 2N   5
SNR = 10 log 1 0   = 10 log 1 0  2  + 10 log 1 0  4 (OSR) 
5
 Pe  2   
= 6.02 N + 1.76 − 12.9 + 50 log 1 0 (OSR)
○Doubling the OSR improves SNR by 15dB or equivalently
2.5bits.

○Example
ADC and second order noise shaping. What is the required
oversampling ratio (OSR)
○102dB SNR needs to be obtained by oversampling.
must be at least 7 octave above 2f0.
f s = 27  2 f 0 = 6.4MHz
○6.4MHz sampling rate is practical with current technology.

○Increasing delta-sigma order increases also out-of band noise.

○Especially, the noise at fs/2 will be downconverted due to the
clock jitter.
○Usually, a zero is put at fs/2 to reduce the sensitivity of the
modulator to clock jitter.

SYSTEM ARCHITECTURE OF
DELTA-SIGMA ADC
○The advantage of Delta Sigma ADC is that the requirement
of anti-aliasing filter is relaxed in the expense of complex
digital filter.
○This tradeoff is usually wanted in digital integrated circuits.

DELTA-SIGMA ADC
○Anti-alias filter: Limits the signal to half of the sampling
frequency.
○Sample and hold: Samples the input signal and keeps the
sampled value for subsequent processing.
○Delta Sigma Modulator: Converts the analog waveform to
digital.
○Digital Low-Pass Filter: Removes unwanted out-of-band
quantization noise.
○OSR: Reduces the sampling rate, since filter output has
redundant information.

DELTA-SIGMA ADC

DELTA-SIGMA DAC
○The digital input is a multi-bit signal and has a sampling rate
of 2f0.
○Interpolation filter removes the images occurred due to the
OSR.
○Delta Sigma modulator converts this multi-bit signal with high
sampling rate to single bit.
○Analog low-pass filter removes the out-of-band quantization
noise,

DELTA-SIGMA DAC

SAMPLE AND HOLDS
○Sample and Hold circuits are used to sample and store its
value for limited time.
○Often sample and hold circuits are called as track-and-hold
circuits.
○Track and hold circuits tracks the input signal at one phase of
the clock signal and keep its output constant at the other
clock phase.
○The main advantage of sample and hold circuits is to
minimize errors due to the delay of operation of internal
circuits of the converter.

SAMPLE AND HOLDS
○Performance metrics
○Sampling pedestal (hold step):
● When sample and hold goes from sample mode to hold mode, a
small error voltage is introduced. That makes the voltage at hold
mode differs from the voltage at the sampling instance.
● This error must be as small as possible.
● It should be independent of the signal, otherwise it will generate
nonlinear distortion.

SAMPLE AND HOLDS
○Isolation at the hold mode:

● Ideally, the output voltage should not be affected by the changes
of inputs signal during the hold mode.
● In reality, there will be some voltage feedthrough between input
and output at the hold mode through parasitic capacitances.
● Obviously, this error must be minimized.
○Speed
● How well the sample and hold tracks the input signal during
sample mode.
● 3-dB bandwidth and slew rate limits the maximum speed of the
sample and hold.
● For high speed operation, 3-dB bandwidth and slew rate must be
maximized.

SAMPLE AND HOLDS
○Droop Rate:
● This error is the slow change of output waveform at hold mode.
● This effects is usually due to the leakage current.
○Aperture Jitter (Aperture Uncertainty):

● This error is due to the effective sampling time changing due to the
clock uncertainty.
● This error creates problems especially for high speed signals.
○Other Performance Metrics

● Dynamic Range
● Linearity, gain and offset error.

SAMPLE AND HOLDS
○Acquisition Time: the time after the sampling command

issued and settling within the input signal
○Hold settling time: the time required for the sample and hold
to settle within the sampled value after hold command is
issued.

SAMPLE AND HOLDS
○The simplest sample and hold circuit is realized using a switch

and a capacitor.
○Usually, MOSFET is used as a switch.
○The capacitor holds the sampled value.
○In order to minimize the droop rate, a buffer circuit is added
between capacitor and output node.

MOS SAMPLE AND HOLD
○When the clock is high, V’ will follow Vin.

○When the clock goes low, V’ stays constant and its value is
equal to Vin at the instance clock went low.
○However, the channel charge Q1 must flow out from the gate
to source and drain of the MOS switch.

MOS SAMPLE AND HOLD
○The charge that flows to V’ node will half of the channel

charge
QCH Co xWLVeff Co xWL(VG S − VTH ) Co xWL(VDD − Vin − VTH )
Q = = = =
2 2 2 2
○This charge is also function of input signal and will generate

voltage change at the hold mode. Note that Q is due to the
C o xWL(VDD − Vin − VTH )

electron flow, therefore there
Q should be a minus sign when
V ' = =− voltage due to charge injection
C h ld 2C h ld is calculated
○This input signal dependence on the error voltage will create

nonlinearity.
○Compensating this charge will remove this input signal
dependency.
MOS SAMPLE AND HOLD
○Example:
● A sample hold circuit has the following parameters
● Chld=1pF
● Cox=1.92 fF/(µm)2
● VTH=0.8V
● W/L=5µm/0.8µm
● Power supply voltage is ±2.5V
● Input signal peak-to-peak amplitude is 1V
● Find the hold step voltage when input is 1V
● Find the hold step voltage when input is -1V

MOS SAMPLE AND HOLD
○Example:
○At Vin=1V
Q C WL(VDD − Vin − VTH ) 1.92  5  0.8(2.5 − 1 − 0.8)

V ' = = − ox =− = −2.69mV
Ch ld 2Ch ld 2  1000
Vh o ld = 1V − 2.69mV = 997.31mV
○At Vin=-1V
Q C WL(VDD − Vin − VTH ) 1.92  5  0.8(2.5 + 1 − 0.8)

V ' = = − ox =− = −10.37mV
Ch ld 2Ch ld 2  1000
Vh o ld = −1V − 10.37mV = −1.01037V

MOS SAMPLE AND HOLD
○To minimize the charge injection, the MOSFET switch can be

replaced by CMOS transmission gate.
○The idea behind this technique is to cancel the charge
flowing out from NMOS with the charge flowing out from
PMOS.
○This technique works best when input voltage is at the half of
the supply voltage.

MOS SAMPLE AND HOLD
○Another method is to use a dummy switch.

○In this technique, the channel charge flows out from the
MOS switch is captured by this dummy switch which is sized
as the half of the switch transistor.
○This technique requires also precise generation of the
opposite of the clock signal.

MOS SAMPLE AND HOLD
○ The input impedance of the sample and hold can be increased using an
opamp
○ During the sampling phase this circuit operates in unity gain feedback
configuration.
○ The feedback reduces the speed of the overall circuit
○ During hold mode the opamp will be in open loop configuration and its
output will go one of the supply rails. Therefore, it takes more time to
track the input signal when it switches to sampling mode.

MOS SAMPLE AND HOLD
○Slew time can be minimized by adding extra switches to put

the opamp in unity gain feedback mode even at the hold
mode.
○However, when Q1 is turns off there will be charge injection
to the hold capacitance, and the output voltage will be
changed.

MOS SAMPLE AND HOLD
○To make the voltages on hold capacitance is independent of

input voltage, another opamp is introduced.
○However, this configuration also have charge injection
problem.

MOS SAMPLE AND HOLD
○In order to reduce the hold pedestal, another capacitance is

added at the positive input of second opamp.
○Since this capacitance and hold capacitance has the same
value, the common mode rejection of the opamp eliminates
the effects of charge injection.

BANDGAP VOLTAGE REFERENCE
○ Constant reference voltage is one of the important circuits used in data

acquisition systems.
○ Using a voltage reference with an accurate resistor a stable dc current can
also be generated.
○ To generate constant voltage reference
● A zener diode can be used.
○ It
is a diode with a known breakdown voltage. Usually, this voltage level is around
5V, which is larger than power supply of modern IC technologies.
● Using the difference in the threshold voltages between an
enhancement and depletion mode transistor
○ Depletion mode transistor is not available in modern technologies
● Cancelling the negative temperature dependence of pn junction with a
PTAT (proportional-to-absolute-temperature) circuit

○A forward-biased base-emitter junction of a bipolar transistor

has the following I-V relationship
VBE
q
IC = I S e kT
○Is pan the saturation current and also has strong dependence
on temperature.

○The base-emitter voltage as a function of collector current

and temperature is
 T  T m kT  T0  kT  J C 
VBE = VG 0  1− +V
 + ln   + ln  

 T0 
BE 0 T
0 q T  q  JC 0 
○VG0 is the bandgap voltage of silicon at 0K and approximately

equal to 1.206V
○k is the Boltzmann constant, m is a temperature constant
approximately equal to 2.3.
○JC is the collector current density and T is the temperature at
kelvin.
○JC0 is the collector current density and VBE0 is the junction
voltage at the reference temperature T0.

○Note that the collector current is

I C = AE J C
○where AE is the emitter area.
○For constant IC, VBE is approximately -2mV/K around room
temperature.
○This negative temperature dependence is cancelled by PTAT
generated by the difference of two base-emitter junctions
biased at different current densities.
kT  J 2 
VBE = VBE , 2 − VBE ,1 = ln  
q  J1 

○Example:
○Calculate the difference of base-emitter voltages of two
transistors biased at a current density ratio of 10 at T=300K
kT  J 2  1.38  10 −2 3  300
VBE = ln   = −1 9
ln (10) = 59.5mV
q  J1  1.602  10
○Increasing the temperature by 1K increases the voltage by

0.198mV.
○Since the temperature dependence of a single VBE is -2mV/K,
base-emitter voltage difference must be amplified almost by
a factor of 10.

○The reference voltage is generated by

Vref = VBE 2 + KVBE
kT  T0  kT  J 2 
+ (VBE 0, 2 − VG 0 ) + (m − 1) ln  + K
T
= VG 0 ln 
T0 q T  q  J1 
○To get zero temperature dependence at a particular

temperature the Vref equation is differentiated and equaled
to zero
Vref k  J2  k   T0  
= (VBE 0, 2 − VG 0 ) + K ln   + (m − 1) ln   − 1
1
T T0 q  J1  q T  

○Setting T=T0, zero temperature dependence at the reference

temperature is obtained.
kT0  J 2  kT0
Vref = VBE 0, 2 +K ln   = VG 0 + (m − 1)
q  J1  q
○For T0=300K and m=2.3 Vref is 1.24V

○The required K value is
kT0
VG 0 + (m − 1) − VBE 0, 2
q 1.24 − V BE 0, 2
K= =
kT0  J 2   J2 
ln   0.0258 ln  
q  J1   J1 
○To obtain reference voltage value for temperatures different

from reference temperature
kT   T0 
Vref = VG 0 + (m − 1) 1 + ln  
q  T 
Vref k  T0 
= (m − 1) ln  
T q T 

○Example:
○Calculate the temperature dependence at 0C for a bandgap
voltage reference that was designed to have zero
temperature dependence at 20C
○0C corresponds to 273K and 20C corresponds 293K
Vref k  T0 
= (m − 1) ln  
T q T 
1.38  10 −2 3  293 
= (2.3 − 1) −1 9
ln   = 8mV / K
1.6  10  273 
○For a reference voltage of 1.24V the dependency is 8/1.24 =

6.5 ppm/K
CIRCUITS FOR BANDGAP REFERENCES
○Following voltage
reference is proposed
by Brokaw and basis
for many bipolar
bandgap references.
○Both transistors have
the same collector
currents, but Q2
current density is 8
times of Q1 current
J2
density. =8
J1

○The reference voltage is the sum of base-emitter voltage of

Q2 and voltage drop on R1 resistor.
Vref = VBE 2 + VR1

= VBE 2 + I R1 R1
= VBE 2 + 2I R 2 R1
○Current on R2 is
VR 2 VBE 2 − VBE1 VBE

I R2 = = =
R2 R2 R2

○The reference voltage becomes
2 R1
Vref = V BE 2 + V BE
R2
○Assuming VBE2 is 0.65V, the resistor ratios becomes
R1 1 1.24 − 0.65
=  = 5.5
R2 2 0.0258  ln (8)

CMOS BANDGAP REFERENCES
○In CMOS technologies independent bipolar transistors are

not available.
○Therefore, parasitic bipolar well transistors are used.

CMOS BANDGAP REFERENCES
○For nwell implementation (NPN)

R3
Vref = V EB1 + VEB
R2
R3 kT  R3 
= V EB1 + ln  
R2 q  R1 

LOW-VOLTAGE BANDGAP REFERENCES
○The bandgap circuits described in previous slides are not

compatible with supply voltages below 1.5V.
○The main reason for that is the voltage drop on pn junction
and PTAT voltage scaled to provide temperature
independence.
○The solution is summing currents instead of summing
voltages.

○VBE and VBE are converted to currents using resistors

Ra and Rb.
○The currents through diodes differ by a factor of M
and diode current densities differ by a factor of MN
○Therefore, the reference voltage is
 KR  kT  KR 
Vref = KI 2 R = VBE1   + ln (MNR ) 
 Ra  q  Ra 
○M, N, Ra and Rb values are chosen so that the reference
voltage is independent of temperature at a reference
temperature.
○This circuit allows supply voltages as low as 0.8V.

CURRENT REFERENCE
○Once bandgap reference voltage is obtained, it can be used

with a precise resistor to generate temperature independent
current reference.
○Usually this resistor is off-the-chip.

○If it is an internal resistor, it is usually trimmed after
manufacturing.

VOLTAGE REGULATION
○Sensitive analog circuits require clean, low noise supply

voltage for proper operation.
○To regulate the supply voltage a voltage regulator is used.

COMPARATOR
○Comparator is used to detect whether a signal is greater or

smaller than another signal.
○They used in many applications such as, ADC, switching
power regulators, PWM generators, etc.
○Many circuits are used as comparators
● Operational Amplifiers operating in open-loop configuration
● Multi-stage amplifier/comparator
● Positive feedback track-and-latch comparator
○Comparators suffer
● Input offset
● Charge injection error

INPUT OFFSET, NOISE AND HYSTERESIS
○ Input Offset:
● The input voltage at which its output changes from one logic to the
other.
● In an ideal comparator this will be at zero for dual supply and half of
the supply voltage for single supply.
○ Noise:
● Noise can cause the output of comparator to change even its input is
kept constant.
○ Hysteresis
● Most comparators have tendency to remain in their past state.
● This memory effect is due to the internal capacitances of the
comparator.
● Generally, hysteresis is unwanted in comparators and should be
minimized.

OPAMP AS A COMPARATOR
○ The simplest comparator is an opamp used in open-loop configuration.

○ The main drawback is the slow response time of opamp causes slow
settling.
○ During 1 (reset phase) the capacitor is connected to ground.
○ During 2 (comparison phase) the opamp is in open-loop configuration
and depending on the input voltage opamp output goes to negative
supply for negative input voltage and positive supply for positive input
voltage.

○Example:
● A 0.2mV signal must be resolved using opamp based comparator.
The positive supply voltage is 2V. Calculate the maximum clocking
rate if opamp’s unity gain frequency is 10MHz.
● Assume 6 time constants is required for settling.
○Solution
● For 2V output and 0.2mV input, the opamp gain must be at least
10000 V/V
● The 3-dB frequency is
ft
f 3d B = = 1kHz
A0

○Solution
● During the comparison phase, the output of the opamp will show a
transient response similar to first order system
1
= = 0.16ms
2f 3d B
● For 6 time constants, the settling time will be approximately 1ms.
● Assuming reset phase also requires the same amount of settling
time as the comparison phase, maximum clocking rate will be
500Hz.

○One method to improve the speed of opamp is to remove

compensation capacitor during comparison phase.
○Using this technique the clock frequencies ten to fifty time
greater than would otherwise is possible.

○Input offset is not

a problem for the
architecture, since
input offset is
stored on the
capacitor during
reset phase and
subtracted during
comparison phase.

○Charge Injection Errors

● The major limitation on the resolution of comparators the charge-
injection error, which is also called as clock feedthrough error.
● This error is due to the injection of unwanted charges to the circuit
when the switch transistors are turned off.

○This charge injection error can be minimized by various

circuit techniques.
○One of the technique is using fully differential circuit to
cancel the charge injection by differential operation.

LATCHED COMPARATORS
○Modern high speed comparators have one or two stages of

preamplification followed by a track-and-latch stage.

LATCHED COMPARATORS
○In this architecture, the preamplifier are used to obtain higher

resolution and to minimize the effect of kickback.
○Although the output level of preamplifier is larger than its
input level, it is not enough to drive digital circuits.
○The track-and-latch stage further amplifies the signal during
track phase and amplifies further it during latch phase using
positive feedback.
○The preamplifier gain is usually 2 to 10. If the gain is selected
is higher than 10, it will be limited by its speed.

LATCHED COMPARATORS
○Kickback is the charge transfer either into or out of the

inputs when track-and-latch stage goes from track mode to
latch mode.
○Without preamplifier, this charge will be entered to the
driving circuitry and disturbs the voltages at the input.
○One important consideration is to ensure that no memory is
transferred from one decision cycle to the next.
○This is achieved by resetting different stages before entering
track mode.

EXAMPLE
○Two-Stage Latched Comparator

EXAMPLE
○Simple CMOS Comparator

EXAMPLE
○Current Steering Comparator

EXAMPLE
○A 7GHz 1mV-Input-Resolution Comparator with 40mV-Input

Referred-Offset Compensation Capability in 65nm CMOS,
IEEE CCECE 2011

EXAMPLE
○A 16-GHz Ultra-High-Speed Si-SiGe HBT Comparator, IEEE

JSSC, Sept. 2003

Analog & Mixed Signal Circuits: Adc and Dac

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ANALOG & MIXED SIGNAL

ADC and DAC

○Digital to Analog Converter (DAC) is used to convert digital

© Burak Kelleci - 2023 ADC and DAC 2

○Nyquist-Rate converters operate ideally at the twice of the

© Burak Kelleci - 2023 ADC and DAC 3

○Oversampling converters operate at much higher rate than

© Burak Kelleci - 2023 ADC and DAC 4

String Binary Interpolating Delta Sigma

© Burak Kelleci - 2023 ADC and DAC 5

○Bin is the N-bit digital signal (word)

○The output signal is related to the Vref

○VLSB is the voltage change when one

○Following input is applied to a 4-bit DAC with 5V Vref.

© Burak Kelleci - 2023 ADC and DAC 7

Interpolating Delta Sigma

Successive Approximation Converter First-Order Low-Pass

Algorithmic Second-Order Low-Pass

Pipelined ADC Band-Pass Modulator

© Burak Kelleci - 2023 ADC and DAC 8

○Bin is the N-bit digital signal (word)

Vin  Vq = Vref b1 2−1 + b2 2−2 +  + bN 2− N = Vref Bin 10

○Vq is the quantization error 00

1 1 Note that maximum value

○Quantization error occurs even in ideal ADC.

○Example: A sinusoidal signal with an amplitude of 100mV is

© Burak Kelleci - 2023 ADC and DAC 11

© Burak Kelleci - 2023 ADC and DAC 12

● Since it is a serial communication, increasing number of bits slows

© Burak Kelleci - 2023 ADC and DAC 13

© Burak Kelleci - 2023 ADC and DAC 14

○LVDS (Low Voltage Differential Signaling)

© Burak Kelleci - 2023 ADC and DAC 15

○In some applications, data is sent in parallel as nibbles (4-bits).

© Burak Kelleci - 2023 ADC and DAC 16

© Burak Kelleci - 2023 ADC and DAC 17

● In ADC, offset error is defined as the deviation of V0…01 from ½

© Burak Kelleci - 2023 ADC and DAC 18

○The gain error is defined to be the difference at the full-scale

© Burak Kelleci - 2023 ADC and DAC 19

○Offset and Gain Error in DAC

1/2 Gain Error

© Burak Kelleci - 2023 ADC and DAC 21

○Offset and Gain Error in ADC

 VLS B VLS B   0.625 0.625 

© Burak Kelleci - 2023 ADC and DAC 23

○INL is defined as the deviation of transfer response from

© Burak Kelleci - 2023 ADC and DAC 24

○INL for DAC and ADC

© Burak Kelleci - 2023 ADC and DAC 25

○In an ideal data converter, each step size corresponds 1 LSB.

© Burak Kelleci - 2023 ADC and DAC 26

© Burak Kelleci - 2023 ADC and DAC 27

○For example, the scaled value of 0.626 is

○The scaled values are

© Burak Kelleci - 2023 ADC and DAC 28

© Burak Kelleci - 2023 ADC and DAC 29

○Let’s show INL and DNL of previous example.

Max DNL: 0.1568 Max INL: 0.1568

© Burak Kelleci - 2023 ADC and DAC 30

© Burak Kelleci - 2023 ADC and DAC 31

○Absolute accuracy is calculated using the largest deviation

© Burak Kelleci - 2023 ADC and DAC 32