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  • HDL Experiment8

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    choudharyarjun1121
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    This document describes experiment 8 which aims to implement a J-K flip flop using Verilog. It provides the code for a module that uses a case statement to update the output q on each clock pulse based on the inputs jk and rst, following the truth table behavior of a J-K flip flop. A circuit diagram and sample waveform are also referenced but not shown.

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    HDL_EXPERIMENT8

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    This document describes experiment 8 which aims to implement a J-K flip flop using Verilog. It provides the code for a module that uses a case statement to update the output q on each clock pulse based on the inputs jk and rst, following the truth table behavior of a J-K flip flop. A circuit diagram and sample waveform are also referenced but not shown.

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    © All Rights Reserved
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    3 views2 pages

    HDL Experiment8

    Uploaded by

    choudharyarjun1121
    This document describes experiment 8 which aims to implement a J-K flip flop using Verilog. It provides the code for a module that uses a case statement to update the output q on each clock pulse based on the inputs jk and rst, following the truth table behavior of a J-K flip flop. A circuit diagram and sample waveform are also referenced but not shown.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 2

    EXPERIMENT:- 8

    AIM: - Implement J-K Flip Flop using Verilog.

    Code: -

    module jkflipflop(q,qbar,clk,rst,jk);
    output reg q;
    output qbar;
    input clk, rst;
    input [1:0] jk;

    assign qbar = ~q;

    always @(posedge clk)


    begin
    if (rst)
    q <= 0;
    else
    case(jk)
    2'b00: q <= q;
    2'b01: q <= 0;
    2'b10: q <= 1;
    2'b11: q <= ~q;
    endcase
    end
    endmodule
    Circuit Diagram: -

    Waveform: -

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