FPGA/ CPLD LAB

EXPERIMENT 13
AIM : To design and simulate the given sequential circuit shown in diagram using Verilog HDL.
EDA TOOL USED : Xilinx ISE 8.1i
METHODOLOGY : The circuit is implemented using two JK flip-flops having the same clock
and an input x which will be used to decide the next state of the circuit. The J and K inputs of the
two flip-flops are designed from the state table using the excitation table and K-map reduction. This
technique is used in complex machines where the different processes can be considered as the
different states of the machine.
State Diagram :

Fig. 13.1 State diagram of given problem

Block diagram :

Fig. 13.2 Block diagram of given problem

VERILOG CODE :
module jk(clk,j,k,q);
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FPGA/ CPLD LAB

input clk,j,k;

output reg q;

initial begin q<=1'b0;

end

always@(posedge clk)
begin

q<=((j&(~q))+((~k)&q));

end

endmodule
module seqct(clk,x,q);
input clk,x;

output [1:0]q;

jk j1(clk,1,1,q[1]);

jk j2(clk,~x,(q[1]^x),q[0]);

endmodule

RTL SCHEMATIC VIEW :

Fig. 13.3 RTL schematic of given problem

OUTPUT WAVEFORM :

Fig. 13.4 Output waveform of given problem

RESULT : The given sequential circuit problem is successfully implemented and its operation is
verified by simulation.

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