FPGA/ CPLD LAB

EXPERIMENT 6
AIM : To design a 16:1 multiplexer using a 4:1 multiplexer at the dataflow and behavioural levels.
EDA TOOL USED : Xilinx ISE 8.1i
METHODOLOGY : 16:1 Mux is a combinational circuit having 16 input lines from I0 - I15
and 4 select lines from S0 S3. On the basis of select lines it is decided which input will be
transmitted to output. Large multiplexers can be implemented by using smaller size multiplexers. On
the basis of this theory, 16:1 mux can be designed by using five 4:1 muxes as shown in figure.
Logic Symbol :

Fig. 6.1 Logic symbol of 16 : 1 MUX

Truth Table:
Select lines
S3
S2
S1
S0
0
0
0
0
0
0
0
1
0
0
1
0
Block
Diagram
:
0
0
1
1
0
1
0
0
Fig.
6.2
Block
0
1
0
1
0VERILOG
1
1
0
0
1
1
1
Dataflow
level
module
input

Output

Output

(Y)
I0
I1
I2
I3
I4
I5
I6
I7

(Y)

diagram of 16 : 1 MUX

CODE :
Modelling

Selec

muxd2(I0, I1, I2, I3, S0, S1, Y);

I0,I1,I2,I3,S0,S1; output Y; assign

lines
S3

S2

S1

S0

endmodule

I8

module

I9

muxg(I, S, Y);

input [15:0]

I10

I;

I11

I12

I13

030

I14

I15

{Y}=S0?(S1?

y1,y2,y3,y4;
muxd2

I3:I1):(S1?I2:I0);

input [3:0] S;

output Y;

wire

m1(I[0],I[1],I[2],I[3],S[0],S[1],y1);

FPGA/ CPLD LAB

muxd2 m2(I[4],I[5],I[6],I[7],S[0],S[1],y2);
muxd2 m3(I[8],I[9],I[10],I[11],S[0],S[1],y3);
muxd2 m4(I[12],I[13],I[14],I[15],S[0],S[1],y4);
muxd2 m5(y1,y2,y3,y4,S[2],S[3],Y);
endmodule
Behavioural level Modelling
module muxb(I,S,Y);
input [3:0]I; input [1:0]S; output reg Y;
always@(I,S)
begin
case(S)
0: begin Y=I[0]; end

1: begin Y=I[1]; end

2: begin Y=I[2]; end

3: begin Y=I[3]; end

endcase

end

endmodule

module mux(I, S, Y, F);

input [15:0] I; input [3:0] S; wire [3:0]Y; output F;
muxb(I[3:0],S[1:0],Y[0]); muxb(I[7:4],S[1:0],Y[1]); muxb(I[11:8],S[1:0],Y[2]);
muxb(I[15:12],S[1:0],Y[3]); muxb(Y[3:0],S[3:2],F);
endmodule

RTL SCHEMATIC VIEW :

Dataflow level Modelling

Fig 6.3

RTL schematic of 16 : 1 MUX

Behavioural level Modelling

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FPGA/ CPLD LAB

Fig 6.4

RTL schematic of 16 : 1 MUX

OUTPUT WAVEFORM :

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FPGA/ CPLD LAB

Fig 6.5

Output waveform of 16 : 1 MUX

RESULT : Successfully implemented 16 : 1 multiplexer using 4 : 1 multiplexer modules and

verified its operation through simulation.

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