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BR93LC66 - Rohm
BR93LC66 - Rohm
•• Features
Low power CMOS Technology
•Pin assignments
CS 1 8 VCC NC 1 8 N.C.
• 256 × 16 bit configuration
• 2.7V to 5.5V operation SK 2 7 N.C. VCC 2 7 GND
BR93LC66 / BR93LC66F /
• Low power dissipation BR93LC66RF BR93LC66FV
DI 3 6 N.C. CS 3 6 DO
– 3mA (max.) active current: 5V
– 5µA (max.) standby current: 5V DO 4 5 GND SK 4 5 DI
•TheOverview
BR93LC66 series are CMOS serial input / output-type memory circuits (EEPROMs) that can be programmed
electrically. Each is configured of 256 words × 16 bits (4096 bits), and each word can be accessed individually and
data read from it and written to it.
Operation control is performed using five types of commands. The commands, addresses, and data are input
through the DI pin under the control of the CS and SK pins. In a write operation, the internal status signal (READY or
BUSY) can be output from the DO pin.
1
Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV
•Block diagram
Power supply
Control
High voltage
Write disable
generator
SK Clock generation
Address Address
8bit
Command buffer decoder 8bit
DI
register
4096bit
2
Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV
3
Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV
•(1)Circuit operation
Command mode
With these ICs, commands are not Start Operating
Command Address Data
recognized or acted upon until the bit code
start bit is received. The start bit is Read (READ)∗1 1 10 A7 ~ A0 —
taken as the first “1” that is received Write Enabled (WEN) 1 00 11XXXXXX —
after the CS pin rises.
Write (WRITE)∗2 1 01 A7 ~ A0 D15 ~ D0
∗1 After setting of the read command
Write to All Addresses (WRAL)∗ 2 1 00 01XXXXXX D15 ~ D0
and input of the SK clock, data corre-
sponding to the specified address is Write Disabled (WDS) 1 00 00XXXXXX —
4
Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV
For low voltage operation (unless otherwise noted, Ta = – 40 to 85°C, VCC = 3V ± 10%)
Parameter Symbol Min. Typ. Max. Unit
SK clock frequency fSK — — 250 kHz
SK "H" time tSKH 1 — — µs
SK "L" time tSKL 1 — — µs
CS "L" time tCS 1 — — µs
CS setup time tCSS 200 — — ns
DI setup time tDIS 400 — — ns
CS hold time tCSH 0 — — ns
DI hold time tDIH 400 — — ns
Data "1" output delay time tPD1 — — 2 µs
Data "0" output delay time tPD0 — — 2 µs
Time from CS to output confirmation tSV — — 2 µs
Time from CS to output High impedance tDF — — 400 ns
Write cycle time tE / W — — 25 ms
When reading at low voltage (Unless otherwise noted, Ta = – 40 to 85°C, VCC = 2.0V)
5
Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV
CS
SK
tDIS tDIH
DI
DO (READ)
tDF
6
Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV
CS
∗1
1 2 4 11 12 27 28
SK
DI 1 1 0 A7 A6 A1 A0
∗2
DO 0 D15 D14 D1 D0 D15 D14
High-Z
∗1 If the first data input following the rise of the start bit CS is "1", the start bit is acknowledged. Also, if a "1" is input following several zeroes in succession,
the "1" is recognized as the start bit, and subsequent operation commences. This applies also to all commands described subsequently.
∗2 Address auto increment function: These ICs are equipped with an address auto increment function which is effective only during reading operations.
With this function, if the SK clock is input following execution of one of the above reading commands, data is read from upper addresses in succession.
CS is held in HIGH state during automatic incrementing.
CS
SK
DI 1 0 0 1 1
DO
High-Z
7
Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV
CS tCS STATUS
1 2 4 11 12 27
SK
DI
1 0 1 A7 A6 A1 A0 D15 D14 D1 D0
tSV
DO BUSY READY
High-Z
tE / W
CS tCS STATUS
1 2 5 12 27
SK
DI
1 0 0 0 D15 D14 D1 D0
tSV
DO BUSY READY
High-Z
tE / W
CS
SK
DI 1 0 0 0 0
DO
High-Z
8
Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV
•(1)Operation notes
Cancelling modes
〈READ〉
〈WRITE, WRAL〉
a b
Fig.7
9
Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV
VCC
GND
DI 0 1
+ 5V
a b CS
GND
Fig.8 Timing during erroneous operation Bad example Good example
DI 0 1
(4) Clock (SK) rise conditions
b
If the clock pin (SK) signal of the BR93LC66 / BR93LC-
66A has a long rise time (tr) and if noise on the signal
Fig.9 Timing during normal operation
line exceeds a certain level, erroneous operation can
(3) Precautions when turning power on and off occur due to erroneous counts in the clock. To prevent
When turning the power supply on and off, make sure this, a Schmitt trigger is built into the SK input of the
CS is set to LOW (see Figure 10). BR93LC66. The hysteresis amplitude of this circuit is
When CS is HIGH, the EEPROM enters the active set to approximately 0.2V, so if the noise exceeds the
state. To avoid this, make sure CS is set to LOW (dis- SK input, the noise amplitude should be set to 0.2VP-P
able mode) when turning on the power supply. or lower. Furthermore, rises and falls in the clock input
(When CS is LOW, all input is cancelled.) should be accelerated as much as possible.
When the power supply is turned off, the low power (5) Power supply noise
state can continue for a long time because of the The BR93LC66 discharge high volumes of high voltage
capacity of the power supply line. Erroneous opera- when a write is completed. The power supply may fluc-
tions and erroneous writing can occur at such times for tuate at such times. Therefore, make sure a capacitor
the same reasons as described above. To avoid this, of 1000pF or greater is connected between VCC (Pin 8)
make sure CS is set to LOW before turning off the and GND (Pin 5).
power supply.
10
Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV
11
Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV
9.3 ± 0.3
5.0 ± 0.2
8 5
6.5 ± 0.3
8 5
6.2 ± 0.3
4.4 ± 0.2
1 4
0.15 ± 0.1
7.62
0.51Min.
1 4
3.2 ± 0.2 3.4 ± 0.3
1.5 ± 0.1
0.3 ± 0.1
0.11
1.27 0.4 ± 0.1 0.3Min.
2.54 0.5 ± 0.1 0°~15°
0.15
DIP8 SOP8
BR93LC66FV
3.0 ± 0.2
8 5
6.4 ± 0.3
4.4 ± 0.2
0.15 ± 0.1
1 4
1.15 ± 0.1
0.1
0.1
SSOP-B8
12