E3-301 Special Topics In Nano-Electronics

Report On
Study of LDMOS Structure, design, current-
voltage configuration and enhancement of
power device using different techniques
Abstract - The Lateral Diffused Metal Oxide elevated power dissipation at a given voltage [1]. Fig.
Semiconductor (LDMOS) represents a significant 1(a) illustrates the LDMOS device, while Fig. 1(b)
power device capable of exhibiting breakdown depicts the extension of drain length. The
voltages ranging from 25V to several hundred conventional LDMOS current configuration is
volts. LDMOS finds extensive utility within power delineated in Fig. 1(c), contrasting with the extended
electronics applications, notably in motor, display, drain length current configuration represented in Fig.
LED drivers, automotive systems, and various 1(d). The observed increase in breakdown voltage is
industrial sectors necessitating high voltage and visually evident in Fig. 1(d) [2]
current requirements. This paper undertakes a
comprehensive review of literature concerning
LDMOS devices and associated technologies
contributing to their high-power characteristics.
Basic structure of LDMOS and current a b
configuration is tests using TCAD sentaurus.
Furthermore, the report addresses Electrostatic
Discharge (ESD), a pervasive phenomenon and
prevalent failure mode within semiconductor
industries, proposing enhanced LDMOS as a
viable solution for mitigating ESD-induced c d
failures. Technology such as RESURF where the
trade-off between On-resistance and breakdown Fig. 1. LDMOS structure and graph representing breakdown
voltage and enhanced current using field plates voltage VS Drift Length. (a) LDMOS with drift length of 0.3um
over LDMOS is also being discussed. (b) LDMOS with drift length of 0.6um (c) LDMOS with drift
length of 0.9um
Key-words:- DeNMOS (drain extended N type
metal oxide semiconductor), LDMOS (laterally
diffused metal oxide semiconductor), BJT(bipolar Conforming to this progression towards heightened
junction transistor) breakdown voltage entails a simultaneous rise in on-
I. INTRODUCTION resistance, necessitating a reduction in the doping
concentration of the p-well or n-well regions [3]. The
In this investigation, attention is directed towards the methodology employed to balance the trade-off
Lateral Diffused Metal Oxide Semiconductor between breakdown voltage and on-resistance is
(LDMOS) power device, wherein modifications in denoted as the Reduced Surface Field (RESURF)
current-voltage characteristics are achieved through technology. Beyond this a limitation of the previous
an extension of the drain length, often referred to as papers [4] is also being discussed either in the form
DeNMOS. The augmentation of breakdown voltage of increased capacitance and latchup behavior in the
is accompanied by an increase in the device's on- device.
resistance due to the extended drain length, leading to
 II. (A) LATCHUP CONDITION IN
RESURF LDMOS
Latchup is a phenomenon observed in devices
featuring PNP and NPN bipolar junction transistors,
and it is particularly prevalent in Lateral Diffused
Metal Oxide Semiconductor (LDMOS)
configurations [5]. This occurrence can lead to the
failure of devices operating under high voltage
conditions, such as during Electrostatic Discharge
(ESD) events or snapback at low voltages. The
introduction of a p-implant in LDMOS to facilitate
the Reduced Surface Field (RESURF) effect
exacerbates latchup propensity by augmenting doping
levels in the n-well, as depicted in Fig. 2(a) [5].
While the specific conditions fostering latchup in
RESURF or with additional p-implants have not been
thoroughly investigated, there exists a promising
avenue for future research and experimentation due
to the presence of additional doping layers and
junctions akin to Bipolar Junction Transistors (BJTs).
––
a exists considerable scope for research in this domain.
b d
Fig. 2. LDMOS with RESURF effect and small junctions to show
n-well and p-well for demonstration. (a) LDMOS with RESURF-
implant (b) npn transistor. (c) pnp transistor.
Fig. 3(a,b) illustrate conventional LDMOS
configurations where latchup predominates,
facilitating comprehension through the elucidation of
the extracted BJT PNP-NPN configuration under
forward biasing conditions [5].
a b
Fig. 3. (a) Showing the conventional LDMOS and its parasitic
BJT, pnp and npn. (b) simplified circuit diagram of BJTs
II. (B) Capacitance increment in RESURF
and p-implant
b
a c
Fig. 4. (a) Showing the LDMOS with RESURF implant and Buried
Oxide. (b) curves showing the breakdown voltage VS drift length
(c) capacitance curve with drift length variation.
In Fig. 4(a), the augmentation of capacitance within
the device is demonstrated as additional layers are
incorporated [6]. A notable breakdown in capacitance
occurs proximal to the junction of the buried oxide,
where a significant portion of depletion takes place.
The emergence of capacitance within the device
introduces a deceleration in operational speed. Fig.
4(b) illustrates the relationship between breakdown
voltage and increased drain length, with the gate
length held constant. Likewise, Fig. 4(c) delves into
the exploration of capacitance, revealing that greater
drain lengths correspond to heightened capacitance
levels for equivalent voltages [6]. Presently, the
capacitance behavior of LDMOS devices featuring p-
implants and RESURF technology remains
unexplored practically on Technology Computer-
Aided Design (TCAD) platforms, although there
III. RESURF TECHNOLOGY
RESURF technology represents a methodological
approach aimed at enhancing the breakdown voltage
of a semiconductor device while concurrently
minimizing its On-Resistance. This enhancement is
achieved through the introduction of an epitaxial
layer onto the substrate, whether it is of p or n type,
thereby promoting the dispersion of the electric field
across two depletion junctions, as depicted in Fig.
4(b) [3]. In essence, RESURF technology serves as a
strategic intermediary, facilitating a balance between
On-Resistance and breakdown voltage. However, it is
pertinent to acknowledge a drawback associated with
this approach: the introduction of an additional
implant layer invariably escalates junction
capacitance, thereby posing a challenge in device
performance optimization.

Fig. 5. (a) RESURF-epi LDMOS (b) graph of non-RESURF and
RESURF LDMOS for comparison electric fields.
improvement in breakdown voltage, followed by
saturation at a specific value. This saturation
phenomenon occurs because no further broadening of
the electric field takes place beyond a certain length
of the gate field plate. Moreover, the extent of
electric field shift and broadening significantly
depends on the doping level within the N-well. As
evidenced in Fig. 8(b), the maximum enhancement
occurs at a specific N-well doping level.

IV. FIELD PLATES DESIGN FOR

CURRENT ENHANCEMENT FOR
V. ELECTROSTATIC DISCHARGE
SAME CONVENTIONAL LDMOS
DESIGN CIRCUIT USING LDMOS
In earlier work the enhancement of a LDMOS device
In scholarly discourse, divergent viewpoints may
is being due to low doping for higher breakdown [7].
arise regarding the efficacy of breakdown voltage in
Is already been studied, in consequence of which On-
Electrostatic Discharge (ESD) protection for circuits.
Resistance is increased very significantly having high
Some assert that a lower breakdown voltage is
affects on static power consumption. As a solution to
advantageous for ESD protection, as evidenced by
this a RESURF technology s been introduced which
reference [8], while others advocate for higher
increases the breakdown of LDMOS and increase the
breakdown and snapback mechanisms to enhance
conductance by decreasing the On-Resistance, due to
circuit protection, as indicated in reference [9]. This
increase in the conduction the chance of failure of the
apparent contradiction can be reconciled by
device at the contact is being increased due to which
considering the specific characteristics and
the method of field plate is been introduced.
requirements of the circuit in question. For instance,
as illustrated in Fig. 5(a), a circuit may feature
designated input and output pads intended for ESD
protection. In scenarios where a device exhibits
higher breakdown with minimal current flow, there is
a risk that the current may not adequately traverse
through the protective clamp, leading to potential
failure of the main internal circuit. Consequently, to
Fig. 6. Conventional LDMOS
ensure effective ESD protection, it may be necessary
Fig 8(a) showing the application of field plate on the to design the protective clamp device with a lower
device which enhance the current conduction in 2d breakdown voltage, thereby facilitating conduction
LDMOS surface. Field plate (Fp) also extends the through this component alone.
electric field both laterally and vertically, thus
reducing the peak field at the n-well surface, due to
which the overall electric field in the n-well region is
modulated (higher area under the electric field curve,
higher the voltage). Therefor the impact ionization at
the p-n junction substantially gets migrated, which
pushes the device to higher voltage[4].
Fig. 7. Circuit diagram of low breakdown voltage ESD protection
In the absence of a field plate, the electric field within circuit.
the device tends to peak near the edge of the gate.
Conversely, devices featuring higher breakdown
However, with the introduction of a gate field plate,
voltages can also serve in ESD protection circuits.
the termination of field lines extends towards this
When subjected to electrostatic charges, these
plate. Consequently, the breakdown of the device
devices may experience forward biasing, facilitating
occurs at a relatively higher voltage. As illustrated by
an easy path for current flow. Conversely, if the
the field profile in Fig. 8(a), an increase in the length
electrostatic charge induces reverse biasing, the path
of the gate field plate initially leads to an
Fig. 8. Showing the electric field distribution of different LDMOS devices. Impact of (a) Gate field plate length, (b) Source field plate and (c)
Drain field plate
for current flow becomes more challenging [9].
Furthermore, employing higher snapback voltages
provides an alternative approach to enhancing ESD
protection by inducing a "fail to protect" condition.
However, in the context of Transient Latchup (TLP)
measurements, a study reported in [9] observed a
“decrease in current attributed to RESURF-implant
presence, due to higher On-Resistance (RON)
compared to conventional devices”. This finding
contradicts those documented in [3][4][5][7]. The
discrepancy arises from the positioning of the
RESURF-implant; instances of lower current entail a
deeper placement of the RESURF-implant, while
higher current scenarios feature a surface-level
implantation.
Fig. 9. Curve of LDMOS with snapback voltage and breakdown
voltage
In Fig. 9(a), it is observed that the snapback trigger
exhibits an upward trend alongside an increase in the
drift length of the device. From this observation, it
can be inferred that an augmentation in drift length
correlates with elevated snapback and breakdown
voltages within the LDMOS device. Notably, the
breakdown voltage consistently remains lower than
the snapback trigger voltage, indicating that snapback
occurs prior to breakdown. This phenomenon
underscores the role of snapback mechanisms in
facilitating Electrostatic Discharge (ESD) protection
for the device.
VI. CONCLUSION
In this report different aspects of a device is been
studied. Device such as LDMOS or DeNMOS having
higher breakdown voltage compared to MOSFETS
using techniques such as RESURF-implant, field
plates and structural engineering we can modify
devices to have even higher breakdown voltage.
Also, in this report some contradicting concepts is
also been explained and trying to prove through
theoretical concepts. With the reference of several
papers, some limitations of the paper is also been
shown and try to explain through the theoretical
concepts such as latchup condition in RESURF-
implant LDMOS and increase of capacitance in the
device. Papers explaining about the different trade-
off such as RON and breakdown voltage is well
explained in this report. In the last topic the ESD
behavior of the device is also been explained, also
contradicting papers[9] and [3][4][5][7] have the
different approach to gate protected from ESD in a
device.
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