15P5D'2000. May Z2-25.Toulouse.
France
LDMOS IMPLEMENTATION I
N A 0.35 pm BCD TECHNOLOGY (BCD6)
A. Moscatefi, A. Merlini, G. Croce, P. Galbiati, C. Contierol
STMicroelectronics, T P A Group
Via C.0livetti 2, 2004 1 A g a t e Brianza, 'Via Tolomeo I , 200 10 Cornaredo, (Milano) Italy
(Tel. : +39-039-603-6829, Fax: +39-039-603-523 3)
E-mail alessandro.moscatelli@st.com
Abstrad-This paper presents the integration approach followed
to implement power LDMOS' up to 60V into a 0.35pm process
technology (BCD6) based on a CMOS plus Flash-Memory
platform of eqnivalent lithography generation, built on a P-
over P+ snbstrate.
Experimental results on LDMOS' in terms of on-state specific
resistance, off and on-state breakdown voltage, frequency
behavior will be described analyzing the interactions between
low voltage ULSI platform and high voltage power elements.
1. INTRODUCTION
The electronic consumer market is today strongly dominated
by portables that are becoming more and more sophisticated
and multimedia oriented. These systems are characterized by
having digital cores (microprocessor or DSP), all the
peripherals like display, RF interface, memory and, of key
importance, power management.
The computation power reached by microprocessor
technology is today good enough for many applications,
while improvements are continuously requested in memory
density and in battery energy conversion efficiency and
management. Big memory banks are required by
multimediality functions like internet connection on the
cellular phone, image recorder, voice recognition, GPS
image processing. All these features in a portable are
justified only if the total system is able to powerfully perform
the battery power management and the energy conversion
with high efficiency. Concerning peripherals displays with
back light illumination are a feature that require high
voltage driving. This has an impact on the technology
evolution that cannot forget high performance HV
components allowing efficient DC/DC converter.
In the field of energy management and battery charging lots
of improvements have been done in just few years. Thanks to
the more and more dense digital blocks all the controlling
h c t i o n s and algorithms can be executed with the minimum
power consumption typical of the CMOS circuitry. These
fimctions are today performed with very cheap and reliable
systems based on complex microprocessor or DSP cores.
To answer to the requirements of these fast growing
electronic markets. RCD6 has been developed having on
board 0.35pm CMOS, high density non volatile memories
and HV components with very small parasitic capacitance to
realize very high efliciency switching power converters.
In developing a high performance digital-analog-power
technology like BCD6 the usual arising key question is:
"how to implement high voltage and power dements onto a
fine lithography feature technology?". This paper will
provide an answer concerning LDMOS device
implementation.
0-7803-6269-1/OO/$lO.OO ,Q2000 IEEE
11. LDMOS BODYARCHITECTURE
AND RESULTS
BCD6 is based on a 0 . 3 5 p CMOS platform with twin
retrograde wells plus buried N-well (called triple-well) built
on a P-/P+ substrate without adding any specific epitaxial
layer growth and junction isolation steps as used in previous
smart power process generations. Thin gate oxide (7nm) and
double flavored gates are used both for 3.3V CMOS and
LDMOS devices.
To guarantee full compatibility with the 0.35pm CMOS
process platform both N-channel and P-channel Power
LDMOS body regions are realized by means of a large angle
tilt Boron implantation [l] self-aligned to the gate, masked
by photo-resist.
Different tilt angles with different doses and energies have
been tried to 6nd the best compromise between lateral and
vertical junction depths and doping charge in order to avoid
source to drain PT limitation, to minimize Drain Induced
Barrier Lowering (DIBL) and Torcurrent, to achieve a low
threshold voltage. Table land 2 show the effect of body
implant tilt angle and dose on electrical parameters, in case
of 20V LDMOS.
120" / 1.5~4mtations 1 I I 520 I 180 I 24.5 I
25.5
30" /1.5x4mt~lons 0.4I I 755
** Values measured on a 0 Smm' power area
I 170 1 26
VGS=3 3V
Tab. 1 Effect of' body implant tilt angle and dose on e l e h c a l
parameters. in case of20 V I_DMOS
For the experimented body implant conditions no channel
punch-through has been observed and the same BVms value
has been measured. Roc parameter too is not affected by the
body region characteristic as, in DMOS device with lateral
structure, the channel resistance contribute is negligible
respect to the drift region one.
Only a weak effect of tilt angle and dose has been detected
on DIBL. In fact though channel length is short (0.3pm,
from process simulation) a reduced DlBL is achieved thanks
to the LDMOS architecture: the voltage drop is completely
sustained by the low doped drain side. without modifying the
channel potential.
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 Tilt / 1°C (fA/pm) 1°K(pNmm2) '
Dose (e 13) cm-2 T=27"C T= 150°C
@Vds=20V @Vds=20V

I 20"/2.5~4mlallons I 2 I 3 I
I 3~"/1.5~4mwns I ~

7 8 1

In all the cases considered the measured Ian value is always

below the target value used for advanced CMOS (IpNpm)
but it results one order of magnitude higher than in previous
BCD generation (BCD5) [I].
The 1,s dependence on P-body implant conditions points out
that the channel diffusion current is a significant &action of
the off state current. Moreover part of this increase is due to
the BCD6 higher buried-layer/substrate leakage current
because the use of a low doped P- epi substrate (12 Qxcm)
enhances junction leakage current with respect to BCDS P
substrate (2 Qxcm).
Since recently LDMOS device has been successhlly used in
RF power amplifier for wireless communication applications
[2, 31, cut-off frequency has to be considered another key
parameter. The peak values of Ft have been measured for the
previous P-body implants on dedicated structures and are
compared in the Tab. 3. The fastest measured DMOS
exhibits a peak value of about I7Ghz.
Tilt /Dose (e13) cm-2 I Ft (GHz)
30" / 1.5 x 4 rotations I 15
I 20" / 2 x 4 rotations I 15.7
I 20" / 1.5x 4 rotations I 17.3
Tab. 3 Cut-off liequency for various P-body implant conditions.
Changing the tilt implant angle from 30 to 20 degrees, the
gate-source capacitance reduces and Ft increases.
As far as the dose is concerned, the lower it is, the higher is
the electron mobility and the resulting device Ft. The
P-body profile maximizing Ft causes high 1,tr.
111. LDMOS DRAINAKCHITECTURE AND RESULTS
Fig. 1 SEM cross sectional view of 20V LDMOS.
A voltage capability of 20V is achieved with a similar field
plate structure but with a dedicated retrograde well added to
the triple-well. This configuration, because of the high
electric fields generated at the bird's beak field oxide, is no
more suitable to sustain higher voltages. A RESURF
solution is then mandatory.
This approach requires a proper high voltage (HV) N-well to
reach high BVoss but two main drawbacks remain: low
on-state breakdown voltage and P-body to P-substrate
punch-through limitation.
In order to solve the first issue, traditional RESURF
technique with long drift region would be necessary but
with consequent Ron performances worsening. An adaptive
RESURF solution is then to be preferred [4, 5, 6): a drain
buffer region must be added, optimizing its dose to find the
best compromise between off and on-state breakdown values.
In BCD6 this is obtained exploiting the 2OV LDMOS drain
pocket doping without adding any dedicated mask to the
process flow.
I In Fig. 2 measured off and on-state breakdown voltage
I versus HV N-well dose, with and without drain buffer, are
reported for 40V N-ch. LDMOS case.
On-state breakdown increases with the I-IV N-well dose,
while off-state one decreases. The intersection point is the
maximum voltage that can be guaranteed at any operating
conditions. This voltage is significantly higher (about 20%)
in case of the adaptive RESURF.
no .~ . . . . , . . . .
- \v/o Dram Butfir '

Both LDMOS and low voltage CMOS circuitry are driven by 70 - e /r

- - 0 - \v Dram Butrcr -
the same voltage (Vgs=3.3V), sharing the same gate oxide 0 -
v., i(1 :

(7". To sustain high voltage with the very thin gate oxide 2 . 0

all LDMOS require a field plated configuration (Fig. I ) to m 50 - 0-

limit high electric fields at the drain side poly edge. 5 . b b

The drain pockets of 16V N-channel and P-channel LDMOS $ 10- a-

.
:
o
,
b 'b

are obtained using the same retrograde well of an optional

5V CMOS. A high energy Phosphorous implant is in -
v =;>v...

e'
.- -*
performed to create a buried well (called triple-well). 20- ' ' ' ' I . ' ' ' I ' ' ' I ' ' '

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The effect of drain buffer region on output characteristics is
shown in Fig. 3 for the 40V N-channel LDMOS. 140 _____ 1

4.0.-as -., -
-

O.O.tM t-4
0.a 10.0 ?o.o 13 o 30 o
Vgs=l.lV
Vd(V)

Fig. 3 40V N-channel LDMOS output characteristics optimization

Fig. 5 QArea in BCDS and BCD6 for small area devices (metal
with drain buffer (W = 9 pm). contributes are negligible)
Enlarging the drain drift region with the same well doses, Anyway, due to a new metalization scheme, an overall
the device voltage capability can be extended up to 60V. significant reduction, 25% less, is observed when power
P-body to P-substrate punch-through voltage can limit the devices (area = 0.5 mm?) are considered (Tab. 4).
Power LDMOS circuit configuration. A 50V punch-through
value has been measured with the optimized HV N-well dose
allowing the implementation of a 40V LDMOS with full
Silicon only 1 Power TotzRon-1
(mR mm?
source swing capability.
I BCD5 I 12.5 I 23 I
I BCD6 I 11.6 I 17.5 I
I b) PT measurement Tab. 4 Ron comparison between BCDS and BCD6

drain well totally depleted The five AI/Cu metal levels available in the ULSl CMOS
(RESURF condibon)
technology are used in the Power section with an
interdigitated layout. The first and second metals contacting
drain and source fingers are stacked, as well as third and

m.:
I I I I
fourth metals, while the fifth metal is 3pm thick to carry the
current to the pads (power LDMOS cross section is reported
in Fig. 6).
Fig. 4 Effect of source bufer implant: a) Equipotential lines
distribution at Vds=70V, Vg=Vs=Vsub=OV; b) Electron
concentration at Vsub==-7OV.Vbr-Vs=Vd=OV

To overcome 50V limitation a simulation activity has been

carried out showing that an anti punch-through implant
(source buffer), self aligned to the body mask, can increase
the punch-through voltage up to 70V, without affecting the
BVdss value (Fig. 4).

Iv. POWER METALIZArlON AND ELECTRICALPERFORMANCES

The improvement measured in BCD6 with respect to BCD5
on silicon R.,,xArea (Fig. 5) is mainly due to the increased
channel density (i.e. channel width integrated in an unit
area) thanks to the reduced lithography feature.
However the new structure adopted in the 16V LDMOS of
BCD6 with respect to the BCD5 counterpart, field plated
configuration versus single active one, vanishes the
lithographic advantages. Slight &,*ea differences are
measured if silicon without metal interconnects contribute is
considered.
Fig. 6 SEM cross section of a power LDMOS.
A better electromigration ruggedness is also expected
because parallel metals can be seen as one thicker metal.
Further improvements in terms of ruggedness and power
performances can be obtained with a Copper fifth metal.
Replacing on a power LDMOS the 3pm thick AI/Cu layer
with a 5pm thick Cu metal, obtained by an electroplating
technique, a 60% reduction of the metal contribution to total

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R., has been achieved with a consequent improvement to the and shallow trench isolations is compatible with power
total power LDMOS on-resistance. requirements.

v. IMPACT OF ULSl CMOS TECHNOLOGY FEATURES

ON
POWERDEVICESINTEGRATION
Lithography reduction is the main aspect of the new process
generations. However some new key technology steps are
normally introduced in advanced ULSI CMOS platforms.
In BCD6 the presence of a P-/P+ substrate together with the
low LDMOS threshold voltage can change the effects of the
parasitic bipolar structure.
The parasitic PNP associated to the LDMOS in a high side
driver configuration has a higher gain because of the lack of
a heavy doped N buried layer. However the very low
resistivity (10mQxcm) P+ substrate minimizes the substrate
potential rising caused by holes injection. The lower
LDMOS threshold voltage can also change the effects of the Fig. 8 BCD7 20V LDMOS SEM photograph up to salicide
parasitic bipolar structure because the LDMOS itself may level: shallow trench field oxide structure is evident under drain
offer an alternative path to the recirculating current. region (right side).
The lateral parasitic NPN shows reduced emitter efficiency
In Fig. 8 and 9, SEM cross-section and output characteristics
and base transport factor leading to a significant decrease of
of a 20V LDMOS in the future BCD7 technology are shown.
its gain. This reduction is a fimction of the P- epi thickness.
In Fig. 7 the current collected by an N-pocket as a function
of the distance from the injecting power is reported for
different epi thickness. Previous generation (BCDS) data are
also reported for comparison.

lcnE [E = ID = Power
1E+O c~
Drain Current = 100mA
__-____--
1E-1
P-IP+
1E-2 P-IP+
1E-3 P-IP+
1E 4 P-IP+
;- *--
1E-5 il 0 .. '0 0

1E-6
1E-7
1ES i"
----.

0 250 500
.- ~

750
~

1000
Collector Distance (pm)
-

1250
Fig. 9
Vd (v)

BCD7 20V LDMOS output characteristics (w=22 pm).

Fig. 7 Parasitic NPN versus distance between Emitter (Power
Drain) and Collector (N-Pocket).
SALICIDE (Self Aligned siLICIDE) technique is commonly
used in deep sub-micron CMOS technologies for high
frequency operat ions.
The use of this technique in power LDMOS realization
improves the device performances both in term of robustness
and of operating speed. Thanks to the very low silicide sheet
resistance (3.5 Q/[]), a more uniform potential distribution is
achieved along the source fingers. Robustness against
inhomogenous parasitic NPN turn on during high current
operations is then increased.
VI. FUTURESTRENDS
The successful approach followed in BCD6 to implement
power components in an available ULSl CMOS platform is
still attractive for the next generations.
Experimental results on a 0.25pm technology seem to
confirm that the trend towards thinner (5 nm) gate oxides
CONCLUSION
High Voltage LDMOS integration in a 0.35pm ULSl CMOS
platform has been realized. The electrical performances and
the interactions with the LlLSl technological features have
been analyzed. The BCD6 technology has been designed to
address energy management and battery charge for portable
market maintaining the typical versatility of BCD
technology that makes it suitable for n wide application
market.
Ac KNOWLEDGM ENT
We like to thank R. Stella and E. Morena for their
hndamental contribute to RF project, F. Tampellini for the
parasitics analysis.
REFERENCES
[ 1 ] C. Contiero et al., ISPSD. 1996, pp. 75-78.
[ 2 ] P. Perugupalli et al., IEEE BCTM, 1997, pp. 92-95.
[3] Y. Tan et al., ESSDERC, 1999, pp.216-219.
[4]C. Tsai et al., IEDM 1997, pp. 367-370.
[ 5 ] K. Kinoshita et al., ISPSD, 1998, pp. 65-68.
[6] S. Pendharkar et al., ISPSD 1998, pp.419-422.

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