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where K = Lr /Lm is defined as the series-parallel inductance where θ = φ − β is the phase angle of the equivalent impedance
ratio. and the quality factor Q is defined as
The normalized fundamental component of the primary
bridge output voltage vr is given as π 2 ZB Po
Q = ZB /(8n2 Ro /π 2 ) = . (11)
8n2 Vo2
√ 4
vr 1,pu (t) = 2Vr 1,rpu sin ωs t = sin ωs t (4) The relationship between the phase angle θ and the control-
π
√ lable phase-shift φ is given as
where Vr 1,rpu = π8 is the normalized fundamental rms voltage
of vr . F K + F − K/F
θ = arctan − cot φ . (12)
As mentioned before, the voltage across the HF transformer Q(F 2 − 1)
vt (t) is also a square-wave voltage whose normalized fundament With the introduction of an equivalent impedance, the steady-
component is state of the dual-bridge LLC resonant converter can be described
√ 4M by an equivalent two-port model shown in Fig. 3.
vt1,pu (t) = 2Vt1,rpu sin(ωs t − φ) = sin(ωs t − φ) (5)
π
√ A. Voltages, Currents, and Power
where Vt1,rpu = 8M π is the normalized fundamental rms volt-
age, φ is a controlled phase-shift with respect to the input voltage With the information obtained above and the equivalent cir-
vr 1 (t), M is defined as the normalized primary-reflected output cuit, the input impedance of the two-port model circuit is defined
voltage or converter voltage gain as
Vr1,pu 1 F
M = Vo /VB = 2nt Vo /Vs . (6) Zin,pu = = j(F − ) + Zac,pu j
Ir1,pu F K
The normalized fundamental transformer current it1,pu (t) is A1 + jA2
√ = Zin,pu ∠α = (13)
A3
it1,pu (t) = 2It1,rpu sin(ωs t − β) (7)
where
where It1,rpu is the rms value of the normalized fundamental
transformer current, β is the phase angle with respect to vr 1 (t). F 2
A1 = Q( )
K
It can be seen from Fig. 3 that the output dc current Io,pu should
be equal to the average value of it1,pu (t) after being actively F QF 2
A2 = −( )2 Q cot φ + ( ) (F − 1/F )
rectified at angle φ K K sin φ
√
1 π +φ 2 2 QF 2 F2 2QF 3 cot φ
Io,pu = it1 (t)dωs t = It1,rpu cos(φ − β). (8) A3 = ( ) +( )2
−
π φ π K sin φ K(F 2 − 1) K 2 (F 2 − 1)
Solving (8) yields to Q(F 2 − 1)
α = arctan − cot φ . (14)
F sin2 φ
Io,pu π
It1,rpu = √ . (9) So, the normalized fundamental resonant current can be found
8 cos(φ − β)
as
The FHA applied for the analysis of conventional reso- √
nant converters uses an equivalent resistance (Rac = 8RL /π 2 ir 1,pu (t) = 2Ir 1,rpu sin(ωs t − α) (15)
or π 2 RL /8 depending on the type of filter) to represent the where the fundamental resonant rms current Ir 1r is given as
secondary-side circuit (including the HF transformer, the diode
bridge, the output filter and load) [24]. However, it is not valid for Vr 1,rpu
Ir 1,rpu = (16)
the dual-bridge resonant converters due to the active control of Zin,pu
the secondary switches. According to a modification proposed
in [15] and [16], the partial circuit including the HF transformer, and the normalized capacitor peak voltage can be evaluated as
√ √
the active rectifier (the secondary-side bridge), the output fil- VC r 1,ppu = 2Ir 1,rpu XC r ,pu = 2Ir 1,rpu /F. (17)
ter, and load in a DBSRC can be represented by an equivalent
impedance Zac,pu . This modification actually is suitable for the It should be noted that the actual maximum capacitor voltage is
steady-state analysis of the dual-bridge resonant converters with VC r,m ax = VC r 1,ppu · VB + VB .
any type of tanks and would be used in this paper. It is noted that the input current before filtering i1 is discon-
With the help of (5) and (9), the equivalent impedance in tinuous, which is equal to the sinusoidal resonant current only
this LLC-type DBRC could be found as the ratio of transformer when the switch S1 is turned ON. So the input dc current after
voltage and current in phasor domain filtering Iin,pu could be evaluated as
√ Ts √
2Vt1,rpu ∠(−90◦ − φ) cos θ 1 2
Zac,pu = √
2
= ∠(−θ) (10) Iin,pu = ir 1,pu (t)dt = Ir 1,rpu cos α. (18)
2It1,rpu ∠(−90◦ − β) Q Ts 0 π
4316 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 8, AUGUST 2014
The normalized input dc power is shown as condition for ZVS in the primary bridge can be derived as
Vs · Iin 4 √ Czvs,p Vsw ,p Czvs,p Vs2
Pin,pu = = 2 Ir 1,rpu cos α. (19) 2Ir 1,r sin(α) ≥ ⇒ tan α ≥
VB IB π TD πPin TD
1 − M cos φ Czvs,p Vs2
The normalized rms ripple current in the input filter Cin is ⇒ fp (φ) = ≥ (26)
M sin φ πPin TD
π 2 − 4 cos2 α
Irip,pu = I1,rpu − Iin,pu =
2 2 Ir 1,rpu . (20) where TD is the deadband of the gating signal, Vsw ,p = Vs
2π 2 is the change of switch voltage on the primary side during
switching transient.
The calculation of the transformer current it is given in (7)–
The necessary or weak strain of ZVS operation on the sec-
(9) and its phase angle β can be found from Fig. 3
ondary side is that the transformer current is capacitive with
regards to the transformer square voltage, i.e., φ − β = θ > 0.
Q(F 2 − 1) csc2 φ
β = arctan − cot φ . (21) With help of (12), this can be written as
K(F + F/K − 1/F )
F+ F
− 1
cos φ
The normalized rms value of the ripple current flowing in the cot φ < K F
⇒M > . (27)
capacitive output filter Cf can be found as
Q
K (F
2 − 1) 1+K − K
F2
√ The ZVS in the secondary bridge can be secured for any phase-
π 2 − 8 cos2 θ shift φ if M ≥ 1 and F > 1.
2
If ,rpu = nt It1,rpu − Io,pu =
2 √ Io,pu. (22)
8 cos θ Similar to the primary side, the strong strain of ZVS on the
secondary side is that the instantaneous value of the transformer
B. Converter Gain current should be large enough to charge and discharge the
The transfer function of the two-port model is defined as total parasitic capacitance Czvs,s during the switching transient
time. With (9) and (12), the sufficient condition of ZVS on the
Vt1,pu Zac,pu j K
F secondary side is written as
T(φ) = = = M ∠ − φ. (23)
Vi1,pu Zin,pu √ Czvs,s Vsw ,s 4Czvs,sec Vo2
2It1,r sin(θ) ≥ ⇒ tan θ ≥
TD πPo TD
Then, normalized voltage gain can be calculated as
M (1 + K − K/F 2 ) − cos φ 4Czvs,s Vo2
sin φ ⇒ fs (φ) = ≥ (28)
M (φ) = T (j2πfs ) = . (24) sin φ πPo TD
Q(F − 1/F )
where Vsw ,s = 2Vo is the change of switch voltage on the
It is assumed that the normalized switching frequency F is secondary side during switching transient.
larger than one in (24), which is a quite common choice to enable
the so-called above resonance or lagging mode operation [23], III. DESIGN EXAMPLE BASED ON THE ANALYSIS RESULTS
[24]. It can be seen that the converter gain is controlled by Q (the A design example is given in the section based on the steady-
load level) and φ (the phase shift). For the actual operation of a state analysis results. The converter to be designed is a 200 V
designed converter with a constant output voltage, the converter input, 40–48 V output, 300 W converter with switching fre-
gain M should be kept constant by manipulating the phase shift quency at 100 kHz. The design point is selected at minimum
φ when the load level, i.e., Q changes. Also, the converter gain input voltage, maximum output voltage, and full load output
is found to have nothing to do with K. condition.
The priority of the design objectives is to maintain ZVS op-
C. ZVS Operation in Both Bridges eration from full load to no load. The sufficient ZVS conditions
The necessary or weak strain of ZVS operation on the primary given in (26) and (28) are hard to solve and the parasitic ca-
side is that the resonant current is inductive with regards to input pacitance value depends on the used switch and circuit imple-
square voltage, i.e., α > 0. With help of (14), this condition can mentation. Thus, the weak conditions of ZVS in (25) and (27)
be written as are used in design for a quick initial calculation. Meanwhile
a certain degree of margin would be given on the selection of
1 sin 2φ other parameters to approach the conditions in (26) and (28).
Q(F − )> ⇒ M < sec φ. (25)
F 2
Because the minimum of sec φ is one, the ZVS in the primary A. Selection of Normalized Switching Frequency F
bridge can be guaranteed for any phase-shift φ if M ≤ 1. The first parameter to be selected is the normalized switching
However, in actual case the instantaneous value of the reso- frequency F , which is key to the ZVS operation in both bridges.
nant current during the switching transient time has to be large As indicated in last section, Zin should be kept inductive and
enough to charge or discharge the total parasitic capacitance Zac should be kept capacitive for ZVS operation in each bridge,
Czvs,p including the primary MOSFET drain-to-source capaci- respectively. On the one hand, in order to have an inductive Zin
tance and the stray capacitance. With (14) and (19), the sufficient for possible ZVS operation in the primary bridge, the normalized
LI: LLC-TYPE DUAL-BRIDGE RESONANT CONVERTER: ANALYSIS, DESIGN 4317
Fig. 5. Plot of α with regards to the phase-shift φ for constant Q (solid lines)
(a) or constant M (marked lines) at F = 1.2.
(b) Fig. 6. Plot of θ with regards to the phase-shift φ for constant Q (solid lines)
or constant M (marked lines) at F = 1.2, K = 0.65.
Fig. 4. (a) Plot of Gain M with regards to the phase-shift φ for different Q at
F = 1.2; (b) ZVS boundary lines of the two bridges at F = 1.2.
level. This ZVS condition on the primary side can also be re-
ferred to Fig. 5 which describes the relationship between α and
switching frequency F is commonly chosen to larger than one φ for different Q and different M . It can be predicted that ZVS
for the above resonance operation. On the other hand, F is operation will be lost at small φ if M is larger than one. Based
also expected to be near one to limit resonant peak current. The on the discussion above, the voltage gain at the design point
commonly selected F for conventional fixed-frequency resonant Mm ax is chosen to simply fulfill the requirement in (25) as
converter is about 1.05–1.1 [18]. However, a large F is expected
Mm ax = 1. (29)
to be used in a DBRC to keep inductive resonant current since
the part of Zin —the equivalent impedance Zac is expected to be So, the turns ratio of the HF transformer is calculated as
capacitive rather than the pure resistive Rac used in conventional Mm ax · Vs /2 100
resonant converters [24]. Hence, F = 1.2 is selected in this nt = = = 2.083 : 1. (30)
Vo,m ax 48
paper initially. The value might be adjusted iteratively for better
performance as long as the ZVS operation is secured. The minimum voltage gain is then given as
According to (24), (25), (27), a series of plots of voltage gain nt Vo,m in 5
with respect to the phase-shift φ is given in Fig. 4 for F = 1.2. Mm in = = . (31)
Vs /2 6
As seen from the figure, the area in which both bridges can
work in ZVS operation is enclosed by two boundary lines of To satisfy the requirement of ZVS operation on the secondary
two bridges. The border line for the primary side is fixed while side, solving (27) at the extreme condition (φ = 0, i.e., no load)
the border line for the secondary side moves down with the with Mm in = 56 , F = 1.2 yields to
increase of the inductor ratio K. K = 0.65. (32)
With K = 0.65 and (12), the relationship between and θ and
B. Selection of Converter Gain M and Inductor Ratio K
φ for different Q and different M can be plotted in Fig. 6. It
The selection of M should let the converter always in ZVS can be confirmed from Fig. 6 that the phase angle θ is always
operation regardless of the variation of output voltage and load positive for the whole range of φ, i.e., ZVS operation on the
4318 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 8, AUGUST 2014
TABLE I
SPECIFICATIONS OF THE DESIGNED LLC-TYPE DBRC
Fig. 7. Plot of resonant rms current with regards to the phase-shift φ for
different Q at M = 1, K = 0.65, and F = 1.2.
Fig. 9. Simulation plots under 200 V input, 48 V output, and full load (300 W) Fig. 11. Simulation plots under 200 V input, 40 V output, and full load (300 W)
condition. From top to bottom: v r and ir (scaled by 20 times); v t and it (scaled condition. From top to bottom: v r and ir (scaled by 20 times); v t and it (scaled
by 10 times); i2 ; v C r . by 10 times); i2 ; v C r .
Fig. 12. Simulation plots under 200 V input, 40 V output, and 20% load
Fig. 10. Simulation plots under 200 V input, 48 V output, and 20% load (60 W) condition. From top to bottom: v r and ir (scaled by 60 times); v t and
(60 W) condition. From top to bottom: v r and ir (scaled by 60 times); v t and it (scaled by 40 times); i2 ; v C r .
it (scaled by 20 times); i2 ; v C r .
Fig. 13. Experimental plots under 200 V input, 48 V output, and full load
(300 W) condition. From top to bottom on the left: v r (200v/div), ir (10 A/div),
v t (200v/div), it (10 A/div). From top to bottom on the right: v C r (200v/div),
i2 (10 A/div).
TABLE II
ESTIMATED APPROXIMATE LOSSES OF THE LLC-TYPE DBRC
AT 300 W OUTPUT
Fig. 14. Experimental plots under 200 V input, 48 V output, and 20% load
(60 W) condition. From top to bottom on the left: v r (200v/div), ir (2.5 A/div),
v t (200v/div), it (2.5 A/div). From top to bottom on the right: v C r (50v/div),
i2 (2.5 A/div).
TABLE III
COMPARISON OF KEY PARAMETERS AT 300 W OUTPUT
Fig. 15. Experimental plots under 200 V input, 40 V output, and full load
(300 W) condition. From top to bottom on the left: v r (200v/div), ir (10 A/div),
v t (200v/div), it (10 A/div). From top to bottom on the right: v C r (200v/div),
i2 (10 A/div).
TABLE IV
COMPARISON OF KEY PARAMETERS AT 60 W OUTPUT
Fig. 16. Experimental plots under 200 V input, 40 V output, and 20% load
(60 W) condition. From top to bottom on the left: v r (200v/div), ir (2.5 A/div),
v t (200v/div), it (2.5 A/div). From top to bottom on the right: v C r (50v/div),
i2 (2.5 A/div).
of estimated losses for the experimental converter at full load for The comparisons of some key parameters are concluded in
output voltage at 48 and 40 V are given in Table II. Calculated Tables III–IV. The experimental values show some deviations
efficiency is slightly more than the measured value. Main source compared with results from theoretical calculation and simu-
of the losses are conduction loss of secondary switches and lation especially at low load, which can be attributed to the
copper loss in inductor and the HF transformer. nonidealities existing in actual implementation.
LI: LLC-TYPE DUAL-BRIDGE RESONANT CONVERTER: ANALYSIS, DESIGN 4321