Professional Documents
Culture Documents
Manuscript received November 15, 1999; revised September 25, 2001. This
work was supported by ABB. where is the duty cycle (the time the upper switch is on rel-
E. R. Ronan is with the University of Missouri–Kansas City, Kansas City, ative to the switching period) and “ ” designates the phasor
MO 64110 USA. representation of the fundamental component.
S. D. Sudhoff and S. F. Glover are with the Department of Electrical Engi-
neering and Computer Science, Purdue University, West Lafayette, IN 47907 Although this is the most straightforward approach to ac–ac
USA. power conversion, it is problematic in several respects. First,
D. L. Galloway was with ABB, Inc, Jefferson City, MO 65101 USA. each switch must be able to block full primary voltage and also
He is now at Galloway Transformer Technology, LLC, Jefferson City, MO
65110-5946 USA (e-mail: gallowaytt@aol.com). be capable of conducting full secondary current. The fact that
Publisher Item Identifier S 0885-8977(02)02713-9. both the blocking voltage and peak current are large implies that
0885–8977/02$17.00 © 2002 IEEE
538 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 17, NO. 2, APRIL 2002
Fig. 5. Input stage control overview. frequency is times the actual switching frequency, where
is the number of modules in the stage. As a result, switching
A. Input Stage Design losses in the input stage are minimal. Voltage division is aided
by varistors placed across the input of each module. These de-
Each input stage module consists of a unity power factor ac- vices are only active during significant imbalances that might
tive rectifier [6] shown in Fig. 4. By control of the active switch occur, for example, during startup.
in the boost converter portion, current entering the rectifier can
be shaped into a sinusoid while the output voltage is regulated. B. Isolation Stage Design
An overview of the control system for the input stage is shown
in Fig. 5. Direct current from each input module is fed to a full bridge
In the voltage regulator, the output dc voltage is compared converter in the isolation stage module, shown in Fig. 6. This
with the required level and used to formulate the input cur- converter provides a high-frequency square wave to a small air-
rent magnitude command , which is in turn passed to the cooled transformer that reduces the voltage approximately in
current command synthesizer. In parallel with this process, the half while providing the needed isolation. The high frequency
voltage observer extracts the shape of the fundamental compo- transformer’s secondary (which is center tapped) is then recti-
nent of the input voltage waveform. There are three signals as- fied to form a bipolar dc supply. The series to parallel connection
sociated with the voltage observer; the estimated instantaneous of the isolation stage provides the bulk of the voltage reduction
value of the waveform obtained as the absolute value of the without a large transformer turns ratio.
fundamental component of the input voltage, an estimate of the The isolation stage converter control has two distinct parts as
time derivative of , designated , and the peak value of shown in Fig. 7. First, the duty cycle control regulates the duty
over a cycle . cycle of the square-wave voltage so as to achieve the desired
The current command synthesizer utilizes , , and output voltage . Second, the switching frequency control
to formulate an instantaneous current command , as well as slowly varies the switching frequency as a function of load to
an estimate for the derivative of this command . The current optimize isolation stage efficiency.
command and its derivative are calculated as One subtlety of the control is that, since the isolation stage
control is based on regulating , the individual dc voltages
(2) are not regulated. However, by proper choice of the voltage set
point, a significant imbalance of the individual rail voltages (as
(3) would occur if the output stage supplied a 120-V half-wave rec-
tifier) can be tolerated without adverse effects.
The current command , its time derivative , and are
inputs to a duty cycle synthesizer which formulates the duty- C. Output Stage Design
cycle command to control the relative amount of time each of The paralleled bipolar dc output from the isolation modules
the modules is “on” to insure that the rectifier current is equal is fed into a single-module output stage, shown in Fig. 8. As
to the commanded current. can be seen, this stage consists of two halves to produce
One of the features of the input stage is that the switching and , respectively. The two converter halves, as well as
of input-stage modules is staggered so the effective switching their controls, operate independently. The ground, or mid-tap, is
540 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 17, NO. 2, APRIL 2002
TABLE I
PRINCIPAL PARAMETERS
anced load in steady state. A fault was applied to both legs of the
secondary, then cleared after 0.15 s. The fault was represented as
a very low resistance for convenience. As can be seen in Fig. 13,
the output stage control has effectively limited the fault current
(lower trace) to a level that can be tolerated by the semiconduc-
tors. Corresponding input traces are shown in Fig. 14. These
demonstrate that the input current and power during this event
are quite small. The current flowing supplies the power being
dissipated by the low-impedance fault as well as system losses.
There is no current surge on the primary, typical of a fault on
a conventional distribution transformer, so the feeder voltage
would not be affected by this fault event. New protective algo-
rithms would be required to recognize and isolate the fault in an
Fig. 11. Simulated full load operation, input.
appropriate manner.
In regard to efficiency of the design, simulation studies have
shown that the input stage efficiency should be very high (99%)
and that the efficiency of this stage will be relatively flat with
power level. The isolation stage efficiency is somewhat lower,
on the order of 97% at one-quarter load and approximately 98%
at full load. The output stage is the least efficient; just over
96% at full load. The combined efficiency of the SST described
herein should be able to exceed 90%. To achieve greater effi-
ciencies in a SST, soft switching could be employed to reduce
switching losses in the isolation and output stages. The use of
(new) high-voltage silicon-carbide (SiC) Shottkey diodes would
also significantly reduce switching losses.
The initial design and prototype were set at 10 kVA, but exten-
sion to the entire range of single-phase distribution transformer
Fig. 12. Suddenly applied load (output), simulated. ratings is possible with the general topology chosen. For higher
voltages, more input-stage modules (or higher-voltage semi-
conductors) would be used. For higher capacity, larger devices
could be employed within the same topology. Eventually, par-
alleled devices would be necessary—particularly for the output
stage. Until higher efficiencies can be achieved, supplemental
cooling would be needed at higher ratings. As capacity is in-
creased, the overall system efficiency should rise since controls
and other overhead would consume a decreasing proportion of
the input power.
V. MEASURED PERFORMANCE
Fig. 15 illustrates a prototype constructed to demonstrate the
solid-state transformer system. In this prototype, the layout was
Fig. 13. Simulated fault performance, output. spread out to facilitate design modifications and to allow ex-
tensive measurements. The transformer has been operated as an
integrated unit at one-half rated voltage. The presence of high
levels of electro-magnetic interference (EMI) precluded opera-
tion of this early prototype at full voltage, although all compo-
nents were individually tested to that level.
Fig. 16 illustrates the output waveforms of the initial pro-
totype at one-half rated voltage, 0.4 per-unit load power and
0.89 pf. The output waveforms are comparable to those pre-
dicted, with a small ripple evident on both current and voltage
due to the switching of the output-stage converter.
The input voltage and current are displayed in Fig. 17. The
input current and particularly the voltage contain much more
ripple than is predicted by the simulation. The cause of this is
Fig. 14. Simulated fault performance, input. that, in the experimental set-up, the transformer was supplied
542 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 17, NO. 2, APRIL 2002
two intermediate dc buses and the isolation-stage control de- [11] S. F. Glover and S. D. Sudhoff, “An experimentally validated nonlinear
scribed earlier. Experiments also confirmed that the prototype stabilizing control for power electronics based power systems,” in Proc
SAE Aerosp. Power Syst. Conf, 1998.
performed well under loads with extreme dc offsets, such as [12] S. D. Sudhoff, “Solid state transformer,” U.S. Patent no. 5 943 229, Aug.
would be encountered with half-wave rectifiers. 24, 1999.