2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)

VDTA Based Fractional Order Floating Inductor

and its Applications
Megha Jain Reshma S Kumar Lakshmi Nair Rajeshwari Pandey
Department of Electronics Department of Electronics Department of Electronics Department of Electronics
and Communication and Communication and Communication and Communication
Delhi Technological Delhi Technological Delhi Technological Delhi Technological
University University University University
Delhi, India Delhi, India Delhi, India Delhi, India
megha98jn@gmail.com gsreji1@gmail.com lakshmi2798@gmail.com rpandey@dce.ac.in

Abstract—In this paper, a fractional order floating inductor
using two Voltage Differencing Transconductance Amplifiers
(VDTAs) and a fractional order capacitor (FC) has been
introduced. Further, three applications of Fractional Inductor
(FI) namely fractional order low pass filter (FLPF), fractional
order high pass filter (FHPF) and fractional order band pass
filter (FBPF) have been presented. The proposed designs are
verified through SPICE simulations using TSMC 180 nm
CMOS model parameters and FC is realized using RC Domino
ladder network truncated to 11-12 blocks.
Keywords—VDTA, FC, FI, filter
I. INTRODUCTION
In recent times, the popularity of fractional calculus has
risen owing to the fact that it serves as a powerful tool to
model real world applications which are generally of
fractional origin and not always of the integral order. This
shift from the traditional integer order systems to fractional
ones has thus facilitated enhanced flexibility, freedom and
provided more room for optimization. The circuit theory
relies on three basic passive circuit elements, i.e. Resistor,
Capacitor and Inductor, hence many attempts have been
made in the past few decades to realize their fractional order
counterparts due to which the phase difference between the
current and voltage is expected to show a linear dependence
on the fractional order and provide a variation over full 2୞
phase [1].
This paper aims at presenting the floating fractional
inductor employing VDTA and the already reported
fractional order capacitor [2].
The choice of VDTA as the active circuit element is
based on the advantages that it offers such as two different
tunable values of transconductance and its usefulness in
achieving compact structure realizations suitable for fully
integrated circuit designs.
This approach of simulating passive inductor
characteristics using active circuit elements is motivated by
the fact that conventional coil type inductors suffer from
resistive losses and capacitive coupling losses whereas their
simulated active counterparts provide electronic tunability
and controllability with relatively broad range of inductance
values at a low cost and comparatively less space [3].
In open literature, several studies that simulate the
fractional capacitors and inductors have been reported using
various active elements like the Current Conveyors [4],
Operational Amplifiers (Op-Amps) [5], operational
transconductance amplifiers (OTAs) [6], Current feedback
Operational Amplifiers (CFOAs) [7], Current Controlled
Current Feedback Operational Amplifier (CCCFOAs) [3] as
summarized in Table I which presents a comparison of the
implemented FI with the existing FI designs in terms of the
active and passive components utilised for its simulation.
Consequently, this reveals the significance of the proposed
configuration which employs only two VDTAs and an FC,
emerging as the design with minimum number of circuit
elements for the fractional inductor (FI) simulation.
Rest of the paper is structured as below: Section II
highlights the design methodology of VDTA and FC based
proposed FI. Section III presents the practicability of the
devised FI in basic filter circuit configurations. Finally,
Section IV compiles all the simulated plots and curves to
draw constructive inferences and conclusions henceforth
which have been presented in section V.
II. THE PROPOSED CONFIGURATION
The impedance and phase function of an FC [8] are
expressed as (1) and (2) respectively
1
Z C ( s) = (1)
α
s Cα

TABLE I. COMPARISON OF PROPOSED FI WITH EXISTING FI DESIGN

Reference Inductance Type Active Block No. of Active No. of No. of Integer No. of
Devices Resistors Order Capacitors FCs
[3] Grounded CCCFOA 2 0 0 1
[5] Floating Op-Amp 2 4 1 0
[6] Floating OTA 3 3 1 0
[7] Grounded CFOA 1 2 0 1
[11] Grounded CMOS-RC network 3 0 0 1
Proposed Floating VDTA 2 0 0 1

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 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)

1
Z C ( jω) = (2)
ωα C α
The capacitance is represented in units of ‫ڵ‬/sĮ , where Į
is the order of the FC.
Similarly, the impedance and phase function of an FI of
fractional order ȕ are given by (3) and (4) respectively.

Z L ( s ) = s β Lβ (3)
Fig. 1. Circuit symbol for VDTA block
β
Z L ( jω) = ω Lβ (4) The routine circuit analysis results in the inductance
The circuit symbol of VDTA [9] as shown in Fig. 1 has value of the FI as presented in (6).
five terminals. While V_p and V_n represent the high
Cα
impedance input terminals, the Z, X+ and X‫ ޤ‬are high Lβ = (6)
impedance current output terminals. The terminal g m1 g m 2
characteristics of VDTA are represented by matrix (5).
where CĮ represents FC of order Į and is designed using
ª I Z º ª g m1 − g m1 0 º ªVV _ p º RC Domino ladder network truncated to 11-12 blocks.
« » « « »
«I X + » = « 0 0 g m 2 »» «VV _ n » (5)
«I » « 0 0 − g m 2 »¼ «¬V Z »¼ III. APPLICATIONS OF PROPOSED FI
¬ X− ¼ ¬
In (5) gm1 and gm2 represent the transconductance gains The proposed FI is functionally verified by using it as a
of the first and second transconductance stages of VDTA circuit element in three fractional order RLȕCĮ filters namely
respectively. The gm1 and gm2 can be tuned electronically FLPF, FHPF and FBPF. The filters are designed by lifting
with the help of bias currents of the transistors. the appropriate node of a parallel resonator. The detailed
mathematical analysis has been presented in following
The proposed FI of order ȕ, as shown in Fig. 3, is the subsections.
generalization of VDTA based integer order inductor [10] in
fractional domain.

Fig. 2. Domino ladder based fractional order capacitor

Fig. 3. Proposed fractional order inductance using VDTA and FC

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 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)

A. Fractional Band pass Filter Equating the magnitude to 1/¥2 times the DC gain, the
cutoff frequency can be computed. On simplification, the
The circuit diagram of the designed FBPF with C = CĮ generalized equation is obtained as below.
and L = Lȕ is shown in Fig. 4. The transfer function (TF) of
this FBPF is computed as
2 απ α + 2β
sβ ω 2( α +β ) + cos( )ω
RC α 2
V out RC α
H(s) = = (7) 2 ª ( α + β )π º α +β
Vin sβ 1 + cos « »ω (12)
s α +β
+ + Lβ C α ¬ 2 ¼
RC α Lβ C α
1 2 βπ β 1
+ ω 2β + cos( )ω − 2 2 = 0
The magnitude of the TF is calculated as R 2Cα 2 RLβ C α 2 2 Lβ C α

e jπβ / 2 ωβ
RC α
H ( jω) = (8)
jπ ( α + β) / 2 α +β e jπβ / 2 ω β 1
e ω + +
RC α Lβ C α

Equating the magnitude to 1/¥2 times the maximum

gain, the half power frequencies (fL, fH) are calculated. Thus
the generalized equation for determining the cut-off
frequencies is presented in (9).
Fig. 5. The proposed FI based FLPF
2( α +β ) 2 απ α + 2β
ω + cos( )ω
RC α 2 C. Fractional High pass Filter
2 ª ( α + β )π º α +β
+ cos « »ω (9) The circuit of proposed FHPF is given in Fig. 6 and its
Lβ C α ¬ 2 ¼ TF is expressed as
1 2 βπ β 1
− ω 2β + cos( )ω + 2 2 = 0
R 2 Cα 2 RLβ C α 2 2 Lβ C α V s α +β
H(s) = out = (13)
Vin α +β sαR 1
s + +
The center frequency (fc) corresponds to the maximum gain Lβ Lβ C α
frequency.

Fig. 6. The proposed FI based FHPF

Fig. 4. The proposed FI based FBPF

B. Fractional Low pass Filter The magnitude of the TF of (13) is calculated as

The proposed FI based FLPF is shown in Fig. 5. The TF

of FLPF is evaluated as follows: ω α +β e jπ( α +β) / 2
H ( jω) = (14)
1 e jπα / 2 ω α R 1
L e jπ( α +β) / 2 ω α +β + +
V β Cα Lβ Lβ C α
H ( s ) = out = (10)
Vin α +β sβ 1
s + +
RC α Lβ C α Equating the magnitude response to 1/¥2 times the
The magnitude of the transfer function is calculated as maximum gain the half power frequency is calculated. On
simplification, the following generalized equation is
1 obtained.
Lβ C α
H ( jω) = (11)
e jπβ / 2 ω β 1
e jπ(α +β) / 2 ω α +β + +
RC α Lβ C α

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2R βπ 2 α +β
ω 2( α +β ) − cos( )ω
Lβ 2
2 ª ( α + β )π º α +β
−
Lβ C α
cos «
2 »ω (15)
¬ ¼
R2 2R απ α 1
− 2
ω2α − 2
cos( )ω − 2 2 = 0
Lβ C α Lβ 2 Lβ C α

IV. SIMULATION RESULTS

The SPICE simulations are carried out for functionality
assessment of proposed FI. The VDTA [9] is biased using
DC power supplies of ± 0.9V and 180 nm TSMC
(a)
technology node is used as process parameters. The channel
length for all transistors is chosen as 0.36 μm. The width of
NMOS transistors is considered to be 3.6 μm and that for
PMOS devices is taken as 16.64 μm. All biasing current
sources are taken as 150 μA and the transconductances are
obtained as gm1 = 605.042 μA /V and gm2 = 594.205 μA /V.
The FC of Fig. 2 [2] is designed for Į = 0.5 and CĮ = 3.75
μ‫ڵ‬/s0.5. The ladder wise component values are chosen as R0
= 330 kȍ, C0 = 4.7 μF, R1 = 82 kȍ, C1 = 3.1 μF, R2 = 33
kȍ, C2 = 1 μF, R3 = 12 kȍ, C3 = 470 nF, R4 = 4.7 kȍ, C4 =
168 nF, R5 =2kȍ, C5 = 68 nF, R6 = 736 ȍ, C6 = 27 nF, R7 =
270 ȍ, C7 = 10 nF, R8 = 120 ȍ, C8 = 4.7 nF, R9 = 47 ȍ, C9 =
1 nF, R10 = 8.2 ȍ, C10 = 2.2 nF and R11 = 18.2 ȍ.

The simulated FC impedance magnitude plot is shown in

Fig. 7(a) whereas the FC value is plotted in Fig. 7(b). The (b)
phase responses of FC are shown in Fig.7 (c). These
responses have been observed to be quite identical to the
theoretical responses i.e. CĮ = 3.75 μ‫ڵ‬/s0.5 and ‫ס‬ZC (jȦ) =
șCĮ = - 45ƕ.
The simulated impedance magnitude plot of floating FI
is depicted in Fig. 8 (a) whereas the variation of FI
inductance value with frequency is plotted in Fig. 8 (b) and
impedance phase response is shown in Fig. 8 (c). It may be
observed from Fig. 8 (a) that the impedance increases with
the increase in frequency which confirms to the expression
for impedance relation of floating FI in a frequency range of
few hundred Hz to 1MHz. Corresponding to the same range
of operational frequency a nearly constant value of
inductance Lȕ = 10.435 Ÿ/s0.5 varying well within ±10% of (c)
the relative error. Further, the phase response shows a Fig. 7. (a) Impedance provided by the fractional order capacitance;
(b) variation of fractional order capacitance with frequency; (c) phase
similar trend where it yields a nearly constant phase which response of fractional order capacitance
matches the theoretically obtained phase ‫ס‬ZL(jȦ) = șLȕ = +
45ƕ. The FLPF employs a parallel R- CĮ network in series
The proposed filter applications are simulated next to with Lȕ where R = 5 kŸ, CĮ = 3.75 μ‫ڵ‬/s0.5 and Lȕ = 10.435
demonstrate the applicability of the proposed floating FI. The Ÿ/s0.5. The magnitude response is shown in Fig. 10 and
magnitude responses of the transfer function have been yields a 3dB frequency of 4.2695 kHz.
analysed for the 3 dB cut-off frequencies corresponding to Similarly, the fractional order High pass filter employs a
the design specifications of each filter. series RLȕCĮ network where R= 3kŸ, CĮ = 3.75 μ‫ڵ‬/s0.5 and
The FBPF employs an Lȕ ‫ ޤ‬CĮ network in series with R Lȕ = 10.435 Ÿ/s0.5. The cut-off frequency from the
where R=1 kŸ, CĮ = 3.75 μ‫ڵ‬/s0.5 and Lȕ = 10.435 Ÿ/s0.5. corresponding magnitude plot of Fig. 11 is obtained as
This filter design yields a center frequency fc = 1.2598 kHz 12.516 kHz. Thus, the usage of a fractional order inductor
and BW = fH ‫ ޤ‬fL = 7.786 kHz as obtained from the yield the appropriate responses with the added advantage of
corresponding magnitude response plot of Fig. 9. obtaining a roll-off which is non-integral multiple of the
standard 20dB/decade slope.

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(a)
Fig. 10. The FLPF magnitude response

(b)

Fig. 11. The FHPF magnitude response

(c)
Fig. 8. (a) Impedance provided by the fractional order inductance;
(b) variation of fractional order inductance with frequency; (c) phase
response of fractional order inductance
V. CONCLUSION
In this paper, a floating FI designed using VDTA has
been presented. The proposed design is verified with the use
of SPICE simulations for fractional order ȕ = 0.5. The
behavior of the proposed FI was tested by comparing the
theoretical impedance magnitude and phase responses with
the simulated ones. Further, proposed FI is employed in
three different filter applications.
The proposed fractional inductor, when compared to
other existing implementations in literature has an edge in
terms of the number of additional passive components
employed and the simplicity of implementation of the active
device.

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