Transistors, Digital Systems, Logic

Damon Anderson
 Review (1/2)
• Floating point approximates real numbers:
– Largest magnitude: 2128 – 2104 (Exp = 0xFE)
Smallest magnitude: 2-149 (denorm)
– Also has encodings for 0, ±∞, NaN
31 30 23 22 0
S Exponent (8) Significand (23)

• Big Takeaways:
– The smallest gap between two FP numbers change
depending on the exponent
– Rounding errors occur because of these gaps
6/29/2017 CS61C Su17 - Lecture 8 2
 Review (2/2)
• Compiler converts a single HLL file into a single
assembly file .c → .s
• Assembler removes pseudo-instructions, converts
what it can to machine language, and creates a
checklist for linker (relocation table) .s → .o
– Resolves addresses by making 2 passes (for internal
forward references)
• Linker combines several object files and resolves
absolute addresses .o → .out
– Enable separate compilation and use of libraries

7/2/2018 CS61C Su17 - Lecture 9 3

 Discuss with Neighbors:
(previous midterm question)
In one word each, name the most common
producer and consumer of the following items.
Choose from: Linker, Loader, Compiler,
Assembler, Programmer

(item) This is the output of: This is the input to:

bne t0,s0,done Compiler Assembler
char *s = “hello world”; Programmer Compiler
app.o string.o Assembler Linker
firefox Linker ?

4
 Discuss with Neighbors:
(previous midterm question)
In one word each, name the most common
producer and consumer of the following items.
Choose from: Linker, Loader, Compiler,
Assembler, Programmer

(item) This is the output of: This is the input to:

bne $t0,$s0,done
t0,s0,done Compiler Assembler
char *s = “hello world”; Programmer Compiler
app.o string.o Assembler Linker
firefox Linker Loader

5
 C program: foo.c

Compiler

• Translation Assembly program: foo.s

• Compiler
Assembler
• Administrivia
Object (mach lang module): foo.o
• Assembler
• Linker Linker
lib.o

• Loader Executable (mach lang pgm): a.out

• Example
Loader

7/2/2018 CS61C Su18 - LectureMemory

8 6
 Loader
• Input: Executable (e.g. a.out for RISCV)
• Output: <program is run>

• Executable files are stored on disk

• When one is run, loader’s job is to load it into
memory and start it running
• In reality, loader is the operating system (OS)
– loading is one of the OS tasks

7/2/2018 CS61C Su18 - Lecture 8 7

 Loader
1) Reads executable file’s header to determine
size of text and data segments
2) Creates new address space for program large
enough to hold text and data segments,
along with a stack segment
<more on this later>
3) Copies instructions and data from executable
file into the new address space

7/2/2018 CS61C Su18 - Lecture 8 8

 Loader
4) Copies arguments passed to the program
onto the stack
5) Initializes machine registers
– Most registers cleared, but stack pointer
assigned address of 1st free stack location
6) Jumps to start-up routine that copies
program’s arguments from stack to registers
and sets the PC
– If main routine returns, start-up routine
terminates program with the exit system call
7/2/2018 CS61C Su18 - Lecture 8 9
~ FFFF FFFFhex
stack

heap
static data
code
~ 0hex

10
 C.A.L.L. Example

#include <stdio.h>
int main(){
printf("Hello, %s\n","world");
return 0;
}

6/28/2018 CS61C Su18 - Lecture 8 11

 Compiled Hello.c: Hello.s
.text # Directive: enter text section
.align 2 #
.global main #
main: #
addi sp,sp,-16 # allocate stack frame
sw ra,12(sp) # save return address
lui a0,%hi(str1) # compute address of string1
addi a0,a0,%lo(str1) #
lui a1,%hi(str2) # compute address of string2
addi a1,a1,%lo(str2) #
call printf
# call function printf
lw ra,12(sp)
# restore return address
addi sp,sp,16
# deallocate stack frame
li a0,0
# load return value 0
ret
.section .rodata
# return
.balign 4 #
str1: #
.string "Hello, %s!\n" # label for first string
str2: #
.string "world" # label for second string
6/28/2018 CS61C Su18 - Lecture 8 12
 Compiled Hello.c: Hello.s
.text # Directive: enter text section
.align 2 #
.global main #
main: #
addi sp,sp,-16 # allocate stack frame
sw ra,12(sp) # save return address
lui a0,%hi(str1) # compute address of string1
addi a0,a0,%lo(str1) #
lui a1,%hi(str2) # compute address of string2
addi a1,a1,%lo(str2) #
jal, ra, printf
# call function printf
lw ra,12(sp)
# restore return address
addi sp,sp,16
# deallocate stack frame
li a0,0
# load return value 0
ret
.section .rodata
# return
.balign 4 #
str1: #
.string "Hello, %s!\n" # label for first string
str2: #
.string "world" # label for second string
6/28/2018 CS61C Su18 - Lecture 8 13
 Compiled Hello.c: Hello.s
.text # Directive: enter text section
.align 2 #
.global main #
main: #
addi sp,sp,-16 # allocate stack frame
sw ra,12(sp) # save return address
lui a0,%hi(str1) # compute address of string1
addi a0,a0,%lo(str1) #
lui a1,%hi(str2) # compute address of string2
addi a1,a1,%lo(str2) #
jal, ra, printf
# call function printf
lw ra,12(sp)
# restore return address
addi sp,sp,16
# deallocate stack frame
addi a0, a0, 0
# load return value 0
ret
.section .rodata
# return
.balign 4 #
str1: #
.string "Hello, %s!\n" # label for first string
str2: #
.string "world" # label for second string
6/28/2018 CS61C Su18 - Lecture 8 14
 Compiled Hello.c: Hello.s
.text # Directive: enter text section
.align 2 #
.global main #
main: #
addi sp,sp,-16 # allocate stack frame
sw ra,12(sp) # save return address
lui a0,%hi(str1) # compute address of string1
addi a0,a0,%lo(str1) #
lui a1,%hi(str2) # compute address of string2
addi a1,a1,%lo(str2) #
jal, ra, printf
# call function printf
lw ra,12(sp)
# restore return address
addi sp,sp,16
# deallocate stack frame
addi a0, a0, 0
# load return value 0
jalr, x0, ra, 0
.section .rodata
# return
.balign 4 #
str1: #
.string "Hello, %s!\n" # label for first string
str2: #
.string "world" # label for second string
6/28/2018 CS61C Su18 - Lecture 8 15
 Compiled Hello.c: Hello.s
.text # Directive: enter text section
.align 2 #
.global main #Symbol Table:
main: # Label: Offset: Type:
0x00 addi sp,sp,-16 main
# allocate 0x00000000
stack frame global text
0x04 sw ra,12(sp) # savestr1return0x00000000
address local data
0x08 lui a0,??? str2
# compute 0x0000000c
address local data
of string1
0x0c addi a0,a0,??? #
0x10 lui a1,??? # compute address of string2
0x14 addi a1,a1,??? #
0x18 jal, ra, ???
# call function printf
0x1c lw ra,12(sp)
#Relocation
restoreTable:
return address
0x20 addi sp,sp,16
Offset:
# deallocate Inst: frame
stack Dependency:
0x24 addi a0, a0, 0
# load0x00000008 lui
return value 0 str1
0x28 jalr, x0, ra, 0
0x0000000c addi
# return str1
.section .rodata
# 0x00000010 lui str2
.balign 4
str1: # 0x00000014 addi str2
0x00
.string "Hello, %s!\n" 0x00000018
# label for first jal stringprintf
0x0c str2: #
.string "world" # label for second string
6/28/2018 CS61C Su18 - Lecture 8 16
 Assembled Hello.s → Hello.o
00000000 <main>:
00: ff010113 addi sp,sp,-16
04: 00112623 sw ra,12(sp)
08: 00000537 lui a0,0x0 # addr placeholder
0c: 00050513 addi a0,a0,0 # addr placeholder
10: 000005b7 lui a1,0x0 # addr placeholder
14: 00058593 addi a1,a1,0 # addr placeholder
18: 000000ef jal ra,0x0 # addr placeholder
1c: 00c12083 lw ra,12(sp)
20: 01010113 addi sp,sp,16
24: 00000513 addi a0,a0,0
28: 00008067 jalr x0, ra, 0

6/28/2018 CS61C Su18 - Lecture 8 17

 Linker
hello.o
text 1
hello.out
data 1 data 1
Relocated data 1
symbol data 2 STATIC
reloc Relocated data 2
text 1
stdio.o reloc Relocated text 1
text 2 CODE
text 2 Relocated text 2
data 2
symbol
6/28/2018 CS61C Su18 - Lecture 8 18
 Linked Text
000101b0 <main>:
101b0: ff010113 addi sp,sp,-16
101b4: 00112623 sw ra,12(sp)
101b8: 00021537 lui a0,0x21
101bc: a1050513 addi a0,a0,-1520 #20a10<str1
101c0: 000215b7 lui a1,0x21
101c4: a1c58593 addi a1,a1,-1508 #20a1c<str2
101c8: 288000ef jal ra,10450 #<printf>
101cc: 00c12083 lw ra,12(sp)
101d0: 01010113 addi sp,sp,16
101d4: 00000513 addi a0,0,0
101d8: 00008067 jalr ra

19
Loader
STACK

HEAP

STATIC

CODE
20
Question: Which statement is TRUE about the
following code?
la t0,Array
Loop: lw t1,0(t0)
addi t0,t0,4
bne a0,t1,Loop
Exit: ...
(A) The la pseudoinstruction will be edited
during the link phase
(B) The bne instruction will be edited during the
link phase
(C) This code will be the output of the compiler
no matter what machine it’s run on
(D) This was written by a programmer because
compilers don’t allow pseudo-instructions 21
Question: Which statement is TRUE about the
following code?
la t0,Array
Loop: lw t1,0(t0)
addi t0,t0,4
bne a0,t1,Loop
Exit: ...
(A) The la pseudoinstruction will be edited
during the link phase
(B) The bne instruction will be edited during the
link phase
(C) This code will be the output of the compiler
no matter what machine it’s run on
(D) This was written by a programmer because
compilers don’t allow pseudo-instructions 22
 Administrivia
• No lab tomorrow, no section Wed, Happy 4th of
July!
• HW2 and Proj 2-1 due this Friday
• Midterm 1 Tomorrow
– Monday, 9:30 – 11 AM, 10 Evans
– Expected Average: 55-75. This is normal!
– One 8.5”x11” cheatsheet
• HW3 releasing on Thurs.

7/2/2018 CS61C Su17 - Lecture 9 23

 Overview
Higher-Level Language temp = v[k];
Program (e.g. C) v[k] = v[k+1];
v[k+1] = temp;
Compiler
lw $t0, 0($2)
Assembly Language lw $t1, 4($2)
Program (e.g. MIPS) sw $t1, 0($2)
sw $t0, 4($2)
Assembler
0000 1001 1100 0110 1010 1111 0101 1000
Machine Language 1010 1111 0101 1000 0000 1001 1100 0110
Program (MIPS) 1100 0110 1010 1111 0101 1000 0000 1001
0101 1000 0000 1001 1100 0110 1010 1111
Machine
Interpretation
Hardware Architecture Description We are here
(e.g. block diagrams)
Architecture
Implementation
Logic Circuit Description
(Circuit Schematic Diagrams)
7/2/2018 CS61C Su17 - Lecture 9 24
 Hardware Design
• Upcoming: We’ll study how a modern processor is
built, starting with basic elements as building blocks
• Why study hardware design?
– Understand capabilities and limitations of hardware in
general and processors in particular (what is fast and slow?)
– Background for more in-depth courses (EECS151, CS152)
– You may need to design own custom hardware for extra
performance (some commercial processors today have
customizable hardware)
– Design methodology – Abstraction; limitations and tradeoffs

7/2/2018 CS61C Su17 - Lecture 9 25

 Synchronous Digital Systems (SDS)
Hardware of a processor, such as a RISC-V processor, is an
example of a Synchronous Digital System

Synchronous:
• All operations coordinated by a central clock
‒ “Heartbeat” of the system!

Digital:
• Represent all values with two discrete values
• Electrical signals are treated as 1’s and 0’s
‒ 1 and 0 are complements of each other
• High/Low voltage for True/False, 1/0
7/2/2018 CS61C Su17 - Lecture 9 26
 Agenda
• Transistors, Switching Networks
• Meet the staff!
• Combinational Logic Representations
– Truth Tables
– Boolean Algebra

7/2/2018 CS61C Su17 - Lecture 9 27

 Hardware Design Hierarchy
system

datapath control

code state combinational

multiplexer comparator
registers registers logic

register logic

switching
networks
7/2/2018 CS61C Su17 - Lecture 9 28
 Switches (1/2)
• The basic element of physical implementations
• Convention: if input is a “1,” the switch is asserted

A Z
Open switch if A is “0” (unasserted)
and turn OFF light bulb (Z)

A Z
Close switch if A is “1” (asserted)
and turn ON light bulb (Z)

In this example, Z ≡ A.
7/2/2018 CS61C Su17 - Lecture 9 29
 Switches (2/2)
• Can compose switches into more complex ones
(Boolean functions)
– Arrows show action upon assertion (1 = close)

A B
AND: “1” Z ≡ A and B
A

OR: “1” Z ≡ A or B

7/2/2018 CS61C Su17 - Lecture 9 30

 Transistors!
• MOSFET:
– Metal Oxide Semiconductor Field Effect Transistor

31
 Transistors and CS61C
• The internals of transistors are important, but
won’t be covered in this class
– Physical limitations relating to speed and power
consumption
– High/Low voltage ↔1/0
– Better understand Moore’s Law
– Can take EE16A/B, EE105, and EE140
• We will proceed with the abstraction of Digital
Logic (0/1)
7/2/2018 CS61C Su17 - Lecture 9 32
1947 → 2018

33
 Basics
N-channel P-channel
Gate
Gate

Source Source Drain

Drain
VGS > VT: Switch CLOSED VSG > |VT|: Switch CLOSED
VGS < VT: Switch OPEN VSG <|VT|: Switch OPEN

● Three terminals: Source, Gate, and Drain

● Switch action based on relative terminal voltages
(VG, VD, VS) and relative voltages (e.g. VGS, VDS)
● Common high of 3V and low of 0V
34
 MOS Networks
• What is the relationship between X and Y?

X
Voltage Source
(“1”) X Y
3V
1
00 V 31V
Y
31V 00V
0V
0
Ground
(“0”)
Called an inverter or NOT gate
7/2/2018 CS61C Su17 - Lecture 9 35
 Two Input Networks
X Y Z

1 0 0 1
0 1 1
1 0 1
0 1 1 0
X Y Z
1 0 0 1
0 1 0
1 0 0
0 1 1 0
36
Question: Which set(s) of inputs will result in the
output Z being 1?

X Y
X Y
1 (A) 0 0
(B) 0 1
Z (C) 1 0
0 (D) 1 1

37
Question: Which set(s) of inputs will result in the
output Z being 1?

X Y
X Y
1 (A) 0 0
(B) 0 1
Z (C) 1 0
0 (D) 1 1

38
 Block Diagrams
• In reality, chips composed of just transistors
and wires
– Small groups of transistors form useful building
blocks, which we show as blocks
X Y

1
X
Z
≡ Y
NAND Z

0
• Can combine to build higher-level blocks
– You can build AND, OR, and NOT out of NAND!
7/2/2018 CS61C Su17 - Lecture 9 39
 Meet the Staff

Nick
Favorite Villain The Other Mother Project 1

What would you

Socks & Sandals Project 1
protest?
What are you
Language Cheese
passionate about?
What would you be New York Times
Nothing
famous for? Bestseller
6/18/2018 CS61C Su18 - Lecture 1 40
 Agenda
• Transistors, Switching Networks
• Meet the staff!
• Combinational Logic Representations
– Truth Tables
– Boolean Algebra

7/2/2018 CS61C Su17 - Lecture 9 41

 Hardware Design Hierarchy
system

datapath control

code state combinational

multiplexer comparator
registers registers logic

register logic

switching
networks
7/2/2018 CS61C Su17 - Lecture 9 42
 Type of Circuits
• Digital Systems consist of two basic types of
circuits:
• Combinational Logic (CL)
– Output is a function of the inputs only, not the history
of its execution
– e.g. circuits to add A, B (ALUs)
• Sequential Logic (SL)
– Circuits that “remember” or store information
– a.k.a. “State Elements”
– e.g. memory and registers (Registers)
7/2/2018 CS61C Su17 - Lecture 9 43
 Representations of
Combinational Logic
✓ Text Description
✓ Circuit Diagram
– Transistors and wires
– Logic Gates
✓ Truth Table
✓ Boolean Expression

✓ All are equivalent

7/2/2018 CS61C Su17 - Lecture 9 44
 Truth Tables
• Table that relates the inputs to a CL circuit to
its output
– Output only depends on current inputs
– Use abstraction of 0/1 instead of high/low V
– Shows output for every possible combination of
inputs
• How big?
– 0 or 1 for each of N inputs, so 2N rows

7/2/2018 CS61C Su17 - Lecture 9 45

 A B C Y
CL: General Form
0 0 0 F(0,0,0)
0
1
0 0 1 F(0,0,1)
1
A
0 1 0 F(0,1,0)
0
1
B Y 0 1 1 F(0,1,1)
0
1 R

C
F 1 0 0 F(1,0,0)
0
1 Rows

1 0 1 F(1,0,1)
1
1 1 0 F(1,1,0)
1
0
1 1 1 F(1,1,1)
0
If N inputs, how many distinct
functions F do we have?
Function maps each row to 0 or 1,
2R N) possible functions
so 2^(2
7/2/2018 CS61C Su17 - Lecture 9 46
 CL: Multiple Outputs
A
X
B
Y
C F
D Z

• For 3 outputs, just three indep. functions:

X(A,B,C,D), Y(A,B,C,D), and Z(A,B,C,D)
– Can show functions in separate columns without
adding any rows!
7/2/2018 CS61C Su17 - Lecture 9 47
 Logic Gates (1/2)
• Special names and symbols:
a c
Circle means NOT!
0 1
NOT 1 0

a b c
0 0 0
0 1 0
AND 1 0 0
1 1 1
a b c
0 0 0
0 1 1
OR 1 0 1
1 1 1
7/2/2018 CS61C Su17 - Lecture 9 48
 Logic Gates (2/2)
• Special names and symbols:
a b c
0 0 1
0 1 1
NAND 1 0 1
1 1 0
a b c
0 0 1
0 1 0
NOR 1 0 0
1 1 0
a b c
0 0 0
0 1 1
XOR 1 0 1
1 1 0
7/2/2018 CS61C Su17 - Lecture 9 49
Question: Convert the following statements into
a Truth Table assuming the output is whether
Damon is comfortable (1) or uncomfortable (0).
• Input X: Damon wears light (0) or heavy (1) clothing
• Input Y: It is cold (0) or hot (1) outside
• Input Z: Damon is indoors (0) or outdoors (1)
X Y Z (A) (B) (C) (D)
0 0 0 1 1 1 1
0 0 1 0 0 0 0
0 1 0 1 1 1 1
0 1 1 1 1 1 1
1 0 0 0 1 1 1
1 0 1 1 1 0 1
1 1 0 1 1 1 0
1 1 1 1 0 1 1
50
Question: Convert the following statements into
a Truth Table assuming the output is whether
Damon is comfortable (1) or uncomfortable (0).
• Input X: Damon wears light (0) or heavy (1) clothing
• Input Y: It is cold (0) or hot (1) outside
• Input Z: Damon is indoors (0) or outdoors (1)
X Y Z (A) (B) (C) (D)
0 0 0 1 1 1 1
0 0 1 0 0 0 0
0 1 0 1 1 1 1
0 1 1 1 1 1 1
1 0 0 0 1 1 1
1 0 1 1 1 0 1
1 1 0 1 1 1 0
1 1 1 1 0 1 1
51
52
 Agenda
• Transistors, Switching Networks
• Meet the staff!
• Combinational Logic Representations
– Truth Tables
– Boolean Algebra

7/2/2018 CS61C Su17 - Lecture 9 53

 More Complicated Truth Tables
3-Input Majority 2-bit Adder
a b c y a1 c2
0 0 0 0 a0
0 0 1 0 b1 + c1
0 1 0 0 b0 c0
0 1 1 1
3 separate
1 0 0 0 functions
1 0 1 1 A B C
1 1 0 1 a1 a0 b1 b0 c2 c1 c0
1 1 1 1 .
How many
.
rows?
.

7/2/2018 CS61C Su17 - Lecture 9 54

 My Hand Hurts…
• Truth tables are huge
– Write out EVERY combination of inputs and
outputs (thorough, but inefficient)
– Finding a particular combination of inputs involves
scanning a large portion of the table
• There must be a shorter way to represent
combinational logic
– Boolean Algebra to the rescue!

7/2/2018 CS61C Su17 - Lecture 9 55

 Boolean Algebra
• Represent inputs and outputs as variables
– Each variable can only take on the value 0 or 1
• Overbar is NOT: “logical complement” For slides,
– e.g. if A is 0, then ¬A is 1 and vice-versa will also use
¬A
• Plus (+) is 2-input OR: “logical sum”
• Product (·) is 2-input AND: “logical product”
– All other gates and logical expressions can be built
from combinations of these
(e.g. ¬AB + A¬B)
7/2/2018 CS61C Su17 - Lecture 9 56
 Laws of Boolean Algebra
These laws allow us to perform simplification:

7/2/2018 CS61C Su17 - Lecture 9 57

 Truth Table to Boolean Expression
• Read off of table a b c
– For 1, write variable name 0 0 0
– For 0, write complement of variable 0 1 1
• Sum of Products (SoP) 1 0 1
– Take rows with 1’s in output column, 1 1 0
sum products of inputs
– c= ¬ab + a ¬b
We can show that these
• Product of Sums (PoS) are equivalent!
– Take rows with 0’s in output column, product the sum of
the complements of the inputs
– c = (a + b) · (¬a + ¬b)
7/2/2018 CS61C Su17 - Lecture 9 58
 Manipulating Boolean Algebra
• SoP and PoS expressions can still be long
– We wanted to have shorter representation than a
truth table!
• Boolean algebra follows a set of rules that
allow for simplification
– Goal will be to arrive at the simplest equivalent
expression
– Allows us to build simpler (and faster) hardware

7/2/2018 CS61C Su17 - Lecture 9 59

 Faster Hardware?
• Recall: Everything we are dealing with is just
an abstraction of transistors and wires
– Inputs propagating to the outputs are voltage
signals passing through transistor networks
– There is always some delay before a CL’s output
updates to reflect the inputs
• Simpler Boolean expressions ↔ smaller
transistor networks ↔ smaller circuit delays
↔ faster hardware
7/2/2018 CS61C Su17 - Lecture 9 60
 Boolean Algebraic
Simplification Example

7/2/2018 CS61C Su17 - Lecture 9 61

 Circuit Simplification

1) (Transistors and/or Gates)

2)

3)

4)

7/2/2018 CS61C Su17 - Lecture 9 62

 Representations of
Combinational Logic
✓ Text Description
✓ Circuit Diagram
– Transistors and wires
– Logic Gates
✓ Truth Table
✓ Boolean Expression

✓ All are equivalent

7/2/2018 CS61C Su17 - Lecture 9 63
 Converting Combinational Logic
Try all input combinations

This is difficult to
Circuit do efficiently! Truth
Diagram Table
Pr hro
op ug

at ut
s
bin np
t
ag h

ion
m ll i
at ga
(e

e s te

co y a
W st t
as
ire o

ign s

Tr
ie

als
inp use

oS
ut AN

rP
st D

Po
op ,O

So
Boolean
ro R,
pe an

Expressi
r
g a

on
te OT)
dN
s

7/2/2018 CS61C Su17 - Lecture 9 64

Circuit Simplification Example (1/4)
• Simplify the following circuit:
A
B D

C
• Options:
1) Test all combinations of the inputs and build the
Truth Table, then use SoP or PoS
2) Write out expressions for signals based on gates
• Will show this method here
7/2/2018 CS61C Su17 - Lecture 9 65
Circuit Simplification Example (2/4)
• Simplify the following circuit:
A
A AB ¬(AB)
B
B A A+¬BC D
¬B
¬BC
C
C
• Start from left, propagate signals to the right
• Arrive a D = ¬(AB)(A + ¬BC)

7/2/2018 CS61C Su17 - Lecture 9 66

Circuit Simplification Example (3/4)
• Simplify Expression:
D = ¬(AB)(A + ¬BC)
= (¬A + ¬B)(A + ¬BC) DeMorgan’s
= ¬AA + ¬A¬BC + ¬BA + ¬B¬BC Distribution
= 0 + ¬A¬BC + ¬BA + ¬B¬BC Complementarity
= ¬A¬BC + ¬BA + ¬BC Idempotent Law
= (¬A + 1)¬BC + ¬AB Distribution
= ¬BC + ¬BA Law of 1’s
Which of these
= ¬B(A + C) is “simpler”? Distribution
7/2/2018 CS61C Su17 - Lecture 9 67
Circuit Simplification Example (4/4)
• Draw out final circuit: How many gates
do we need for each?
– D = ¬BC + ¬BA = ¬B(A + C)
4 3

• Simplified Circuit:
A
B D

C
– Reduction from 6 gates to 3!
7/2/2018 CS61C Su17 - Lecture 9 68