FET DC BIASING

Prepared by:
Seigfred Prado, ECE, M. Sc. ELEG
INTRODUCTION

 The relationship between the input and

output quantities in a field-effect transistor
is nonlinear due to the squared term in
Shockley’s equation.
 The nonlinear relationship between ID and
VGS complicates the mathematical approach
to the dc analysis of FET configurations.

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INTRODUCTION

 The input-controlling variable for a BJT

transistor is a current level, whereas for the
FET a voltage is the controlling variable.
 The general relationships that can be
applied to the dc analysis of all FET circuits
are:

IG  0 ID  IS

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INTRODUCTION

 Shockley’s Equation

2
 VGS 
I D  I DSS 1  
 VP 

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BIASING TECHNIQUES

 FIXED BIAS CONFIGURATION

 The Q-point is established by a fixed amount of
gate-source voltage.

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BIASING TECHNIQUES

 FIXED BIAS CONFIGURATION

Input Loop Equation:

 VGG  I G RG  VGS  0

VGS  VGG

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BIASING TECHNIQUES

 FIXED BIAS CONFIGURATION

Output Loop Equation:

VDD  I D RD  VDS  0

VDS  VDD  I D RD
2
Where:  VGS 
I D  I DSS 1  
 VP 

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SAMPLE PROBLEM 1

 GIVEN: VDD = 16 V, RD = 2 KΩ, RG = 1 MΩ, VGG = 2 V,

IDSS = 10 mA, VP = -8 V
 Determine the following:
VDS = VDD - IDRD
 VGSQ
 IDQ
 VDS
 VD = VDS = 4.75 V
 VG = -VGS = -2V
 VS

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SAMPLE PROBLEM 1

 GRAPHICAL SOLUTION
NOTE: When VGS is equal to
half of VP, the drain current
is equal to one-fourth of IDSS.

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SAMPLE PROBLEM 2

 GIVEN: VDD = 12 V, RD = 1.2 KΩ, RG = 1 MΩ, VGG = 1.5 V,

IDSS = 12 mA, VP = -4 V
 Determine the following:
 VGSQ VDS=VD

 IDQ
 VDS
 VD
 VG =-VGG = VG = 1.5 V
 VS

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SAMPLE PROBLEM 2

 GRAPHICAL SOLUTION
NOTE: When VGS is equal to
half of VP, the drain current
is equal to one-fourth of IDSS.

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SAMPLE PROBLEM 3

 GIVEN: VDD = 14 V, RD = 1.6 KΩ, RG = 1 MΩ, VD = 9 V,

VDS= VDD =IDRD
IDSS = 8 mA, VP = -4 V
 Determine the following:
 ID VD-VDS

 VDS = VD = 9 V
VGS = -VGG = 1.5 V
 VGG

ID = IDSS/4
VGS = VP/2

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BIASING TECHNIQUES

 SELF-BIAS CONFIGURATION
 It eliminates the need for two dc supplies.
 The controlling gate-to-source voltage is
determined by the voltage across the resistor
RS.
 Recall that a JFET must be operated such that
the gate-source junction is always reverse-
biased. This can be achieved by the self-bias
arrangement.

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BIASING TECHNIQUES

 SELF-BIAS CONFIGURATION

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BIASING TECHNIQUES

 SELF-BIAS CONFIGURATION

Input Loop Equation:

0  I G RG  VGS  I S RS  0
NOTE: ID  IS

VGS   I D RS

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BIASING TECHNIQUES

 SELF-BIAS CONFIGURATION
• Substitute VGS   I D RS to Shockley’s Equation:
2 2
 VGS    I D RS 
I D  I DSS 1   I D  I DSS 1  
 VP   VP 
2
 VP  I D RS 
I D  I DSS  
 VP 

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BIASING TECHNIQUES

 SELF-BIAS CONFIGURATION
I DSS
VP
2

I D  2 VP  2 I D RSVP  I D RS
2 2

2 2
2 I DSS RS I D I DSS RS I D
I D  I DSS   2
VP VP
• Rearranging:
  RS 
2
 2  2I R 
 I DSS    I D   DSS S
 1 I D  I DSS  0
  VP    VP 
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BIASING TECHNIQUES

 SELF-BIAS CONFIGURATION
• Recall: Ax  Bx  C  0
2
(Quadratic Equation)

 B  B  4 AC 2
x
2A
• Let:
2
 RS  2 I DSS RS
A  I DSS   B 1 C  I DSS
 VP  VP

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BIASING TECHNIQUES

 SELF-BIAS CONFIGURATION

 B  B  4 AC
2
ID 
2A

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BIASING TECHNIQUES

 SELF-BIAS CONFIGURATION
 GRAPHICAL SOLUTION
 Assume a value for VGS by letting ID = 0.5 IDSS.
 On the transfer curve, draw a line from the
origin to the point (VGS, ID), where ID = 0.5 IDSS.
 The intersection of the line with the transfer
curve gives us the Q-point (approximate
value).

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SAMPLE PROBLEM 1

 GIVEN: VDD = 20 V, RD = 3.3 KΩ, RG = 1 MΩ, RS = 1 KΩ,

IDSS = 8 mA, VP = -6 V
 Determine the ff:
 VGSQ = VGS = -IDRS =
 IDQ
 VDS VDS = VDD - ID(RS+RD)

 VS = IDRS =
 VG
 VD
ID = IDSS/2 = 4 mA

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SAMPLE PROBLEM 1

 GRAPHICAL SOLUTION

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SAMPLE PROBLEM 2

 GIVEN: VDD = 18 V, RD = 1.5 KΩ, RG = 1 MΩ, RS = 750 Ω,

IDSS = 10 mA, VP = -4 V
 Determine the ff:
 VGSQ = - IDRS = -3.75 V
 IDQ
 VDS = VDD -ID(RS+RD)
 VS
 VG
 VD

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SAMPLE PROBLEM 2

 GRAPHICAL SOLUTION
ID = 5 mA

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SAMPLE PROBLEM 3

 GIVEN: VDD = 18 V, RD = 2 KΩ, RG = 1 MΩ, RS = 510 Ω,

VS = 1.7 V, VP = -4 V
 Determine the ff:
 VGSQ
 IDQ
 VDS = VDD - ID(RS+RD)
 IDSS
 VD

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BIASING TECHNIQUES

 VOLTAGE-DIVIDER BIAS
 The bias is provided by a voltage divider
network at the input side.

R2
VG  VDD
R1  R2

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BIASING TECHNIQUES

 VOLTAGE-DIVIDER BIAS

Input Loop Equation:

VG  I G RG  VGS  I D RS  0

VGS  VG  I D RS

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BIASING TECHNIQUES

 VOLTAGE-DIVIDER BIAS
• If we substitute VGS  VG  I D RS to Shockley’s Equation,
we will arrive at the following equations:

 VG 
2
 RS  2 I DSS RS
1    1
A  I DSS   B
 VP  VP  VP 
2
 VG 
C  I DSS 1  
 VP 

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BIASING TECHNIQUES

 VOLTAGE-DIVIDER BIAS

 B  B  4 AC
2
ID 
2A

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BIASING TECHNIQUES

 VOLTAGE-DIVIDER BIAS
 GRAPHICAL SOLUTION
 Assume two values for VGS by letting ID = 0 and
ID = 0.5 IDSS.
 On the transfer curve, draw a line from (VGS1, ID1),
where ID1 = 0, to the point (VGS2, ID2), where
ID2 = 0.5 IDSS.
 The intersection of the line with the transfer
curve gives us the Q-point (approximate value).

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