CMOS Analog IC Design SE

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Chapter 5

Single Stage
Differential Pair Amplifier

jwu@seu.edu.cn

Version-II, 2012,09
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Differential Pair single stage Amplifier
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What – Structure
Why – Common Mode problems
How – Operation principles and limitations
Key points:
1. Signal in differential (AC small) mode and in Common
mode (DC large), differential gain & common mode gain, same?
2. Small signal gain improved for differential pair as compared
with classical CS under same static current?
3. CMRR and CM range for input signal improved? And how
the CM & DM signal can be distinguished by differential pair?

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DP Symbol
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High frequency, high speed, Low Voltage, low

power OP, Differential Pair is in critical.

SE: D-in; SE-out Fully Differential:

D-in & out
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DP Amp: Contents & primary structure
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Fully differential:
Differential IN,
Differential OUT

2 configurable
CS coupled?

Differential pair Tr: A pair of same type of amplified transistors, M1/M2;

Load of DP: can be passive or active, fully differential or single end output;
Tailing current or resistor: constant current source to biasing DP.
Single end view: CS with (for CM) or without (for DM) source resistor.
Differential view: additional rejection for CM by symmetrical structure.
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DP Amp: Signal type related behavior
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Differential input: Vid=Vin1-Vin2, generally

is AC small signal property.
Common mode input: ViC=(Vin1+Vin2)/2.
generally is DC/AC large signal property.

x For any type of input signal Vin1,Vin2

1 1
Vin1 = ViC + Vid ; Vin 2 = ViC − Vid
2 2
If Vid=0, Vin1=Vin2=ViC, CM voltage obtained.
For CM ViC input, x-gnd (-Vss) sees a large resistance of RS;
For DM Vid input, x is virtual grand, or RS=0. (valid for small signal)
In this way, DM & CM signals are well distinguished by DP.

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DP Amp DC & AC Common Mode Problems
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Split the circuit in two symmetrical parts.

For CM input, if it is variable, the gain is
g m1,2
AV _ CM _ SE = −Gm ro ≈ − RL
1 + g m1,2 (2 RS )

x AV _ DM _ SE = − g m ro ≈ − g m1,2 ( RL / / rn )

AV _ DM RL / / rn
CMRR = ≈ (1 + 2 g m1,2 RS ) ≈ γ g m RS γ≈1-2.
AV _ CM RL

Due to differential output by Vo+=Vo- for CM Voltage, so CMRR of

fully differential output DP is approaching to ∞.
Input common range (PMOS): VTN+2Δ≤VCM≤VCC
(NMOS): 0 ≤VCMΔ≤VCC-(VTP+2Δ)
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DP Amp with current source as loads
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Fully differential output Single output by current mirror

Vic,min=VTH+2Δ

Single LF Pole, Vic,max=VCC, Double Poles, one low & one high,
High PSRR, CMFB needed Vic,mam<VCC, No CMFB is needed.
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DP Amp: PMOS Vs NMOS type
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5Tr-DP

structure
⇔
mirrored

N_DP: High CM, Fast, small area; P_DP: Low CM, Slow, Low Noise

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Dynamic behavior of fundamental DP
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Restriction from structure & operation mode

I1 + I 2 = I SS
solved
ΔI DS = I1 − I 2
Vid = VGS 1 − VGS 2
⇒
2 (VGS − VTH )

= 2 I1 / k1 − 2 I 2 / k2

Odd harmonic left 1 4 I SS kVid2

ΔI DS = kVid − Vid = Vid kI SS ⋅ 1 −
2

I1 = ( I SS + ΔI DS ) / 2; 2 k 4 I SS
⇒ kVid2
I 2 = ( I SS − ΔI DS ) / 2
≈ g mVid (1 − )
8 I SS
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Dynamic & linear range of DP
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Due to symmetrical structure, even harmonic

are removed, only odd harmonic components
are existed.
Linear term: linear amplification, linear range;
2 (VGS − VTH )
High order odd harmonic: distortion for Linear
Amplification.

Dynamic Range: Vid is large enough to make I1 or I2 cut-off critically, ΔIDS=±ISS

Related with static
Vid ,max = ± 2 I SS / k1,2 = 2 2( I SS / 2) / k1,2 = 2Δ M 1,M 2
overdrive voltage
Linear range: the acceptable range valid for io=ΔIDS≈gmVid approximation,
LR is far smaller than the maximum dynamic, so LR is nonlinear error level
related, strict linear requirement results in a narrow linear range. If errors
level is same, LR will expand with extension of DR.
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Linearity improvement methods
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nonlinear error = N %
linear accurate = 1 − N %
} ⇒ 1-N = 1 −
kVid2
4 I SS

I SS Vid ,line
⇒ Vid ,lin = 2 [1 − (1 − N ) 2 )
k1,2
⇒ Vid ,max
= 2[1 − (1 − N %) 2 ]

Linear range is only a portion of total dynamic range,

The linear range is error sensitive, more error permitted,
wide the linear range (LR).
Large dynamic range, more errors can be tolerated, large LR.

Example: N=1%, LR Ratio≈20%; Errors occurred

N=10%, LR Ratio≈61.6%; in large DR!

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Slew Rate: Larger Signal Performance
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Single Stage

dQ dV
iC = =C C
dt dt

dVC (t ) iC
SR = =
dt C

I C ,max
SRmax =
C

The peak SR is limited by ISS the

tailing current in DP. Fast SR &
low power are in conflict

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Slew Rate in multi-stage Amplifier
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The internal slew rate is generally limited by current available

to charge and discharge Cc from input stage. Therefore,

dVo I x I SS I SS g m1 I SS
SRint = = = = = × GBW
dt max CC CC g m1 CC g m1
= (VGS 1 − VTH 1 ) × GBW = Δ1 × GBW

The external slew rate is limited by the available current to charge

and discharge CL. Thus,

I out − I x (max) I out − I SS

SRext = = SRmax = min(SRint , SR ext )
CL CL
Settling time minimum if larger GBW & SR are combined.

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Offset Voltage Definition
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Mismatch of DP: Symmetrical in form (Theory), not in real (Practical);

Offset voltage applied at input to compensate the circuit errors or
mismatches and to recovery the symmetrical property.
Definition: Applied Differential Signal of Vos to set static output of OP
that at any point changing to the need Common state of VDD/2

Example: Unit FB Follower with Vref input at V+

VCM − Vref VCM ,real − Vref
Ideal distinguish Vid = practically Vid ,real =
AV AV
VCM ,real − VCM
Offset VOS = Vid ,real − Vid = High gain Æ less offset
AV
Demand: VOS <<Vin, offset can be ignored, even though gain is high

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VOS Voltage Calculation
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Tow Part: Process Radom Offset+ Systemic Offset

VOS = VOS , R + VOS , S

g m3 (VGS − VTH )1,2

VOS , R = ΔVTH 1,2 + ΔVTH 3,4 VOS ,S = (λ3 + λ1 )(V1 − Vy )
g m1 2
(VGS − VTH )1,2 g m3 1 1
− MG = =
2 g m1 g m1/g m 3 gain(CM Load )

Δ(W / L) Δ(W / L)
MG = [ ]1, 2 + [ ] 3, 4 Poor conditions?
(W / L) (W / L)

Random offset voltage is dominant and hard to cut-down !

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Error by Variation of W & L
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For strong inversion operation conditions

ΔI DS ∂I DS 1 I DS I DS k Δ 2 / 2 Δ
≈ = k 'Δ 2 = = =
Δ (W / L) ∂ (W / L ) 2 (W / L) g m1 kΔ 2

ΔI DS ro ΔI DS Δ (W / L) Δ (W / L) I DS Δ Δ (W / L)
Vos ,W / L = =− =− × =− ×
− g m1ro Δ(W / L) g m1 (W / L) g m1 2 (W / L)

Δ(W / L) Δ(W / L)
Total W/L mismatch MG = [ ]1, 2 + [ ] 3, 4
(W / L) (W / L)

ΔI r I λ ΔV Δ
System mismatch Vos ,ΔV = DS o = − DS T D = − × λT (Vout -Vy )
Induced.
− g m1ro g m1 2

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Variation of Classic DP Amplifiers
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Modifications in structures For improving properties

- Differential pair transistors - linear range
- Differential pair loads - gain & gain stability
- Differential pair tailing current - large Common range
may be individually - CMRR & PSRR
or combined. - Speed (GBE & SR)

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LR improved by Gain Limited
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Passive way: Increasing ISS to extend DR, thus get a large LR

Basic way: Decreasing gain by small source resistor RS,
transient slope reduced to improve LR.
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Cross-Coupled DP used for NL Error Eliminate
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k1,2
Main DP I1 − I 2 ≈ k1,2 I SS 1Vid (1 − Vid2 )
8 I SS 1
k3,4
CC DP I 3 − I 4 ≈ k3,4 I SS 2 Vid (1 − Vid2 )
8I SS 2

Output current by compound DP

I o = I1 + I 4 − ( I 2 + I 3 ) = ( I1 − I 2 ) − ( I 3 − I 4 )

Two NL can be compensated

3 3
Vid3 k3,4 k1,2
I o = Vid ( k1,2 I SS 1 − k3,4 I SS 2 ) + ( − )
8 I SS 2 I SS 1
k
NL canceled I SS1 = ( k1,2 )3 but I SS 1 ≠ 3,4 Two DP can not be the same.
Conditions: I SS 2 k3,4 I SS 2 k1,2

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Cascode DP Amp: Telescope & Fold type
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Telescope cascode Fold cascode

VCC
ISS/2 ISS/2
+ Vo -

Vbn
M3 M4

+ M1 M2 VI2
Vi
-

ISS

-VSS
Swing Lost, suitable for input Wide output Swing, wide input CM
signal with fixed CM level. range, Current doubled.
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Telescope cascode DP Amplifier
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Telescope cascode biasing voltage set the upper limit of input signal.

Push-pull TS Cascode, Self-adjustable

Output doubled? Cascode biasing
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Folded Cascode DP Amplifier
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CS: NMOS DP

CG: PMOS
(middle)

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Regulated Cascode DP Amp: Gain Boost
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Regulated cascode used either in DP and Loads for gain boost.

Auxiliary fully
differential DP
Primary DP
may be FD or
SE output DP

AFD-DP: type?
CM level?
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DP Amp with Diode Loads
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Low output resistance Æ small gain, gain stable, increased driving

capability, it’s poor than that of closed loop Amplifier with FB.

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DP Amp with combined loads
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Why the combined Trade-off between large

loads are used? and small output load.

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Nearly Symmetrical DP Amp: OTA
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OTA: Operational Transconductance Amplifier

Symmetrical;
Push-pull output;

Gm
AV ( s ) =
g dT + sCL

Gm = M × g m1, 2

io = GmVid

Conception:
V-A & TC-A

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OTA with Combinational Loads
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The static current in MOS diode loads are reduced for total
static current limitation, gain improved but SR degenerated.

Which loads are additional? Current or Voltage transfer?

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OTA: Cascode output stage for improving gain
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MC3 for matching: M6~M9

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Cross-Couple Load & output cascode OTA
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Cross Pair (CP): M7 & M8, (W/L)M7,M8<(W/)M5,M6, to reduce effective

W/L of MOS diode load. CP is only effective in small AC conditions
for gain improvement due to gm boost (large AC current transfer ratio),
while static current transfer ratio is remain small.

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OTA: Modifying in Tailing Current Biasing
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Static tailing current + dynamic tailing current biasing

M18: IM18=I2-I1 if I2≥I1, otherwise IM18=0;

M9: Static biasing
M19: IM19=I1-I2 if I1≥I2, otherwise IM19=0;
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Regulated Fully Differential Cascode DP
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M4a M4b
Vcmfb
Vbp1
M4r
Vya Vyb
Primary Amp is fully
+
differential regulated
-
CMFB + A

-
M3a M3b

Vbp2
cascode DP, CMFB
Vyop Vyon M3r
Von needed to stabilized the
Vxop Vxon
Vop
Vbn2
CM levels of main Amp.
M2r

M2a M2b
B+
Tailing current biasing
-

+
-

Vxa Vxb M1ar M1br

Vip
modifying suitable for
Vip M1a M1b Vin Vin
low power operation.
M5 M5r

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Example: Mode, Structures integration
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Class A
Class B
Class AB

Push-Pull

Push-Pull + Class AB for

Low power operation;
Fast driving capability;
NL compensated for wide LR.

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Single End- Different End, SE-Push Pull
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Class AB?

No fixed tailing
current source!

Push Pull?

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N+P MOS equivalent DP Biasing
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Class AB operation, No fixed tailing current

same
⇔

Biasing outside Biasing inside

Compound DP: N+P MOSFET

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Compound DP treated as a classic DP
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For compound DP, the total VGS under the static current I=ISS:
1 1
VGS ,T = VGSn + VGSp = ( + ) 2 I + (VTN + VTP )
kn kp
If it’s treated as a single equivalent transistor, then:
1
VGS ,eq = VGS ,T = 2 I + VTH ,eq = Δ eff + VTH ,eq
keq
Where the equivalent single transistor model for DP are:
knk p
k eq =
( kn + k p )2 1

{
I D1 = k eq (VGS1eq − VTHeq ) 2
2
VTH ,eq = VTN + VTP ⇔
1
I D 2 = k eq (VGS 2eq − VTHeq ) 2
Δ eff = 2 I / keq 2
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Class AB for Linearity improvement
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Output current by Differential mode Io=ΔI=M(ID1-ID2):

1
Io = Mkeq (VGS 1eq + VGS 2 eq − 2VTHeq )(VGS 1eq − VGS 2 eq )
2
Both VGS1,eq & VGS2,eq are variable, but DM & CM signal satisfied:

VGS1,eq − VGS 2,eq = Δ1,eff − Δ 2,eff = Vid (Similar as classic DP)

VGS 1,eq + VGS 2,eq -2VTH ,eq = Δ1,eff + Δ 2,eff = 2Δ eff (Different with classic DP)

Linearity holds within fully dynamic range by nonlinear canceled off

1
Io = Mkeq (2Δ eff )Vid = Mkeq Δ eff Vid = M 2keq I SS ⋅ Vid = Mg m ,eff Vid
2
M: current ratio delivered to the output.
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A fully differential class AB DP Amplifier
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Symmetrical structure;
Output Cascode;
CMFB needed;

Large SR & high speed;

Linearity;
High gain;

N-Upper/P-Down:
remain suitable for
wide CM & PSRR
High VCC;

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Summary
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Primary Differential Pair Amplifier : 5 Transistor Architecture;

2 Transistors: differential pair amplifying, self-configurable CS;
2 Transistors: Active loads, FD/SE, translate differential voltage
to differential output current;
1 Transistors: Static tailing current biasing for PSRR improving.

Variable in DP Amplifier :
Structure modified or varied both in DP Tr., load Tr and tailing
current biasing Tr individually or combinative, Mode selected;
For overall performance improvement both in DC, AC, Transient
suitable for small & large signal.

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Break
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END of Unit 5

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