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•Differential-mode output
•Common-mode output
•Voltage
V lt gain:
i N Note
t th
the effects
ff t off the
th mismatches,
i t h especially
i ll iin Ad
Adc and
dAAcd
d
OCMR VDD VSS VDSsatN VDSsatP OCMR VDD VSS 2VDSsatN 2VDSsatP
•Both output voltages are measured. Since we only want feedback on the common-mode
signals, we have to cancel out the differential signals. This is done at node 4.
•Now we have to close the loop with an amplifier,
amplifier and feed it to a common-mode point.
point Any
biasing point in the circuit can be used for that. For this amplifier it is node 5.
•Clearly, part of the circuit belongs to both the common-mode and the differential amplifier. For
example, transistors M3 and M4 are DC current sources for the differential signals, but single-
transistor amplifiers for the common-mode signals.
•Also, the CMFB amplifier is always connected in unity-gain feedback. Nodes 1 and 2 are at
the same time the input and output of the CMFB amplifier. It may thus require more power to
ensure stability.
stability
•The differential amplifier is evidently shown without feedback
Radivoje Đurić, 2015, Analogna Integrisana Kola
10
Simple CMOS fully-differential OTA with CMFB-2
•Again, the output voltages are measured. The differential signals are cancelled out and the
CMFB loop is closed by means of an amplifier.
amplifier
•Now transistors M1 and M2 are common to both amplifiers. They function as a (differential)
amplifier for differential signals, but as cascodes for the common-mode signals.
•The common-mode equivalent circuit is easily found by putting all differential devices in
parallel and connecting them to the common-mode input signals
•Actually, the open-loop gain is B1B2gm5Rn1 . This gain is not so high but only a small amount of
gain
i iis needed.
d d
•The stabilization of the common-mode output voltage does not need to be so accurate.
•The outputs will both be at VGS5,6 above the negative supply.
The GBWCM will evidently be given by the B1B2gm5/(2πCL). We have two input transistors M5
•The
and M6 but also two load capacitors. The GBWCM can therefore be made quite high, at the
cost of a lot of power consumption though!
•Finally, it is important to note that the gain of the CMFB amplifier is used to increase the
common-mode d rejection
j ti ratio.
ti
•It is clear that in the linear region, the transconductances are much smaller than in the
saturation region. The common-mode GBWCM is therefore smaller than the GBWDM. This is a
disadvantage!
•Why do the transistors M3 operate in the linear region?
•There
There are two reasons:
First of all, to have an output voltage in the middle, we need a large VGS3. So as not to
loose a large voltage drop, we need a small VDS3. Clearly M3 must be in the linear region.
The other reason is linearity. We need a linear cancellation of the differential signal to
avoid the reduction of the differential gain because of the feedback. Transistors in the
linear region are very linear indeed!
The main advantage of this first principle of CMFB is that no additional power is required.
The main disadvantage is that this CMFB amplifier may not be sufficiently fast, depending on
the application.
Radivoje Đurić, 2015, Analogna Integrisana Kola
17
Fully-differential amplifier with resistive CMFB
•This fully-differential
y amplifier
p uses two equalq
resistors R to cancel out the differential signals. In
this way a common-mode biasing voltage is
obtained for the gates of transistors M2.
•The main disadvantage is that the resistors R
must be increased in size to ensure a lot of gain.
•An easy solution is to insert source followers
between the drains of the input
p transistors M1 and
the two resistors R. Smaller values of R are then
possible.
Vo+ Voc
CM VoCM
Vo- detect M5
M6 M7
M1 M2
I B g m6
•M6, M7 matched I c 6,7 Voc V0cm
4 2
•The
The CMFB loop will adjust Ic6,7
6 7 so that
I D 3 I D 4 2 I c 6,7
6 7 I D5
IB VCM IB
M3 M4
Vo+ M1 M2 Vo-
-Δi
+Δi
+Δi -Δi
M5 +Δi
+Δi
VCMFB -Δi
-Δi
Δi=0 2Δi
Vin
Vin Vcm
2
Vin
Vin Vcm
2
V V
I C ,d g md Vcm in I C ,d g md Vcm in
2 2
V V
I 0 I C ,d I C g md Vcm in I C I 0 I C ,d I C g md Vcm in I C
2 2
Vin V
g mc g md I 0 g md , I 0 g md in
2 2
•Correcting
C ti signal
i l can b
be voltage
lt or current.
t NNote
t th
thatt IIo+, and
d IIo- are equall tto
I 0 g m Vin Vin
I 0 g m Vin Vin
•That
That is, we are sensing the input voltage. We are not sensing the output voltage. In practice
the value of aIo is a = 1 or a = 1/2.
Radivoje Đurić, 2015, Analogna Integrisana Kola
24
FD OTA with common-mode feedforward (current-mode)
•Current
Current addition transformed into a Vcm
•Since Vreference = 0, Vcorrection = Vcm and can be applied to MY’ and MY
i1 i2
M7 M3 M4 M8
M5 M6
VSS
1
i7 i5 i3 i1 i8 i6 i4 i2 i11 i12 i1 i2
2
i9 i11 i10 i12
i i i i i i i i
iI 1 i10 i8 1 2 i2 1 2 iI 2 i9 i7 1 2 i1 2 1
2 2 2 2
B B B B
i1 vGS1 VTP vGS1 VT i2 vGS 2 VTP vGS 2 VT
2 2 2 2
2 2 2 2
i1 i2 B v1 v2 iI 2 i2 i1 B v2 v1 VDD v1 v2 VT
iI 1 v2 v1 VDD VT
2 2 2 2 2 2
Radivoje Đurić, 2015, Analogna Integrisana Kola
27
g d ii / vd ?
vd 1 1
vggs 5 vggs 7 rd 1 g m rd 1 rds1 || rds 3 ||
2 gm gm
rds 9
vd vd vd
ii1d gm vgs 5 vgs 7 ii1d g m vgs 7 g m
2 2 2
i g ii 2 d g
g md 1 i1d m g md 2 m
vd 2 vd 2
rd1 vgs 5 vgs 7
rds 7 g m vgs 7 g m vgs 5
g d ii1 ii 2 / vd g m
g s ii / vs ?
v1 v2 vgs 9 rd 5 g m vgs 5
vs
2
g m vgs 9
rds 9 1 1 1
rd 5 vggs 9 rd 5 rds11 || rds 5 || vgs 5 vgs 7 g m vs vs
gm gm gm
g m vs
ii1s 1
vgs 9 g m vs vs
gm
rd1
vgs 5 vgs 7
ii1s g m vgs 7 g m vgs 9 g m vgs 7 vgs 9
rds 7 g m vgs 7 g m vgs 5 ii1s g m vs vs 0
CMRRideal
•Next OTA is detecting the common mode from this OTA and feeding back to this OTA.
Radivoje Đurić, 2015, Analogna Integrisana Kola
29
•Fully Balanced 4 current-mirror OTA
•Block
Bl k Di
Diagram R
Representation:
t ti
•When a clock is available, as in all sampled data circuitry, it can be used towards a low-
power CMFB loop.
•The outputs are measured by a number of switches and capacitors, which provide common-
mode feedback to the gates of transistors M11/M12.
•This feedback is not applied directly to the Gates of M8/M6 to make sure that not all current
can be switched in the output devices. For common-mode disturbance in the supply lines or
substrate, large transients at the outputs can be avoided in this way.
In this slide, clock W1 is high, all the transistors, which are driven by this clock, are on. The
other
th ones are off. ff Thick
Thi k lines
li i di t which
indicate hi h paths th theth signals
i l can take.
t k Clearly,
Cl l the
th outputs
t t
are AC coupled by capacitors C1/C2. Their differential content is then cancelled out. Finally,
this signal is then applied to the Gate of transistor M12 to close the feedback loop.
The GBWCM is set by gm12 and the output load capacitor.
The
The DC level at the Gate of M12 is not defined because of the coupling capacitances
C1/C2. Radivoje Đurić, 2015, Analogna Integrisana Kola
34
•This is why the other two capacitances C3/C4 are precharged to the proper DC voltages.
•Their left side is set to analog ground (Vdd/2), whereas their right side is set at a biasing
voltage which is the same as at the Gates of current mirror transistors M5/M6/M8.
voltage, M5/M6/M8
•On the next phase, the capacitors are swapped around, as shown in the next slide.
Continuous CMFB is thus ensured.