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CMOS Analog IC Design

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Chapter 6

Operational Amplifier Design

jwu@seu.edu.cn

Version-II, 2012, 09

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2-Stages Operational Amplifier (OP-Amp)
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Open loop: generally 3 stages: DP + CS + V-Buffer (selectable),


2 LF poles, 1 HF pole.

Why input stage always using DP ?


Second Stage using CS for gain, complementary with DP in type;
Output stage using CD (or/even Push-Pull) for load driving.
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Example 1A: N-DP/P-CS/CD-Buffer
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Internal node CM
Voltage is clamped by
VGS of next stage;
Level matching

Define of output
CM voltage ?
for output, the next
stage is input stage;
Because FB used!

OP always operated under the Feedback control!

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Example 1B: P-DP/N-CS/CD-Buffer
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CM:
low ends

Mode: Class A, Matching Need for 2nd stage

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2-Stage Amp with internal level shift
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Telescope cascode DP
with adaptive biasing

CD buffer used for CM


voltage level shift

P-CS output stage

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2-stage Class A/Push-Pull OP
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Unsymmetrical push-pull for Output stage, polarity in driving


M6 & M7 is the same, but magnitude is different, more similar as
conventional 2-stage OP, suitable for class A biasing.

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2-stage Push-Pull/Class A or AB OP
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Internal CD CM level shift used to provide the same driving


voltage in polarity & AC magnitude for M8 & M9 (AC short);
It can be biased on either class A or class AB. RHP zero in
class AB is more serious and should be removed far away.
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2-Stage OP design Principle
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Primary operation conditions:


Structure used
Power VDD, Total Static current, Load
Key Specs: DC: Static point
Gain, Bandwidth, GBW, SR, settling time,
AC: small signal
PM, VCM, CMRR, PSRR, Vos
Process conditions: Transient:
gain factor k’, VTH, VA0, n, γ, ϕf ; large signal

The results are not unique, optimal design required!

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W/L design Principle
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The total static currents are divided to each branches, unless


special indicated, strong inversion driving condition with
Δ(I)=Δmin=0.2V is adopted by low voltage and low power
requirement , and the W/L of corresponding MOS can be
simply determined by

1 W 2 W 2I restriction
I DS ≈ k ' Δ ⇒ ( ) = DS2
2 L L k'Δ Accuracy ⇔ Speed

For DP transistors or other transistors:


large L and thus W are benefit for less VOS, high gain,
but lost in speed and area.

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PMOS DP design Example
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Primary parameters in SIMC 0.13μm CMOS process


kn’=182.7μA/V2, kp’=54.3μA/V2; γn≈γp≈0.82V1/2;
VTN=0.55V, VTP=-0.65V; VAN0=20V/μm, VAP0=50V/μm.

ISS=10μA, I1=I2=5μA, Iout,max=10μA, SI mode with Δ≈0.2V

W W 2 ×10 μ 20 9.2μ m 18.4


( )M 1 = ( )M 2 = = ≈ 9.2 = =
L L 54.3μ × 0.22 2.172 1.0 μ m 2

Selected: L=2 μm, W=18.5μm Gain, GBW, PM, -- ok?

Initial W/L & thus W,L are coming from static point condition,
And modified by AC and transient requirements.

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Frequency Response & Compensation
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Frequency Response (behavior)


- Why & how the circuit gain behavior varied with frequency
- capacitance effects Gain/Phase Shift ~ f
System stability requirement
- poles and zero, Open loop & closed loop (FB)
- PM/GM
Frequency Compensation principles
- Miller capacitance methods.

To guarantee the op stable operated under closed feedback loop


and wide frequency range environments

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Phase shift of capacitor with frequency
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Capacitive Load effect


inducing AV ↓ , Phase shift ϕ ↑; NF ⇒ PF, unstable.

Phase shift quantities: related with relative relation between f~fp


f<<0.1fp, ϕ≈0, No PS;
ϕ = -arctg ( f/f p )
f=0.1fp, ϕ≈-5.7°, PS start;
f=fp, ϕ=-45°, PS linear with frequency; -3dB bandwidth
f=10fp, ϕ≈-84.3°, PS tend to saturation.
f>>10fp, ϕ≈-90°, maximum PS by one pole.
Phase shift concentrate around fp 10times front and back.
Linear system: PS from multi-pole or zero can be linear summed up.
zero and pole? Phase shift polarity: RHP zero ⇔ LHP pole
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FP: Gain Degradation & Phase Shift
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Function of LHP Pole


• Gain Degradation
-20dB/Dec, -6dB/Oct
• Phase Shift - (Negative)

Linear
approximation

1 1 p 1 1 1
G ( s) = ≈ = G ( jω ) = = =
1 + s / p s / p jω 1 + jω / p 1 + j1 2
p: Dominant Pole, -3dB Bandwidth ∠G ( jω ) = −45 o
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Loop Gain ~ FB ratio
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AV: open OP gain; ACL: Close loop gain; AV0/ACL0: gain in DC or LF.
For voltage-series negative FB with FB ratio F, ideal close loop gain.
AV 1 T 1 1 ACL 0
ACL = = = −1

1 + FAV F 1 + T F 1 + T 1 + T −1

Loop gain T=FAV, consider if positive FB happened when T=1 by


phase shift in high frequency, true for oscillation.
Fmax=1 under passive FB network, thus AV is degenerated more in
HF when T=1, phase shift is maximum. So, if CL OP is stable
under F=1(worst case), it’s more stable when F<1.
Worst case under F=1: T=FAV=AV, T=1→AV=1→phase shift reach
to 180° at GBW frequency to form positive FB?
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Open Loop ~ Close Loop (PM)
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For open loop: all poles are LHP in nature, in generally open
loop is convergence.
For closed loop: poles are changed by FB, it’s possible to turn
original pole from OL-LHP to CL-RHP, bring in disperse.
It’s enough only when all closed loop poles are keep as LHP?
CL-LHP is not enough, CL should be far away from Positive
FB to obtain sufficient phase margin (PM) for stability. Over
stability with more PM is slow in transient response.
Phase margin: Phase shift distance when positive FB occurred.
it’s poles & zero numbers and operation frequency related.
PM: minimal 45° (fast); middle 60° (optimal), >70°(slow)

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Loop gain: form & content, relation
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In the form, CL & OL are related & relative.


For a particular transportation function, it can be achieved by
OL, or CL.
A CL-TP function, can be treated as a single OL-TP function
of the upper level system.

For OL single pole approximation, the CL formed with small


gain and wide band, F×GBW is -3dB bandwidth of CL-OP.

1 1 A 1 ACL 0
ACL ( s ) = = 0 ≈
F 1 + 1 + s / p 1 + T0 1 + s
1+
s
T0 (1 + T0 ) p F ⋅ GBW

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Root Locus: Close Loop Poles Shift
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To=|ao|f

OL pole is push left by (1+T0) time if negative FB hold.

OL-pole is push right, if


T<1, CL-pole remain in
LHP, if T>1, CL-pole
entering RHP, for T=1
the CL-pole is located
at boundary between
LHP and RHP.
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Frequency property characteristics
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1 RL
Compound Loads X o (ω ) = RL / /( )=
sCL 1 + sRLCL
g m RL AV 0 1
AV ( s )=-g m X = − = p=
1 + sRLCL 1 + s / p RL C L

gm
-3dB, |AV|=AV0/√2, GBW = p−3dB AV 0 ≈
CL
io g mVin g 1 gm
= = m × =1 ⇒ ωT =
iin Vinω T C gs C gs ω T Cgs

Device > Circuit;


ωT >>GBW Frequency property:
current > voltage
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Single pole unconditional Stable system
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For one pole system, only one dominant pole within GBW

GBW = AV 0 pd >> pd

The maximum phase shift at GWB is ϕ=90° at most, so PM=180


-ϕ≥90°, OP is stable at any situation, gain is poor. If secondary pole
or other HF poles far large than GBW, the circuit can be treated as
single pole system when the relation between poles and GBW are
unchangeable;
-- When HF poles approaching to GBW, PM decreased;
-- If HF poles<GBW, turn to two pole conditionally stable system.

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Two Poles conditional Stable Systems
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Simple (instinct) two pole system formed by two-stage Amp


AV 1,0 AV 2,0 AV 0 AV 1, 0 = − g m1ro1 ;
AV ( s ) = =
(1 + s / p1 )(1 + s / p2 ) 1+(p1-1 +p2-1 )s +(p1 p2 )-1s 2 AV 2, 0 = − g m 2 ro 2
a b
Two poles: real & separated for each other

If p1<<p2, p1 is dominant pole; AV0p1<p2 ? 1 a


p1 ≈ , p2 ≈
a b
g m1ro1 g m 2 ro 2 g m1
GBW ≈ p1 AV 0 = = AV 2,0
ro1C1 C1

Generally, gm1/C1>p2, so p2<<GBW, PM≈0, oscillation.


Frequency compensation needed to maintain system stable.

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Parallel & Miller Cap Compensation Principles
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Aims: separate two poles of p1 & p2 by decreasing the small one,


increasing the larger one.
Methods: adding parallel cap. to surprises pole of this node;
cut-down the output resistance in HF to extend the poles

Parallel Cap. Compensation way:


- only decreasing the dominant pole to surprises GBW far small
than secondary pole by ultra large compensation cap.
Miller Cap. Compensation way:
- decreasing front stage pole
- simultaneously extend back stage pole
thus two poles are separated and HF pole is more easy located
outside GBW to grantee the sufficient PM.
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Miller Cap. Needed
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Miller Cap (Cm). Equivalent to the front C1,eff = C1 + AV 2,0Cm ≈ AV 2,0Cm

Back stage output resistance reduction ro 2,eff = ro 2 / /(1/ g m 2 ) ≈ 1/ g m 2

The variation of two gain stage poles

}
If p2>>GBW
1 1 1
p1 = ⇒ p1 = ≈
ro1C1 ro1C1,eff ro1 AV 2,0Cm g m1
GBW ≈ p1 AV 1,0 AV 2,0 =
Cm
1 1 g
p2 = ⇒ p2 = = m2 gm2 g necessary
ro 2C2 ro 2,eff C2 CL >> m1
CL Cm
For PM=60°, p2≈√3×GBW g m1
⇒ Cm ≥ 2 CL restriction
GBW
= arctg (180 - 60 - 90) =
1 gm2
p2 3
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RHP zero by Miller Cap.
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How zero formed ? Why RHP zero by Miller Cap? How to deal with?

Except conventional resonant way, feed forworth


to make output current disappear can generate zero.
io =0 ⇒ vo = 0
g m 2vo1 = (vo1 − vo ) sCm
} ⇒s =z =
gm2
Cm
PM↓

gm2 g m1 g m 2 ≥ 10 g m1
RHP zero>10GBW, ≥ 10
Cm Cm Cm ≥ 0.2CL
Nulling resistor Rm added to remove or altering RHP zero
1 −1 1 gm2 1
g m 2 vo1 = vo1 ( + Rm ) s =z = − ⋅ Rm ≥
sCm ( g m 2 Rm − 1) Cm gm2
In s domain, for pole or zero, +∞ is the same as -∞, To push far and alternate
in polarity. If gm2Rm>>1, z=-1/(RmCm), so gm2≥10gm1 unnecessary
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More complicated 2 or 3 poles system
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Miller Cap. universal in Frequency compensation?


No, only effective when former pole is low than pole at back stage.

Complicated 2 poles system


- One gain Stage when parasitic pole considered
two poles: one in LF (dominate), one in HD, two poles separated,
one pole system approximation.
- two gain stage ignore parasitic poles, 2 LF poles system;
parallel or Miller Cap. Compensation should be used
- two gain stage with Voltage buffer or considering parasitic poles
2 LF pole + 1 HF pole (far way)
2 poles: 2 separated poles; 2 conjunction complex poles;
2+1 poles: 1 LF pole + 2 conjunction complex poles; 2 low + 1 High .
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General form of two Poles System
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No matter what kind of 2 poles, the generally form for scaled


transportation function is ςQ = 1/ 2
AV 0ω02 AV 0ω02 AV 0
AV (s ) = 2 = =
s + 2ζω0 s + ω02 s 2 + ω0 s + ω 2 1+ 2ς s + 1 s 2
Q
0
ω0 ω02
ω0: characteristic angle frequency; All are determined by nodes
Q: quality factor, ζ: damping factor. RC within the circuit

1 1
p1,2 = ςω0 (-1 ± 1- )= ω0 (-1 ± 1-4Q 2 )
ς 2
2Q

ς > 1, 0 ≤ Q ≤ 1/ 2 , two real poles


0 < ς < 1, Q ≥ 1/ 2, Conjunction complex poles

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Overshot & Oscillation under Q>1/2
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1
ς =Q = Special point
1 1 2
p1,2 = ςω0 (-1 ± 1- ) ςQ =
ς 2
2
ζ=1 (Q=1/2) critical point

Large DF ζ (small Q) Æ p1, p2 1- ς 2


Remain LHP ϕ = arctg ( )
Small DF ζ (large Q) Æ p1,2=a±jb. ς

Transient response under step input with ζ≤1


1
r (t ) ≈ A0 [1 - exp(-ςω0t ) sin ( 1 - ς 2 ω0t + ϕ )]
1- ς 2
Overshot & oscillation observed under ζ<1.
Vo , peak - Vo , static - πς π
OS = = exp( ) tp =
Vo , static 1- ς 2 ω0 1 - ς 2

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Relation between ζOL & ζCL (From OL to CL) SE
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For two real poles OL Amp, ζOL>1; p1<<p2 for dominant pole assumption.
For complex poles CL Amp configured by OL Amp with unit N-FB, ζCL
1 AV 0
AV_CL = ≈ AV 0_CL = AV 0 /(1+FAV 0 )
F + AV_OL
-1
1 1 s2
FAV 0 + 1 + ( + )s +
p1 p2 p1 p2 ω0_CL = (1 + FAV 0 )p1 p2
AV 0_CL
=
1 1 s s2 2ς CL 1 1 1
1+ ( + ) + = ( + )
p1 p2 (1 + FAV 0 ) (1 + FAV 0 )p1 p2 ω0_CL 1 + FAV 0 p1 p2

ω0_CL 1 1 p +p 1 p2
⇒ ς CL = ( + )= 1 2 ≈
2(1 + FAV 0 ) p1 p2 2ω0_CL 2 (1 + FAV 0 )p1

If p2>>(1+FAV0)p1 to make ζCL>1, two poles of CL-Amp remain real.


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Analysis from OL to CL
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The CL DF of ζCL , which is determined by OL p1,p2 & AV0, F,

AV 0 AV 0 >>AV 0_CL F↓ ⇒ AV0 ↓


AV 0_CL =
1+FAV 0 If FB F=0,
CL return ω0 = p1 p2 F↓ ⇒ ω0 ↓
ω0_CL = (1 + FAV 0 )p1 p2 back to OL

1 p2
⇒ ς≈
1
2
p2
p1
F↓ ⇒ ζ↑
ς CL ≈
2 (1 + FAV 0 )p1 Subscript OL are omit
If poles of OL is not separated far enough, ζOL is not larger enough, thus
easily ζCL<1 when F increased, both ζOL & ζCL decreasing more when p1,
p2 closed for each other, resulting a strong OS & OSC in a CL-Amp
constructed by a unit-FB OL-Amp without or poor compensated.
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Design from CL to OL
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PM & GBW should be obtained by open loop, from CL Æ OL


1 1 parameters
AV (s )= ≈
-1
AV_CL (s)-F A-1 + 2ς CL 1 in CL form
s+ s2
AV 0_CLω0_CL AV 0_CLω0_
V0 2
CL

F=1 CL considered, AV0_CL≈1/F=1, 1/AV0≈0, OL have real poles

ω0_CL /2ς CL 1 ω0_CL p2 = 2ς CLω0_CL


AV (s ) ≈ GBW0 ≈
s 1 2ς CL
1+ s
2ς CLω0_CL

Due to p2 activity, GBW<GBW0, by two separated real pole, PM

GBW 2ς CLω 0 _CL


PM = 180 -90 -arctg (
o o
) = arctg ( ) ≈ arctg (4ς 2 )
2ς CLω 0 _CL GBW
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Calculation under GBW=GBW0 approximation
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ω0_CL GWB 1 p2
GBW ≈ GWB0 = ⇒ = = 2ς CL
2ς CL ω0_CL 2ς CL ω0_CL
For CL Butterworth filter response by ζCL=1, QCL=1/2:

1 p2
ς CL ≈ =1 ω0_CL = (1 + FAV 0 )p1 p2
2 (1 + FAV 0 )p1

⇒ p2 ≈ 4(1 + FAV 0 )p1, ω0_CL ≈ 2(1 + FAV 0 )p1 , GBW ≈ F × AV 0 p1


PM = arctg (4ς 2 ) = arctg (4) ≈ 76o

Similarly, for CL response with ζCL=QCL=1/√2, then


p2≈2GBW0, ω0_CL≈√2GBW0, GBW0=(1+FAV0)p1≈F×AV0p1

⇒ PM = arctg (4ς 2 ) = arctg (2) ≈ 63.4o


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Accurate calculation with GBW≠GBW0
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By using more accurate approximation of OL derived from CL to


calculate GBW and PM, supposing x=(GBW/ω0_CL)2
1 1 1
AV (s ) ≈ x = 4ς 4 +1-2ς 2 ≈ 2ς 2 [1+ -1] ≈
2ς CL 1 8ς 4 4ς 2
AV-10 + s+ s2
ω0_CL ω 2
0_CL
GBW 1
= 4ς 4
+ 1-2ς 2

AV (s ) =1 x 2 + 4ς CL
2
x =1 ω0_CL CL CL
2ς CL
2ς CL (GBW /ω0_CL ) 2ς CL 2
PM = 180o -arctg[ ] ≈ arctg ( )=arctg ( )
AV-10 -(GBW /ω0_CL ) 2
GBW /ω0_CL 4+1/ς -2 4

}
GBW 2
ς CL =1 = 5-2 PM ≈ arctg ( ) ≈ 76.35o PM is slightly large
ω0_CL 5-2 due to actual GBW
1 GBW 2 is a bit small.
ς CL = ≈ 2-1 PM ≈ arctg ( ) ≈ 65.5 o
2 ω0_CL 8-2 ζ↑, difference↓
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General Expression for GBW & PM
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By CL Æ OL, either in separated pole or Q, ζ description, we have

1 1+4Q 4 -1 1+(4ς 4 )-1 -1


GBW ≈ 2 GBW0 =4ς 2 GBW0
Q 2 2
1 1+4Q 4 +1 All Q, ζ are
PM =arctg[ 2 ] GBW0 =F × AV 0 p1
Q 2 for CL

Slow (Stable) Fast (OSC)


CL (required)
1 1 1 1
Q≤ , ς≥ Q> , ς<
2 2 2 2
OL (Designed)
3
GBW ≈ GBW0 GBW ≈ (1- 2
)GBW0
16Q GBW,PM,Q,ζ
1 Q2 1 1
PM =arctg ( 2 + ) PM =arctg[ (1+ 2 )] (obtained)
Q 2 Q 4Q
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How to Deal with a Multi-stage OP
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Analysis ways Based (OLÆCL)


Multi-stage OP -> AV(s) -> Pole, zero, Gain, PM
Freq. Compensation methods used to adjust Poles/zeros,
and thus AV(s) is changed, until all requirements holds.

Design ways Based (CLÆOL, Butterworth Filter response)


Close Loop OP needed -> Open Loop OP -> AV(s)
-> Location & realize major pole, zero, Gain, PM

More complicated for 3 poles system design, No 4 gain-stage OP used.

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OP Simulation & Testing methods - Bode
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U1
OP CUT
+
Vout
OUT CL
Vin 200 uF
-
1V AC R1
DC short Loads
AC/DC AC gnd
RL
Signal & open 100 M 4 Ohm
source Istatic
VCM + C1 1000 F
Feedback by Gain
- simulation
GND
GBW
GND
PM
GND

AC Bode Figure Simulation circuit, signal and circuit connection:


-- DC: Static Biasing applied; -- AC: Open loop for gain figure
How to test total static current, GBW, SR? Voltage following property?
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OP Testing: VOS
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VOS is difficult in simulation, because all MOSFET & elements


are supposed to be same implicitly.
VOS open loop testing: difficult
- One differential input applied a suitable CM voltage and fixed;
- varying another CM voltage to the other input terminal, till
static statue established, when output stay at nearby VCC/2;
- the Vos is the difference between to input CM voltage.
VOS closed loop testing: easy
- Configure the unit FB voltage follower, V- is connected with
output of OP;
- V+ of DP OP is applied a CM voltage, measuring Vout;
- the difference between Vout & V+ is offset voltage.
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OP Testing: DC gain
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DC gain is easy in simulation, but rather difficult in testing,


because usually large gain required wide dynamic range or
accurate distinguishability.

VOS closed loop testing, similar as Vos testing


- Configure the unit FB voltage follower, V- is connected with
output of OP;
- V+ of DP OP is applied a CM voltage, measuring Vout;
- the offset voltage can be cancelled if two group date are closed.

ΔV V -V AV AV_CL
AV_CL = out = outB outA AV_CL = ⇒ AV =
ΔVin VinB - VinA 1 + AV 1 - AV_CL

VOS can not be totally removed due to it’s variation with circuit statue.
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Summary
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OP-> Structure, Parameters -> DC, AC, transient

AC properties is most important, all poles should be LHP:


All coefficient of B(s) in denominator of AV(s) can not be negative,
RHP zeros should be avoid by push away or turn back to LHP, for less
PM lost;
Multistage-OP stable principles:
Loop within GBW, only one net pole existed;
zeros used to compensate pole for satisfying one net pole demand;
all LHP poles & RHP zeros should be far away GBW, at least 2 time large;
DF ζ can not be too small, Q can not be too large; CL & OL different!
PM=60 is selected in balance speed & stability requirement.

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Break
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End of Unit 6

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