電子學(二) 第一次作業

1. An NMOS transistor operated with an overdrive voltage of 0.25 V is required to

have a gm equal to that of an npn transistor operated at IC= 0.1 mA. What must ID
be? What value of gm is realized? (Hint: npn transistor VT=0.025V)

2. A CS amplifier utilizes an NMOS transistor with L = 0.54 μm and W/L = 8. It was

fabricated in a 0.18-μm CMOS process for which μnCox= 400 μA/V2 and V’A=5
V/μm. What is the bias current of the transistor for which A0= 18 V/V?

3. Consider the CMOS amplifier of figure A when fabricated with a process for
which k’n= 4k’p= 400 μA/V2, |Vt|=0.5 V, and|VA|=5 V. Find IREF and (W/L)1 to
obtain a voltage gain of –40 V/V and an output resistance of 100 kΩ. Recall that
Q2 and Q3 are matched. If Q2 and Q3 are to be operated at the same overdrive
voltage as Q1, what must their W/L ratios be?

【figure A】

4. It is required to design the current source for figure B to deliver a current of 0.2
mA with an output resistance of 500 kΩ. The transistor has VA = 20 V and Vt = 0.5
V. Design for VOV = 0.2 V and specify Rs and VBIAS.

【figure B】

5. Figure C shows a current source realized using a current mirror with two matched
transistors Q1 and Q2. Two equal resistances Rs are inserted in the source leads to
increase the output resistance of the current source. If Q2 is operating at Gm =1
mA/V and has VA =10 V, and if the maximum allowed dc voltage drop across Rs is
0.3 V, what is the maximum available output resistance of the current source?
Assume that the voltage at the common-gate node is approximately constant.

【figure C】