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➢ Analog systems are used when wide bandwidth is required or when lower
accuracy can be allowed.
➢ Digital systems are used when the physical process being monitored slowly
varies and when high accuracy and low per-channel cost is required.
Data acquisition systems are being used in various applications such as
biomedical and aerospace. So, we can choose either analog data acquisition
systems or digital data acquisition systems based on the requirement.
Analog and Digital IO:
At the simplest level, data acquisition hardware is characterized by the
subsystems it possesses. A subsystem is a component of your data acquisition
hardware that performs a specified task.
Common subsystems include
▪ Analog input
▪ Analog output
▪ Digital input/output
▪ Counter/timer Hardware devices that consist of multiple subsystems, such
as the one depicted below, are called multifunction boards.
Analog input subsystems are also referred to as AI subsystems, A/D converters,
or ADCs.
Analog Output Subsystems - Analog output subsystems convert digital data
stored on your computer to a real-world analog signal. These subsystems perform
the inverse conversion of analog input subsystems
Digital Input/output Subsystems- Digital input/ output (DIo) subsystems are
designed to input and output digital values (logic levels) to and from hardware.
These values are typically handled either as single bits or lines or as a port, which
typically consists of eight lines.
Counters and Timers
Counter/Timer Subsystems- Counter/timer (C) subsystems are used for event
counting, frequency and period measurement, and pulse train generation.
A counter contains the following four main components:
• Count Register- Stores the current count of the counter. The user can query the
count register with software.
• Source- An input signal that can change the current count stored in the count
register. The counter looks for rising or falling edges on the source signal.
Whether a rising or falling edge changes the count is software selectable. The
type of edge selected is referred to as the active edge of the signal. When an active
edge is received on the source signal, the count changes. Whether an active edge
increments or decrements the current count is also software selectable.
• Gate- An input signal that determines if an active edge on the source will
change the count. Counting can occur when the gate is high, low, or between
various combinations of rising and falling edges. Gate settings are made in
software.
Types of ADC
Successive Approximation
➢ This means if Vin is greater than the output of the DAC, the most
significant bit wall stay as it is, and the next bit will be set for a new
comparison. Otherwise, if the input voltage is less than the DAC value, the
most significant bit wall be set to zero, and the next bit will be set to 1 or a
new comparison. This process will continue until the value closest to the
input voltage reaches.
Sigma-Delta
➢ In mathematics and physics, the capital Greek letter delta (Δ)
represents difference or change, while the capital letter sigma (Σ)
represents summation: the adding of multiple terms together. Sometimes
this converter is referred to by the same Greek letters in reverse order:
sigma-delta, or ΣΔ.
➢ In a ΔΣ converter, the analog input voltage signal is connected to the input
of an integrator, producing a voltage rate-of-change, or slope, at the output
corresponding to input magnitude. This ramping voltage is then compared
against ground potential (0 volts) by a comparator.
➢ The comparator acts as a sort of 1-bit ADC, producing 1 bit of output
(“high” or “low”) depending on whether the integrator output is positive or
negative.
➢ The comparator’s output is then latched through a D-type flip-flop clocked
at a high frequency, and fed back to another input channel on the
integrator, to drive the integrator in the direction of a 0 volt output. The
basic circuit looks like this:
Schematic diagram of sigma-delta
➢ The leftmost op-amp is the (summing) integrator. The next op-amp the
integrator feeds into is the comparator, or 1-bit ADC. Next comes the D-
type flip-flop, which latches the comparator’s output at every clock pulse,
sending either a “high” or “low” signal to the next comparator at the top of
the circuit.
➢ This final comparator is necessary to convert the single-polarity 0V / 5V
logic level output voltage of the flip-flop into a +V / -V voltage signal to
be fed back to the integrator.
➢ If the integrator output is positive, the first comparator will output a “high”
signal to the D input of the flip-flop.
➢ At the next clock pulse, this “high” signal will be output from the Q line
into the noninverting input of the last comparator.
➢ This last comparator, seeing an input voltage greater than the threshold
voltage of 1/2 +V, saturates in a positive direction, sending a full +V signal
to the other input of the integrator.
➢ This +V feedback signal tends to drive the integrator output in a negative
direction. If that output voltage ever becomes negative, the feedback loop
will send a corrective signal (-V) back around to the top input of the
integrator to drive it in a positive direction.
➢ This is the delta-sigma concept in action: the first comparator senses
a difference (Δ) between the integrator output and zero volts. The
integrator sums (Σ) the comparator’s output with the analog input signal.
➢ Functionally, this results in a serial stream of bits output by the flip-flop.
➢ If the analog input is zero volts, the integrator will have no tendency to
ramp either positive or negative, except in response to the feedback
voltage.
➢ In this scenario, the flip-flop output will continually oscillate between
“high” and “low,” as the feedback system “hunts” back and forth, trying to
maintain the integrator output at zero volts:
Output Waveforms
If, however, we apply a negative analog input voltage, the integrator will have a
tendency to ramp its output in a positive direction. Feedback can only add to the
integrator’s ramping by a fixed voltage over a fixed time, and so the bit stream
output by the flip-flop will not be quite the same:
By applying a larger (negative) analog input signal to the integrator, we force its
output to ramp more steeply in a positive direction. Thus, the feedback system
has to output more 1’s than before to bring the integrator output back to zero
volts:
As the analog input signal increases in magnitude, so does the occurrence of 1’s
in the digital output of the flip-flop:
Types of DAC
Weighted Resistor
➢ A weighted resistor DAC produces an analog output, which is almost equal
to the digital (binary) input by using binary weighted resistors in the
inverting adder circuit. In short, a binary weighted resistor DAC is called
as weighted resistor DAC.
The circuit diagram of a 3-bit binary weighted resistor DAC is shown in the
following figure −
➢ Recall that the bits of a binary number can have only one of the two values.
i.e., either 0 or 1. Let the 3-bit binary input is b2b1b0. Here, the bits b2
and b0 denote the Most Significant Bit (MSB) and Least Significant Bit
(LSB) respectively.
➢ The digital switches shown in the above figure will be connected to
ground, when the corresponding input bits are equal to ‘0’. Similarly, the
digital switches shown in the above figure will be connected to the negative
reference voltage, −VR−VR when the corresponding input bits are equal
to ‘1’.
➢ In the above circuit, the non-inverting input terminal of an op-amp is
connected to ground. That means zero volts is applied at the non-inverting
input terminal of op-amp.
➢ According to the virtual short concept, the voltage at the inverting input
terminal of opamp is same as that of the voltage present at its non-inverting
input terminal. So, the voltage at the inverting input terminal’s node will
be zero volts.
➢ The above equation represents the output voltage equation of a 3-bit binary
weighted resistor DAC. Since the number of bits are three in the binary
(digital) input, we will get seven possible values of output voltage by
varying the binary input from 000 to 111 for a fixed reference
voltage, VRVR.
➢ We can write the generalized output voltage equation of an N-bit binary
weighted resistor DAC as shown below based on the output voltage
equation of a 3-bit binary weighted resistor DAC.
➢ Recall that the bits of a binary number can have only one of the two values.
i.e., either 0 or 1.
➢ Let the 3-bit binary input is b2b1b0. Here, the bits b2 and b0 denote the
Most Significant Bit (MSB) and Least Significant Bit (LSB) respectively.
➢ The digital switches shown in the above figure will be connected to ground,
when the corresponding input bits are equal to ‘0’.
➢ Similarly, the digital switches shown in above figure will be connected to
the negative reference voltage, −VR−VR when the corresponding input
bits are equal to ‘1’.
➢ It is difficult to get the generalized output voltage equation of a R-2R
Ladder DAC. But, we can find the analog output voltage values of R-2R
Ladder DAC for individual binary input combinations easily.
➢ R-2R Ladder DAC contains only two values of resistor: R and 2R. So, it is
easy to select and design more accurate resistors.
➢ If more number of bits are present in the digital input, then we have to
include required number of R-2R sections additionally.
Due to the above advantages, R-2R Ladder DAC is preferable over binary
weighted resistor DAC.
Use of Data Sockets for Networked Communication
A socket is created by concatenating the IP Number of a system and a software
port number. This allows the process to know the address of the system the IP
address and the address where the information needs to be sent the port number.
The IP number and the port number are separated by a:
Data Sockets
The diagram above shows two different applications communicating with one
another through sockets. In this diagram, application 1 sends the data to ID
number 192.168.16.21 of application 2, port 100 while application 2 sends the
data to IP number 192.168.1.1 of application 1, port 80.