NTD5867NL

MOSFET – Power,
N-Channel
60 V, 20 A, 39 mW
Features
• Low RDS(on) http://onsemi.com
• High Current Capability
V(BR)DSS RDS(on) MAX ID MAX
• 100% Avalanche Tested
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS 60 V
39 mW @ 10 V 20 A

Compliant 50 mW @ 4.5 V 18 A

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) D

Parameter Symbol Value Unit
Drain−to−Source Voltage VDSS 60 V
N−Channel
Gate−to−Source Voltage − Continuous VGS ±20 V G
Gate−to−Source Voltage VGS ±30 V
− Non−Repetitive (tp < 10 ms) S
Continuous Drain TC = 25°C ID 20 A 4
Current (RqJC)
Steady TC = 100°C 13
State
Power Dissipation TC = 25°C PD 36 W 4
(RqJC)
Pulsed Drain Current tp = 10 ms IDM 76 A 1 2 1
2
3 3
Operating Junction and Storage Temperature TJ, Tstg −55 to °C
150 DPAK IPAK
CASE 369AA CASE 369D
Source Current (Body Diode) IS 20 A (Surface Mount) (Straight Lead)
Single Pulse Drain−to−Source Avalanche EAS 18 mJ STYLE 2 STYLE 2
Energy (VDD = 50 V, VGS = 10 V, RG = 25 W,
IL(pk) = 19 A, L = 0.1 mH, TJ = 25°C) MARKING DIAGRAMS
& PIN ASSIGNMENT
Lead Temperature for Soldering Purposes TL 260 °C
(1/8″ from case for 10 s) 4
Drain
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be 4
67NLG
AYWW

assumed, damage may occur and reliability may be affected. Drain

58

THERMAL RESISTANCE MAXIMUM RATINGS

67NLG
AYWW

Parameter Symbol Value Unit

58

Junction−to−Case (Drain) RqJC 3.5 °C/W

2
Junction−to−Ambient − Steady State (Note 1) RqJA 45
1 Drain 3 1 2 3
1. Surface−mounted on FR4 board using 1 in sq pad size Gate Source Gate Drain Source
(Cu area = 1.127 in sq [2 oz] including traces.
A = Assembly Location*
Y = Year
WW = Work Week
5867NL = Device Code
G = Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.

ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

May, 2019 − Rev. 3 NTD5867NL/D
 NTD5867NL

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Parameter Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 60 V
Drain−to−Source Breakdown Voltage V(BR)DSS/TJ 60 mV/°C
Temperature Coefficient
Zero Gate Voltage Drain Current IDSS VGS = 0 V, TJ = 25°C 1.0 mA
VDS = 60 V TJ = 125°C 100
Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±20 V ±100 nA
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250 mA 1.5 1.8 2.5 V
Negative Threshold Temperature Coefficient VGS(TH)/TJ 5.2 mV/°C
Drain−to−Source On Resistance RDS(on) VGS = 10 V, ID = 10 A 26 39 mW
VGS = 4.5 V, ID = 10 A 33 50
Forward Transconductance gFS VDS = 15 V, ID = 10 A 8.0 S
CHARGES, CAPACITANCES AND GATE RESISTANCES
Input Capacitance Ciss 675 pF
VGS = 0 V, f = 1.0 MHz,
Output Capacitance Coss 68
VDS = 25 V
Reverse Transfer Capacitance Crss 47
Total Gate Charge QG(TOT) 15 nC
Threshold Gate Charge QG(TH) VGS = 10 V, VDS = 48 V, 1.0
Gate−to−Source Charge QGS ID = 20 A 2.2
Gate−to−Drain Charge QGD 4.3
Total Gate Charge QG(TOT) VGS = 4.5 V, VDS = 48 V, 7.6 nC
ID = 20 A
Gate Resistance RG 1.3 W
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time td(on) 6.5 ns
Rise Time tr VGS = 10 V, VDD = 48 V, 12.6
Turn−Off Delay Time td(off) ID = 20 A, RG = 2.5 W 18.2
Fall Time tf 2.4
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage VSD VGS = 0 V, TJ = 25°C 0.87 1.2 V
IS = 10 A TJ = 100°C 0.78
Reverse Recovery Time tRR 17 ns
Charge Time ta VGS = 0 V, dIs/dt = 100 A/ms, 13
Discharge Time tb IS = 20 A 4.0
Reverse Recovery Charge QRR 12 nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperatures.

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 NTD5867NL

TYPICAL PERFORMANCE CURVES

40 40
10V 4.5 V TJ = 25°C VDS ≥ 10 V
35 35
4V
ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

30 30
3.8 V
25 25
3.6 V
20 20
3.4 V
15 15
TJ = 125°C
3.2 V
10 10
TJ = 25°C
3.0 V
5 5
2.8 V TJ = −55°C
0 0
0 1 2 3 4 5 2 3 4 5
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)

0.060 0.040
ID = 20 A TJ = 25°C
TJ = 25°C
0.050 0.035 VGS = 4.5 V

0.040 0.030

VGS = 10 V

0.030 0.025

0.020 0.020
3 4 5 6 7 8 9 10 5 10 15 20
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and
Voltage Gate Voltage

2.2 10000
RDS(on), DRAIN−TO−SOURCE RESISTANCE

ID = 20 A VGS = 0 V
2.0
VGS = 10 V
1.8 TJ = 150°C
IDSS, LEAKAGE (nA)

1000
1.6
(NORMALIZED)

1.4

1.2
100 TJ = 125°C
1.0

0.8

0.6 10
−50 −25 0 25 50 75 100 125 150 10 20 30 40 50 60
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current

Temperature vs. Drain Voltage

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3
 NTD5867NL

TYPICAL PERFORMANCE CURVES

1000 10

VGS , GATE−TO−SOURCE VOLTAGE (VOLTS)

VGS = 0 V QT
900
TJ = 25°C
800 8
C, CAPACITANCE (pF)

700 Ciss VGS

600 6
500
Qgs Qgd
400 4
300
200 2 VDS = 48 V
Coss
100 ID = 20 A
Crss TJ = 25°C
0 0
0 10 20 30 40 50 60 0 5 10 15
DRAIN−TO−SOURCE VOLTAGE (VOLTS) QG, TOTAL GATE CHARGE (nC)

Figure 7. Capacitance Variation Figure 8. Gate−To−Source Voltage vs.

Total Charge

1000 20
VDD = 48 V VGS = 0 V
ID = 20 A
IS, SOURCE CURRENT (AMPS)
TJ = 25°C
VGS = 10 V
15
100
tf td(off)
t, TIME (ns)

tr 10

10 td(on)
5

1 0
1 10 100 0.5 0.6 0.7 0.8 0.9 1.0
RG, GATE RESISTANCE (OHMS) VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 9. Resistive Switching Time Figure 10. Diode Forward Voltage vs. Current
Variation vs. Gate Resistance

100 20
EAS, SINGLE PULSE DRAIN−TO−SOURCE

ID = 20 A
I D, DRAIN CURRENT (AMPS)

10 ms
AVALANCHE ENERGY (mJ)

15
10 100 ms

1 ms
10
10 ms
VGS = 10 V
1 SINGLE PULSE
TC = 25°C dc
5
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1 0
1 10 100 25 50 75 100 125 150
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C)

Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy vs.
Safe Operating Area Starting Junction Temperature

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4
 NTD5867NL

TYPICAL PERFORMANCE CURVES

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

10
(NORMALIZED)

1.0
D = 0.5

0.2
P(pk)
0.1 RqJC(t) = r(t) RqJC
0.1 0.05 D CURVES APPLY FOR POWER
0.02 PULSE TRAIN SHOWN
t1 READ TIME AT t1
0.01 t2 TJ(pk) − TC = P(pk) RqJC(t)
SINGLE PULSE DUTY CYCLE, D = t1/t2
0.01
0.000001 0.00001 0.0001 0.001 0.01 0.1
t, TIME (s)

Figure 13. Thermal Response

ORDERING INFORMATION
Order Number Package Shipping†
NTD5867NL−1G IPAK (Straight Lead) 75 Units / Rail
(Pb−Free)
NTD5867NLT4G DPAK 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

IPAK
CASE 369D−01
ISSUE C
DATE 15 DEC 2010

B C NOTES:
SCALE 1:1 1. DIMENSIONING AND TOLERANCING PER
V R E ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.

INCHES MILLIMETERS
4 DIM MIN MAX MIN MAX
Z A 0.235 0.245 5.97 6.35
A B 0.250 0.265 6.35 6.73
S C 0.086 0.094 2.19 2.38
1 2 3
D 0.027 0.035 0.69 0.88
E 0.018 0.023 0.46 0.58
−T− F 0.037 0.045 0.94 1.14
SEATING G 0.090 BSC 2.29 BSC
PLANE K H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.350 0.380 8.89 9.65
R 0.180 0.215 4.45 5.45
J S 0.025 0.040 0.63 1.01
F V 0.035 0.050 0.89 1.27
H
Z 0.155 −−− 3.93 −−−
D 3 PL
G 0.13 (0.005) M T
MARKING
DIAGRAMS
STYLE 1: STYLE 2: STYLE 3: STYLE 4: Integrated
PIN 1. BASE PIN 1. GATE PIN 1. ANODE PIN 1. CATHODE
2. COLLECTOR 2. DRAIN 2. CATHODE 2. ANODE Discrete Circuits
3. EMITTER 3. SOURCE 3. ANODE 3. GATE
4. COLLECTOR 4. DRAIN 4. CATHODE 4. ANODE
YWW xxxxx
STYLE 5: STYLE 6: STYLE 7:
xxxxxxxx ALYWW
PIN 1. GATE PIN 1. MT1 PIN 1. GATE
2. ANODE 2. MT2 2. COLLECTOR x
3. CATHODE 3. GATE 3. EMITTER
4. ANODE 4. MT2 4. COLLECTOR

xxxxxxxxx = Device Code

A = Assembly Location
lL = Wafer Lot
Y = Year
WW = Work Week

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON10528D Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: IPAK (DPAK INSERTION MOUNT) PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

4 DPAK (SINGLE GUAGE)

CASE 369AA−01
ISSUE B
1 2
3 DATE 03 JUN 2010
SCALE 1:1 NOTES:
C 1. DIMENSIONING AND TOLERANCING PER ASME
A Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
E A 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
b3 B c2 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
4 5. DIMENSIONS D AND E ARE DETERMINED AT THE
L3 Z OUTERMOST EXTREMES OF THE PLASTIC BODY.
D 6. DATUMS A AND B ARE DETERMINED AT DATUM
DETAIL A H PLANE H.
1 2 3
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
L4 A 0.086 0.094 2.18 2.38
b2 A1 0.000 0.005 0.00 0.13
b c b 0.025 0.035 0.63 0.89
b2 0.030 0.045 0.76 1.14
e 0.005 (0.13) M C H b3 0.180 0.215 4.57 5.46
c 0.018 0.024 0.46 0.61
GAUGE SEATING c2 0.018 0.024 0.46 0.61
L2 PLANE C PLANE D 0.235 0.245 5.97 6.22
E 0.250 0.265 6.35 6.73
e 0.090 BSC 2.29 BSC
H 0.370 0.410 9.40 10.41
L
A1 L 0.055 0.070 1.40 1.78
L1 L1 0.108 REF 2.74 REF
L2 0.020 BSC 0.51 BSC
DETAIL A L3 0.035 0.050 0.89 1.27
ROTATED 905 CW L4 −−− 0.040 −−− 1.01
Z 0.155 −−− 3.93 −−−
STYLE 1: STYLE 2: STYLE 3: STYLE 4:
PIN 1. BASE PIN 1. GATE PIN 1. ANODE PIN 1. CATHODE
2. COLLECTOR 2. DRAIN 2. CATHODE 2. ANODE GENERIC
3. EMITTER 3. SOURCE 3. ANODE 3. GATE MARKING DIAGRAM*
4. COLLECTOR 4. DRAIN 4. CATHODE 4. ANODE

STYLE 5: STYLE 6: STYLE 7:

PIN 1. GATE PIN 1. MT1 PIN 1. GATE XXXXXXG YWW
2. ANODE 2. MT2 2. COLLECTOR
3. CATHODE 3. GATE 3. EMITTER ALYWW XXX
4. ANODE 4. MT2 4. COLLECTOR XXXXXG

SOLDERING FOOTPRINT*
IC Discrete
6.20 3.00
0.244 0.118 XXXXXX = Device Code
2.58 A = Assembly Location
0.102 L = Wafer Lot
Y = Year
5.80 WW = Work Week
1.60 6.17
0.228 G = Pb−Free Package
0.063 0.243
*This information is generic. Please refer
to device data sheet for actual part
marking.
SCALE 3:1 ǒinches
mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON13126D Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: DPAK (SINGLE GAUGE) PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

 onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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