JL-Jaladhulagori(via, Andul Mouri Rd, District, Sankrail, Howrah, West Bengal 711302

Name:-Sumangal Kayal

Roll No:-20600223055
Semester:-3rd

Department:- Information Technology(IT) Lateral

Year:-2nd year

Subject:-Analog and Digital Electronics(ESC301)

Session:-2023-24
 Analog and Digital Electronics (ESC301)
CA - 2
In digital logic, the inputs and output of a function are in the form of binary numbers (boolean
values) i.e., the values are either zero (0) or one (1). Therefore, digital logic is also known as
‘Boolean logic’. These inputs and output can be termed as ‘Boolean Variables’. The output
boolean variable of a digital signal can be expressed in terms of input boolean variables which
forms the ‘Boolean Expression’.
Representation of Boolean expression can be primarily done in two ways. They are as
follows:
1. Sum of Products (SOP) form
2. Product of Sums (POS) form

Note:
If the number of input variables are n, then the total number of combinations in Boolean
algebra is 2n.
If the input variable (let A) value is :
 Zero (0) – a is LOW -It should be represented as A’ (Complement of A)
 One (1) – a is HIGH -It should be represented as A

In boolean logic,
AND is represented as '.'
A AND B is written as 'A.B'

OR is represented as '+'
A OR B is written as 'A+B'
For example, Considering number of input variables =3, Say A, B and C.
Total number of combinations are: 2 3=8.

A B C

0 0 0

0 0 1

0 1 0
A B C

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1
Sum of Products (SOP):
It is one of the ways of writing a boolean expression. As the name suggests, it is formed by
adding (OR operation) the product terms. These product terms are also called as ‘min-terms’.
Min-terms are represented with ‘m’, they are the product(AND operation) of boolean
variables either in normal form or complemented form.
Therefore, SOP is sum of minterms and is represented as:
F in SOP = m(0, 3)
Here, F is sum of minterm0 and minterm3.
For Example:
A=0, B=0, C=0 Minterm is A'.B'.C'
A=1, B=0, C=1 Minterm is A.B'.C
Consider a function X, whose truth table is as follows:

A B C X

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1
A B C X

1 1 1 0
The function X can be written in SOP form by adding all the min-terms when X is HIGH(1).
While writing SOP, the following convention is to be followed:

If variable A is Low(0) - A'

A is High(1) - A
X (SOP) = m(1, 3, 6)
= A’.B’.C + A’.B.C + A.B.C’
Product of Sums (POS):
As the name suggests, it is formed by multiplying(AND operation) the sum terms. These sum
terms are also called as ‘max-terms’. Max-terms are represented with ‘M’, they are the sum
(OR operation) of Boolean variables either in normal form or complemented form.
Therefore, POS is product of maxterms and is represented as:
F in POS = M(1, 2) Here, F is product of maxterm1 and maxterm2.
For Example:
A=0, B=1, C=0 Maxterm is A+B'+C
A=1, B=1, C=1 Maxterm is A'+B'+C'
Consider a function X, whose truth table is as follows:

A B C X

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 0
The function X can be written in POS form by multiplying all the max-terms when X is
LOW(0).

While writing POS, the following convention is to be followed:

If variable A is Low(0) - A
A is High(1) - A'

X (POS) = M(0, 2, 4, 5, 7)

= (A+B+C).(A+B'+C).(A'+B+C).(A'+B+C').(A'+B'+C')
Difference between SOP and POS :

S.No. SOP POS

A way of representing boolean expressions A way of representing boolean

1.
as sum of product terms. expressions as product of sum terms.

SOP uses minterms. Minterm is product of POS uses maxterms. Maxterm is sum of
2. boolean variables either in normal form or boolean variables either in normal form
complemented form. or complemented form.

It is sum of minterms. Minterms are It is product of maxterms. Maxterms are

3.
represented as ‘m’ represented as ‘M’

SOP is formed by considering all the POS is formed by considering all the
4.
minterms, whose output is HIGH(1) maxterms, whose output is LOW(0)

While writing minterms for SOP, input with
value 1 is considered as the variable itself
5.
and input with value 0 is considered as
complement of the input.
While writing maxterms for POS, input
with value 1 is considered as the
complement and input with value 0 is
considered as the variable itself.

In digital electronics, a combinational circuit is a circuit in which the output depends on the
present combination of inputs. Combinational circuits are made up of logic gates. The output of
each logic gate is determined by its logic function.

What are Combinational Circuits?

A combinational circuit is a digital circuit whose output depends not only on the present input
but also on the sequence of past inputs. The output of a combinational circuit can thus be
considered as a function of all the inputs, past and present. This type of circuit is contrasted
with a sequential circuit, in which the output depends not only on the present input but also on
the state of the circuit, i.e. its previous history.

Half Adder (HA):

Half adder is the simplest of all adder circuits. Half adder is a combinational arithmetic circuit
that adds two numbers and produces a sum bit (s) and carry bit (c) both as output. The
addition of 2 bits is done using a combination circuit called a Half adder. The input variables
are augend and addend bits and output variables are sum & carry bits. A and B are the two
input bits.
let us consider two input bits A and B, then sum bit (s) is the X-OR of A and B. it is evident
from the function of a half adder that it requires one X-OR gate and one AND gate for its
construction.
Truth Table:

Implementation:

Full Adder is the adder that adds three inputs and produces two outputs. The first two inputs
are A and B and the third input is an input carry as C-IN. The output carry is designated as C-
OUT and the normal output is designated as S which is SUM. The C-OUT is also known as the
majority 1’s detector, whose output goes high when more than one input is high. A full adder
logic is designed in such a manner that can take eight inputs together to create a byte-wide
adder and cascade the carry bit from one adder to another. we use a full adder because when
a carry-in bit is available, another 1-bit adder must be used since a 1-bit half-adder does not
take a carry-in bit. A 1-bit full adder adds three operands and generates 2-bit results.
Truth table:-

Logical Expression for SUM: = A’ B’ C-IN + A’ B C-IN’ + A B’ C-IN’ + A B C-IN = C-IN (A’ B’ + A B)
+ C-IN’ (A’ B + A B’) = C-IN XOR (A XOR B) = (1,2,4,7)
Logical Expression for C-OUT: = A’ B C-IN + A B’ C-IN + A B C-IN’ + A B C-IN = A B + B C-IN + A
C-IN = (3,5,6,7)
Another form in which C-OUT can be implemented: = A B + A C-IN + B C-IN (A + A’) = A B C-IN
+ A B + A C-IN + A’ B C-IN = A B (1 +C-IN) + A C-IN + A’ B C-IN = A B + A C-IN + A’ B C-IN = A B +
A C-IN (B + B’) + A’ B C-IN = A B C-IN + A B + A B’ C-IN + A’ B C-IN = A B (C-IN + 1) + A B’ C-IN +
A’ B C-IN = A B + A B’ C-IN + A’ B C-IN = AB + C-IN (A’ B + A B’)
Therefore COUT = AB + C-IN (A EX – OR B)

Full Adder logic circuit.

A full subtractor is a combinational circuit that performs subtraction of two bits, one is
minuend and other is subtrahend, taking into account borrow of the previous adjacent lower
minuend bit. This circuit has three inputs and two outputs. The three inputs A, B and Bin,
denote the minuend, subtrahend, and previous borrow, respectively. The two outputs, D and
Bout represent the difference and output borrow, respectively. Although subtraction is
usually achieved by adding the complement of subtrahend to the minuend, it is of academic
interest to work out the Truth Table and logic realisation of a full subtractor; x is the
minuend; y is the subtrahend; z is the input borrow; D is the difference; and B denotes the
output borrow. The corresponding maps for logic functions for outputs of the full subtractor
namely difference and borrow.

Inputs:
A: minuend bit
B: subtrahend bit
Bin: borrow-in bit from the previous stage
Outputs:
Diff: difference bit
Bout: borrow-out bit for the next stage
Truth Table –

Logic Circuit for Full Subtractor –

Implementation of Full Subtractor using Half Subtractors – 2 Half Subtractors and an OR gate
is required to implement a Full Subtractor.

What is Parity Bit?

The parity generating technique is one of the most widely used error detection techniques for
the data transmission. In digital systems, when binary data is transmitted and processed, data
may be subjected to noise so that such noise can alter 0s (of data bits) to 1s and 1s to 0s.

Hence, a Parity Bit is added to the word containing data in order to make number of 1s either
even or odd. The message containing the data bits along with parity bit is transmitted from
transmitter to the receiver.

At the receiving end, the number of 1s in the message is counted and if it doesn’t match with
the transmitted one, it means there is an error in the data. Thus, the Parity Bit it is used to
detect errors, during the transmission of binary data.

Parity Generator and Checker

A Parity Generator is a combinational logic circuit that generates the parity bit in the
transmitter. On the other hand, a circuit that checks the parity in the receiver is called Parity
Checker. A combined circuit or device of parity generators and parity checkers are commonly
used in digital systems to detect the single bit errors in the transmitted data.

Even Parity and Odd Parity

The sum of the data bits and parity bits can be even or odd. In even parity, the added parity bit
will make the total number of 1s an even number, whereas in odd parity, the added parity bit
will make the total number of 1s an odd number.

The basic principle involved in the implementation of parity circuits is that sum of odd number
of 1s is always 1 and sum of even number of 1s is always 0. Such error detecting and correction
can be implemented by using Ex-OR gates (since Ex-OR gate produce zero output when there
are even number of inputs).

To produce two bits sum, one Ex-OR gate is sufficient whereas for adding three bits, two Ex-OR
gates are required as shown in below figure.

Parity Generator

It is combinational circuit that accepts an n-1 bit data and generates the additional bit that is to
be transmitted with the bit stream. This additional or extra bit is called as a Parity Bit.

In even parity bit scheme, the parity bit is ‘0’ if there are even number of 1s in the data stream
and the parity bit is ‘1’ if there are odd number of 1s in the data stream.

In odd parity bit scheme, the parity bit is ‘1’ if there are even number of 1s in the data stream
and the parity bit is ‘0’ if there are odd number of 1s in the data stream. Let us discuss both
even and odd parity generators.

Even Parity Generator

Let us assume that a 3-bit message is to be transmitted with an even parity bit. Let the three
inputs A, B and C are applied to the circuit and output bit is the parity bit P. The total number of
1s must be even, to generate the even parity bit P.

The figure below shows the truth table of even parity generator in which 1 is placed as parity
bit in order to make all 1s as even when the number of 1s in the truth table is odd.
1’s complement of a binary number is another binary number obtained by toggling all bits in
it, i.e., transforming the 0 bit to 1 and the 1 bit to 0. Examples:
Let numbers be stored using 4 bits

1's complement of 7 (0111) is 8 (1000)

1's complement of 12 (1100) is 3 (0011)
2’s complement of a binary number is 1 added to the 1’s complement of the binary number.
Examples:
Let numbers be stored using 4 bits

2's complement of 7 (0111) is 9 (1001)

2's complement of 12 (1100) is 4 (0100)
These representations are used for signed numbers.
The main difference between 1′ s complement and 2′ s complement is that 1′ s complement
has two representations of 0 (zero) — 00000000, which is positive zero (+0), and 11111111,
which is negative zero (-0); whereas in 2′ s complement, there is only one representation for
zero — 00000000 (0) because if we add 1 to 11111111 (-1), we get 100000000, which is nine
bits long. Since only eight bits are allowed, the left-most bit is discarded(or overflowed),
leaving 00000000 (-0) which is the same as positive zero. This is the reason why 2′ s
complement is generally used.
Another difference is that while adding numbers using 1′ s complement, we first do binary
addition, then add in an end-around carry value. But, 2′ s complement has only one value for
zero and doesn’t require carry values.
Range of 1’s complement for n bit number is from -2n-1-1 to 2n-1-1 whereas the range of 2’s
complement for n bit is from -2n-1 to 2n-1-1.
There are 2n-1 valid numbers in 1’s complement and 2 n valid numbers in 2’s complement.
Difference between 1’s Complement representation and 2’s Complement representation in
tabular form:
1’s
Criteria 2’s Complement
Complement

The 1’s complement of a The 2’s complement of a binary

Definition binary number is obtained by number is obtained by adding 1 to
inverting all its bits. the 1’s complement of the number.

Range of values that

From -2^(n-1) + 1 to 2^(n-1) –
can be represented From -2^(n-1) to 2^(n-1) – 1
1
with n bits

Number of
Can be represented in two Can be represented in only one way
representations for
ways (all 0s and all 1s). (all 0s).
zero

Addition of positive Same as unsigned binary

Same as unsigned binary addition.
and negative numbers addition.

Subtract the smaller number

Subtraction of Add the negative number to the
from the larger one, then add
numbers positive one using binary addition.
a sign bit to the result.