2021 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER) | 978-1-6654-1244-5/21/$31.

00 ©2021 IEEE | DOI: 10.1109/DISCOVER52564.2021.9663628

MTCMOS 8T SRAM Cell with Improved Stability

and Reduced Power Consumption
Anusha S Bommidi Shivanath Nikhil K Sai Manoj
Department of Electronics and Department of Electronics and Department of Electronics and
Communication Engineering Communication Engineering Communication Engineering
Amrita Vishwa Vidyapeetham Amrita Vishwa Vidyapeetham Amrita Vishwa Vidyapeetham
Bengaluru, India Bengaluru, India Bengaluru, India
anusha9904@gmail.com bommidinikhil123@gmail.com manojmmjx6@gmail.com

Kirti S. Pande
Department of Electronics and
Communication Engineering
Amrita Vishwa Vidyapeetham
Bengaluru, India
sp_kirti@blr.amrita.edu

Abstract—The semiconductor industry is expanding swiftly
and the demand for memory and faster access of memory is
increasing. The data stability and energy usage are the basic
requirements of cache memory in embedded processors that uses
SRAM. The SRAM cell parameters that require scrutiny at lower
supply voltages are data stability, leakage current and delay. In
order to ameliorate the stability further and lower the substrate
(junction) leakage current in comparison to the existing SRAM
cells, the MTCMOS 8T SRAM cell is introduced in this paper. The
proposed MTCMOS 8T SRAM cell uses HVT and LVT
MOSFETs that helps in reduction of the average power
consumption by subsiding the leakage current. The proposed
MTCMOS 8T SRAM cell is implemented, analysed, verified and
compared to the existing SRAM cells using Cadence Virtuoso with
a channel length of 45 nm at a power supply of 500 mV. In
proposed MTCMOS 8T SRAM cell, i) read stability RSVNM is
increased by 5.89%, 5.72% and 4.74% ii) write stability WTV is
increased by 4.16%, 4.16% and 5.05% iii) hold stability HSNM is
increased by 0.24% iv) power consumption is decreased by
58.87%, 3.164% and 66.49% in comparison to conventional 6T,
existing 8T and existing 9T SRAM cell respectively v) overall read
path leakage current is reduced by 94.83% and 87.420%, when
compared with existing 8T and existing 9T SRAM cell
respectively.
Keywords—SRAM, SNM, MTCMOS (HVT, LVT), CMOS,
Subthreshold region, Low power, Leakage current, N-curve
I. INTRODUCTION
Modern technological advancements demand for high speed,
low power memory cells to store and access the data from cache
memory. For such high expeditious applications, a well-
designed SRAM (Static Random-Access Memory) cell is
needed. SRAM is one such volatile memory used in many
electronic devices for quick access of data, similar to cache
memory. It uses cross coupled inverter circuitry to store each bit
of information. SRAM cells do not require periodic refreshing
of data unlike DRAM (Dynamic Random-Access Memory). To
achieve the present-day requirements such as high speed write
& read along with minimum power consumption & read
destruction, an SRAM cell with suitable MOS (Metal Oxide
Semiconductor) transistor sizing needs to be designed. While
scaling down of transistors enable high density, it also increases
the leakage current [1].
Maximum area on SoC (System on Chip) is occupied by
SRAM cells which influences the overall power consumption
significantly. On chip memory cells, use an array of SRAM cells
for higher performance [2]. In order to attain lower power
consumption, full scaling (both dimension and voltage
parameters scaled down) is used which in turn increases the
subthreshold current exponentially [3]. The use of a single-
ended SRAM cell minimises data charging and discharging at
the output node, resulting in lower leakage current and power
consumption. [4].
The SRAM cell’s stability is determined by the SNM (Static
Noise Margin). SRAM's SNM is the minimum amount of noise
voltage necessary to flip data stored on storage nodes. When the
MOSFET is operating in the vicinity of the threshold voltage
(where the potential difference between gate and source is
slightly lesser than the threshold voltage) a weak inversion is
formed, called the subthreshold region [5]. Decreasing the
supply voltage can affect the value at the storage nodes there
upon changing the logic values garnered in the SRAM cell while
performing the read function (the stability of data at the storage
nodes needs to be maintained) which reduces the stability.
Therefore, it is important to maintain the stability while working
with lower supply voltages. Thus, to improve the stability
various SRAM cell topologies are adopted. In the traditional 6T
SRAM cell, the pull-down transistors belonging to the latch,
must be slightly wider than the access transistors to attain better
stability [6]. However, compared to other existing SRAM cells,
this does not enhance cell stability. The access, pull-up, and pull-
down transistors can be sized appropriately to improve stability
[3]. The 6T SRAM cell's lower read stability results in read
destruction and greater power consumption. To resolve this
problem of read stability, a read destruction free 7T SRAM cell
[7] was introduced and to reduce power utilization during the
write phase, a 7T SRAM cell with a control transistor [8] was

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introduced. In order to improve the read stability and lower the
power utilization, a single ended 8T SRAM cell [9] and a 9T
SRAM cell [10] with separate read and write path are devised.
But these cells have high read path leakage current with lower
stability.
To improve the stability further with reduced leakage current
& power consumption, a MTCMOS (Multi Threshold CMOS)
8T SRAM cell suitable for subthreshold operations is proposed.
It uses low threshold voltage (LVT) and high threshold voltage
(HVT) MOSFETs. The HVT transistors help in reducing the
leakage current, while LVT transistors allow faster switching
rates [11]. The existing SRAM cells and proposed MTCMOS
8T SRAM cell are simulated, analysed and compared using
Cadence Virtuoso with a channel length of 45 nm at a power
supply of 500 mV.
The rest of the work is divided into the following sections:
The various topologies of SRAM cells are explained in Section
II. In Section III, the proposed MTCMOS 8T SRAM cell is
discussed. Section IV deals with the analysis and comparison of
the simulation outcomes. Section V concludes the work carried
out along with the further scope.
II. LITERATURE SURVEY
A. Conventional 6T SRAM Cell
Two cross-coupled inverters combine to form the
conventional 6T SRAM cell, as depicted in Fig. 1. These two
inverters serve as a latch, allowing complementary values to be
stored at Q and QB, the output nodes. The bit lines BL and BLB
are connected to the output storage nodes Q and QB by the
access transistors [12]. During write and read operations, the
word line (WL) switches ON these access transistors (M5 and
M6). While performing write operation, the bit lines BL and
BLB are charged to complementary voltages, depending on the
data to be cached in the cell. The output nodes are charged
based on the voltage present on BL and BLB. During the
retention phase, the access transistors are OFF which enables
the SRAM cell to hold the data.
Read destruction is the fundamental drawback observed in
the conventional 6T SRAM cell. While performing the read
operation, BL and BLB are supplied with a high voltage. The
node which is at logic ‘0’ allows the discharge of the
corresponding bit line, in turn charging this storage node. This
activates the pull-down transistor of the other inverter pair
causing a change in the value on the other storage node [13].
Fig. 1. Conventional 6T SRAM Cell
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B. Existing 8T SRAM Cell
The existing 8T SRAM cell [9] is made up of latched
circuitry with M5 and M6 as the access transistors which are
responsible for writing & reading the data into & from the cell
as depicted in Fig. 2. While writing data into the cell, WWL is
held high to turn ON the access transistors. Hence, creating a
path to write the data present on the bit lines into the cell.
Throughout the hold operation, WWL is kept low to conserve
the data at the output nodes. While reading the data from the cell,
the transistors M5 & M6 are deactivated and RBL, RWL are
furnished with a high voltage. While reading logic ‘1’ from node
Q, the transistor M8 is turned OFF and hence RBL preserves its
value. While reading logic ‘0’ from node Q, transistor M8 is
activated and allows the discharge of RBL. Although, only a
single bit line (RBL) is used for reading, there is reduction in
read destruction and power consumption, yet this deteriorates
the stability of the cell. Since a single bit line is used, it indicates
that the differential input required to be generated, making the
sense amplifier a complex circuit.
Fig. 2. Existing 8T SRAM Cell [9]
C. Existing 9T SRAM Cell
The existing 9T SRAM cell [10] is illustrated schematically
in Fig. 3. The read access transistors M7, M8 and M9 provide
a separate read path that assists in improving the SRAM cell’s
read stability [10]. The write access transistors M5 and M6 are
activated only during the write operation, allowing the value on
WBL and WBLB to be recorded at node Q and QB respectively.
The read access and write access transistors are switched OFF
during the hold operation in order to retain the previously
written value. During the read operation, transistor M7 is ON
and the high value on RBL or RBLB is discharged through M8
or M9 respectively, based on the value stored at node QB and
Q. It can be perceived that there may be an increase in the
substrate current through transistor M9 (standard threshold
voltage transistor) during logic ‘1’ and hence contributing
towards the leakage power. Section IV outlines the
corresponding analysis.
Fig. 3. Existing 9T SRAM Cell [10]
 III. PROPOSED MTCMOS 8T SRAM CELL
For improving the stability further and to curtail the substrate
(junction) leakage current, the MTCMOS (Multi Threshold
CMOS) 8T SRAM cell is proposed as delineated in Fig. 4. It is
a requisite to have M6 and M8 transistors with HVT to curtail
the substrate (junction) leakage current. Therefore, the proposed
MTCMOS 8T SRAM cell uses HVT MOSFETs (M6 and M8)
and LVT MOSFETs (M1-M5& M7). This design of SRAM cell
is implemented using Cadence Virtuoso with a channel length
of 45 nm at a power supply of 500 mV.
The use of discrete write and read path in proposed
MTCMOS 8T SRAM cell obviates read destruction and
ameliorates the stability as compared to the conventional 6T
SRAM cell. The use of two-bit lines provides the differential
input required for the sense amplifier circuitry, and there by
reducing the complexity of the sense amplifier in contrast to the
existing 8T SRAM cell [9] (requires extra hardware to generate
the differential input since single bit line is used). When
compared to the existing 9T SRAM cell [10], the HVT
transistors in the read path help to reduce substrate leakage
current during read operation, lowering the overall power
utilization.

Transistor Sizing: The SRAM cell’s stability can be

ameliorated by transistor sizing. The cell ratio (CR) is the
proportion of pull-down transistors to access transistors in a
circuit. The CR must be larger than 2 for improved read stability
[14]. The ratio of the pull-up transistor to the access transistor
is known as the pull-up ratio (PR). For improved write stability,
the PR has to be lower than 1.8 [14]. Hence, in the proposed
Fig. 4. Proposed MTCMOS 8T SRAM Cell
MTCMOS 8T SRAM cell the width of the pull-down transistor
(M1) is 360 nm and for M2-M8 the width is maintained at 120
TABLE I. VOLTAGE LEVELS OF INPUT SIGNALS DURING WRITE, HOLD nm, making the cell ratio to be 3 and pull-up ratio to be 1.
AND READ OPERATION FOR PROPOSED MTCMOS 8T SRAM
CELL IV. SIMULATION RESULTS
Stored Operation WWL WBL/RBLB RBL RWL The existing 8T and 9T SRAM cell experiences lower
Data stability and higher leakage current. The MTCMOS (Multi
Write VDD VDD GND GND Threshold CMOS) 8T SRAM cell is proposed and analysed in
Logic Hold GND VDD VDD GND Section III so as to ameliorate the stability further in contrast to
‘1’ the existing SRAM cells and to reduce the substrate (junction)
Read GND VDD VDD VDD
leakage current found in existing 8T and 9T SRAM cells. The
Write VDD GND GND GND design of traditional 6T, existing 8T and existing 9T SRAM cells
Logic Hold GND VDD VDD GND and the proposed MTCMOS 8T SRAM cell are simulated using
‘0’ Cadence Virtuoso. All the simulations are carried out using the
Read GND VDD VDD VDD
45 nm technology at a source voltage of 500 mV. All transistors
used in the conventional 6T, existing 8T and 9T SRAM cells are
During the write operation, the write access transistor M5 is simulated with a width of 120 nm and thus maintaining the CR
enabled by applying a high voltage to WWL and low voltage to and PR at 1. For the proposed MTCMOS 8T SRAM cell, the
RBL & RWL bit lines. WBL is supplied with either logic ‘1’ or pull-down transistor M1 and transistors M2-M8 have a width of
logic ‘0’ based on the logic value to be recorded in the SRAM 360 nm and 120 nm respectively making the CR to be 3 and PR
cell (i.e., at node Q and QB). Since M7 is OFF, RBL and RBLB to be 1.
do not find a discharge path through M8 or M6. During the hold A. Functionality of Proposed MTCMOS 8T SRAM Cell
operation, the access transistor M5 is turned OFF due to logic The proposed MTCMOS 8T SRAM cell is devised with the
‘0’ forced onto WWL and hence retaining the data at the output use of HVT MOSFETs (M6 & M8) and LVT MOSFETs (M1-
nodes Q & QB with the help of latched circuitry. M5 & M7). The functionality of this SRAM cell is as mentioned
in the above Section III. The transient response for logic ‘1’ and
During the read operation, WWL is forced with logic ‘0’ logic ‘0’ are illustrated in Fig. 5 and Fig. 6.
and RWL, RBL & RBLB are forced with logic ‘1’. Since M7
is ON, while reading a logic ‘0’ at Q, transistors M8 and M7 The proposed MTCMOS 8T SRAM cell's transient analysis
is performed on a 60 ns time period. Table II lists the voltage
provides a discharge path for RBL. Similarly, while reading a
levels acquired at nodes Q and QB throughout write, hold, and
logic ‘1’ at Q, transistors M6 and M7 provides a discharge path
read operations. While reading logic ‘0’ at QB & Q a slight
for RBLB. Therefore, irrespective of the value stored at the deviation of 912.416 nV and 839.241 nV is found. These
output nodes, the discharge of RBL or RBLB does not affect voltages are significantly lower when compared to standard 6T
the stored value in the cell, and hence abating the read SRAM cell, thus overcoming read destruction.
destruction. A succinct of required voltage levels for the
working of the proposed MTCMOS 8T SRAM cell during the
write, hold and read operation are tabulated in Table I.

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TABLE II. VOLTAGE VALUES OBTAINED AT NODES Q AND QB DURING
THE TRANSIENT ANALYSIS OF PROPOSED MTCMOS 8T
SRAM CELL

Data Operation
Node
Stored Write (mV) Hold (mV) Read (mV)
Q 500.002 499.998 499.997
Logic ‘1’
QB 0.006230 0.000837 0.000912
Q 0.000236 0.000804 0.0008392
Logic ‘0’
QB 499.999 500 499.998
Fig. 7. N-Curve for Proposed MTCMOS 8T SRAM Cell

The difference in voltage betwixt the first and second points

that intersect at the zero-current line is used to calculate the
Read SVNM. The difference in voltage betwixt the second and
third points, which cuts at the zero-current line, is used to
calculate write trip voltage (WTV). A comparison of RSVNM
and WTV attained from the N-Curve plots of the conventional
6T, existing 8T, existing 9T and proposed MTCMOS SRAM
Cells are illustrated in Fig. 8.

Fig. 5. Working Principle of Proposed MTCMOS 8T SRAM Cell for Logic

‘1’

Fig. 8. Read and Write Static Noise Margin Comparison

When comparing the proposed MTCMOS 8T SRAM cell

Fig. 6. Working Principle of Proposed MTCMOS 8T SRAM Cell for Logic
‘0’
B. Static Noise Margin Measurements for Read and Write
Operation
The SNM (Static Noise Margin) is used to assess the
stability of an SRAM cell. The minimal amount of noise
voltage necessary to flip the data stored on the storage nodes is
known as the SNM of SRAM. Adjusting the CR and PR of an
SRAM cell can improve its read and write stability respectively
[15].
N-curve is a plot of the voltage supply Vin enforced at the
storage node Q versus the equivalent current Iin flowing
through the source [16]. The N-curve method is used to
determine the static voltage noise margin (SVNM) of read and
write for the SRAM cell. Fig. 7 shows the N-curve plot of the
proposed MTCMOS 8T SRAM cell.
with the traditional 6T, existing 8T and existing 9T SRAM cells
it can be inferred that the, i) RSVNM is improved by 5.89%,
5.72% and 4.74%, ii) WTV is improved by 4.16%, 4.16% and
5.05% respectively.
C. Static Noise Margin Measurements for Hold Operation
The hold SNM is calculated by setting the SRAM cell in
hold mode and connecting two DC sources in series with the
inverters [17]. A butterfly curve is plotted and the maximum
size of the square that fits into the curve is taken as the HSNM.
The butterfly curve plot of proposed MTCMOS 8T SRAM cell
is delineated in Fig. 9. A comparison of HSNM obtained from
the butterfly curve for the conventioanl 6T, existing 8T,
existing 9T and proposed MTCMOS 8T SRAM cells are
delineated in Fig. 10.
The HSNM of the traditional 6T, existing 8T and existing
9T SRAM cells are measured to be 409 mV whereas that of the
proposed MTCMOS 8T SRAM cell is 410 mV as delinated in
Table III. The proposed MTCMOS 8T SRAM cell has an
HSNM of 0.24% higher than existing SRAM cells.

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 existing 8T, existing 9T and proposed MTCMOS 8T SRAM
cells are 1366.3 fA, 381.1775 fA and 0.00991 fA respectively.
This leakage current in the proposed design is decreased by
99.99% when compared to existing 8T and 9T SRAM cell
respectively.

Junction leakage current is the current flow between PN

Fig. 9. Butterfly Curve for HSNM of Proposed MTCMOS 8T SRAM Cell
junction (towards the substrate terminal) when the transistor is
in OFF state. The junction leakage current for the existing 8T,
existing 9T and proposed MTCMOS 8T SRAM cells are
7.587 fA, 23.0786 fA and 2.92741 fA respectively. This
junction leakage current for the proposed MTCMOS 8T SRAM
cell is decreased by 61.419%, 66.113% in comparison with the
existing 8T and existing 9T SRAM cell respectively.

The gate leakage current is the current flow from gate to

source, drain and body during the transistor’s OFF state. The
gate leakage current for the existing 8T, existing 9T and
proposed MTCMOS 8T SRAM cells are 157.059 fA, 224.8755
fA and 76.2015 fA respectively. When compared to existing
8T and 9T SRAM cells, the proposed MTCMOS 8T SRAM cell
Fig. 10. Hold Static Noise Margin Comparison
has shown a reduction in gate leakage current by 51.482% and
87.315%, respectively.
D. Average Power Consumption
The total power consumed by the SRAM cell is computed All these leakage currents are also tabulated in Table III. It
by taking the average power obtained while performing write, can be perceived that the use of HVT MOSFETs in the read
hold and read operations for logic ‘0’ and logic ‘1’. The power path have reduced leakage current for the proposed MTCMOS
analysis is carried out for 60 ns. The average power 8T SRAM cell.
consumption for conventional 6T, existing 8T, existing 9T and
proposed MTCMOS 8T SRAM cells are 47.87 pW, 20.2715 TABLE III. OVERALL COMPARISON OF EXISTING AND PROPOSED SRAM
CELLS
pW, 58.585 pW and 19.63 pW respectively as depicted in Table
III. From Fig. 11, it is inferred that the overall power consumed Parameter Conventional Existing Existing Proposed
6T SRAM Cell 8T 9T MTCMOS
by the proposed 8T MTCMOS SRAM cell is lowered by
SRAM SRAM 8T SRAM
58.70%, 3.164% and 66.49% when compared to conventional Cell [9] Cell [10] Cell
6T, existing 8T and existing 9T SRAM cells. The inclusion of
Area *(fm²) 32.4 43.2 48.6 54
HVT and LVT transistors in the proposed circuit results in a
RSVNM (mV) 209.658 210 212.034 222.0195
reduction in power consumption.
WTV (mV) 240 240 237.966 250
HSNM (mV) 409 409 409 410
Average Power 47.87 20.2715 58.585 19.63
Consumption
(pW)
Subthreshold 1366.3 381.1775 0.009912
Leakage
Current (fA)
Gate Leakage 7.5877 23.0786 2.92741
Current (fA) (No separate
read path)

Fig. 11. Average Power Consumption Comparison Junction 157.059 224.8755 76.2015
Leakage
Current (fA)

E. Read Path Leakage Current

The read path leakage (i.e., the subthreshold, junction and *Area is calculated by sum of product of width and length corresponding to
gate leakage) currents are measured across the HVT transistors each transistor.
M6 and M8. The current flow between drain and source of the
MOSFET in the subthreshold region (i.e., gate to source voltage
goes below the threshold voltage) is called subthreshold
leakage current [18]. The subthreshold leakage current for the

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 V. CONCLUSION AND FURTHER SCOPE
The parameters of SRAM cell that require scrutiny at lower
supply voltages are data stability, leakage current and delay. It
is surveyed from the literature that the conventional 6T SRAM
cell exhibits higher read destruction while other existing single
ended 8T and 9T SRAM cell show higher leakage current with
reduced data stability. The MTCMOS 8T SRAM cell is
proposed so as to ameliorate the stability further when compared
with the existing SRAM cells and to reduce the substrate
(junction) leakage current found in existing 8T and 9T SRAM
cells. The proposed MTCMOS 8T SRAM cell uses HVT
MOSFETs (M6 and M8) and LVT MOSFETs (M1-M5 & M7).
The use of HVT transistors help in subsiding the leakage current
and average power consumption. The conventional 6T, existing
8T, existing 9T and proposed MTCMOS 8T SRAM cells are
implemented, analysed, verified and compared at 45 nm
technology using Cadence Virtuoso with source voltage of 500
mV. In proposed MTCMOS 8T SRAM cell, i) read margin
RSVNM is increased by 5.89%, 5.72% and 4.74% ii) write
margin WTV is increased by 4.16%, 4.16% and 5.05% iii) hold
margin HSNM is increased by 0.24% iv) power consumption is
decreased by 58.87%, 3.164% and 66.49% when compared to
conventional 6T SRAM cell, existing 8T and existing 9T SRAM
cell respectively, v) overall read path leakage current is reduced
by 94.83% and 87.420%, when compared to existing 8T and
existing 9T SRAM cell respectively. Low power cache
memories and digital signal processors can be designed using
the proposed MTCMOS 8T SRAM cell. As a further work, the
body bias technique can be used and a cell array can be analysed.
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