Boolean Algebra

Digital Electronics (Boolean Algebra)
Boolean Algebra and Logic Gates
Objectives
Upon completion of this chapter you will be able to:
 Simplify Logic Expressions using Boolean Theorems.

 Represent Logic Expressions in SOP and POS Forms.
 Implement Logic Expressions using basic Logic Gates.
 Implementing Dual and Complement of Logic Expressions.
 Form the Logic Expressions from Switching Circuits and Venn Diagrams.
Introduction
In the digital age, the cost of digital circuits used to implement the logic becomes a crucial
factor. Hence finding simpler, cheaper but equivalent realization of logic can result in huge
benefits in reducing overall cost of the design.
Advantages of minimization
 Number of logic gates required to implement the logic is reduced so it leads to a

simpler and cheaper logic.
 Speed of circuit increases due to the fact that signal now traverses through a lot less
logic gates so the propagation delay encountered is less.
 Power dissipation is also reduced due to lesser number of logic gates.
 Fan in (no. of input) is reduced due to simpler logic.
Logic Reduction Techniques
There are some standard Logic reduction Techniques and each one is used under different
circumstances which are mentioned below:
Boolean Algebra
 When no. of variable are less (1,2,3)

 It is preferred when output is 0 or 1.
K – map
 When no. of variables are 2,3,4,5 (up-to 5 variable)

 Output is 0, 1 or x (don’t care)
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Tabulation method
 It is used when no. of variables are more.
Boolean Algebra
Boolean Constants and Variables are allowed to have only two possible values 0 and 1. The
Boolean 0 and 1 do not represent actual numbers but rather the state of a voltage variable
or what is called as its Logic Level. Boolean Algebra is a means of expressing a relationship
between inputs and output of a logic circuit.
Logic 0 Logic 1
False True
Off On
Low High
No Yes
Open Switch Closed Switch
Various Significance of Logic 0 and 1
Truth Table
A Truth Table is a means to show how the output logic of the circuit depends on the input
logic level for various combinations of the inputs.
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
The figure above shows a logic circuit with two inputs A and B and one output Y. The truth
table shown on the right depicts the logic level of the output for each possible combination
of the input. This is the most basic way of representing the functionality of a logic circuit.
Boolean Algebra Operations
 NOT ( A or A' )
0 1 AA
1 0

 AND (.)
0.0 = 0 A.A = A
0.1 = 0 A.1 = A
1.0 = 0 A.0 = 0
1.1 = 1 A.A  0
 OR (+)
0+0=0 A+A=A
0+1=1 A+1=1
1+0=1 A+0=A
1+1=1 AA 1
Solved Examples
Problem: Simplify AB  AB
Solution: A B  B  = A  B B 1
Problem: find the min. no. of NAND Gate required to implement this function:
AB  ABC  ABC a) 0 b) 1 c) 2
d) 3

Solution: AB  ABC  ABC  AB  AB C  C   
C  C 1
 AB  AB  A B  B = A
No NAND gate required

Boolean Algebra Theorems

1. Transposition theorem:  A  B A  C  A  BC
Similarly:  x  y  x  z   x  yz
2. Distribution theorem: A  BC   A  B A  C
A  AB  A  B
ABC  A  B  C
3. Demorgan’s theorem:
A B  C  A . B . C
4. Consensus Theorem: AB  AC  BC  AB  AC
Shortcut method:-
a) Three variable
b) Each variable comes twice.
c) One variable is complemented.
Solved Examples
Simplify the following logic expressions:
a) AB  ABC  ABCD
Solution: ABC  AB 1  CD  1    1
 ABC  AB  A B  BC   B  BC  B  C 
 
 A B  C = AB  AC
b) (A + B) (A + C)
Solution: A.A + A.C + AB + BC = A + A(C + B) + BC
=A(1 + B + C) + BC = A + BC
c)  A  B  C  A  B  C  A  B  C
Solution: take A + B = X
   
  X  C  A  B  C X  C  X  CC  A  B  C  (By Distribution Theorem)
 X  A  B  C    A  B   A  B  C   A  B B  C  A  BB  BC = A + BC

d)  A  B  A  B  A  B A  B 
Solution:  A  B  A  B   A  B  A  B    A  BB  A  BB    A   A  = 0 (Distribution
Theorem)
e) A  AB
Solution:  A  A   A  B   1  A  B  A  B (Distribution Theorem)
f) A  AB
Solution:  A  A  A  B   1  A  B   A  B (Distribution Theorem)
g) AB  AB  AB
Solution: A B  B   AB = A  AB   A  A  A  B   A  B (Distribution Theorem)
h) AB  AB  AB
Solution: B  A  A   AB  B  AB = B  A  B  B  = A  B (Distribution Theorem)
i) ABC  ABC  ABC
Solution: ABC  ABC  ABC  ABC  A  A  A
 
 AB C  C   A  A BC  AB  BC  B  A  C
j) AB  AC  BC   redundant term
Solution: AB  AC  BC  A  A   AB  AC  BCA  ABC  AB 1  C   AC 1  B   AB  AC
k) AB  BC  AC
Solution: BC  AC (The term which is complemented is taken)
l) AB  BC  AC
Solution: AB  BC
m)  A  B  A  C B  C
Solution:  A  B  A  C ( B  C  is redundant term)
n)  A  B  B  C   A  C
Solution:  A  B B  C (Consensus Theorem)

o) AB  AC  BC
Solution: In this case all the variables are complemented only one is un-complemented
then.
 AB  AC (the term which is un-complemented is taken)
p) AB  BC  AC
Solution: BC  AC (Consensus Theorem)
q)  A  B  B  C   A  C 

Solution: B  C A  C   (Consensus Theorem)
r) Let f  A,B  A  B then the value of f f  x  y, y  , z  is

Solution: f f  x  y  , y , z   f  x  y  y , z   f  x.y  y, z   x.y  y  z  x y.y  z
 
 
 x  y y  z  xy  yy  z  xy  z
Minterms, Maxterms & Properties
Minterm: It is a standard product term i.e. a product term which contains all variables of a
given function either in normal form or compliment form. The variables are so arranged that
the product should be 1.
Maxterm: It is standard sum term i.e. a sum term which contains all the variables of the
function either in normal or compliment form. The variables are so arranged that the sum
should be 0.
F (A, B, C) = min terms F  A,B,C   max terms

ABC=m  0,0,0  A+B+C=M (1,1,1)
0 7
ABC=m  0,0,1 A+B+C=M (1,1,0)
1 6
ABC=m 1,1,1 A+B+C=M (0,0,0)
7 0
Properties

1) n – variable function  2n minterms & 2n max terms 
2) M  m & m  M
j j j j

3) m  M ; M m ; D = indicates dual
iD  2n  1  i  iD  2n  1  i 
   
   
2n  1 2n  1
 mi  1  M 0
j
4) i0 ; j0
Forms of Boolean function
1) Sum of product (SOP) form = DNF (Distinjunctive Normal Form)

2) Canonical SOP form = DCF (Disjunctive Canonical Form)
3) Product of sum (POS) form = CNF (Conjunctive Normal Form)
4) Canonical POS form = CCF (Conjunctive Canonical Form)
SOP (Sum of Product Form)

It consists of two or more AND terms ORed together. The AND terms contain Boolean
variables in normal or complemented form.
Solved Examples
Problem: For the given truth table, minimum SOP expression.
A B Y
0 0 1
0 1 0
1 0 1
1 1 0
Solution: In SOP form only 1 taken.

 AB  AB  B  A  A   B
Y can written as:- Y (A, B) =  m  0, 2 
Problem: Simplified the expression for Y  A, B  m0, 2,3
Solution: logical expression in SOP form:-
 
Y  AB  AB  AB  B A  A  AB  B  AB  B  A B  B     AB  AB
In canonical form, each term must have all variable.

Y  AB  AB  AB is canonical form whereas Y  A  B is minimal form

Problem: In canonical SOP form, no. of min term presenting the logical expression: A  BC
is___.
       
Solution: A  BC  A B  B C  C  BC A  A  AB  AB C  C  ABC  ABC
 ABC  ABC  ABC  ABC  ABC  ABC  ABC  ABC  ABC  ABC  ABC
i.e. 5 terms.
POS form (Product of Sum)
It consists of two or more OR terms ANDed together. The OR terms contain Boolean
variables in normal or complemented form.
Solved Examples
Problem: For a given truth table minimize POS expression.
A B Y
0 0 1
0 1 0
1 0 1
1 1 0
Solution: We take only that value at which o/p is ‘0’
Y   A  B  A  B   B  AA  B
 Y can be written in POS form as: Y  A,B  M1,3  B
And for SOP:- Y  A,B  m0,2  B
i.e. m0,2  M1,3

 If F  A,B,C  m0,1, 4,7
There are 3 variable then 8 combination then max term are 2,3,5,6
F  A,B,C  m0,1, 4,7  M2,3,5,6 
n
Note: With n variable maximum possible logical expression are 22
2
Ex. for n = 2, logical expression  22  16

Logic Gates
Logic Gates are the most fundamental digital circuits that can be constructed from diodes,
transistors and resistors connected in such a way that the circuit output is the result of a
basic logic operation performed on the inputs. It is a device which accepts two or more
inputs and produces a single output. The function of each logic gate can be represented by a
Boolean expression.
Logic Gates can be broadly classified as shown below:

Logic Gates
Basic Gates Universal Gates

Others
(NOT, AND, OR) (NAND, NOR) (EXOR,
EXNOR)
NOT Gate
Figure shown below shows the symbol for a NOT Gate which is more commonly referred to
as Inverter. This circuit always has a single input and the output logic level is opposite to the
input.
A Y
0 1
1 0
Solved Examples
Problem: Circuit shown in the figure represents
a) Buffer
b) Astable MV
c) Bistable MV
d) Square wave generator.

Solution: If there is no feedback then it is buffer, in buffer if we apply 0 then get 0.
Input =“ 1 ” then output= “ 1 ”.
Buffer means whatever the input i.e. the output
 But there is a feedback and the output is stable if we give 1 as input, output is also 1 and
if gives 0 then output is 0 then two stable state. Hence it is bi-stable multi-vibrator.
Problem: Circuit shown is
Solution: t = propagation delay.

pd
This waveform has:
‘0’ for = 3t
pd
1 for = 3t
pd
It is called
i) Square wave generator.

ii) As o/p is not stable sometime 1 and sometime 0 Hence it is also called astable
multivibrator.
iii) Clock generator.
iv) Ring oscillator.
Total time period  T   6T
pd
Then, T  2Nt , where N = no. of inverters in feedback.
pd

Problem: In a circuit shown in figure the proportion delay of each not gate is 100p sec. then
frequency of generator square wave.
a) 10 GHz
b) 1 GHz
c) 100 MHz
d) 10 MHz
Solution: T  2Nt
pd  2  5 100psec  1000psec
1 1
f   109 Hz = 1GHz
T 1000  10 12 sec
Problem: The circuit shown in the fig. the proportion delay of each NOT gate is 2nsec. Then
time period of generated square wave is.
a) 6 ns
b) 14 ns
c) 12 ns
d) 18 ns
Solution: Astable multivibrator, square wave generator.
T  2Nt  2  3  2nsec  12nsec

pd
Thus time period at x and y is same.

AND Gate
The output of AND Gate is AND product of the inputs. In other words, the output of an AND
Gate is high only if all the logic inputs are high and otherwise the output is low.
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
 AND gate follow both commutative law and associative law.

 Commutative Law:- AB = BA
 Associative Law:- ABC   AB .C  A. BC
Disable & Enable
 Thus o/p remains in ‘0’ due to control input disable. AND gate is not in working state.
 AND gate is in working state output is changing in enabled state.

 In TTL logic family, if any input is open, and float then it will act as ‘1’.
 In ECL logic family, floating input will act as logic ‘0’.
Unused Inputs
1.
 In multi pin (input) AND gate unused input can be connected to logic 1 or “pull up”.
 Unused Input can be connected to logic ‘0’ or “pull Down”.
2.
 Unused Input can be connected to one of the used I/P.
3.
 If it is TTL logic family, then unused Input can be open or floated. (unconnected)
Note:
 Because of unnecessary Input attached to B, fan in will be down. (Fan-in is the

maximum number of Inputs that a digital logic Gate can accept).

 Best way to connecting unused pin (I/P) in AND gate is connecting to logic ‘1’.
OR Gate (Inclusive OR)
OR Gate has two or more inputs and the output is equal to OR combination of the inputs. It
operates in such a way that output is High when either or both inputs are high and else
output is Low.
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
 OR gate follows both commutative and associative law.

i) Commutative law:- A + B = B + A
ii) Associative law:- A  B  C   A  B   C  A  B  C 
Enable and Disable:
 Output is changing as input is changing or we say the gate is enabled.

 Output is fixed or not changing, the gate is said to be disable.
Unused I/P’s:
1. In OR gate, unused I/P is connected to logic. ‘0’ “pull down”

2. Connect to be one of the used I/P.
3. If it is ECI then unused I/P can be open or floated.
 In OR gate, Best way of connecting the unused I/P is to connect to logic ‘0’.
Solved Examples
Problem: In the circuit shown in fig. in TTL, AND, OR, INVERTER circuit for the given input,
output is
a) 0
b) 1
c) AB
d) AB
Solution: In TTL, all inputs are float then it is logic ‘1’. Hence option (a) is correct
Problem: For ECL AND, OR, INVERTER circuit for the given input, output is
a) 0
b) 1
c) AB
d) AB
Solution: If all inputs are floating in ECL then it is ‘0’ and output Y  AB

NAND Gate
It behaves like an AND Gate followed by an Inverter. The output of this gate is Low if both
inputs are high and otherwise High.
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
Enable and Disable:
 NAND gate follow commutative law but not follow associative law.
 There are only two gate that do not follow associative law i.e. universal gate NAND or
NOR gate:
 Unused input in NAND gate can be connected similar to unused input in AND gate.

NOR Gate (Bubbled AND)
It behaves like an OR gate followed by an Inverter. The output of this logic Gate is High when
both the inputs are low and otherwise Low.
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
Enable and Disable:
 NOR gate follows commutative law but not follow associative law.
i.e. A  B  B  A and A  B  C  A  B .C
 Unused I/P in NOR gate can be connected similar to OR gate (i.e. connected to logic low)
EXOR or XOR
 Exclusive OR gate. The output of this logic Gate is High when number of 1’s at the input is
Odd and Low when number of 1’s at the input is even.
 For two input XOR Gate, this condition translates to output being Low when both inputs
are equal and High when both inputs are different.
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

 SOP expression = AB  AB
 POS expression =  A  B   A  B
 It is also called as controlled inverter.
Note:
AA 0
AA 1
A0  A
A 1  A
 If A  B  C then
AC B
BC  A
A B  C  0
B , if n is odd
 B  B  B  .............n  
0 , if n is even
Solved Examples
Problem: The circuit shown in fig. contains cascading of 20 EXOR gate. If x is the Input then
output is
a) 0
b) 1
c) x
d) x
Solution: output of even EXOR gate is same as input, So Y = X

 Internal diagram of EXOR gate
 EXOR gate follow both commutative and associated law.

 EXOR gate is available with two inputs only.
Truth Table of 3 input XOR Gate:-
A B C Y   A  B  C
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
 The o/p of EXOR gate is 1. When no. of 1’s at the input is odd.
EXNOR or XNOR
 Exclusive NOR gate. The output of this logic Gate is High when number of 1’s at the input
is Even and Low when number of 1’s at the input is odd.
 For two input XNOR Gate, this condition translates to output being High when both
inputs are equal and Low when both inputs are different.
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

 SOP expression = AB  AB
 POS expression =  A  B  A  B
 Therefore it is called coincidence logic circuit and also called as equivalent detector.
Enable and Disable
Note:
AA 1
AA  0
A 0  A
A 1  A
 1 , if n  even
 B  B  B .................n 
 0 , If n  odd
 EXOR and EXNOR is not always complement, it is complement only when the number of
inputs is even and if number of inputs is odd then EXOR and EXNOR are same.
i.e. A  B  C  A B  C  same
and A  B  C  D  A  B  C  D  complement
Solved Examples
Problem: Find expression of A B  C
 
Solution: A B  C   AB  AB  C  AB  AB C   AB  AB  C
Since,  AB  AB   A  B   A  B  AB  AB
  AB  AB  C   AB  AB C  ABC  ABC  ABC  ABC

Problem: Minimize
A B C Y
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
Solution: For EXOR = o/p is 1 when odd number of 1’s at input
In this case, y  A  B  C = A B  C
 EXOR and EXNOR are never always complemented, it is complement only when even
variable occurs.
 EXNOR gate is even number of 1’s detector when number of inputs are even.
 EXNOR gate is odd number of 1’s detector when number of inputs are odd.
Solved Examples
Problem: Prove A  B  A  B
Solution: Put x  A, y  B
x  y  XY  XY  AB  AB  A  B
Problem: Simplify A  B  AB
  
Solution:  AB  AB  AB   AB  AB  AB  AB  AB AB  AB  A  B   AB A  B   AB.AB AB 
 AB  AB   A  B  A  B  AB  AB  AB  AB  A B  B  AB  A  AB
  A  A  A  B  A  B

Problem: Find Y
Solution:
Symbols
NAND as Universal Gate
i) NOT
1 gate required

ii) AND
2 gates required
iii) OR
3 gates required
iv) EXOR
4 gates required
v) EXNOR
5 gates required
vi) NOR
4 gates required

NOR as Universal Gate
i) NOT
1 gate required
ii) AND
3 gates required
iii) OR
2 gates required
iv) EXNOR
4 gates required
v) EXOR
5 gates required

vi) NAND
4 gates required
Summary of Universal Gates
Logic Number of NAND Gate Number of NOR Gate

Required Required
NOT 1 1
AND 2 3
OR 3 2
XOR 4 5
XNOR 5 4
Solved Examples
Problem: To implement xyz the minimum number of two input NAND gate required.
Solution:
Total no. of NAND gate = 2 + 2 + 1 = 5
Problem: To implement XY+WZ, the minimum number of 2 input NAND gate required.
Solution:

1st inverter cancelled 2nd and 3rd cancelled 4th
Now the total no. of NAND gate is= 2 + Bubbled OR (= NAND) = 2 + 1 = 3
3 NAND gate required.
Note:
 AND  OR  NAND  NAND

 To implement SOP form, only NAND gate are required.
 To implement POS form, only NOR gate are required.
Solved Examples
Problem: If (A + B)(C + D) then minimum number of NOR Gate required are?

Solution:
Three NOR Gates are required.
 OR – AND = NOR - NOR

Dual Form
+ve logic -ve logic

+ve logic means higher -ve logic means higher
voltage corresponds to voltage corresponds to
logic ‘1‘. logic ‘0’.
logic '0'  0v logic ‘0’ = + 5v
logic '1'  5v logic ‘1’ = 0v
Solved Examples
Problem: logic 0  5v and logic 1  0v . Find the logic ?
Solution: Higher value of voltage (0v) for logic 1. Then +ve logic.
Problem: ECL ; logic 0  1.7v and Logic 1  0.8v

Solution: -0.8v is larger value than -1.7v then it is +ve logic.
Positive and Negative Logic Gates
+ve logic AND -ve logic AND
A B Y A B Y
0 0 0 1 1 1
0 1 0 1 0 1
1 0 0 0 1 1
1 1 1 0 0 0
+ve logic OR -ve logic OR
A B Y A B Y
0 0 0 1 1 1
0 1 1 1 0 0
1 0 1 0 1 0
1 1 1 0 0 0
 For –ve logic OR gate, convert 1 to 0 and 0 to 1.

 We can say that +ve logic AND gate is equal to –ve. Logic OR gate and –ve logic AND
gate is equal to +ve logic OR gate.
 Dual expression is used to convert +ve logic into –ve Logic or –ve logic to +ve logic.

 Dual is nothing but –ve logic

AB Dual A  B
 ve logic
 AND   OR
Dual
 ve logic
 OR   AND
Dual
AND  OR 

.   
 Dual
1  0 
Keep var iable as it is 
Solved Examples
Problem: Find Dual ABC  ABC  ABC
  
Solution: Dual:- A  B  C A  B  C A  B  C 
If we find again dual then, ABC  ABC  ABC
Important Points
 For any logical expression, it two times dual is used it results in same expression.
 Self Dual:
AB + BC + AC
Dual: = (A + B)(B + C)(A + C)= (B + AC)(A + C)= BA + BC + AC + AC
= AB + BC + AC (Again same expression)
 In some of the logical expression not all its dual gives the same expression.
 In self Dual expression, it one time dual is used to result in same expression.
n1
 If there are n variables then total no. of self dual expression is 22
n
i) For n = 1.  22  2 . Then 2 dual expression.
A  self dual  A 
 Total self dual expression are 2
A  self dual  A 
1
ii) For n = 2,  22  4 Then 4 dual expression.
A  A , B B and A  A , B  B

Complement
If Y  ABC  ABC  ABC
  
Complement is Y  A  B  C A  B  C A  B  C 
AND  OR 

.   
 complement
1  0 
Complement of each var iable. 
Venn Diagram
For two variable (A, B)
Solved Examples
Problem: For a given venn diagram, minimize the SOP expression for shaded region.
Solution: Y  AB  AB  AB  B  A  A   AB  B  AB = B  A B  B  A  B

Problem: SOP expression for shaded region.
Solution: Y  AB  AB  AB  A B  B   AB   A  A   A  B  A  B
Problem: SOP expression
Solution: AB  AB  AB  AB  B  A  A   B  A  A   B  B = 1
 For 3 variable:-
SOP form for shaded portion.
 ABC  ABC  ABC  ABC  ABC  ABC  extra added
 
 BC  A  A   AB C  C  AC B  B  = AB + BC + CA

Switching Circuit
For series:-
Truth table:-
A Y
0 0
1 1
For parallel:-
Truth table:-
A Y
0 1
1 0
 In place of bulb it there is resistor then answer remains the same but some drop.
Truth table:
A Y
0 1
1 0
 In place of switch if there is a transistor
Truth table:
A Y
0 1
1 0
 For A = 1 transistor become short circuit.

For two switch A and B:
AND
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
NAND
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
OR
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
NOR
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

Solved Examples
Problem:
Solution: Y  A. B  C  . D   AB  AC  D  ABD  ACD
Problem: A logic circuit have 3 input A, B, C and o/p is Y. o/p Y is -1. For the following
combination.
i) B and C are true = BC.
ii) A and C are false = AC
iii) A, B and C are true = ABC
iv) A, B and C are false = ABC
Then minimize the o/p for Y.
Solution: o/p Y = 1. (take min term = SOP form)
Y  BC  AC  ABC  ABC  BC 1  A   AC 1  B   BC  AC
If o/p Y = 0, then take max term (POS form)
Problem: A logic circuit have 3 input A, B, C and o/p is F = 1. When majority no. of I/p’s are
logic 1. Minimize expression F.
Solution:
A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1 F  ABC  ABC  ABC  ABC  ABC  ABC  ABC  ABC  ABC  ABC
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
 
 BC  A  A   AC B  B   AB C  C  AB  BC  CA

Boolean Algebra

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Boolean Algebra

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Digital Electronics (Boolean Algebra)

Boolean Algebra and Logic Gates

Upon completion of this chapter you will be able to:

 Simplify Logic Expressions using Boolean Theorems.

 Number of logic gates required to implement the logic is reduced so it leads to a

Logic Reduction Techniques

 When no. of variable are less (1,2,3)

 When no. of variables are 2,3,4,5 (up-to 5 variable)

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 It is used when no. of variables are more.

Various Significance of Logic 0 and 1

Boolean Algebra Operations

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No NAND gate required

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Boolean Algebra Theorems

Solution: ABC  AB 1  CD  1    1

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i) ABC  ABC  ABC

Solution: ABC  ABC  ABC  ABC  A  A  A

j) AB  AC  BC   redundant term

Solution: AB  AC  BC  A  A   AB  AC  BCA  ABC  AB 1  C   AC 1  B   AB  AC

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r) Let f  A,B  A  B then the value of f f  x  y, y  , z  is

Minterms, Maxterms & Properties

F (A, B, C) = min terms F  A,B,C   max terms

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Forms of Boolean function

1) Sum of product (SOP) form = DNF (Distinjunctive Normal Form)

SOP (Sum of Product Form)

Solution: In SOP form only 1 taken.

Y can written as:- Y (A, B) =  m  0, 2 

Problem: Simplified the expression for Y  A, B  m0, 2,3

Solution: logical expression in SOP form:-

In canonical form, each term must have all variable.

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POS form (Product of Sum)

Solution: We take only that value at which o/p is ‘0’

 Y can be written in POS form as: Y  A,B  M1,3  B

And for SOP:- Y  A,B  m0,2  B

i.e. m0,2  M1,3

F  A,B,C  m0,1, 4,7  M2,3,5,6 

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Logic Gates can be broadly classified as shown below:

Basic Gates Universal Gates

Problem: Circuit shown in the figure represents

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Solution: If there is no feedback then it is buffer, in buffer if we apply 0 then get 0.

Input =“ 1 ” then output= “ 1 ”.

Buffer means whatever the input i.e. the output

Problem: Circuit shown is

Solution: t = propagation delay.

This waveform has:

i) Square wave generator.

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Solution: Astable multivibrator, square wave generator.

T  2Nt  2  3  2nsec  12nsec

Thus time period at x and y is same.

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 AND gate follow both commutative law and associative law.

 Associative Law:- ABC   AB .C  A. BC

Disable & Enable

 AND gate is in working state output is changing in enabled state.

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