Lab 05: - LATCHES AND FLIP-FLOPS

ITI 1100A- Digital Systems

Winter 2023
School of Electrical Engineering and Computer Science
University of Ottawa

Course Coordinator: Dr. Fadi Malek

Teaching Assistants: Varun
Emmanuel
Negin

Group 14

Student Name and number: Hung

Hoang, 300325340
Student Name and number Felipe
Garcia, 300290722

Experiment Date: 11th Feburary, 2023

Submission Date: 30th March, 2023
Objectives
● Provide insight into the characteristics of several important latches and flip-flops.
● Build latches and flip-flops from basic gates.
● Explain concepts of latching and edge-triggering.
● Test latches and flip-flops to understand their operation.
Equipment & Components
● Quartus II 13.0 Service-Pack 1
● Altera DE2-115 circuit board
Circuit Diagrams
Part I – SR Latch
NAND SR Latch

Figure 1: Screen-shot of a NAND SR Latch (diagram)

Part II – D Latch
NAND D – latch

Figure 2: Screen-shot of NAND D - latch diagram

Part III – D Flip-Flop
D Flip-Flop

Figure 3: Screen-shot of a D Flip-Flop (As Figure 5.5.4 lab manual)

Part IV – T Flip-Flop
T flip-flop using D flip-flop

Figure 4: Screen-shot of a T flip-flop using D flip-flop diagram

Experimental Data and Data Processing
Part I – SR Latch

SR Latch

Figure 5 : Simulation output waveform of a SR Latch

Table 1 : Experimental data observed from Altera DE2-115 card

Part II – D Latch

D Latch

Figure 6 : Simulation output waveform of a D Latch

Table 2 : Experimental data observed from Altera DE2-115 card

Part III – D Flip-Flop

D Flip-Flop

Figure 7 : Simulation output waveform of a D Flip-Flop

Table 3 : Experimental data observed from Altera DE2-115 card

Part IV – T Flip-Flop

T Flip-Flop

Figure 8 : Simulation output waveform of a T Flip-Flop

Table 4 : Experimental data observed from Altera DE2-115 card

Comparison of Theoretical Data and Experimental Data
Part I – SR Latch
Table 5 : Comparison of Theoretical and Experimental results for SR Latch

The results observed experimentally for one chip circuit from Altera DE2-115 card were
identical to results obtained theoretically as expected.
Output image

Part II – D Latch

Table 6 : Comparison of Theoretical and Experimental results for D Latch

The results observed experimentally for one chip circuit from Altera DE2-115 card were
identical to results obtained theoretically as expected.
Output image

Part III – D Flip-Flop

Table 7 : Comparison of Theoretical and Experimental results for D Flip-Flop

The results observed experimentally for one chip circuit from Altera DE2-115 card were
identical to results obtained theoretically as expected.
Output image
Part IV – T Flip-Flop
Table 8 : Comparison of Theoretical and Experimental results for T Flip-Flop

The results observed experimentally for one chip circuit from Altera DE2-115 card were
identical to results obtained theoretically as expected.
Discussion & Conclusions
● Before the lab we did truth tables to predict what the outcome of the experiment would
be. Through the lab after we created simulations, we verified our tables with the simulations.
With data that matched our tables we put the logic into the circuit board which gave us the
same results. Proving our predictions.
● The procedure went through without any trouble for the first three part of this lab. For
the final part, the simulation output gave nothing output for the whole procedure so we thought
there maybe an error. After consult with the TA, we conduct testing on the Altera board and we
receive the expected output.
● The objective of explain, build and test latches and flip flop has been met.
Appendix (Pre-Lab)