5 UEE1412 LDIC Labmanual-Compressed

ANALOG AND DIGITAL ELECTRONIC
CIRCUITS LABORATORY (UEE1412)
Lab Manual
Prepared by
Dr. R. Ramaprabha
Dr. J. Anitha Roseline
Dr. S. Krishnaveni
DEPARTMENT OF ELECTRICAL & ELECTRONICS

ENGINEERING
SSN COLLEGE OF ENGINEERING
Jan 2021 – APRIL 2021

2
NAME OF THE STUDENT: __________________________________________
REGISTER NO.: _____________________________________________________
SEMESTER: _____________________ SECTION: ____________
CONTENTS
EXPT. DATE OF FACULTY

TITLE OF THE EXPERIMENT MARKS
NO. EXPT. INITIAL
10
11
12
13
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UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

3
List of experiments
1. a. Study of Basic Digital ICs
b. Implementation of Boolean Functions, Adder and Subtractor circuits.
2. Code converters: Excess‐3 to BCD and Binary to Gray code converter and
vice‐versa.
3. Parity generator and parity checking.
4. Encoders and Decoders.
5. Multiplexer and de‐multiplexer
6. Counters: Design and implementation of 4‐bit modulo counters as
synchronous and Asynchronous types using FF IC’s and specific counter
IC.
7. Shift Registers: Design and implementation of 4‐bit shift registers in SISO,
SIPO, PISO, PIPO modes using suitable IC’s.
8. Static Characteristics of Semiconductor devices: PN diode and BJT in CE
configuration
(Add 3 numbers of Linear graph sheets after this experiment)
9. Design and Frequency response characteristics of a Common Emitter
amplifier
(Add 1number of semilog graph sheets after this experiment)
10. Basic Op‐amp applications using IC 741: inverting and non‐inverting
amplifier, voltage follower
11. Adder, Subtractor and comparator circuits using Op‐amp
12. Integrator and Differentiator circuits using Op‐amp
13. Timer NE/SE 555 applications: Astable, Monostable Operations.
14. Waveform generators using Op‐amp: Sine, Triangular & Square – Using
PSpice Simulation Software
(Install PSpice software in Laptop)


4
EXPT NO:
DATE:
Study of Basic Digital ICs

AIM:
To verify the truth table of logic gates & flip‐flops using digital ICs.
APPARATUS REQUIRED:
S.
Apparatus Range Type Quantity
No
IC 7404 (NOT), IC 7432 (OR),
1 1 each
IC 7402 (NOR)
IC 7408 (AND),
2 1 each
IC 7400 (NAND), IC 7486 (EX‐OR)
3 Digital IC trainer Board 1
4 Connecting wires
THEORY:
A. Gates:
1. NOT Gate
It is called so because its output is not the same as its input. It is also called an
Inverter, as it inverts the input signal. It has one input & one output. If A is an
input, then the output is A’.
2. OR Gate
The OR gate has an output of 1 when either A or B or both are 1.In other words, it
is an any‐or‐all gate because an output occurs when any or all inputs are present.
If A and B are inputs, then the output is Y = A+B.
3. NOR Gate
This is NOT‐OR gate. It can be made out of an OR gate by connecting an inverter
at its output. A NOR gate will have an output of 1 only when all its inputs are 0. If
any one of the input is 1, then output is 0. If A & B are inputs, then output Y =
(A+B)’
4. AND Gate
The AND gate has output 1 if both A & B are 1. Hence this is an all‐or‐nothing
gate. The output Y= A . B.
5. NAND Gate
This is NOT‐AND gate. It can be made out of an AND gate by connecting an
inverter at its output. A NAND gate will have an output of 1 when all its inputs
are 0. If any one of the input is 1, then output is 1. If A & B are inputs, then output
Y = (A.B)’


5
6. EX‐OR Gate
It has an output of 1 if the inputs are different. The output is 0, if its inputs are
same. It is also called Inequality Comparator. The output Y= A’ B + A B’
7. Universal Gates
The Universal gates are NAND and NOR gates because the logic gates like NOT,
OR and AND can be realized using these gates.
B. Flip‐flops:
Flip Flop is a bi‐stable multi vibrator circuit that has two stable states. The FF can
be used as memory device since it can maintain a binary state indefinitely (as
long as power is delivered to the circuit) until directly by an input signal to
switch states. The different types of Flip Flops are RS FF, Clocked RS FF, D FF, JK
FF and T FF.
PROCEDURE:
A. Gates:
 In a digital IC trainer board, Fix the IC s firmly.

 Apply +5 V to the 14th pin of IC s 7404, 7432, 7402, 7408, 7400 & 7486
and connect ground to the 7th pin of IC s.
 Apply inputs to the circuit & verify the outputs with truth table.
 To realize a particular gate using Universal gates, Connect the IC s as
shown in logic diagram and verify the truth table for that particular gate,
Repeat the same for other gates.
B. Flip‐flops:
 Fix the IC s firmly in a digital IC trainer.

 Give the supply and ground connections to the IC.
 Apply the clock inputs and verify the output for all the input
combinations.
TTL Gate Pin Details

6

Logic Diagram & Function Table of Different Types of Gates

7
Flip‐Flops:
1. JK Flip‐Flop:

2. D Flip‐Flop:
RESULT:

8
EXPT NO:
DATE:
Implementation of Boolean Functions, Adder and Subtractor

Circuits
AIM:
i. To simplify the given Boolean function using Karnaugh map and

implement the reduced expression using logic gates.
ii. To design and implement the binary adder and subtractor circuits using
logic gates.
APPARATUS REQUIRED:
S. No Apparatus Range Type Quantity

IC 7432 (OR), IC 7408 (AND),
1
IC 7486 (EX‐OR),IC7404(NOT)
2 Digital IC trainer Board
3 Connecting wires
Boolean Function Reduction
THEORY:
Canonical Forms (Normal Forms): Any Boolean function can be written in

disjunctive normal form (sum of min‐terms) or conjunctive normal form
(product of max‐terms). A Boolean function can be represented by a Karnaugh
map in which each cell corresponds to a minterm. The cells are arranged in such
a way that any two immediately adjacent cells correspond to two minterms of
distance 1. There is more than one way to construct a map with this property.
Realization of Boolean Expression

After simplifying


9
LOGIC DIAGRAM:
Using Basic Gates

Using Only NAND Gates

Using Only NOR Gates

10
Truth Table
Adder & Subtractor
ADDER
1. Half Adder
Half adder adds two binary bits and generates 2 outputs namely sum and carry.
Logic Diagram
2. Full Adder
It has three inputs and two outputs. It can add 3 bits at a time. The bits A and B
which are to be added come from two registers and third input comes from the
carry which is generated by the previous addition. It produces two outputs: Sum
& Carry.


11
Logic Diagram
Co

Truth Table
INPUT OUTPUT
Sum Carry
A B C S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
SUBTRACTOR
1. Half Subtractor
Two inputs minuend and subtrahend are given to get two outputs difference and
borrow.
Logic Diagram

12
2. Full Subtractor
It performs a subtraction between two bits, taking into account that a 1 may have
been borrowed by a LSB. Three inputs minuend, subtrahend and previous
borrow are given to get two outputs difference and borrow.
Logic Diagram

Truth Table
INPUT OUTPUT
Difference Borrow
A B Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
PROCEDURE:
 In a digital IC trainer board, fix the IC s firmly and connect the circuit as
given in the logic diagram.
 Apply +5 V to the 14th pin of ICs 7432, 7408 & 7486 and connect ground
to the 7th pin of ICs.
 Verify the truth table for all input combinations.
RESULT:

13
EXPT NO:
DATE:
Design of Code Converters

AIM:
To design and implement combinational logic circuits that converts

1. BCD Code to Excess ‐3 code
2. 4 Bit Binary Code to Gray Code.
APPARATUS REQUIRED:
S. No. Apparatus Required Range Type Quantity

2 IC 7404,
3 IC 7408
4 IC7432
5 IC7486
6 Connecting Wires.
THEORY:
The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different digital systems. It is
sometimes necessary to use the output of one system as the input to another. A
code convertor must be inserted between the two systems as each uses a
different binary code. To convert a binary code A to binary code B, the input lines
must supply the bit combination of elements as specified by code A and the
output lines must generate the corresponding bit combination of code B. A
combinational circuit performs this transformation by means of logic gates.
General Design Procedure:
1. Derive the truth table for the code converter including don’t care conditions.
2. Minimize the logic functions using Karnaugh maps.
3. Implement the code converters using the logic gates.

BCD code to Excess‐3 Code Converter

1. List the bit combinations (truth table) for the BCD input code and Excess‐3
output codes. Since each code uses four bits to represent a decimal digit,
there must be four input variables and four output variables. Let us designate
the four input binary variables by the symbols A, B, C and D, and the four
output variables by w, x, y and z.
2. Four bit binary variables may have 16 bit combinations, only 10 of which are
listed in the truth table. The six bit combinations not listed for the input
variables are don’t care combinations. Since they will never occur, we have
the liberty to assign the output variables either a 1 or 0, whichever gives a
simpler circuit.
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3. The maps are drawn to obtain a simplified Boolean function for each output.
Each of the four maps represents one of the four outputs of this circuit as a
function of the four input variables. The 1’s marked inside the squares are
obtained from the min‐terms that make the output equal to 1.The 1’s are
obtained from the truth table by going over the output columns one at a time.
4. The Boolean expressions obtained may be manipulated algebraically for the
purpose of using common gates for two or more outputs. This manipulation,
shown below, illustrates the flexibility obtained with multiple‐output systems
when implemented with three or more levels of gates.
z =D’
y =CD +C’D’ = CD+(C+D)’
x =B’C+B’D+BC’D’ = B’(C+D) +BC’D’=B’(C+D) +B(C+D)’
w =A+BC+BD =A+B(C+D)
5. The logic diagram that implements the above expression is shown in figure.
Truth table

Karnaugh maps

15

Logic Diagram

Binary to Gray Code Converter

Truth table

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Karnaugh’s Maps

Logic Diagram
PROCEDURE:
 In a digital IC trainer board, fix the IC s firmly and connect as given in the
logic diagram.
 Give the supply and ground connections to all the ICs.
 Verify the truth table for all the input combinations.
RESULT:

17
EXPT NO:
DATE:
Parity Generator and Parity Checking

AIM:
To design and implement 3‐bit even/odd parity generator and checker circuits.
APPARATUS REQUIRED:

1 Digital IC trainer Board ‐ ‐ 1
2 IC 7486 ‐ ‐ 1
6 Connecting Wires.
THEORY:
A parity bit is an extra bit included with a binary message to make the number of
1’s either even or odd. The message, including the parity bit, is transmitted and
then checked at the receiving end for errors. The circuit that generates the parity
bit in the transmitter is called a parity generator; the circuit that checks the
parity in the receiver is called a parity checker.
An even parity bit generator generates an output of 0 if the number of 1’s
in the input sequence is even and 1 if the number of 1’s in the input sequence is
odd. An odd parity bit generator generates an output of 0 if the number of 1’s in
the input sequence is odd and 1 if the number of 1’s in the input sequence is
even. The checker circuit gives an output of 0 if there is no error in the parity bit
generated. Thus it basically checks to see if the parity bit generator is error free
or not.
3‐Bit Even Parity Generator
DESIGN:
Truth Table
Parity bit
Three bit message
generated
X Y Z P
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1


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Karnaugh Map Reduction

From this the minimal output equation is
P  X Y Z  X Y Z  XYZ  X Y Z  X  Y  Z
Logic Diagram
3‐Bit Even Parity Checker
Truth Table
Parity
Four bits received error
check
X Y Z P C
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

The minimal output equation is C  X  Y  Z  P

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Logic Diagram

Now the parity bit generator and the checker circuit can be combined into one
circuit for simplicity.
PROCEDURE:
logic diagram.
 Give supply voltage to IC and connect the ground pins.
RESULT:

20
EXPT NO:
DATE:
Encoders and Decoders

AIM:
i. To design and implement a 4‐to2 line encoder circuit using logic gates.
ii. To design and implement a 2‐to4 line decoder circuit using logic gates.

APPARATUS REQUIRED:

2
3
4
5
THEORY:
An Encoder is a combinational logic circuit that converts an active input signal

(i.e. decimal) into a binary coded output signal. An encoder has 2n (or less) input
lines and ‘n’ output lines. The output lines generate the binary code for the 2n
input variables. Discrete quantities of information are represented in digital
system with binary codes. A binary code of ‘n’ bits is capable of representing up
to 2n distinct elements of the coded information.
A decoder is a combinational circuit that converts binary information
form ‘n’ input lines to a maximum of 2n distinct elements of coded information. If
the n‐bit decoded information has unused or don’t combinations, the decoder
output will have less than 2n outputs. The name decoder is also used in
conjunction with some code converters such as a BCD to seven‐segment decoder.
4‐to‐2 Line Encoder
DESIGN:
Truth Table
Inputs Outputs
D3 D2 D1 D0 A1 A0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1


21
Logic Diagram
2‐to‐4 Line Decoder
DESIGN:
Truth Table
Inputs Outputs
A1 A0 D3 D2 D1 D0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

Logic Diagram
PROCEDURE:
logic diagram.
 Give supply voltage to IC and connect the ground.
RESULT:

22
EXPT NO:
DATE:

Multiplexer & Demultiplexer

AIM:
To design and verify the truth table of 4×1 Multiplexer, 8×1 Multiplexer, 1×4
Demultiplexer and 1×8 Demultiplexer.
APPARATUS REQUIRED:

1 Digital IC trainer Board ‐ ‐ 1
2
3
4
THEORY:
A digital multiplexer is a combinational circuit that selects binary information

from one of many input lines and directs it to a single output line. The selection
of particular input line is controlled by a set of selection lines. Normally, there
are 2n input lines and n selection lines whose bit combinations determines which
input is selected. A multiplexer is called as data selector, since it selects one of
many inputs and steers the binary information to the output line.
A demultiplexer is a circuit that receives information on a single line and
transmits this information on one of 2n possible output lines. The selection of
specific output line is controlled by the bit values of n selection lines. The
decoder and demultiplexer operations are obtained from the same circuit; a
decoder with an enable input is referred to as a decoder / de‐multiplexer.
4 × 1 Multiplexer
Block Diagram

23
Truth Table
SELECTION INPUT OUTPUT

S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
PIN Diagram of IC 7411:

Logic Diagram

24
1 × 4 DEMULTIPLEXER
Block Diagram

Truth Table
Selection Input Output

S1 S0 Y0 Y1 Y2 Y3
0 0 D 0 0 0
0 1 0 D 0 0
1 0 0 0 D 0
1 1 0 0 0 D
Logic Diagram

25
Working of IC74151‐ 8 × 1 Multiplexer
It is an 8 × 1 multiplexer with eight data inputs (D0‐D7), three select input lines
(S2‐S0) and a single output (Y). It also has an enable input Ğ and provides both
normal and inverted outputs (i.e. Y & Ў) and Since 23=8, three bits are required
to select any one of the eight data bits. When Ē=0, the select inputs S2, S1, S0 will
select one of the data input to pass through the output Y. When Ğ =1, the
multiplexer is disabled. The enable input can be used to expand two or more
multiplexer ICs to a digital multiplexer with a large number of inputs. The logic
symbol of IC 74151 is shown in Fig. (a) And its logic diagram is shown in Fig (e).
Logic Function Generation Using Multiplexer
Multiplexers can be used to implement logic functions directly from a truth table
without the need for simplification when a multiplexer is used for this purpose,
the select inputs are used as the logic variables, and each data inputs is
connected permanently HIGH or LOW as necessary to satisfy the truth table.
The figure shown below illustrates how an 8 input multiplexer can be
used to implement the given three variable logic functions,
.The input variables A, B, C are connected to select inputs S0, S1,
S2 respectively, so that the levels on these inputs determine which data input
appears at output Z. According to the truth table, Z is supposed to be low when
CBA=000. Thus, multiplexer input D0 should be connected LOW; likewise D2,
D4, D6 and D7 should be low. The other sets of CBA conditions must produce
Z=1, and so multiplexer input’s D1,D3, and D5 are connected permanently HIGH.
This method of implementation is often more efficient than using separate logic
gates.
Diagram for 8‐input Multiplexer
Implementation of Four Variable Logic Function
The circuit of figure shows how an 8‐input MUX can be used to generate
a 4 variable logic function. Even though the MUX has only three select inputs,
three of the logic variables A, B and C are connected to select data inputs. The
fourth variable ‘D’ and its inverse ‘D’ are connected to be selected. Data inputs of
the MUX as required by desired logic function, the other MUX data inputs are
connected to a low or a high as required by the function.

26
+5 V
E
D0
D1
2
D2
D3
D4
D5
D6
D7
D C B A
LOGIC INPUT VARIABLES Fig (h)
8×1 MULTIPLEXER ‐IC 74151
(4)
D3 1 16 Vcc D0 (3)
D2 2 15 D4 D1 (2)
D2 Y
IC 74151
D1 3 14 D5 (1) 9
D3 (15)
D0 4 13 D6 D4 (14) W
D5 9
Y 5 12 D7 (13)
D6 (12)
W 6 11 A
D7
G 7 10 B
9 10 11 12
GND 8 9 C
G A B C
Fig (a) PIN Diagram Fig (b) Logic Symbol

Logic Diagram: IC 74151:‐ 8 × 1 Multiplexer

27

Truth Table for the Multiplexer

Working of IC 74138‐ 1× 8 Demultiplexer:
The 1to 8 demultiplexer has a single input (D), eight outputs (Ỹ0 toỸ7) and three
select inputs (A2, A1 and A0). Figure (f) shows how 74138 IC can be used as a
Demultiplexer.The enable inputĒ1 is used as the data input ‘D’ While the other
two enable inputs are held in their active states .The A2, A1,A0 Inputs are used as
select code. To illustrate the operation, let’s assume that the select inputs are
‘000’. With this input code, the only output that can be activated is Ỹ0, while all
other outputs are HIGH, Ỹ0 will go LOW only if Ē1 goes LOW and will be HIGH if
Ē1 goes HIGH .In other words , Ỹ0 will follow the signal on Ē1 (i.e. the data
input) while all other outputs stay HIGH .In a similar manner, a different select
code applied to A2,A1,A0 will cause the corresponding output to follow the data
inputs ‘D’.
1 × 8 Demultiplexer –IC 74138
Fig (c) PIN Diagram Fig (d) Logic Symbol

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Logic Diagram: 1 To 8 Demultiplexer IC:‐74138
Truth Table for the DeMultiplexer

Inputs Outputs
Ê1
E3 Ê2 Ā2 Ā1 Ā0 Ỹ0 Ỹ1 Ỹ2 Ỹ3 Ỹ4 Ỹ5 Ỹ6 Ỹ7
Data I/P
X X H X X X H H H H H H H H
L X X X X X H H H H H H H H
X H X X X X H H H H H H H H
H L D L L L D H H H H H H H
H L D L L H H D H H H H H H
H L D L H L H H D H H H H H
H L D L H H H H H D H H H H
H L D H L L H H H H D H H H
H L D H L H H H H H H D H H
H L D H H L H H H H H H D H
H L D H H H H H H H H H H D
PROCEDURE:
logic diagram.
 Give supply voltage to IC and connect the ground.
RESULT:

29
EXPT NO:
DATE:
Counters
AIM:
i. To design and implement 4‐bit asynchronous binary up, down and modulo‐
10 (decade) counter using JK flip‐flop.
ii. To design and implement 4‐bit synchronous modulo‐10 (decade) counter
using JK flip‐flop.
APPARATUS REQUIRED:

2
3
4
THEORY:
A counter is a digital circuit which has a clock input and a number of count
outputs which give the number of clock cycles. The output may change either on
rising or falling clock edges. The circuit may also have a reset input which sets all
outputs to zero when asserted. The counter may be either a synchronous counter
or a ripple counter.
In asynchronous or ripple counters, each flip‐flop is triggered by the
output of the previous flip‐flop. The first flip flop must change state before it can
trigger the second FF, and the second FF has to change state before it can trigger
the third FF and so on. But in synchronous counters, all flip‐flops change states
simultaneously since all clock inputs are driven by the same clock and the
settling time is equal to the delay time of a single flip‐flop. Therefore the speed of
operation can be increased.
IC 7476 Dual Edge Triggered ‘JK’ Flip‐Flop

30
Four‐Bit Asynchronous Binary Up‐Counter
Logic Diagram

Truth Table

Timing Diagram

31
Four‐Bit Asynchronous Binary Down Counter
Logic Diagram

Truth Table
Four‐Bit Asynchronous Modulo‐10 Counter
Logic Diagram

32
Truth Table
Four‐Bit Synchronous Modulo‐10 Counter
DESIGN
State Diagram

Excitation Table

33
Karnaugh Map

Logic Diagram

34
Truth Table

Timing Diagram
PROCEDURE:
1. Give the circuit connections as per the logic diagram.

2. Give the input signal (clear & preset inputs) and the clock pulse.
3. Observe the output and verify it with the truth table.
RESULT:

35
EXPT NO:
DATE:
Shift Registers
AIM:
To design and implement 4‐bit SISO, SIPO, PISO and PIPO shift registers using
flip‐flops.
APPARATUS REQUIRED:
S. No. Apparatus Range Type Quantity

1 IC 7474 (D’FF) 2
2 Digital IC trainer Board 1
3 Connecting wires
THEORY:
A register is a group of flip‐flops that can be used to store a binary number.

There must be one flip‐flop for each bit in the binary number. An ‘n’ bit register
has a group of ‘n’ FFs and is capable of storing any binary information containing
‘n’ bits. A group of flip‐flops connected in such way that a binary number can be
shifted into or out of the flip‐flops is called shift register. There are two ways to
shift data into a resister (i.e. serial or parallel) and similarly two ways to shift the
data out of the register. Serial shifting involves shifting data one bit at a time in a
serial fashion beginning with either the MSB or LSB. Parallel shifting involves
shifting all the data bit simultaneously with single clock transition. Hence, the
parallel shifting method is much faster than the serial shifting method. They are
classified into following four types based on how the binary information is
entered or shifted out.
a) Serial‐in Serial‐out Shift Register (SISO)
b) Serial‐in Parallel‐out Shift Register (SIPO)
c) Parallel‐in Serial‐out Shift Register (PISO)
d) Parallel‐in Parallel‐out Shift Register (PIPO)
IC 7474 Dual Edge Triggered ‘D’ Flip‐Flop

36
Serial in – Serial out Shift Register (SISO)
Logic Diagram

Truth table
Inputs Outputs
Clear Clock Data FF‐A FF‐B FF‐C FF‐D
0 0 0 0 0 0 0
1 1 1 1 0 0 0
1 2 0 0 1 0 0
1 3 1 1 0 1 0
1 4 1 1 1 0 1
1 5 0 0 1 1 0
1 6 0 0 0 1 1
1 7 0 0 0 0 1
Timing Diagram
Serial in ‐ Parallel out Shift Register (SIPO)
Logic Diagram

37

Truth table
Inputs Outputs
Clear Clock Data FF‐A FF‐B FF‐C FF‐D
0 0 0 0 0 0 0
1 1 1 1 0 0 0
1 2 0 0 1 0 0
1 3 1 1 0 1 0
1 4 1 1 1 0 1
Timing Diagram
Parallel in – Serial out Shift Register (PISO)
Logic Diagram

38
Timing Diagram
Parallel in ‐ Parallel out Shift Register (PIPO)
Logic Diagram

39
Timing Diagram
PROCEDURE:
1. Give the circuit connections as per logic diagram.

2. Give the input signal (clear & preset inputs) and the clock pulse.
3. Observe the output and verify this with the truth table.
RESULT:

40
EXPT NO:
DATE:
Static Characteristics of Semiconductor Devices: PN Diode & BJT

in CE Configuration
AIM:
 To determine the static characteristics of semiconductor diode under
forward and reverse biased conditions and to calculate its dc and ac
resistance values.
 To determine the input and output characteristics of the given NPN
transistor under common emitter (CE) configuration and calculate the h‐
parameters.
APPARATUS REQUIRED:
1 Regulated Power Supply (0‐30)V
2 Voltmeter (0‐10) V MC 1
5 Ammeter (0‐50) mA MC 1
8 Diode 1N4007 1
9 Transistor BC 107 1
10 Resistor 1kΩ 2
11 Bread board 1
12 Connecting wires
Semiconductor Diode
THEORY:
Forward Bias:
The positive terminal of the voltage source is connected to the anode of the diode
and negative terminal to the cathode. When forward voltage (VF) is increased in
steps of 0.1, there is a particular voltage at which diode starts conducting is
called knee voltage (or) cut‐in voltage. Below the cut in voltage, VK, current is
zero. After the cut in voltage, VK, current is sharply increased.
Reverse Bias:
In the case of reverse biased condition, there is little flow of current through the
diode with increase in reverse voltage VR, until a particular point called
breakdown voltage VBR is reached. Beyond VBR, the reverse current IR increases
for a constant value of VR.


41
PROCEDURE:
Forward Bias:
1. Give the connections as per the circuit diagram.

2. Switch on the power supply.
3. Vary the supply voltage in steps and note down the corresponding
voltmeter and ammeter readings.
Reverse Bias:
1. Give the connections as per the circuit diagram (polarity of the diode is
reversed and meters are replaced suitably).
2. Switch on the power supply.
3. Vary the supply voltage in steps and note down the corresponding
voltmeter and ammeter readings.
PIN DIAGRAM:
CIRCUIT DIAGRAM:
Forward Bias:
Reverse Bias:

42
MODEL GRAPH:

CALCULATION:
Vf
Static resistance, RD  R D  =
If
V f
Dynamic resistance, rd  rd  =
I f
TABULATION:
S. Forward Forward S. Reverse Reverse
No. Voltage, Current, No. Voltage, Current,
Vf (V) If (mA) VR (V) IR (µA)
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19

43
BJT in CE Configuration
THEORY:
Input Characteristics:
1. There exists a threshold (or) knee voltage (Vk) below which base current is
very small.
2. Beyond the knee, IB increases with the increase in base to emitter voltage,
VBE, for a constant collector to emitter voltage, VCE. Since the input resistance
is high for CE configuration than CB mode, the value of IB does not increase as
rapidly as that of input characteristics of common base.
3. When collector to emitter voltage, VCE is increased above 1V, curve shift
downwards. It occurs because of the fact, that as VCE is increased, the
depletion width in base region increases. The effective width of base
decreases, which in turn reduces IB.
4. With the help of input characteristics, ac input resistance can be calculated
V BE
with  Ri 
I B
Output Characteristics:
1. There are 3 regions namely saturation region, active region and cut‐off
region.
2. As the collector to emitter voltage, VCE, is increased above zero, the collector
current, IC increases rapidly to a saturation value ,depending upon the value
of base current.
3. When VCE is increased further, the IC slightly increases. It is due to the fact
that increase in VCE, will decrease the IB and hence IC increases. This
phenomenon is called early effect.
4. When IB is zero, small IC exists. This is called leakage current.
5. With the help of output characteristics, ac output resistance can be calculated
VCE
with  Ro 
I C
Hybrid Parameters:
V BE
 Input resistance, hie   at constant VCE.
I B
V BE
 Reverse voltage transfer ratio, hre  at constant IB .
VCE
I C
 Forward current transfer ratio, h fe  at constant VCE.
I B
I C
 Output conductance, hoe   1 or mho at constant IB
VCE


44

PROCEDURE:

2. Keep the voltage VCE constant at a particular value.
3. Vary the voltage VBE in steps and note down the corresponding current
IB.
4. Repeat the same procedure for different VCE but constant values of VCE.

2. Keep the base current IB constant at a particular value.
3. Vary the voltage VCE in steps and note down the corresponding current
IC.
4. Repeat the same procedure for different IB but constant values of IB.

PIN DIAGRAM:
CIRCUIT DIAGRAM:

45
MODEL GRAPH:

CALCULATION:
V BE
 Input resistance, hie   =
I B
V BE
 Reverse voltage transfer ratio, hre  =.
VCE
I C
 Forward current transfer ratio, h fe  =.
I B
I C
 Output conductance, hoe   1 =
VCE
TABULATION:
S. VCE = V VCE = V
No. VBE (V) IB (mA) VBE (V) IB (mA)
1
2
3
4
5
6
7
8
9
10
11
12
13
14

46
S. IB = mA IB = mA
No. VCE (V) IC (mA) VCE (V) IC (mA)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

RESULT:
 The forward and reverse bias characteristics of PN junction diodes have
drawn. The calculated dc and ac resistance are,
o dc (or) Static resistance, RD =
o ac (or) Dynamic resistance, rd =
 The input and output characteristics of common emitter configuration of
BJT have been drawn and their h parameters are determined from the
graph.
Parameters hie (Ω) hre hfe hoe (1/Ω)
Values

47
EXPT NO:
DATE:
Design and Frequency Response Characteristics of Common

Emitter Amplifier
AIM:
To design a common emitter amplifier and study it’s frequency response

characteristics.
APPARATUS REQUIRED:

1 BJT BC 107 1
Regulated power
2 (0‐30)V 1
Supply
3 Function Generator (0‐1)MHz 1
4 Capacitor 10µF 3
5 Resistor 1kΩ, 18kΩ, 3.3kΩ, 250Ω 1 (each)
6 Bread board
7 CRO (0‐20) MHz 1
8 Digital multi‐meter 1
9 Connecting wires
THEORY:
The resistor (R) and capacitor (C) forms the coupling network. The capacitor Cin
couples the input signal to the base of the transistor whereas Cout couples to the
output signal to the load resistor (RL). The resistors R1 and R2 provide the DC
biasing. The input signal is amplified by Q1 and appears across RC. The output of
first stage is coupled to the input of second stage/ load resistance (RL). The
voltage gain of the amplifier varies with signal frequency due to the effect of
variations in circuit capacitive reactance with signal frequency on the output
voltage. If the curve is drawn between voltage gain and signal frequency of an
amplifier, it is known as frequency response. If the input frequency of an
amplifier is varied with constant input voltage, it is observed that the amplifiers
gain,
 Remains constant over range of mid‐frequency
 Falls off at low as well as high frequencies
The fall‐off in amplifier gain at low frequencies is due to the effect of coupling
and bypass capacitors. At medium and high frequencies, the capacitive reactance
Xc is very small and therefore all coupling and bypass capacitors behave as short
circuits. At low frequencies, capacitive reactance increases and some of the signal
voltage is lost across the capacitors. Thus with the increase in frequency, the
reactance of the capacitor increases and therefore the gain in the circuit falls. The
CE configuration is capable of obtaining the voltage gain greater than the unity
and this configuration is the most versatile and widely used. Low frequency roll

48
off is determined by the coupling capacitor Cin and bypass capacitor CE. The
higher frequency cut off is determined by the stray capacitance of a transistor.
DESIGN:
 Choose transistor: As before, the transistor type should be chosen according

to the anticipated performance requirements.
 Calculate collector resistor: It is necessary to determine the current flow
required to adequately drive the following stage. Knowing the current flow
required in the resistor, choose a collector voltage of around half the supply
voltage to enable equal excursions of the signal up and down. This will define
the resistor value using Ohms law.
 Calculate the emitter resistor: Generally a voltage of around 1 volt or 10%
of the rail value is chosen for the emitter voltage. This gives a good level of DC
stability to the circuit. Calculate the resistance from knowledge of the
collector current (effectively the same as the emitter current) and the emitter
voltage.
 Determine base current: It is possible to determine the base current by
dividing the collector current by β (or hfe which is essentially the same). If a
range for β is specified, work on the cautious side.
 Determine the base voltage: This is easy to calculate because the base
voltage is simply the emitter voltage plus the base emitter junction voltage.
This is taken to be 0.6 volts for silicon and 0.2 volts for germanium
transistors.
 Determine base resistor values: Assume a current flowing through the
chain R1 + R2 of around ten times that of the base current required. Then
select the correct ratio of the resistors to provide the voltage required at the
base.
 Emitter bypass capacitor: The gain of the circuit without a capacitor across
the emitter resistor is approximately R3/R4. TO increase the gain for AC
signals the emitter resistor bypass capacitor C3 is added. This should be
calculated to have a reactance equal to R4 at the lowest frequency of
operation.
 Determine value of input capacitor value: The value of the input capacitor
should equal the resistance of the input circuit at the lowest frequency to give
a ‐3dB fall at this frequency. The total impedance of the circuit will be β times
R3 plus any resistance external to the circuit, i.e. the source impedance. The
external resistance is often ignored as this is likely to not to affect the circuit
unduly.
 Determine output capacitor value: Again, the output capacitor is generally
chosen to equal the circuit resistance at the lowest frequency of operation.
The circuit resistance is the emitter follower output resistance plus the
resistance of the load, i.e. the circuit following.
 Re‐evaluate assumptions: In the light of the way the circuit has developed,
re‐assess any circuit assumptions to ensure they still hold valid. Aspects such
as, the transistor choice, current consumption values, etc.
 Take VCC = 10V; IC = 4mA (may vary based on the requirement).

49
 The steps are,

1. Transistor type: BC107
2. VCE = VCC/2 ; VC = VCE + VE (Let VE = 1V) ; ICRC = VCC – VC ; RC = (VCC – VC)/IC.
3. VE = 1V ; VE = IERE ; IE = IC ; RE = VE/IC.
4. VBE = VB ‐ VE.
5. VB = VBE+VE.
6. VB = (VCC×R2)/(R1+R2); R2 = (VB/VCC)×(R1+R2)
7. XC = RE at lower frequencies
8. CE = 100µF; C1 = 22µF; C2 = 22µF
CIRCUIT DIAGRAM:
MODEL GRAPH:

50
FORMULA USED:
Voltage Gain (dB) = 20 log (Vo/Vi)

where Vo = Output Voltage, Vi = Input Voltage
TABULATION:
Frequency Input Signal Output Voltage Gain Voltage Gain

(Hz) (mV) Signal (V) (dB)


51
RESULT:
The frequency response of the CE amplifier has been obtained and the
bandwidth is found to be

52
Bread Boarding Suggestions for IC 741

1. Do all the wiring with power off.
2. Keep wiring under component leads as short as possible.
3. Wire the +Vcc and –Vcc supply leads first to the op‐amp.
4. Try to wire all the ground leads to one tie point, with power supply
common. This type of connection is called star grounding.
5. Do not use a ground bus because we may create a ground loop thereby
generating unwanted noise voltage.
6. Recheck wiring before applying power to the op‐amp.
7. Connect signal voltages to the circuit only after the op‐amp is powered.
8. Take all measurements with respect to ground. For (e.g.) if a resistor is
connected between two terminals of an IC, do not connect either a
meter or a CRO across the resistor. Instead measure the voltage on one
side of the resistor and then on the other side, calculate the voltage
across the resistor.
9. Avoid using ammeters if possible measure voltage and calculate
current.
10. Disconnect the input signal before the DC power is removed otherwise
the IC may be destroyed.
11. These IC‐s will stand much abused but never
 Reverse the polarity of the power supply.
 Drive the op‐amp input pins above or below the potentials at the
positive terminals.
 Leave an input signal connected with no power on the IC.
12. If unwanted oscillations appear at output and circuit connections are
incorrect, then
 Connect a 0.1µF capacitor in between op‐amp, +Vcc pins and ground
and 0.1µF capacitor between op‐amp, ‐Vcc pins and ground.
 Shorten the leads.
 Check the testing instrument like signal generator, power supply
ground leads and load. They should come together at one point.


53
EXPT NO:
DATE:
Basic Applications of Op‐Amp: Inverting and Non‐inverting

Amplifiers & Voltage Follower
AIM:
To design, implement and verify the outputs of (i) inverting amplifier, (ii) non‐
inverting amplifier, (iii) voltage follower using op‐amps.
APPARATUS REQUIRED:

1 IC 741
2 Dual power supply
3 Capacitors
4 Resistor
5 Resistor
Bread board/ Linear IC Trainer
6
Kit
7 Connecting wires
8 Cathode Ray Oscilloscope
9 Function generator
10 Digital multimeter
PIN Details: IC ‐741 OP AMP

IC 741 Specifications:

 Supply Voltage : ±18 V
 Input voltage : ±15 V
 Power Dissipation: 500 mW
 Input Resistance : 2 MΩ
 Output Resistance: 75 Ω


54
Inverting Amplifier
THEORY:
In an Inverting amplifier, the output voltage Vo is fed back to the inverting input
terminal through the feedback resistor Rf. The input volatge Vi is applied to the
inverting input terminal through Ri and the non‐inverting terminal is grounded.
The gain Av = ‐(Rf / Ri), there is a 180o phase shift between Vo & Vi .The value of Ri
must be larger to avoid loading effect, but this limits the gain of the circuit.
CIRCUIT DIAGRAM:
DESIGN:
 Closed loop voltage gain A =Vo /Vi = ‐(Rf / Ri )

 Given A = 10, Assume Ri = 1kΩ
 Vo / Vi = A = 10 = ‐( Rf / 1KΩ) Rf =10 kΩ
TABULATION:
Vo Vo = ‐Rf/Ri ×Vi
S. No. Vi
(Practical Value) ( Theoretical Value)

55
Non‐Inverting Amplifier
THEORY:
In the non‐inverting amplifier, the input is applied to the non‐inverting terminal

& the output is fed to the inverting terminal, so the circuit amplifies without
inverting the output. Since Rf & Ri form a potential divider network, Vi = VoRi /
(Ri+Rf). Since no current flows through the Op‐Amp the voltage gain is given by
Av = Vo / Vi = 1+(Rf / Ri). The input resistance of the non‐inverting amplifier is
very high since the op‐amp draws negligible current from the signal source.
CIRCUIT DIAGRAM:
DESIGN:
 Closed loop voltage gain A =Vo /Vi = 1+(Rf / Ri )

 Given A = 10, Assume Ri = 1kΩ
 Vo / Vi = A = 10 =1+( Rf / 1KΩ) ; Rf =9 kΩ
TABULATION:
Vo= (1+Rf/Ri) ×Vi

Vo
S. No. Vi ( Theoretical Value)
(Practical Value)


56
Voltage Follower
THEORY:
The special case of non‐inverting amplifier is voltage follower, where the input
resistance is infinite and the feedback resistance is zero. As the input impedance
is very high, voltage follower may be used as buffer for impedance matching. The
input and output voltages are equal in magnitude as well as phase.
CIRCUIT DIAGRAM:
PROCEDURE:
 Give the connections as per circuit diagram & apply the input voltage(s)
 Measure the corresponding output on CRO / using multimeter.
 Repeat the same for different values of frequencies / voltages.
 Observe the input & output waveforms & tabulate the values.
RESULT:

57
EXPT NO:
DATE:
Adder, Subtractor and Comparator Circuits using Op‐Amps

AIM:
To design, implement and verify the outputs of (i) adder, (ii) subtractor, (iii)
comparator using op‐amp.
APPARATUS REQUIRED:

1 IC 741
2 Dual power supply
3 Capacitors
4 Resistor
5 Resistor
6
Kit
7 Connecting wires




58
Adder
THEORY:
Adder is a circuit whose output is the sum of several input signals. It can be an
inverting or a non‐inverting summer. In an inverting summer, the output is
inverted sum of input signals. In practical circuit Rcomp is provided which is
parallel combination of input & feedback resistors. Rcomp is Ri in parallel with Rf.
CIRCUIT DIAGRAM:
DESIGN:
 Let R1 = R2 = R3 =Rf , Rf =1kΩ & Gain = Vo / Vi =1

 Vo / Vi = ‐Rf / Ri = 1 Ri =1 kΩ.
TABULATION:
Vi Vo Vo =‐(V1+V2+V3)
S. No.
V1 V2 V3 (Practical Value) ( Theoretical Value)

Subtractor
THEORY:
A basic differential amplifier can be used as subtractor. If all the resistors are
equal in value, then the output voltage is difference between the input signals
and the circuit act as simple subtractor.

59
CIRCUIT DIAGRAM:
TABULATION:
Vi Vo Vo =(V1‐V2)
S. No.
V1 V2 (Practical Value) ( Theoretical Value)

PROCEDURE:
 Measure the corresponding output on CRO / using digital multi‐meter
(DMM).
Comparator
THEORY:
A comparator is a circuit which compares a signal voltage applied at one input of

an op‐amp with a known reference voltage at the other input. It is basically an
open loop op‐amp with output ±Vsat.

60
CIRCUIT DIAGRAM:
MODEL GRAPH:
TABULATION:
Vo(Peak to Peak)
Vo (Peak to Peak)
S. No. Vi Vref ( Theoretical
(Practical Value)
Value)

1 +

2
―

RESULT:

61

EXPT NO:
DATE:
Integrator and Differentiator Circuits using Op‐amp

AIM:
To design, implement and verify the outputs of integrator &

differentiator circuits using op‐amp.
APPARATUS REQUIRED:

1 IC 741
2 Dual power supply
3 Capacitors
4 Resistor
5 Resistor
6
Kit
7 Connecting wires




62
Integrator
THEORY:
In an integrator the output is ‐1/RfC1 times the integral of the input & RfC1 is the
time constant of the integrator. The gain at low frequency can be limited to avoid
saturation if the feedback capacitor is shunted by resistance Rf. The parallel
combination dissipates power so it is a lossy integrator. Rf also limits the low
frequency gain to Rf/R1 and thus gives DC stabilization.
CIRCUIT DIAGRAM:
DESIGN:
 Given Time constant T = 1 ms; Assume R1 = 1 kΩ

 T = R1 Cf Cf =1μF & Rf =10R1 Rf=10 kΩ.
MODEL GRAPH:
TABULATION:
Observed
Vi Input Frequency
Vo


63
Differentiator
THEORY:
In the differentiator, the output waveform is the derivative of the input

waveform. In a practical differentiator circuit, the high frequency noise &
stability problems are avoided by the capacitor Cf across Rf. For good
differentiation, the time period of the input signal T should be greater than or
equal to RfC1.
CIRCUIT DIAGRAM:
DESIGN:
 fa = 1/2πRfC1 , fb=1/ 2πR1C1 ,RfCf = R1C1 & fb=10fa

 Let fa = 800Hz & C1 =0.1 μF
 Rf = 1/2πfaC1= 1.98 kΩ
 R1= 1/ 2π fbC1=198 Ω
 R1 C1= Rf Cf Cf =0.01 μF.
MODEL GRAPH:

64
TABULATION:
(i)For Triangular wave input
Vi Input Frequency Observed

Vo

(ii) For Square wave input
Vi Input Frequency Observed

Vo

PROCEDURE:
 Measure the corresponding output on CRO / using multimeter.
RESULT:

65
General Design Considerations – 555 Timer

 The timer will operate over a guaranteed voltage range from 4.5V to
18V DC.
 The timing interval is independent of supply voltage since the
change rate and threshold level of the comparator are both directly
proportional to supply.
 The supply voltage should be filtered and adequately bypassed,
because ripple can cause timing inaccuracy.
 Due to the nature of the output structure, which is a high power
totem pole design, the output of the timer can exhibit large current
spikes on the supply line. Bypassing is necessary to eliminate this.
Use 0.01μF to 10‐μF capacitor across VCC & ground and as close to
the device.
 Stable external components should be used for the RC network to
maintain good timing accuracy.
 The timer exhibits a typical internal accuracy of 1%, i.e. with any
one RC network; from timer to timer only 1% change is to be
expected.
 Most timing is due to external component tolerance. Therefore,
where timing is critical, use precision components.
 For best results, a quality drim POT placed in series with largest
resistance will allow for the best adjustability and performance.
 The timing capacitor should be high quality stable component with
very low leakage characteristics. Never use ceramic disc capacitor in
timing networks. Acceptable capacitor types are: Silver Mica, Mylar,
Polycarbonate, Polystrene, Tantalum and similar materials.
 The timer exhibits a small negative temperature co‐efficient. If timer
accuracy over temperature is important, use timing components
with a small positive temperature co‐efficient to nullify.
 A minimum value of threshold current is necessary to trip the
thresold comparator. This is 0.25μA. To calculate the maximum
value of resistance, at the time of the threshold current is required,
2
the voltage on the threshold pin is VCC
3
 Maximum R is then, R max  V CC / 0 .25 μA. With +15V supply, this is
3
20MΩ while with +5V, this is 6.6 MΩ


66
EXPT NO:
DATE:
Timer IC Application: Study of NE/SE 555 Timer in Astable,

Monostable Operation
AIM:
To design, implement and verify the outputs of the monostable & astable
multivibrator circuits using IC 555 timer.
APPARATUS REQUIRED:

1 IC 555 timer 1
2 Power supply (0‐15) V 1
3 Capacitors 0.01uF, 1uF 1 each
4 Resistors 1kΩ, 10kΩ 1 each
5 Pulse generator 1
6 Bread board 1
7 Connecting wires
8 Cathode Ray Oscilloscope 1
9 Digital multimeter 1
Monostable Multivibrator
THEORY:
A monostable multivibrator often called a one‐shot multivibrator is a pulse

generating circuit in which the duration of the pulse is determined by the RC
network connected externally to the 555 timer. In the stable state, the output of
the circuit is at logic low level. When an external trigger pulse is applied, the
output is forced to go high. The time during which the output remains high is
given by, T = 1.1 RC. At the end of the timing interval, the output automatically
reverts back to its logic low state. The output stays low until a trigger pulse is
applied again. Then the cycle repeats. Thus the monostable state has only one
stable state hence the name monostable.
DESIGN:
 Given T = 1ms
 T =1.1 RC
 Assume C= 0.1 μF
 R = T / 1.1 C = 1 ms / (1.1 × 0.1 μF) =9.09 kΩ ≈10kΩ
 Hence calculated T = 1.1× 0.1 μF×10kΩ =1.1ms


67
IC 555 PIN Diagram:
CIRCUIT DIAGRAM:
MODEL GRAPH:

68
TABULATION:
Parameter Observed value Calculated value
Trigger input
(i) T
(ii) Ton
(iii) Vi PP
Output Voltage
Output pulse width
Capacitor Voltage
Astable Multivibrator
THEORY:
An astable multivibrator, often called a free‐running multivibrator, is a

rectangular‐wave‐generating circuit. This circuit do not require an external
trigger to change the state of the output. The time during which the output is
either high or low is determined by two resistors and a capacitor, which are
connected externally to the 555 timer. The time during which the capacitor
charges from 1/3 Vcc to 2/3 Vcc is equal to the time the output is high and is given
by, tHIGH = 0.69 (RA + RB) C.
Similarly, the time during which the capacitor discharges from 2/3 Vcc to
1/3 Vcc is equal to the time the output is low and is given by, tLOW = 0.69 RB C.
Thus the total time period of the output waveform is,
T = tHIGH + tLOW = 0.69 (RA + 2RB) C
The term duty cycle is often used in conjunction with the astable
multivibrator. The duty cycle is the ratio of the time tc during which the output is
high to the total time period T. It is generally expressed in percentage. In
equation form,
D = [(RA + RB) / (RA + 2RB)] ×100%
DESIGN:
 Given, T = 1ms, D = 70%

 T = 0.69 (RA +2RB)C, here T = 1 ms, Assume C= 0.1 μF
 1 ms = 0.69 × 0.1 μF (RA + 2R B) ………(i)
 D = [(RA + RB) / (RA + 2RB)] = 0.7………..(ii)
 Solving (i) & (ii) RA = 10.1 kΩ ≈ 10 kΩ & RB = 4.37 kΩ ≈ 4.7 kΩ
 Hence, calculated T = 0.69 (10 kΩ +2×4.7 kΩ) 0.1 μF =1.3ms

69
CIRCUIT DIAGRAM:
MODEL GRAPH:
TABULATION:
Parameter Observed value Calculated value
Output Voltage
Capacitor Voltage
tHIGH
tLOW
Frequency
Duty Cycle


70
PROCEDURE:
 Give the connections as per circuit diagram.

 Give the supply voltage at pin 8.
 Note down the input & output waveforms on CRO at pins 2 & 3.
 Also note down the capacitor voltage.
 Plot the waveforms on a graph.
RESULT:

71
EXPT. NO:
DATE:
Waveform Generators using Op‐Amp: Sine, Square & Triangular

– Using PSpice Software
AIM:
To simulate the waveform generators using IC 741 with the PSPICE software.
APPARATUS REQUIRED:
PSPICE ORCAD VERSION 9.3.
THEORY:
SPICE is a general‐purpose circuit program that simulates Electrical & Electronic

Circuits. SPICE is an acronym of Simulation Program With Integrated Circuit
Emphasis. PSPICE is a PC version of SPICE developed by Microsim Corporation.
The PC version needs 512 kilobytes of memory to run. It is possible to simulate
circuits that contained both analog & digital devices using this package. It
contains models for common circuit elements & it is capable of simulating most
of the Electrical & Electronic Circuits. This software allows the designer to
investigate the behavior of a circuit without having to actually breadboard the
circuit in the laboratory. This allows for a considerable savings in the materials
and labour. Also if the design needs to be modified, changes can be easily
submitted to the computer for another look at the results. PSPICE allows various
types of analysis.PSPICE is a simulation program that models the behavior of a
circuit. It is a software‐based breadboard of the circuit that can be used to test
and refine the design.Information about Pspice is available from the OrCAD
website: http://www.orcad.com.
PROCEDURE:
 Simulate the circuit using PSPICE by the instructions.

72
SIMULATIONS:
(i). Sine wave generator – RC phase shift oscillator
PSpice Netlist (using A/D lite)

Simulation Output:

73
(ii). Wein Bridge Oscillator
PSpice Circuit (using Capture)

Simulation Output

74
(iii). Square wave generator
PSpice Circuit (using Capture): Design 1

Simulation Output for Design 1

75


76
(iv). Triangular wave generator


77

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ANALOG AND DIGITAL ELECTRONIC

CIRCUITS LABORATORY (UEE1412)

DEPARTMENT OF ELECTRICAL & ELECTRONICS

SSN COLLEGE OF ENGINEERING

Jan 2021 – APRIL 2021

NAME OF THE STUDENT: __________________________________________

REGISTER NO.: _____________________________________________________

SEMESTER: _____________________ SECTION: ____________

EXPT. DATE OF FACULTY

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

Study of Basic Digital ICs

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

 In a digital IC trainer board, Fix the IC s firmly.

 Fix the IC s firmly in a digital IC trainer.

TTL Gate Pin Details

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

Implementation of Boolean Functions, Adder and Subtractor

i. To simplify the given Boolean function using Karnaugh map and

S. No Apparatus Range Type Quantity

Boolean Function Reduction

Canonical Forms (Normal Forms): Any Boolean function can be written in

Realization of Boolean Expression

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

Using Basic Gates

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

Adder & Subtractor

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

Design of Code Converters

To design and implement combinational logic circuits that converts

S. No. Apparatus Required Range Type Quantity

General Design Procedure:

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

Parity Generator and Parity Checking

S. No. Apparatus Required Range Type Quantity

3‐Bit Even Parity Generator

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

Karnaugh Map Reduction

3‐Bit Even Parity Checker

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

Encoders and Decoders

S. No. Apparatus Required Range Type Quantity

An Encoder is a combinational logic circuit that converts an active input signal

4‐to‐2 Line Encoder

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

2‐to‐4 Line Decoder

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

Multiplexer & Demultiplexer

S. No. Apparatus Required Range Type Quantity

A digital multiplexer is a combinational circuit that selects binary information

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

SELECTION INPUT OUTPUT

PIN Diagram of IC 7411:

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

Selection Input Output

UEE1412 - ADEC Lab, Department of EEE / SSN College of Engineering

SEMESTER: _________ SECTION: