Chap - 06 - Nano-Scaled Fet

CHAP #06 - PART 1
Nano-Scale FETs
In this lecture you will learn:
• Nano-scale FETs
• FET size scaling
• Short channel length effects
• Fin-FETs
gate
gate
source drain source drain
y 0 y L
y 0 y L
x
x
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
Why Nano-Scale FETs?

● Smaller FETs (shorter channel lengths L) are faster (in both analog and digital
applications):
Smaller FETs will have a larger current ID, larger gm, smaller
capacitances Cgs and Cgd , higher fT, shorter rise and fall times tr and tf , all
for the same voltages VGS and VDD
● Smaller FETs occupy smaller areas
This means more FETs can be put in a chip
● Since power dissipation in a digital chip goes as VDD2, the higher performance of
smaller FETs can be traded-off for lower power dissipation by scaling down the
voltages
● New physics emerging at nano-scales enables one to design better FETs (…..but
can also create new problems)
Quantum transport, wave mechanics, energy level quantization, mobility

engineering, ballistic scattering-free transport, coulomb blockade, …….
How does one scale down the size of a FET?
1
The Poisson Equation and the FET
The gradual channel approximation: Electrostatics in the vertical (x) direction are
decoupled from the electrostatics in the horizontal (y) direction
gate
The “gradual channel approximation” works for
source drain a large channel length MOS transistors:
y 0 y L  2  x  

x x 2 
100 nm
TEM of a 100 nm gate length MOS transistor

The Poisson Equation and the FET

gate
Gradual channel approximation fails for a sub-micron
MOS transistor – need to solve a 2-dimensional source drain
Poisson equation
Na
y 0 x y L
 2  x , y   2  x , y   x, y 
 
x 2 y 2 
The charge density is approximately that associated

with the depletion regions (at least below
threshold):
  x , y   qN a  x , y  50 nm
L = 35 nm
What new physics does a 2D Poisson equation
produces?
TEM of a 35 nm gate length FET
2
Scaling Down the FET
 2  x , y   2  x , y  qN a  x , y 
  gate
x 2 y 2  source drain
Suppose we:
y 0 y L
1) Scale down all the dimensions by “”
x
x y
x'  y' 
  gate
   x ' , y '     x ' , y '  qN a  x ' , y ' 2

2 2
    source drain
x ' 2 y ' 2 
Na
2) Scale down all the potentials by “” y'  0 y '  L'
x'
  x ' , y '
 '  x ' , y ' 

 2 '  x ' , y '   2 '  x ' , y '  qN a  x ' , y '   2 
    
x ' 2 y ' 2   
gate
Scaling Down the FET
 2 '  x ' , y '   2 '  x ' , y '  qN a  x ' , y '   2  source drain
    
x ' 2 y ' 2    Na
And suppose we: y'  0 y '  L'
3) Scale up all the dopings by “ ” x'
N a'  x ' , y '    N a  x ' , y '  gate
 2 '  x ' , y '  2 '  x ' , y ' qN a'  x ' , y '   2 

source drain
     
x ' 2 y ' 2    N’a
y'  0 y '  L'
If we choose: 2
 x'
1

then the 2D spatial potential profiles in the scaled device (whose
dimensions are smaller by ) would be the same as that in the
prescaled device (however, the potentials would be scaled down by )

The electric field in the scaled device would be larger by a factor:

 '    '  
 
x '  x y '  y
3
Scaling Down the FET: Problems
Constant electric field scaling:
If we choose: gate
   source drain
then the electric field in the scaled device would be the

same as in the pre-scaled device y 0 y L
x
gate
End result:
1) We reduced the device dimensions (good for faster operation)
2) We reduced the potentials (good for lower power dissipation) source drain
3) We kept the device electric field the same (so no device

N’a
breakdown problems in the smaller device)
y'  0 y '  L'
Problems with the device scaling described above: x'

1) Potentials cannot be scaled down too much when the device dimensions are
reduced (need to leave enough room for noise margins, for example)
2) Consequently, electric field increases in smaller devices (and causes problems)
3) Material constants, like the potential M of the gate metal and built-in potentials B,
and thermal voltage KT/q do not scale when the external applied voltages are scaled
4) Increase in device doping in smaller devices causes carrier mobility degradation
=> Smaller devices suffer from many problems (termed “short channel effects”)
The Nano-Scale FET: 2D Poisson Equation

In the gradual channel approximation we had obtained:
gate
source drain  2  x , y  qN a
 In the bulk
x 2 s
y 0 y L
2  s qN a  2 p  VSB 
Na x
VTN  VFB  2 p 
Cox
In nano-scale FET we need to consider the 2D Poisson
gate
equation:
source drain
 2  x , y   2  x , y  qN a
 
y 0 y L x 2 y 2 s
Na
x  2  x , y  qN a  2  x , y 
  
x 2 s y 2
   2  x , y  
q  N a  s
 2  x , y  q y 2  qN a eff
   
x 2 s s
4
Threshold Voltage Roll-Off (A Short Channel Effect)
gate
 2  x , y  qN a eff
source drain 
x 2 s
 s  2  x , y 
y 0 y L N a eff  N a   Na
Na q y 2
x Curvature
As the channel length is reduced, the potential curvature in the
s(y) = -p + VCS(y) y-direction increases, and the effective doping is reduced
2  s qN a eff  2 p  VSB 
Since: VTN  VFB  2 p 
Cox
The threshold voltage of the device reduces as the channel
y length is reduced!
y=0 y=L
VTN
Difficult to turn small

FETs off!
~ 1.0 m Channel length (L)

Current Saturation Via Velocity Saturation

(A Short Channel Effect)
Current saturation in long channel length (> 1 m) FETs is due to
pinch-off
In short channel length (< 1 m) FETs, something else saturates the
current before pinch-off; velocity saturation!
nE
Recall that the drift velocity for electrons (handout 9) is: v dn  
E
1
In Silicon: E sat ~ 5  10 4 V/cm E sat
And the FET current is (handout 9):

dVCS y 
n
 n E y  dy
I D  W QN y   W Cox VGS  VTN  VCS 
E 1 dVCS y 
1 1
E sat E sat dy
In the linear region, the above integrates to (handout 9):
 n Cox VGS  VTN  DS  Vsat  E sat L

W V VDS
ID 
L  2   V 
 1  DS  Vsat smaller for
 V sat  shorter FETs
5
In the linear region:
 n Cox VGS  VTN  DS 
W V VDS
ID 
L  2   VDS  Vsat  E sat L
 1  
 V sat 
If Vsat was ∞, the above expression, as a function of VDS, has a maximum when VDS
equals VGS – VTN (corresponding to channel pinch-off near the drain end)
But if Vsat was very small, much smaller than VGS – VTN , the above expression has a
maximum when VDS is smaller than VGS – VTN
ID Without velocity I D SAT

Vsat  E sat L saturation
With velocity I D SAT

saturation
Vsat is smaller for
smaller channel
length devices
VDS SAT  ? VDS SAT  VGS  VTN VDS


In the linear region:
 n Cox VGS  VTN  DS 
W V VDS
ID 
L  2   VDS  Vsat  E sat L
 1  
 V sat 
In saturation (due to velocity saturation):
dI D 2VGS  VTN 
0 VDS SAT   VGS  VTN 
dVDS 2VGS  VTN 
1 1
Vsat
The expression for IDS-SAT is complicated but in the limit Vsat << VGS-VTN (extreme short
channel FET):
W
I D SAT   n Cox VGS  VTN Vsat Note the linear dependence
L of the saturation current on
W the gate-to-source voltage
  n Cox VGS  VTN E sat L (this is a characteristic
L
behavior of velocity
 W  n E sat Cox VGS  VTN 
saturation)
 W v dn  sat Cox VGS  VTN 
6
A long channel FET (current saturation via channel pinch-off):

ID
kn
I D SAT  VGS  VTN 2
2
VTN VGS
A very short channel FET (current saturation via velocity saturation):
ID
I D SAT  W v dn  sat Cox VGS  VTN 
VTN VGS
Electrostatic Potential in FETs below Threshold

Consider the electrostatic potential in a long channel FET at flatband (VGS << VTN):
+
+ VDS
VGS
gate
source drain  tox 0
x
p
y 0 y L
Na x
VDS  0  s y 
n  VSB n  VDB
VDS  0
Now assume VDS > 0:  n  n
+
+ VDS y
VGS p
gate 0 L
source drain
n  VSB  s y 
VDS  0 n  VDS
y 0 y L  n
Na x
VDS  0 y
p
0 L
7
Electron Potential Energy in FETs below Threshold
Consider the electron potential energy in a long channel FET at flatband (VGS << VTN):
+
+
 q s  y 
VDS
VGS
gate
source drain VDS  0
y 0 y L y
Na x
 q n  qn
VDS  0 0 Potential L
barrier for
Now assume VDS > 0: electrons
+
+
VDS
 q s  y 
VGS
gate
VDS  0
source drain
y
y 0 y L
 q n
Na x 0 L  q n  VDS 
VDS  0 No large current flow because there are no
electrons in the inversion channel
Drain Induced Barrier Lowering (DIBL) in Short FETs

Now assume VDS >> 0:
 q s  y 
+ VDS  0
+ VDS
qbh
VGS
gate
source drain
y
 q n
y 0 y L 0
Na x
VDS  0  q n  VDS 

L
Current can flow because the potential Log10( ID )
barrier for electrons to enter the channel Weak inversion
from the source has been reduced. This 0 Strong inversion
is called drain induced barrier lowering
VTN
(DIBL) -1 Larger VDS
Smaller VDS
It is as if the device threshold voltage VTN qbh
becomes a function of VDS (becoming -2
smaller fro larger VDS) I D ~ e KT
-3 q
This effect becomes more pronounced VGS VTN 
for short (sub-micron) FETs I D ~ e mKT

VTN VGS
8
Electrostatic Potential in FETs above Threshold
Consider the electrostatic potential in a long
channel FET above threshold (VGS > VTN):
+
+
VGS
VDS s   p
gate
source drain
x
p
y 0 y L  tox 0 xd
Na x
VDS  0  s y 
n  VSB VDS  0
n  VDB
Now assume VDS > 0:  n
 p  n
+
+ VDS y
VGS
gate 0 L
source drain
n  VSB  s y  n  VDS
VDS  0
y 0 y L  n
Na x  p
VDS  0 y
p
0 L
Electron Potential Energy in FETs above Threshold

Consider the electron potential energy in a long channel FET above
threshold (VGS > VTN):
+
+
VGS
VDS  q s  y 
gate VDS  0
source drain
y 0 y L y
Na x
 qn q p  q n
0 L
VDS  0
Now assume VDS > 0:

 q s  y 
+
+ VDS
VDS  0
VGS
gate
source drain
y
 q n q p
y 0 y L
Na x
0  q n  VDS 
L
VDS  0 Large current flow because there are lots
of electrons in the inversion channel
9
Punch-Through in FETs (A Short Channel Effect)
Consider the electron potential energy in a long channel FET below threshold (VGS < VTN):
+  q s  y 
+ VDS
VGS VDS  0
gate
source drain
y
y 0 y L  qn
0 Potential L  q n  VDS 
VDS  0 barrier for
electrons
Now make the channel length shorter (VGS < VTN):
+  q s  y 
+ VDS
VGS
gate VDS  0
source drain
y y
y 0 y L  qn
0 L  q n  VDS 
VDS  0 Potential barrier for
electrons is still there

Channel is short (VGS < VTN):
 q s  y 
+
VGS
+ VDS VDS  0
gate
source drain y
 q n
y 0 y L 0 L  q n  VDS 
VDS  0 Potential barrier for electrons
Now make the channel even shorter (VGS < VTN):

 q s  y 
+
VGS
+ VDS VDS  0
gate
source drain y
 qn
y 0y L 0 L  q n  VDS 
Potential barrier for electrons is significantly

VDS  0 reduced when the source-drain depletion
regions overlap (this is “punch-through”)
10
+ Consider a nano-scale FET with VGS < VTN but VDS >0
VGS<VTN VDS>0
● When the depletion regions of the source and drain
+ gate
come close, the barrier to electron flow from the source
to the drain reduces significantly
source drain ● This results in leakage current even when VGS < VTN!!
● The problem is particularly bad when VDS is large
● The leakage current contributes to subthreshold
conduction
y 0 y L ● Therefore, it is difficult to completely turn-off nano-
Na scale FETs!
Log10( ID )
+ Weak inversion
VGS<VTN VDS>0 0 Strong inversion
+ gate Very short L

-1
source drain Long L
-2
q
-3 VGS VTN 
y 0 y L I D ~ e mKT
Na
VTN VGS
Mitigating Short Channel Effects: The Double-Gate FET

+ To understand why double-gate FET mitigates the short
+ VDS channel effects one needs to start from the 2D Poisson
VGS
tsi gate
tox equation:
source drain  2  x , y   2  x , y  qN a
gate  
VGS
y x 2 y 2 s
y 0 y L x
If the curvature of the potential in the semiconductor in the x-
direction is reduced, the curvature in the y-direction will
increase (to satisfy Poisson equation)
Fully depleted Si layer
Helps control DIBL and punch-through in nano-scale FETs
 q s  y   q s  y 
VDS  0 VDS  0
y y
 qn  q n
0 L  q n  VDS  0 L  q n  VDS 
Single-Gate Device Double-Gate Device
11
Mitigating Short Channel Effects: The Double-Gate FET
+ To understand why double-gate FET mitigates the short
+ VDS channel effects one needs to start from the 2D Poisson
VGS
tsi gate
tox equation:
source drain  2  x , y   2  x , y  qN a
gate  
VGS
y x 2 y 2 s
y 0 y L x
The main result from 2D Poisson equation:

Fully depleted Si layer
In order to reduce the short channel effects, minimize the
value of the length parameter:
s
t t
 ox ox Si
This implies:
● Choose a high-dielectric-constant gate dielectric (in place of SiO2) (e.g. use HfO2)
● Keep the thickness tox of the gate dielectric layer as small as possible
● Keep the thickness tSi of the Si layer as small as possible
The Traditional Planar Single-Gate FET
 ox   o
High- dielectric
instead of SiO2
12
The Fin-FET: Gate All-Around 3D Device Geometry
High- dielectric
instead of SiO2
Technology of choice for the sub-30 nm FETs
Smaller footprint
Better control over short channel effects
The FinFET
Side View
13
The Multiple-Fin FinFET
High
dielectric instead
of SiO2
Can use any number

of fins per FET for
increased current
drive!
Technology of choice for the sub-30 nm FETs

Superior current drive
Smaller footprint
Better control over short channel effects
The Multiple-Fin FinFETs
(Intel) (Infineon)
Gate 1
Two FETs in series

Gate 2
One FET
14
Multiple-Fin FinFET Logic Gates
Ground
Ground
VOUT VOUT
B
Intel C
A
VOUT
VDD
VOUT
(IMEC: Three input NOR
gate using Fin-FETs
Technology Trends
Proceedings of the IEEE, 96, 212 (2008)
Technology miniaturization allows for higher integration density and faster

switching speeds, and the power-delay product for a single device continues
to decrease.
15
Making CMOS Analog Circuits go Terahertz (100-1000 GHz)
Prof. Afshari’s group at Cornell
A ~281 GHz CMOS RF imaging chip
16
CHAP #06 - PART 2
New Materials and New Physics at the Nano-Scale
In this lecture you will learn:
• New physics at the nano-scale

• Quantum physics and the FETs
• New materials for electronics and optoelectronics
What is Nano-Technology?
1
Quantum Physics and Matter
Electron confined in Large box:
mv 2 P 2
Energy  
2 2m
L
Quantum Physics:
Electron behaves like a wave
And the wavelength is related to its momentum P as:
2 Plank’s constant:
P
   1.05458  10  34 Joule  Sec
Electron confined in small box:

Electron wavelength
must fit in the box

Ln
2
n  1,2,3
L L
Quantum Physics and Matter

Electron confined in small box: Electron wavelength must fit
in the box:

Ln
2
2L
 
n
L L n  1,2,3
2
Momentum  P  

P 2  2  2 
2
Energy    
2m 2m   

 2  n   2
 
2m  L 
The momentum and the energy of the electron confined in a small box are “quantized”
– they can only have discrete values
2
Mass and Dynamics of Electrons in Solids
Atom
Electron
Mass is a measure of
Electron inertia – that
Electron motion and determines the
dynamics inside the acceleration resulting
crystal are determined by from an applied force
the interaction between
the electron wave and the
crystal atoms A crystal
Outside the crystal, in free-space, electron has a mass mo
mo  9.1 10 31 kg K.E 

1
2
1
mov 2  mo v x2  v y2  v z2
2
 
Inside the crystal, electrons can have different masses in different directions that
are very different from the electron mass in free-space:
K.E 
1
2

m x v x2  m y v y2  m z v z2 
Electrons can “appear” heavier when moving in some directions and “lighter” when
moving in other directions as a result of the interaction of the electron wave with the
atoms
Mass of Electrons in Silicon
Silicon atom
Electron
A silicon crystal
There are 6 different kinds of electrons in silicon:

Small mass is
1,2:
1

K.E  m v x2  mt v y2  mt v z2
2
 better for higher
mobility:
3,4: K.E 
1
2

mt v x2  m v y2  mt v z2  m   0.92 mo
mt  0.19 mo
n 
q n
mn
5,6: K.E 
1
2

mt v x2  mt v y2  mv z2 
3
Mass of Holes in Silicon
Silicon atom
Hole
A silicon crystal
Inside the silicon crystal, holes can also have different masses
Small mass is
There are two different kinds of holes in silicon: better for higher
mobility:
1: K.E 
1
2

m h v x2  v y2  v z2  m h  0.16 mo p 
q p
mp
mhh  0.49 mo
2: 1

K.E  mhh v x2  v y2  v z2
2

Electrons in FET Inversion Layers: Classical Picture

Electrostatic potential:   x 
M  VGB
The classical picture of electrons
in an inversion layer s   p
x
p
 tox 0 xd
Electron potential
energy:  q  x 
+
 q p VGS
Inversion
x layer gate
 tox 0 xd source drain
q p Inversion layer y 0 y L
x
electrons
 q M  VGB 
4
Electrons in FET Inversion Layers: Total Potential Energy
Electron potential
energy:  q  x 
~3.1 eV
Potential
energy
from the
atoms
+  q p
x
x  tox 0 xd
Electrostatic
 tox 0 xd potential
q p
=
Electron potential energy
energy:  qVatoms  x 
 q M  VGB 
 tox 0 xd
Total electron potential

energy:  q Vatoms  x     x 
Electrons in FET Inversion Layers: Quantum Picture

Total electron potential energy:  q Vatoms  x     x 
T=~5 nm
Classical picture
Quantum picture
n=1
x x
n=2
 tox 0 xd  tox 0 xd
Electron waves confined in

the x-direction
But free to propagate in the
y-direction
Inversion layer is an
electron “waveguide”
5
T = ~5 nm
Quantum picture
n=1
x
n=2
 tox 0 xd
Electron waves confined in the x-

direction but free to propagate in
the y-direction
K.E 
1
2
 P2
m x v x2  m y v y2  m z v z2  x  Py2 P2
 z
2m x 2m y 2m z
x 2 Momentum in the x-direction
T n Momentum  Px   can have only discrete
2 x
2T (“quantized”) values
 x 
n
K.E 
 2 
2 Py2 P2
 z
n=1 energy state contains
n   majority of the electrons
n  1,2,3 2m x  T  2m y 2m z (but not all)
Quantum picture
 tox 0 xd
IDEA:
1,2: K.E 
1
2

mv x2  mt v y2  mt v z2  What if one could only have
electrons of kinds 1,2 and 5,6
and eliminate electrons of kind
3,4: K.E 
1
2

mt v x2  mv y2  mt v z2  3,4?
Then the mass of the electrons in
the direction of current transport
5,6: K.E 
1
2

mt v x2  mt v y2  mv z2  (y-direction) would be only the
lighter mass and the electron
mobility would be very high!!
This elimination automatically happens because of quantization!!

6
T
Quantum picture
 tox 0 xd
The lowest quantized energy levels
 
1 correspond to the heaviest mass mℓ
1,2: K.E  mv x2  mt v y2  mt v z2 in the x-direction (quantization
2 direction):
3,4: K.E 
1

mt v x2  mv y2  mt v z2  K.E 
 2    2  Py2

Pz2
2  
2m  T  2mt 2mt
5,6: 1

K.E  mt v x2  mt v y2  mv z2
2

The higher energy levels are much
less occupied by electrons at room
temperature
Mobility Engineering via Strain in FETs

NFET PFET
Normal
silicon
crystal
SiGe 45 nm SiGe
45 nm
Intel Intel
Channel under uniaxial Channel under uniaxial Uniaxial
tensile strain tensile strain tensile
strained
Strain completely eliminates the unwanted electrons
silicon
crystal
Strain also reduces the electron and hole masses
1,2: K.E 
1
2

mv x2  mt v y2  mt v z2  Strain changes the distance
between the atoms and,
3,4: 1
2

K.E  mt v x2  m v y2  mt v z2  thereby, modifies the
electronic energy levels in
the crystal
5,6: K.E 
1
2

mt v x2  mt v y2  mv z2 
7
Quantum Ballistic Transport in Electron Waveguides
+ The electron drift current density is:
VDS
+
J ndrift  qn n E
VGS
Inversion
layer gate Where:
q n Mean time between
n  electron collisions
source drain mn
Mean distance between electron collisions (also
y 0 y L
x called “mean free path”) is:
n  v n  n
Mean velocity of
~20-30 nm in silicon
electrons
What is the device is so short that the electron can travel through the entire length of
+
the device without a collision?  n   or L  n VDS
+
VGS
The classical expression for current via drift
does not work: Electron wave in the
J ndrift  qn n E
Inversion layer gate
source drain
Concepts like mobility and conductivity don’t make
sense anymore
Electron transport is described as a the propagation y 0 y L
x
of a wave from the source end to the drain end
Flash Memory: A Single FET based Non-Volatile Memory

Floating +
Electron quantum VDS Floating
Si gate +
tunneling VGS Si gate
Inversion
layer gate
Inversion layer
electrons
x source drain
0 xd y 0 y L
Floating x
Si gate
Low VTN state
 tox
x
0 xd High VTN state
Storage of electrons inside the floating gate

increases the device threshold voltage which
can be sensed
 tox
8
Future of Electronics and Optoelectronics
Flexible, stretchable, Solid state lighting Energy harvesting
transparent electronics
Solar cells
Water-splittng
photocatalysis
Portable Health Monitoring
Security and healthcare Optics, sonic, Sensor chip in a
Energy Storage imaging THz, chemical contact lens
mm-wave
Supercapacitor
3D intravenous
cell imager
New materials and devices are needed!

Neural Interfacing
New Materials Looking for Applications

2D material
Graphene, carbon allotropes
heterostructures
Quantum
Dots
Plasmonic Metamaterials Multiferroics

Perovskite solar
Spintronics
absorbers
9
Graphene: A 2D Semiconductor
Pencil Leads
Graphite
Graphene is a two dimensional

single atomic layer of Carbon
atoms arranged in a
honeycomb lattice
Graphene Atomic Membranes

A graphene membrane
A flexible transparent electronic

chip made from graphene
A flexible transparent
touch-screen for
displays made of
graphene (Samsung) Grpahene atoms
(STEM)
10
Massive and Massless Particles
Energy of a massive particle (e.g. electron):
1 P2 Velocity  v
Energy  mv 2 
2 2m
Energy of a massless particle (e.g. photon):
Energy  Pc c = speed of light = 3x108 m/s
Massive and Massless Particles
Electrons in graphene behave like light (or photons):
Velocity  v
Energy  Pv v = speed of electrons = 106 m/s
Electrons move faster in graphene than in any other known semiconductor at

room temperature (~100 times faster than in Silicon)!!
(2010 Nobel Prize in Physics for Graphene)
11
Folded Graphene: Carbon Nanotubes
Nanotube: A carbon nanotube is a folded sheet of graphene:
A long carbon nanotube is a one-dimensional (1D) conductor (or semi-conductor)
Carbon Nanotubes: A 1D Material
Carbon Nanotube FET (IBM)
Carbon Nanotube LEDs (IBM)
12
Semiconductor Plasmon Lasers: The Nanopatch Laser
Circular Nanopatch Laser Circular Nanopatch Laser: Radiation Pattern
(Size of a FET)
R=100 nm SNLs are optical
z versions of microwave
 patch antennas
p y Lasers on chip are

i gain becoming much
n
smaller than the size
of a photon!!
Substrate
(Cornell, UCB)
x
Surface-normal emission
Ex z
Manolatou, Rana (2009)

Tailoring and Designing Complex 3D Materials and Devices

with 2D Materials
Stacks of 2D materials can be
used to tailor 3D materials with
Light
desired properties….!!
Exciton
Graphene e
h
WS2
A “hydrogen atom” of an
electron and a hole
Graphene
e
h
ph
A solar cell made using 2D material stacks
Polariton
13
AMOLED Displays (Samsung Galaxy)
Exciton Photon
e 
h
A “hydrogen atom” of an electron and a hole
Visions of the Future (From Samsung)
https://youtu.be/RTp8kEuZ1eY
14
The Last Slide
ECE Courses after 3150 to Match your Interests

Sem Devices, Nanostructures, Analog Circuits, Digital Circuits,
Nano-Scale Phys, Nano Materials Analog VLSI Digital VLSI
3150 3150 3150
ECE: 4060 or
4570 4530 4740
PHYS: 3316
Si Dev Quantum Analog VLSI Digital VLSI
Phys
4070 4360
Sem and Micro

Nano Str Fabrication
Phys
15

Chap - 06 - Nano-Scaled Fet

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Chap - 06 - Nano-Scaled Fet

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CHAP #06 - PART 1

In this lecture you will learn:

ECE 315 – Spring 2005 – Farhan Rana – Cornell University

Why Nano-Scale FETs?

● Smaller FETs occupy smaller areas

This means more FETs can be put in a chip

Quantum transport, wave mechanics, energy level quantization, mobility

How does one scale down the size of a FET?

ECE 315 – Spring 2005 – Farhan Rana – Cornell University

TEM of a 100 nm gate length MOS transistor

The Poisson Equation and the FET

The charge density is approximately that associated

TEM of a 35 nm gate length FET

ECE 315 – Spring 2005 – Farhan Rana – Cornell University

   x ' , y '     x ' , y '  qN a  x ' , y ' 2

ECE 315 – Spring 2005 – Farhan Rana – Cornell University

N a'  x ' , y '    N a  x ' , y '  gate

 2 '  x ' , y '  2 '  x ' , y ' qN a'  x ' , y '   2 

then the electric field in the scaled device would be the

3) We kept the device electric field the same (so no device

Problems with the device scaling described above: x'

ECE 315 – Spring 2005 – Farhan Rana – Cornell University

The Nano-Scale FET: 2D Poisson Equation

Difficult to turn small

~ 1.0 m Channel length (L)

Current Saturation Via Velocity Saturation

And the FET current is (handout 9):

 n Cox VGS  VTN  DS  Vsat  E sat L

ECE 315 – Spring 2005 – Farhan Rana – Cornell University

ID Without velocity I D SAT

With velocity I D SAT

VDS SAT  ? VDS SAT  VGS  VTN VDS

Current Saturation Via Velocity Saturation

ECE 315 – Spring 2005 – Farhan Rana – Cornell University

A long channel FET (current saturation via channel pinch-off):

I D SAT  W v dn  sat Cox VGS  VTN 

Electrostatic Potential in FETs below Threshold

Drain Induced Barrier Lowering (DIBL) in Short FETs

VDS  0  q n  VDS 

ECE 315 – Spring 2005 – Farhan Rana – Cornell University

Electron Potential Energy in FETs above Threshold

Now assume VDS > 0:

ECE 315 – Spring 2005 – Farhan Rana – Cornell University

Punch-Through in FETs (A Short Channel Effect)

VDS  0 Potential barrier for electrons

Now make the channel even shorter (VGS < VTN):

Potential barrier for electrons is significantly

+ gate Very short L

Mitigating Short Channel Effects: The Double-Gate FET

Single-Gate Device Double-Gate Device

ECE 315 – Spring 2005 – Farhan Rana – Cornell University

The main result from 2D Poisson equation:

● Keep the thickness tSi of the Si layer as small as possible

ECE 315 – Spring 2005 – Farhan Rana – Cornell University

The Traditional Planar Single-Gate FET

ECE 315 – Spring 2005 – Farhan Rana – Cornell University

Technology of choice for the sub-30 nm FETs

ECE 315 – Spring 2005 – Farhan Rana – Cornell University

ECE 315 – Spring 2005 – Farhan Rana – Cornell University

Can use any number

Technology of choice for the sub-30 nm FETs

The Multiple-Fin FinFETs