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1 1

Compal Confidential
2 2

STORM3 M/B Schematic


LA-F421P
Vinafix.com
Rev: 1.0_ B
2017.10.23
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
COVER PAGE
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 1 of 73
A B C D E
5 4 3 2 1

STORM 3 Block-Diagram
Two Channel (A) DDR4 memory down 2400MHz
P.22

eDP Conn. 4 Lane eDP


P.26
(B) DDR4 memory down 2400MHz
P.24
D D

HDA Maximum 16GB


2-Ch. SPK Conn.P.39
DMIC Audio Codec USB2.0 USB 3.0 Conn
P.35 USB3.0 AOU5 P.31
Combo Jack Conn.
Sub/B USB 3.0 Conn.
USB2.0
4 Lane DDI1 P.31
4 Lane TBT Intel Intel Kabylake
Type C Conn. Alpine Ridge PCIEx2 RU/U-Processor
P.50 USB 2.0 USB 2.0
PD P.47
P.4
P.51
C
I2C C

DDI2 Sub board


HDMI Conn. 4 Lane Mux ALS
P.28
P.29
PCI-E
WLAN & BT USB2.0 Accelerometer & Gyro
M.2 Conn. PCIEx1(WLAN)
USB 2.0(BT)
SPI Vinafix.com
P.32
LPC SPI eCompass
BIOS ROM FPR P.34
WWAN 16M P.21 I2C TPM P.45
M.2 Conn. PCIEx1
Touch Panel P.26
B

USB 2.0 Accelerometer(1) B

P.32
EC P.41
P.53 Smart Card P.34
PCIEx1
Mini RJ45P.52 Intel LANP.52
P.26 SMBUS
Int.KBD NFC
P.42 DMIC Camera & DMIC P.43

M.2 Conn. SATA/PCIEx1


SSD [M.2 2280/2242]
Click Pad
PCIEx3 P.43
P.30
Micro SD
Card Reader PCIEx1 Track Point
P.42
P.27

Card Reader DMIC IR Camera


Slot Conn. P.33 P.33
A
LID A

Accelerometer(2) Sub/B Option


P.41

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BLOCK DIAGRAM
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 2 of 73
5 4 3 2 1
5 4 3 2 1

[Storm3 PWR Sequence_KBL-RU_DDR4_Non-Deep Sx]

[AC Mode] [DC Mode]


D
BAT-PWR12 D

AC_IN
AC_PRESENT

VINT12
VINT12
VCC3SW
VCC3SW
-PWRSWITCH
EN_3V moniter AC_IN (51_ON)
SUS_ON2 T=10ms Moniter ON/OFFBTN#
VCC3M/VCC5M
VCC3M/VCC5M
VCC1R0_SUS
VCC1R0_SUS
SUS_ON1
SUS_ON1
VCC1R8_PRIM

-PWRSWITCH
Moniter ON/OFFBTN# rising edge VCC1R8_PRIM
-PWRSW_EC_R 20ms
-RSMRST T=10ms Moniter ON/OFFBTN# and EN_3/5V both of risgin edge
-RSMRST
-SUSWARN
-SUSWARN
-PWRSW_EC_R 20ms T=110ms Moniter ON/OFFBTN# rising edge
AC_PRESENT

C C

-PCH_SLP_S5 Montier PBTN_OUT# falling edge.

-PCH_SLP_S4

-PCH_SLP_S3

A_ON

+VCC2R5A

+VCC1R2A

DDR_PG_CTRL immediately, After PM_SLP_S4# falling edge

+VCC0R6B

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B_ON T=20ms After PM_SLP_S3# moniter SYSON rising edge. immediately, After PM_SLP_S3# falling edge

VCC5B

VCC3B

B B

EC_VCCST_PG T=20ms After SUSP# risign edge immediately, After SUSP# falling edge

VR_ON immediately, VCCST_PG_PWR & VCCST_PG_EC risign edge

VCCCPUCORE Vboot

VGATE

PCH_PWROK T=10ms After VCCST_PG_EC rising edge immediately, After SUSP# falling edge

BPWRG T=99ms After VCCST_PG_EC assertion immediately, After SUSP# falling edge

-PLTRST

After CPUPWRGD/PCH_PWRGD/SYS_PWROK assertion

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Title
Issued Date 2016/03/21 Deciphered Date 2017/03/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 3 of 73
5 4 3 2 1
5 4 3 2 1

D D

VCCCPUIO VCC3B

2
R5 R9357
24.9_0201_1% 2.2K_0201_5%

1
U58A @ SKL-U

DDIP1_0N E55 C47 EDP_TXN0


[47] DDIP1_0N DDI1_TXN[0] EDP_TXN[0] EDP_TXN0 [26]
DDIP1_0P F55 C46 EDP_TXP0
[47] DDIP1_0P DDI1_TXP[0] EDP_TXP[0] EDP_TXP0 [26]
DDIP1_1N E58 D46 EDP_TXN1
[47] DDIP1_1N DDI1_TXN[1] EDP_TXN[1] EDP_TXN1 [26]
DDIP1_1P F58 C45 EDP_TXP1
[47] DDIP1_1P DDI1_TXP[1] EDP_TXP[1] EDP_TXP1 [26]
C DDIP1_2N F53 A45 EDP_TXN2 C
[47] DDIP1_2N DDI1_TXN[2] EDP_TXN[2] EDP_TXN2 [26]
DDIP1_2P G53 B45 EDP_TXP2
[47] DDIP1_2P DDI1_TXP[2] EDP_TXP[2] EDP_TXP2 [26]
DDIP1_3N F56 A47 EDP_TXN3
[47] DDIP1_3N DDI1_TXN[3] EDP_TXN[3] EDP_TXN3 [26]
DDIP1_3P G56 B47 EDP_TXP3
[47] DDIP1_3P DDI1_TXP[3] EDP_TXP[3] EDP_TXP3 [26]
DDIP2_0N C50 E45 EDP_AUXN
[28] DDIP2_0N DDI2_TXN[0] DDI EDP_AUXN EDP_AUXN [26]
DDIP2_0P D50 EDP F45 EDP_AUXP
[28] DDIP2_0P DDI2_TXP[0] EDP_AUXP EDP_AUXP [26]
DDIP2_1N C52
[28] DDIP2_1N DDI2_TXN[1]
DDIP2_1P D52 B52
[28] DDIP2_1P DDI2_TXP[1] EDP_DISP_UTIL
DDIP2_2N A50
[28] DDIP2_2N DDI2_TXN[2]
DDIP2_2P B50 G50 DDIP1_AUXN
[28] DDIP2_2P DDI2_TXP[2] DDI1_AUXN DDIP1_AUXN [47]
DDIP2_3N D51 F50 DDIP1_AUXP
[28] DDIP2_3N DDI2_TXN[3] DDI1_AUXP DDIP1_AUXP [47]
DDIP2_3P C51 E48
[28] DDIP2_3P DDI2_TXP[3] DDI2_AUXN F48
DISPLAY SIDEBANDS
DDI2_AUXP
DDI3_AUXN
G46
F46
FVT_C_EC010
L13 DDI3_AUXP
TABLE : Functional Strap L12 GPP_E18/DDPB_CTRLCLK L9 DDIP1_HPD DDIP1_HPD [47]
GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0

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L7 DDIP2_HPD DDIP2_HPD [28]
DDIP2_CTRLCLK N7 GPP_E14/DDPC_HPD1 L6
[28] DDIP2_CTRLCLK GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2
DDIP2_CTRLDATA N8 N9
[28] DDIP2_CTRLDATA GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10
DDPB_CTRLDATA N11 GPP_E17/EDP_HPD EDP_HPD [26]
N12 GPP_E22/DDPD_CTRLCLK R12
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN VGA_BLON [53]
R11
HIGH Port B is detected. EDP_COMP E52
EDP_RCOMP
EDP_BKLTCTL
EDP_VDDEN
U13
PANEL_BKLT_CTRL [26]
PANEL_POWER_ON [26]
1 OF 20
KBL-RU_BGA1356
LOW Port B is not detected.

2
R433 R138 R8
100K_0201_5% 100K_0201_5% 100K_0201_5%

1
DDPC_CTRLDATA

B
HIGH Port C is detected. B

LOW Port C is not detected.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(1/16) : DDI/EDP
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 4 of 73
5 4 3 2 1
5 4 3 2 1

VCC2R5A / 0.8A
Storm3 Power tree VCC5M / 7A
RT8061AZQW
Richtek

RT8061AZQW VCC1R8_SUS / 0.8A


TPS51285B-1RUKR
TI Richtek
VCC3M / 7A

D D

VCC1R0_SUS_P / 7.12A
TPS51362RVER
TI
Converter
PU1
VINT12
VINT20 Charger (BQ25700)
VCC1R2A / 6.4A
RT8207PGQW
Richtek VCC0R6B / 0.8A

VCCCPUCORE
NCP81218MNTXG U22: 21A
+ U42: 42A
NCP302045MNTWG
Dr-MOS
On-semi

NCP81218MNTXG
+ VCCGFXCORE_I / 18A
NCP302045MNTWG
Dr-MOS
On-semi

C
NCP81218MNTXG C

+ VCCSA / 4A
NCP302035MNTWG
Dr-MOS
On-semi

U143 VCCST
VCC5M PU151 VCC2R5A
VCC1R2A

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PU118

VINT12 PU145
VCC1R8_PRIM
U53
USB_PWR_S2
U88
USB_PWR_S1
VCC5M_BUTTON
PU41 R9570

J9237
VCC5M_PD
PU154 VCC3_SUS
F31 VCC3M_PEN
B
F34
VCC3M_SENS_CN B

F39
VCC3M_IR
VCC3M VCC3M_KEY_CONN
F25

R9309
VCC3M_BUTTON
R2485
VCC3M_PCH
R9406
VCC3_TBT
RT9369
VCC3M_PD
U19
VCC3WLAN U110 VCC5B_HDMI
U153
VCC3LAN F40 VCC5B_IR
F35
VCC5B_CN
F23
VCC5_TP
VCC5B
F4 VCC5B_F4
F15 FUSEVCC5B
VCC5B_CODEC
U55 R2031

R2015
VCC5BA

VCC3B R2463 VCC3B_PS8337B


J9240 VCC3WAN
A A

F24
VCC3B_TOUCH_CN
F17
FUSEVCC3B
F8 FUSEVCC3FP
F41 VCC3B_IR
R2029
VCC3B_CODEC
U9
VCC3P
R2472 VCC3B_RTS5236S
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/06/09 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power MAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F483P
Date: Monday, October 23, 2017 Sheet 4 of 44
5 4 3 2 1
5 4 3 2 1

[6,22] DDR_A_D[63:0]

[6,24] DDR_B_D[63:0]

D D

TABLE

Pin Interleave Non-Interleave

U58B @ SKL-U
AL71 DDR0_DQ[0] DDR0_DQ[0]
AL68 DDR0_DQ[1] DDR0_DQ[1] AU53 -DDR_A_CLK0
DDR0_CKN[0] -DDR_A_CLK0 [22,23]
AN68 DDR0_DQ[2] DDR0_DQ[2] DDR_A_D0 AL71
DDR0_DQ[0] DDR0_CKP[0]
AT53 DDR_A_CLK0
DDR_A_CLK0 [22,23]
AN69 DDR0_DQ[3] DDR0_DQ[3] DDR_A_D1 AL68 AU55
DDR_A_D2 AN68 DDR0_DQ[1] DDR0_CKN[1] AT55
AL70 DDR0_DQ[4] DDR0_DQ[4] DDR_A_D3 AN69 DDR0_DQ[2] DDR0_CKP[1]
AL69 DDR0_DQ[5] DDR0_DQ[5] DDR_A_D4 AL70 DDR0_DQ[3] BA56 DDR_A_CKE0
DDR0_DQ[4] DDR0_CKE[0] DDR_A_CKE0 [22,23]
AN70 DDR0_DQ[6] DDR0_DQ[6] DDR_A_D5 AL69
DDR0_DQ[5] DDR0_CKE[1]
BB56
DDR_A_D6 AN70 AW56
AN71 DDR0_DQ[7] DDR0_DQ[7] DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56
AR70 DDR0_DQ[8] DDR0_DQ[8] DDR_A_D8 AR70 DDR0_DQ[7] DDR0_CKE[3]
DDR0_DQ[8]
Block 0 AR68 DDR0_DQ[9] DDR0_DQ[9] DDR_A_D9 AR68
DDR0_DQ[9] DDR0_CS#[0]
AU45 -DDR_A_CS0
-DDR_A_CS0 [22,23]
DDR_A_D10 AU71 AU43
AU71 DDR0_DQ[10] DDR0_DQ[10] DDR_A_D11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45 DDR_A_ODT0
AU68 DDR0_DQ[11] DDR0_DQ[11] DDR0_DQ[11] DDR0_ODT[0] DDR_A_ODT0 [22,23]
DDR_A_D12 AR71 AT43
AR71 DDR0_DQ[12] DDR0_DQ[12] DDR_A_D13 AR69 DDR0_DQ[12] DDR0_ODT[1]
DDR_A_D14 AU70 DDR0_DQ[13] BA51 DDR_A_MA5
AR69 DDR0_DQ[13] DDR0_DQ[13] DDR_A_D15 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR_A_MA9
TABLE
AU69 BB54
AU70 DDR0_DQ[14] DDR0_DQ[14] DDR_A_D32 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 DDR_A_MA6
AU69 DDR0_DQ[15] DDR0_DQ[15] DDR_A_D33 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_MA8
DDR_A_D34 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDR_A_MA7
Pin DDR3L LPDDR3 DDR4
DDR_A_D35 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_BG0
DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_BG0 [22,23]
DDR_A_D36 BA65 AW54 DDR_A_MA12
DDR_A_D37 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11
BA51 DDR0_MA[5] DDR0_CAA[0] DDR0_MA[5]
DDR_A_D38 BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 -DDR_A_ACT BB54 DDR0_MA[9] DDR0_CAA[1] DDR0_MA[9]
DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# -DDR_A_ACT [22,23]
DDR_A_D39 BB63
DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
AY54 DDR_A_BG1
DDR_A_BG1 [22]
BA52 DDR0_MA[6] DDR0_CAA[2] DDR0_MA[6]
DDR_A_D40 BA61 AY52 DDR0_MA[8] DDR0_CAA[3] DDR0_MA[8]
DDR_A_D41 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 DDR_A_MA13
BB65 DDR0_DQ[16] DDR0_DQ[32] DDR_A_D42 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_MA15 AW52 DDR0_MA[7] DDR0_CAA[4] DDR0_MA[7]
AW65 DDR0_DQ[17] DDR0_DQ[33] DDR_A_D43 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_MA14 AY55 DDR0_BA[2] DDR0_CAA[5] DDR0_BG[0]
AW63 DDR0_DQ[18] DDR0_DQ[34] DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
C DDR_A_D44 BB61
DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
AU50 DDR_A_MA16 AW54 DDR0_MA[12] DDR0_CAA[6] DDR0_MA[12] C
AY63 DDR0_DQ[19] DDR0_DQ[35] DDR_A_D45 AY61 AU52 DDR_A_BA0
DDR_A_D46 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR_A_MA2
DDR_A_BA0 [22,23] BA54 DDR0_MA[11] DDR0_CAA[7] DDR0_MA[11]
BA65 DDR0_DQ[20] DDR0_DQ[36] DDR_A_D47 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDR_A_BA1 BA55 DDR0_MA[15] DDR0_CAA[8] DDR0_ACT#
AY65 DDR0_DQ[21] DDR0_DQ[37] DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR_A_BA1 [22,23]
DDR_B_D0 AY39
DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
AT50 DDR_A_MA10 AY54 DDR0_MA[14] DDR0_CAA[9] DDR0_BG[1]
BA63 DDR0_DQ[22] DDR0_DQ[38] DDR_B_D1 AW39
DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
BB50 DDR_A_MA1
DDR_B_D2 AY37 AY50 DDR_A_MA0
BB63 DDR0_DQ[23] DDR0_DQ[39] DDR_B_D3 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDR_A_MA3
Block 2 BA61 DDR0_DQ[24] DDR0_DQ[40] DDR_B_D4 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDR_A_MA4
DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_A_MA[16:0] [22,23]
AW61 DDR0_DQ[25] DDR0_DQ[41] DDR_B_D5 BA39
DDR0_DQ[37]/DDR1_DQ[5]
DDR_B_D6 BA37 AM70 -DDR_A_DQS0
BB59 DDR0_DQ[26] DDR0_DQ[42] DDR_B_D7 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDR_A_DQS0
-DDR_A_DQS0 [22] AU46 DDR0_MA[13] DDR0_CAB[0] DDR0_MA[13]
AW59 DDR0_DQ[27] DDR0_DQ[43] DDR_B_D8 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 -DDR_A_DQS1
DDR_A_DQS0 [22] AU48 DDR0_CAS# DDR0_CAB[1] DDR0_MA[15]
DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] -DDR_A_DQS1 [22]
BB61 DDR0_DQ[28] DDR0_DQ[44] DDR_B_D9 AW35
DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1]
AT70 DDR_A_DQS1
DDR_A_DQS1 [22]
AT46 DDR0_WE# DDR0_CAB[2] DDR0_MA[14]
AY61 DDR0_DQ[29] DDR0_DQ[45] DDR_B_D10 AY33 BA64 -DDR_A_DQS4 AU50 DDR0_RAS# DDR0_CAB[3] DDR0_MA[16]
DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] -DDR_A_DQS4 [22]
DDR_B_D11 AW33 AY64 DDR_A_DQS4
BA59 DDR0_DQ[30] DDR0_DQ[46] DDR_B_D12 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 -DDR_A_DQS5
DDR_A_DQS4 [22] AU52 DDR0_BA[0] DDR0_CAB[4] DDR0_BA[0]
AY59 DDR0_DQ[31] DDR0_DQ[47] DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] -DDR_A_DQS5 [22] AY51 DDR0_MA[2] DDR0_CAB[5] DDR0_MA[2]
DDR_B_D13 BA35 BA60 DDR_A_DQS5
DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] DDR_A_DQS5 [22]

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DDR_B_D14 BA33
DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0]
BA38 -DDR_B_DQS0
-DDR_B_DQS0 [24] AT48 DDR0_BA[1] DDR0_CAB[6] DDR0_BA[1]
DDR_B_D15 BB33 AY38 DDR_B_DQS0
DDR_B_D32 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 -DDR_B_DQS1
DDR_B_DQS0 [24] AT50 DDR0_MA[10] DDR0_CAB[7] DDR0_MA[10]
DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] -DDR_B_DQS1 [24] BB50 DDR0_MA[1] DDR0_CAB[8] DDR0_MA[1]
DDR_B_D33 AW31 BA34 DDR_B_DQS1
DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] DDR_B_DQS1 [24]
DDR_B_D34 AY29
DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4]
BA30 -DDR_B_DQS4
-DDR_B_DQS4 [24] AY50 DDR0_MA[0] DDR0_CAB[9] DDR0_MA[0]
DDR_B_D35 AW29 AY30 DDR_B_DQS4
DDR_B_D36 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 -DDR_B_DQS5
DDR_B_DQS4 [24] BA50 DDR0_MA[3] Not Used DDR0_MA[3]
DDR_B_D37 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_B_DQS5
-DDR_B_DQS5 [24] BB52 DDR0_MA[4] Not Used DDR0_MA[4]
AY39 DDR0_DQ[32] DDR1_DQ[0] DDR_B_D38 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_DQS5 [24]
AW39 DDR0_DQ[33] DDR1_DQ[1] DDR_B_D39 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50 -DDR_A_ALERT
DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# -DDR_A_ALERT [22,23]
AY37 DDR0_DQ[34] DDR1_DQ[2] DDR_B_D40 AY27
DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR
AT52 DDR_A_PAR
DDR_A_PAR [22,23]
AW37 DDR0_DQ[35] DDR1_DQ[3] DDR_B_D41 AW27
DDR_B_D42 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67 +0.6V_A_VREFDQ
BB39 DDR0_DQ[36] DDR1_DQ[4] DDR_B_D43 AW25 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA AY68
+0.6V_A_VREFDQ [23]
BA39 DDR0_DQ[37] DDR1_DQ[5] DDR_B_D44 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR CH - A
DDR0_VREF_DQ BA67 +0.6V_B_VREFDQ
DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ +0.6V_B_VREFDQ [25]
BA37 DDR0_DQ[38] DDR1_DQ[6] DDR_B_D45 BA27
DDR0_DQ[61]/DDR1_DQ[45]
DDR_B_D46 BA25 AW67 DDR_PG_CTRL
BB37 DDR0_DQ[39] DDR1_DQ[7] DDR_B_D47 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL VCC3M
AY35 DDR0_DQ[40] DDR1_DQ[8] DDR0_DQ[63]/DDR1_DQ[47]
LOGIC
Block 4 AW35 DDR0_DQ[41] DDR1_DQ[9] 2 OF 20
AY33 DDR0_DQ[42] DDR1_DQ[10] KBL-RU_BGA1356
B AW33 DDR0_DQ[43] DDR1_DQ[11] B

2
BB35 DDR0_DQ[44] DDR1_DQ[12]
BA35 DDR0_DQ[45] DDR1_DQ[13] TABLE R1838
100K_0201_5%
BA33 DDR0_DQ[46] DDR1_DQ[14]
BB33 DDR0_DQ[47] DDR1_DQ[15] Pin Interleave Non-Interleave

1
VCC1R2A DDR_VTT_PG_CTRL
DDR_VTT_PG_CTRL [69]
AM70 DDR0_DQSN[0] DDR0_DQSN[0]

1
AM69 DDR0_DQSP[0] DDR0_DQSP[0]
Block 0 AT69 DDR0_DQSN[1] DDR0_DQSN[1]
AT70 DDR0_DQSP[1] DDR0_DQSP[1] Q170
AY31 DDR0_DQ[48] DDR1_DQ[32] 2 DTC015TMT2L_VMT3
AW31 DDR0_DQ[49] DDR1_DQ[33]
AY29 DDR0_DQ[50] DDR1_DQ[34] BA64 DDR0_DQSN[2] DDR0_DQSN[4]
AW29 DDR0_DQ[51] DDR1_DQ[35] AY64 DDR0_DQSP[2] DDR0_DQSP[4]

3
BB31 DDR0_DQ[52] DDR1_DQ[36] Block 2 AY60 DDR0_DQSN[3] DDR0_DQSN[5]
BA31 DDR0_DQ[53] DDR1_DQ[37] BA60 DDR0_DQSP[3] DDR0_DQSP[5]

2
BA29 DDR0_DQ[54] DDR1_DQ[38] @
R1858
BB29 DDR0_DQ[55] DDR1_DQ[39] 10K_0201_5%
AY27 DDR0_DQ[56] DDR1_DQ[40] BA38 DDR0_DQSN[4] DDR1_DQSN[0]
Block 6 AW27 DDR0_DQ[57] DDR1_DQ[41] AY38 DDR0_DQSP[4] DDR1_DQSP[0]

1
AY25 DDR0_DQ[58] DDR1_DQ[42] Block 4 AY34 DDR0_DQSN[5] DDR1_DQSN[1]
AW25 DDR0_DQ[59] DDR1_DQ[43] BA34 DDR0_DQSP[5] DDR1_DQSP[1]
BB27 DDR0_DQ[60] DDR1_DQ[44]
BA27 DDR0_DQ[61] DDR1_DQ[45]
BA25 DDR0_DQ[62] DDR1_DQ[46]
BB25 DDR0_DQ[63] DDR1_DQ[47] BA30 DDR0_DQSN[6] DDR1_DQSN[4]
AY30 DDR0_DQSP[6] DDR1_DQSP[4]
Block 6 AY26 DDR0_DQSN[7] DDR1_DQSN[5]
BA26 DDR0_DQSP[7] DDR1_DQSP[5]

A A

LOGIC LOGIC LOGIC LOGIC

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(2/16) : DDR CHANNEL-A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 5 of 73
5 4 3 2 1
5 4 3 2 1

[5,22] DDR_A_D[63:0]

[5,24] DDR_B_D[63:0]

D D

TABLE

Pin Interleave Non-Interleave


SKL-U
U58C @
AF65 DDR1_DQ[0] DDR0_DQ[16]
AF64 DDR1_DQ[1] DDR0_DQ[17] DDR_A_D16 AF65 AN45 -DDR_B_CLK0
DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] -DDR_B_CLK0 [24,25]
AK65 DDR1_DQ[2] DDR0_DQ[18] DDR_A_D17 AF64
DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1]
AN46
AK64 DDR1_DQ[3] DDR0_DQ[19] DDR_A_D18 AK65 AP45 DDR_B_CLK0 DDR_B_CLK0 [24,25]
DDR_A_D19 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46
AF66 DDR1_DQ[4] DDR0_DQ[20] DDR_A_D20 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1]
AF67 DDR1_DQ[5] DDR0_DQ[21] DDR_A_D21 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDR_B_CKE0
DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDR_B_CKE0 [24,25]
AK67 DDR1_DQ[6] DDR0_DQ[22] DDR_A_D22 AK67
DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1]
AP55
DDR_A_D23 AK66 AN55
AK66 DDR1_DQ[7] DDR0_DQ[23] DDR_A_D24 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
AF70 DDR1_DQ[8] DDR0_DQ[24] DDR_A_D25 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDR1_DQ[9]/DDR0_DQ[25]
Block 1 AF68 DDR1_DQ[9] DDR0_DQ[25] DDR_A_D26 AH71
DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0]
BB42 -DDR_B_CS0 -DDR_B_CS0 [24,25]
DDR_A_D27 AH68 AY42
AH71 DDR1_DQ[10] DDR0_DQ[26] DDR_A_D28 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDR_B_ODT0
AH68 DDR1_DQ[11] DDR0_DQ[27] DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] DDR_B_ODT0 [24,25]
DDR_A_D29 AF69 AW42
AF71 DDR1_DQ[12] DDR0_DQ[28] DDR_A_D30 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1]
DDR_A_D31 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48 DDR_B_MA5
TABLE
AF69 DDR1_DQ[13] DDR0_DQ[29] DDR_A_D48 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR_B_MA9
AT66 AP50
AH70 DDR1_DQ[14] DDR0_DQ[30] DDR_A_D49 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_MA6
AH69 DDR1_DQ[15] DDR0_DQ[31] DDR_A_D50 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDR_B_MA8
Pin DDR3L LPDDR3 DDR4
DDR_A_D51 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_MA7
DDR_A_D52 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDR_B_BG0
DDR_A_D53 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_B_MA12
DDR_B_BG0 [24,25] AY48 DDR1_MA[5] DDR1_CAA[0] DDR1_MA[5]
DDR_A_D54 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR_B_MA11 AP50 DDR1_MA[9] DDR1_CAA[1] DDR1_MA[9]
DDR_A_D55 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 -DDR_B_ACT BA48 DDR1_MA[6] DDR1_CAA[2] DDR1_MA[6]
DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# -DDR_B_ACT [24,25]
DDR_A_D56 AT61 AN52 DDR_B_BG1 DDR_B_BG1 [24] BB48 DDR1_MA[8] DDR1_CAA[3] DDR1_MA[8]
DDR_A_D57 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR_A_D58 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43 DDR_B_MA13 AP48 DDR1_MA[7] DDR1_CAA[4] DDR1_MA[7]
AT66 DDR1_DQ[16] DDR0_DQ[48] DDR_A_D59 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_MA15 AP52 DDR1_BA[2] DDR1_CAA[5] DDR1_BG[0]
AU66 DDR1_DQ[17] DDR0_DQ[49] DDR_A_D60 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDR_B_MA14 AN50 DDR1_MA[12] DDR1_CAA[6] DDR1_MA[12]
AP65 DDR1_DQ[18] DDR0_DQ[50] DDR_A_D61 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 DDR_B_MA16
C C
DDR_A_D62 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 DDR_B_BA0 AN48 DDR1_MA[11] DDR1_CAA[7] DDR1_MA[11]
AN65 DDR1_DQ[19] DDR0_DQ[51] DDR_A_D63 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR_B_MA2
DDR_B_BA0 [24,25] AN53 DDR1_MA[15] DDR1_CAA[8] DDR1_ACT#
AU60 AY47
AN66 DDR1_DQ[20] DDR0_DQ[52] DDR_B_D16 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 DDR_B_BA1 AN52 DDR1_MA[14] DDR1_CAA[9] DDR1_BG[1]
DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR_B_BA1 [24,25]
AP66 DDR1_DQ[21] DDR0_DQ[53] DDR_B_D17 AT40 AW46 DDR_B_MA10
DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
AT65 DDR1_DQ[22] DDR0_DQ[54] DDR_B_D18 AT37
DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
AY46 DDR_B_MA1
DDR_B_D19 AU37 BA46 DDR_B_MA0
AU65 DDR1_DQ[23] DDR0_DQ[55] DDR_B_D20 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 DDR_B_MA3
AT61 DDR1_DQ[24] DDR0_DQ[56] DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] DDR_B_MA[16:0] [24,25]
DDR_B_D21 AP40 BA47 DDR_B_MA4
Block 3 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4]
AU61 DDR1_DQ[25] DDR0_DQ[57] DDR_B_D22 AP37
DDR1_DQ[38]/DDR1_DQ[22] BA43 DDR1_MA[13] DDR1_CAB[0] DDR1_MA[13]
DDR_B_D23 AR37 AH66 -DDR_A_DQS2
AP60 DDR1_DQ[26] DDR0_DQ[58] DDR_B_D24 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_A_DQS2
-DDR_A_DQS2 [22] AY43 DDR1_CAS# DDR1_CAB[1] DDR1_MA[15]
AN60 DDR1_DQ[27] DDR0_DQ[59] DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] DDR_A_DQS2 [22]
DDR_B_D25 AU33
DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3]
AG69 -DDR_A_DQS3 -DDR_A_DQS3 [22] AY44 DDR1_WE# DDR1_CAB[2] DDR1_MA[14]
AN61 DDR1_DQ[28] DDR0_DQ[60] DDR_B_D26 AU30
DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3]
AG70 DDR_A_DQS3 DDR_A_DQS3 [22] AW44 DDR1_RAS# DDR1_CAB[3] DDR1_MA[16]
AP61 DDR1_DQ[29] DDR0_DQ[61] DDR_B_D27 AT30 AR66 -DDR_A_DQS6
DDR_B_D28 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_A_DQS6
-DDR_A_DQS6 [22] BB44 DDR1_BA[0] DDR1_CAB[4] DDR1_BA[0]
AT60 DDR1_DQ[30] DDR0_DQ[62] DDR_B_D29 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 -DDR_A_DQS7
DDR_A_DQS6 [22]
AY47 DDR1_MA[2] DDR1_CAB[5] DDR1_MA[2]
DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] -DDR_A_DQS7 [22]
AU60 DDR1_DQ[31] DDR0_DQ[63] DDR_B_D30 AR30 AR60 DDR_A_DQS7 DDR_A_DQS7 [22] BA44 DDR1_BA[1] DDR1_CAB[6] DDR1_BA[1]
DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7]

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DDR_B_D31 AP30 AT38 -DDR_B_DQS2
DDR_B_D48 AU27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDR_B_DQS2
-DDR_B_DQS2 [24] VCC1R2A AW46 DDR1_MA[10] DDR1_CAB[7] DDR1_MA[10]
DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] DDR_B_DQS2 [24] AY46 DDR1_MA[1] DDR1_CAB[8] DDR1_MA[1]
DDR_B_D49 AT27 AT32 -DDR_B_DQS3 -DDR_B_DQS3 [24]
DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3]
DDR_B_D50 AT25
DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3]
AR32 DDR_B_DQS3 DDR_B_DQS3 [24] BA46 DDR1_MA[0] DDR1_CAB[9] DDR1_MA[0]
DDR_B_D51 AU25 AR25 -DDR_B_DQS6
DDR_B_D52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 DDR_B_DQS6
-DDR_B_DQS6 [24] BB46 DDR1_MA[3] Not Used DDR1_MA[3]
DDR1_DQ[52] DDR1_DQSP[6] DDR_B_DQS6 [24] BA47 DDR1_MA[4] Not Used DDR1_MA[4]

2
DDR_B_D53 AN27 AR22 -DDR_B_DQS7 -DDR_B_DQS7 [24]
DDR_B_D54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDR_B_DQS7 R1726
AU40 DDR1_DQ[32] DDR1_DQ[16] DDR_B_D55 AP25 DDR1_DQ[54] DDR1_DQSP[7] DDR_B_DQS7 [24]
470_0201_5%
AT40 DDR1_DQ[33] DDR1_DQ[17] DDR_B_D56 AT22 DDR1_DQ[55] AN43
DDR1_DQ[56] DDR1_ALERT# -DDR_B_ALERT [24,25]
AT37 DDR1_DQ[34] DDR1_DQ[18] DDR_B_D57 AU22 AP43
DDR_B_PAR [24,25]

1
DDR_B_D58 AU21 DDR1_DQ[57] DDR1_PAR AT13 -DRAMRST
AU37 DDR1_DQ[35] DDR1_DQ[19] DDR_B_D59 DDR1_DQ[58] DRAM_RESET# -DRAMRST [22,24]
AT21 AR18 R7 1 X76@ 2 200_0201_1%
AR40 DDR1_DQ[36] DDR1_DQ[20] DDR_B_D60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 R84 1 2 80.6_0201_1%
AP40 DDR1_DQ[37] DDR1_DQ[21] DDR_B_D61 AP22 DDR1_DQ[60] DDR CH - B DDR_RCOMP[1] AU18 R576 1 2 100_0201_1%
DDR1_DQ[61] DDR_RCOMP[2]
AP37 DDR1_DQ[38] DDR1_DQ[22] DDR_B_D62 AP21
DDR1_DQ[62]
DDR_B_D63 AN21
AR37 DDR1_DQ[39] DDR1_DQ[23] DDR1_DQ[63]
AT33 DDR1_DQ[40] DDR1_DQ[24] 3 OF 20
LOGIC LOGIC
Block 5 AU33 DDR1_DQ[41] DDR1_DQ[25] KBL-RU_BGA1356
AU30 DDR1_DQ[42] DDR1_DQ[26]
B AT30 DDR1_DQ[43] DDR1_DQ[27] B

AR33 DDR1_DQ[44] DDR1_DQ[28] TABLE


AP33 DDR1_DQ[45] DDR1_DQ[29]
AR30 DDR1_DQ[46] DDR1_DQ[30]
AP30 DDR1_DQ[47] DDR1_DQ[31] Pin Interleave Non-Interleave

AH66 DDR1_DQSN[0] DDR0_DQSN[2] SDP DDP


AH65 DDR1_DQSP[0] DDR0_DQSP[2]
Block 1 AG69 DDR1_DQSN[1] DDR0_DQSN[3]
AG70 DDR1_DQSP[1] DDR0_DQSP[3]
R7 200 1% 121 1%
AU27 DDR1_DQ[48] DDR1_DQ[48]
AT27 DDR1_DQ[49] DDR1_DQ[49]
AT25 DDR1_DQ[50] DDR1_DQ[50] AR66 DDR1_DQSN[2] DDR0_DQSN[6]
AU25 DDR1_DQ[51] DDR1_DQ[51] AR65 DDR1_DQSP[2] DDR0_DQSP[6]
Block 3 AR61 DDR1_DQSN[3] DDR0_DQSN[7]
AP27 DDR1_DQ[52] DDR1_DQ[52]
AN27 DDR1_DQ[53] DDR1_DQ[53] AR60 DDR1_DQSP[3] DDR0_DQSP[7]
AN25 DDR1_DQ[54] DDR1_DQ[54]
AP25 DDR1_DQ[55] DDR1_DQ[55]
AT22 DDR1_DQ[56] DDR1_DQ[56] AT38 DDR1_DQSN[4] DDR1_DQSN[2]
AU22 DDR1_DQ[57] DDR1_DQ[57] AR38 DDR1_DQSP[4] DDR1_DQSP[2]
Block 7 Block 5 AT32 DDR1_DQSN[5] DDR1_DQSN[3]
AU21 DDR1_DQ[58] DDR1_DQ[58]
AT21 DDR1_DQ[59] DDR1_DQ[59] AR32 DDR1_DQSP[5] DDR1_DQSP[3]
AN22 DDR1_DQ[60] DDR1_DQ[60]
AP22 DDR1_DQ[61] DDR1_DQ[61]
AP21 DDR1_DQ[62] DDR1_DQ[62] AR25 DDR1_DQSN[6] DDR1_DQSN[6]
AN21 DDR1_DQ[63] DDR1_DQ[63] AR27 DDR1_DQSP[6] DDR1_DQSP[6]
Block 7 AR22 DDR1_DQSN[7] DDR1_DQSN[7]
AR21 DDR1_DQSP[7] DDR1_DQSP[7]

A A

LOGIC LOGIC
LOGIC LOGIC

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(3/16) : DDR CHANNEL-B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 6 of 73
5 4 3 2 1
5 4 3 2 1

D D

VCCSTG VCCST
C C

2
R64 R9055
1K_0201_5% 1K_0201_5%

1
U58D @ SKL-U

D63
PECI A54 CATERR#
[53] PECI PECI
-PROCHOT R85 1 2 510_0402_5% C65 JTAG
[53] -PROCHOT PROCHOT#
C63
A65 THERMTRIP# B61 XDP_TCK0
SKTOCC# PROC_TCK XDP_TCK0 [20]
CPU MISC D60 XDP_TDI XDP_TDI [20]
PROC_TDI

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C55 A61 XDP_TDO XDP_TDO [20]
D55 BPM#[0] PROC_TDO C60 XDP_TMS
BPM#[1] PROC_TMS XDP_TMS [20]
B54 B59 -XDP_TRST -XDP_TRST [20]
C56 BPM#[2] PROC_TRST#
BPM#[3] B56
PCH_JTAG_TCK PCH_TCK [20]
A6 D59
A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56
BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59
AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61
GPP_B4/CPU_GP3 PCH_TRST# A59
R2126 1 2 49.9_0201_1% AT16 JTAGX
R2127 1 2 49.9_0201_1% AU16 PROC_POPIRCOMP
R2128 1 2 49.9_0201_1% H66 PCH_OPIRCOMP
R2129 1 2 49.9_0201_1% H65 OPCE_RCOMP
OPC_RCOMP

2
4 OF 20
R2 R9397
KBL-RU_BGA1356
51_0201_5% @ 51_0201_5%

1
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(4/16) : MISC/JTAG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 7 of 73
5 4 3 2 1
5 4 3 2 1

D D

VCC3M

TABLE : Functional Strap


SPI0_MOSI (Boot Halt)
TABLE : Functional Strap
HIGH Disabled (Default)
GPP_C5/SML0ALERT # (LPC or eSPI) FVT_C_EC016
LOW Enabled

2
HIGH eSPI is selected
EC_SMB_CK2 6 1 SMB_CK2
LOW LPC is selected (Default) LOGIC [41,51,53] EC_SMB_CK2
Q211A
SSM6N48FU 2N SC-88-6 ET88
TABLE : Functional Strap

5
SPI0_MISO (JTAG ODT Diable) TABLE : Functional Strap EC_SMB_DA2 3 4 SMB_DA2
[41,51,53] EC_SMB_DA2
HIGH Enabled (Default) GPP_C2/SMBALERT# (TLS Confidentiality) Q211B
LOW Disabled HIGH Enable ME Crypto TLS with Confidentiality LOGIC SSM6N48FU 2N SC-88-6 ET88

LOW Disable ME Crypto TLS (Default)

VCC3_SUS VCC3B

VCC3_SUS VCC3_SUS VCC3B


1K_0201_5%

1K_0201_5%

C C
8.2K_0201_5%
2

8.2K_0201_5%
2

2
@ @
R226 R394 R397 R106 R107
1K_0201_5% 4.7K_0201_5% 4.7K_0201_5% 499_0201_1% 499_0201_1% @
1

1
R9311

R9310

R860

1
R28
SKL-U
U58E @
SPI - FLASH
SMBUS, SMLINK
AV2
[21,45] SPI_CLK SPI0_CLK
AW3 R7 SMB_CLK
[21,45] SPI_MISO_IO1 SPI0_MISO GPP_C0/SMBCLK SMB_CLK [46]
AV3 R8 SMB_DATA
[21,45] SPI_MOSI_IO0 SPI0_MOSI GPP_C1/SMBDATA SMB_DATA [46]
AW2 R10
[21] SPI_IO2 SPI0_IO2 GPP_C2/SMBALERT#

Vinafix.com
AU4
[21] SPI_IO3 SPI0_IO3
AU3 R9 SMB0_CLK
[21] -SPI_CS0 SPI0_CS0# GPP_C3/SML0CLK SMB0_CLK [52]
AU2 W2 SMB0_DATA
SPI0_CS1# GPP_C4/SML0DATA SMB0_DATA [52]
AU1 W1
[45] -SPI_CS2 SPI0_CS2# GPP_C5/SML0ALERT#
W3 SMB_CK2
SPI - TOUCH GPP_C6/SML1CLK SMB_CK2 [41]
V3 SMB_DA2
GPP_C7/SML1DATA SMB_DA2 [41]
M2 AM7
M3 GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT#
J4 GPP_D2/SPI1_MISO
V1 GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2 LPC_AD[3:0] [46,53]
V2
M1 GPP_D22/SPI1_IO3
LPC
GPP_D0/SPI1_CS# AY13 LPC_AD0
GPP_A1/LAD0/ESPI_IO0 BA13 LPC_AD1
C LINK GPP_A2/LAD1/ESPI_IO1 BB13 LPC_AD2
CL_CLK_WLAN G3 GPP_A3/LAD2/ESPI_IO2 AY12 LPC_AD3
[32] CL_CLK_WLAN CL_CLK GPP_A4/LAD3/ESPI_IO3
CL_DATA_WLAN G2 BA12
[32] CL_DATA_WLAN CL_DATA GPP_A5/LFRAME#/ESPI_CS# -LPC_FRAME [46,53]
-CL_RST_WLAN G1 BA11
[32] -CL_RST_WLAN CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET# -SUS_STAT [46]

[53] -KBRC AW13 AW9 LPCCLK_0 R193 1 RF@ 2 27_0402_1%


B GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK LPCCLK_EC_24M [53] B
AY9 LPCCLK_1 R220 1 2 0_0402_5%
GPP_A10/CLKOUT_LPC1 LPCCLK_DEBUG_24M [46]
AY11 AW11
[46,53] IRQSER GPP_A6/SERIRQ GPP_A8/CLKRUN# -CLKRUN [46]
5 OF 20

KBL-RU_BGA1356
FVT_C_EC002 RF@
2 2
@RF@
2

2 C8609 C8610
@RF@ @ @ 18P_0201_50V8J 18P_0201_50V8J
C264 R9308 R9305 1 1
33P_0201_25V8J 1K_0201_5% 1K_0201_5%
1
1

TABLE : Functional Strap


SPI0_IO2 (Consent Strap)
HIGH Enabled (Default)
LOW Disabled

TABLE : Functional Strap


SPI0_IO3 (A0 Personality Strap)
HIGH Disabled (Default)
A LOW Enabled A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(5/16) : LPC/SPI/SMBUS/C-LINK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 8 of 73
5 4 3 2 1
5 4 3 2 1

VCC1R8_SUS VCC3B VCC3_SUS TABLE : Functional Strap


D GPP_B22/GSPI1_MOSI (Boot BIOS Destination) D

HIGH Boot BIOS from LPC


LOW Boot BIOS from SPI (Default) LOGIC

10K_0201_5%

10K_0201_5%

10K_0201_5%

1K_0201_5%
TABLE : Functional Strap

2
GPP_B18/GSPI0_MOSI (No Reboot) VCC3B VCC3B VCC3B VCC1R8_SUS

@
HIGH Enable "No Reboot" Mode
LOW Disable "No Reboot" Mode (Default)

1
R2748

R2749

R2340

R65

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%
1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%
2

2
@

@
1

1
SKL-U

R9257

R9261

R9262

R9263

R9565

R9375

R2750

R2751
U58F @
LPSS ISH

AN8
[43] NFC_DLREQ GPP_B15/GSPI0_CS#
AP7 P2 -NFC_DTCT [43]
AP8 GPP_B16/GSPI0_CLK GPP_D9 P3
[32] -WWAN_PWROFF GPP_B17/GSPI0_MISO GPP_D10 -INT_IR_DTCT [27]
AR7 P4 -TS_RESET [26]
GPP_B18/GSPI0_MOSI GPP_D11 P1
AM5 GPP_D12
[32] -WWAN_DISABLE GPP_B19/GSPI1_CS#
AN7 M4
GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA ISH_I2C0_SDA [26,27,41]
AP5 N3
GPP_B21/GSPI1_MISO GPP_D6/ISH_I2C0_SCL ISH_I2C0_SCL [26,27,41]
AN5
GPP_B22/GSPI1_MOSI N1
GPP_D7/ISH_I2C1_SDA I2C_DATA_GSENSE_SH [53]
C AB1 N2 I2C_CLK_GSENSE_SH [53] C
AB2 GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL
W4 GPP_C9/UART0_TXD AD11
GPP_C10/UART0_RTS# GPP_F10/I2C5_SDA/ISH_I2C2_SDA WWAN_CFG2 [32]
AB3 AD12 WWAN_CFG3 [32]
[32] BDC_ON GPP_C11/UART0_CTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
AD1 VCC3B VCC3B
[48] -TBT_PLUG_EVENT GPP_C20/UART2_RXD
AD2 U1
[48] TBT_FORCE_PWR GPP_C21/UART2_TXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
[53] -EC_SCI AD3 U2
AD4 GPP_C22/UART2_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3
[53] -EC_WAKE GPP_C23/UART2_CTS# GPP_D15/ISH_UART0_RTS# U4
GPP_D16/ISH_UART0_CTS#/SML0BALERT#

4.7K_0201_5%

4.7K_0201_5%

4.7K_0201_5%

4.7K_0201_5%

4.7K_0201_5%
2

2
[43] I2C0_DATA U7 AC1
GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD

R9259

R9260
R154

R155

R156
[43] I2C0_CLK U6 AC2
GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD AC3
U8 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4
U9 GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS#

1
GPP_C19/I2C1_SCL AY8 ISH_GP0_R R9419 1 RF@ 2 0_0201_5%
GPP_A18/ISH_GP0 ISH_GP0 [26,27]
AH9 BA8 ISH_GP1_R R9420 1 RF@ 2 0_0201_5% ISH_GP1 [26,27]
[32] -WWAN_RESET GPP_F4/I2C2_SDA GPP_A19/ISH_GP1

Vinafix.com
AH10 BB7 ISH_GP2_R R9421 1 RF@ 2 0_0201_5% ISH_GP2 [26,27,41]
GPP_F5/I2C2_SCL GPP_A20/ISH_GP2 BA7 ISH_GP3 2 1 -LID_CLOSE
GPP_A21/ISH_GP3 -LID_CLOSE [26,43,53]
AH11 AY7 ISH_GP4 D801 RB521CM-30T2R_SOD923-2
AH12 GPP_F6/I2C3_SDA GPP_A22/ISH_GP4 AW7 ISH_GP5 TP922 @
[26,27] -INT_MIC_DTCT GPP_F7/I2C3_SCL GPP_A23/ISH_GP5 AP13 ISH_GP6 TP923 @ 2 1 -TABLET_MODE
GPP_A12/BM_BUSY#/ISH_GP6 -TABLET_MODE [43,53]

C8649

C8650

C8651
[32] WWAN_CFG0 AF11 D802 RB521CM-30T2R_SOD923-2
AF12 GPP_F8/I2C4_SDA
[32] WWAN_CFG1 GPP_F9/I2C4_SCL 6 OF 20 FVT_C_EC018 2 2 2

KBL-RU_BGA1356
1 1 1

RF@

RF@

RF@
0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K
FVT_C_EC018
B B

For ISH debug


ISH_I2C0_SCL TP924 @
ISH_I2C0_SDA TP925 @
I2C_CLK_GSENSE_SH TP926 @
I2C_DATA_GSENSE_SH TP927 @
ISH_GP0 TP928 @
ISH_GP1 TP929 @
ISH_GP2 TP930 @
ISH_GP3 TP931 @

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU(6/16) : LPSS/ISH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 9 of 73
5 4 3 2 1
5 4 3 2 1

D D

TABLE : Functional Strap


HDA_SDO/I2S0_TXD
Flash Descriptor Security Override
VCC3_SUS R9564 1 @ 2 0_0201_5%
[53] ME_FLASH
HIGH Disable Flash Descriptor Security (Override)
C LOW Enable Flash Descriptor Security (Default) C

2
R1009
@ 1K_0201_5%
U58G @ SKL-U

1
AUDIO

R423 1 2 33_0201_5% BA22


[35] HDA_SYNC HDA_SYNC/I2S0_SFRM
R60 1 2 33_0201_5% AY22
[35] HDA_BCLK HDA_BLK/I2S0_SCLK
R74 1 2 33_0201_5% HDA_SDOUT BB22 SDIO/SDXC
[35] HDA_SDO HDA_SDO/I2S0_TXD
[35] HDA_SDIN0 BA21
AY21 HDA_SDI0/I2S0_RXD AB11
R456 1 2 33_0201_5% AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
[35] -HDA_RST HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0
J5 AB12
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
I2S1_SFRM GPP_G3/SD_DATA2

Vinafix.com
AW20 W11
I2S1_TXD GPP_G4/SD_DATA3 W10
AK7 GPP_G5/SD_CD# W8
R9380 1 @ 2 0_0201_5% AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
[43] NFC_ACTIVE GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK9
AK10 GPP_F2/I2S2_TXD BA9
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
GPP_A16/SD_1P8_SEL
H5 AB7
D7 GPP_D19/DMIC_CLK0 SD_RCOMP
GPP_D20/DMIC_DATA0
D8 AF13 -SC_DTCT [34]
C8 GPP_D17/DMIC_CLK1 GPP_F23
GPP_D18/DMIC_DATA1
PCH_SPKR AW5
[40] PCH_SPKR GPP_B14/SPKR
7 OF 20
2
KBL-RU_BGA1356
RF@ C38
1
47P_0201_25V8J R60, C38 close to CPU
B B

TABLE : Functional Strap


GPP_B14/SPKR (Top Swap Override)
HIGH Enable "Top Swap" Mode
LOW Disable "Top Swap" Mode (Default) LOGIC

VCC3M

R54 1 @ 2 1K_0201_5% HDA_SDOUT

HDA_SDOUT
ME debug mode,this signal has a weak internal PD
Low = Disabled (Default)
* High = Enabled [Flash Descriptor Security Overide]

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU : AUDIO/SDXC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 10 of 73
5 4 3 2 1
5 4 3 2 1

D Flexible I/O Configuration PCIe Port Assignment D

I/O High Speed Signals Configuration Net Name


0 MEDIA CARD
Port 1 USB3 1 USB3 1 USB3P0 2 M.2 WLAN Slot Port 0 for WLAN
Port 2 USB3 2/SSIC SSIC SSIC 3 GbE PHY
Port 3 USB3 3 USB3 3 USB3P2 4 (x4) PCIe SSD
Port 4 USB3 4 USB3 4 USB3P3 8 Thunder bolt
Port 5 USB3 5/PCIE 1 PCIE 1 PCIE0 11 WWAN
Port 6 USB3 6/PCIE 2 USB3 6 USB3P5
Port 7 PCIE 3 (GbE) PCIE 3 PCIE2 VCC3_SUS
Port 8 PCIE 4 (GbE) PCIE 4 PCIE3
Port 9 PCIE 5 (GbE) PCIE 5 (x4) PCIE4_L3
Port 10 PCIE 6 PCIE 6 (x4) PCIE4_L2
Port 11 PCIE 7/SATA 0 PCIE 7 (x4) PCIE4_L1 VCC3_SUS SATA Port Assignment
Port 12 PCIE 8/SATA 1A GPIO STRAP PCIE4_L0_SATA1

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%
Port 13 PCIE 9 (GbE) PCIE 9 (x4) PCIE5_L0 0 (PCIE 7)
Port 14 PCIE 10 (GbE) PCIE 10 (x4) NA 1A SATA SSD
Port 15 PCIE 11/SATA 1B PCIE 11 (x4) NA 1B NA
Port 16 PCIE 12/SATA 2 PCIE 12 (x4) NA

2
2 (PCIE 11)
@ @

R2307

R2308
R648

R248
1

1
R2341
10K_0201_5%

U58H @ SKL-U

1
SSIC / USB3
PCIE/USB3/SATA
H8 USB3P0_RXN [31]
USB3_1_RXN G8
USB3_1_RXP USB3P0_RXP [31]
[33] PCIE0_RXN H13 C13
PCIE1_RXN/USB3_5_RXN USB3_1_TXN USB3P0_TXN [31]
[33] PCIE0_RXP G13 D13
PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3P0_TXP [31]
C B17 C
[33] PCIE0_TXN PCIE1_TXN/USB3_5_TXN
A17 J6
[33] PCIE0_TXP PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN H6 USB Port Assignment
G11 USB3_2_RXP/SSIC_1_RXP B13
F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13
D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP
C16 PCIE2_TXN/USB3_6_TXN J10
0 USB 3.0 System Port (AOU)
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN USB3P2_RXN [31] 1 M.2 WWAN Slot
H10 USB3P2_RXP [31]
H16 USB3_3_RXP/SSIC_2_RXP B15 2 USB 3.0 System Port
[32] PCIE2_RXN PCIE3_RXN USB3_3_TXN/SSIC_2_TXN USB3P2_TXN [31]
[32] PCIE2_RXP G16 A15 3 RGB camera
PCIE3_RXP USB3_3_TXP/SSIC_2_TXP USB3P2_TXP [31]
D17
[32] PCIE2_TXN
C17 PCIE3_TXN E10 4 SMART CARD
[32] PCIE2_TXP PCIE3_TXP USB3_4_RXN 5 IR CAMERA
F10
USB3_4_RXP
[52] PCIE3_RXN G15
PCIE4_RXN USB3_4_TXN
C15 6 M.2 WLAN Slot for BT
F15 D15
[52] PCIE3_RXP
B19 PCIE4_RXP USB3_4_TXP 7 USB Camera
[52] PCIE3_TXN PCIE4_TXN 8 Fingerprint Reader
A19 AB9
[52] PCIE3_TXP PCIE4_TXP USB2N_1 USBP0- [31]
USB2P_1
AB10
USBP0+ [31] 9 Touch Panel

Vinafix.com
[30] PCIE4_L3_RXN F16
E16 PCIE5_RXN AD6
[30] PCIE4_L3_RXP PCIE5_RXP USB2N_2 USBP1- [32]
C19 AD7
[30] PCIE4_L3_TXN PCIE5_TXN USB2P_2 USBP1+ [32]
D19
[30] PCIE4_L3_TXP PCIE5_TXP AH3
USB2N_3 USBP2- [31]
[30] PCIE4_L2_RXN G18 AJ3
PCIE6_RXN USB2P_3 USBP2+ [31]
[30] PCIE4_L2_RXP F18
D20 PCIE6_RXP AD9
[30] PCIE4_L2_TXN PCIE6_TXN USB2N_4 USBP3- [27]
C20 AD10 USB 3.0 Port Assignment
[30] PCIE4_L2_TXP PCIE6_TXP USB2P_4 USBP3+ [27]

[30] PCIE4_L1_RXN F20 AJ1


PCIE7_RXN/SATA0_RXN USB2N_5 USBP4- [34]
[30] PCIE4_L1_RXP E20 AJ2 0 USB 3.0 System Port (AOU)
PCIE7_RXP/SATA0_RXP USB2P_5 USBP4+ [34]
B21 USB2
[30] PCIE4_L1_TXN
A21 PCIE7_TXN/SATA0_TXN AF6 1 NA
[30] PCIE4_L1_TXP PCIE7_TXP/SATA0_TXP USB2N_6 USBP5- [27]
USB2P_6
AF7
USBP5+ [27]
2 USB 3.0 System Port
[30] PCIE4_L0_SATA1_RXN G21 3 NA
F21 PCIE8_RXN/SATA1A_RXN AH1
[30] PCIE4_L0_SATA1_RXP
D21 PCIE8_RXP/SATA1A_RXP USB2N_7 AH2
USBP6- [32] 4 (PCIE 1)
[30] PCIE4_L0_SATA1_TXN PCIE8_TXN/SATA1A_TXN USB2P_7 USBP6+ [32] 5 (RESERVED)
C21
[30] PCIE4_L0_SATA1_TXP PCIE8_TXP/SATA1A_TXP AF8
USB2N_8 USBP7- [26]
[49] PCIE8_L0_RXN E22 AF9
PCIE9_RXN USB2P_8 USBP7+ [26]
[49] PCIE8_L0_RXP E23
B
B23 PCIE9_RXP AG1 B
[49] PCIE8_L0_TXN PCIE9_TXN USB2N_9 USBP8- [34]
A23 AG2
[49] PCIE8_L0_TXP PCIE9_TXP USB2P_9 USBP8+ [34] VCC3_SUS
[49] PCIE8_L1_RXN F25 AH7
PCIE10_RXN USB2N_10 USBP9- [26]
[49] PCIE8_L1_RXP E25 AH8
PCIE10_RXP USB2P_10 USBP9+ [26]
D23 113_0201_1%
[49] PCIE8_L1_TXN PCIE10_TXN
100_0201_1% C23 AB6 USBCOMP 1 2
[49] PCIE8_L1_TXP PCIE10_TXP USB2_COMP AG3 R564
1 2 F5 USB2_ID AG4
PCIE_RCOMPN USB2_VBUSSENSE

2
R8964 E5
PCIE_RCOMPP A9 R44
GPP_E9/USB2_OC0# -USB_PORT0_OC0 [31]
-XDP_PRDY D56 C9 -USB_PORT1_OC1 [31] 10K_0201_5%
[20] -XDP_PRDY PROC_PRDY# GPP_E10/USB2_OC1#
[20] -XDP_PREQ -XDP_PREQ D61 D9
-TPM_IRQ BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9
[45] -TPM_IRQ NFC_INT [43]

1
GPP_A7/PIRQA# GPP_E12/USB2_OC3#
E28 J1
PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 NFC_ON [43]
E27 J2
PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 SATA1_DEVSLP [30]
D24 J3
C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
E30 PCIE11_TXP/SATA1B_TXP H2
[32] PCIE11_RXN PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0
[32] PCIE11_RXP F30 H3 -PE_DTCT -PE_DTCT [30]
A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4
[32] PCIE11_TXN PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
B25
[32] PCIE11_TXP PCIE12_TXP/SATA2_TXP H1
GPP_E8/SATALED#
8 OF 20
KBL-RU_BGA1356

2
@
R72 R77
1K_0201_5% 0_0201_5%

A 1 A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU : PCIE/USB/SATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 11 of 73
5 4 3 2 1
5 4 3 2 1

D D

SKL_ULT
U58I @

CSI-2

A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
C C
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
C31 E13
D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3 MEMORYID0
A29 GPP_F16/EMMC_DATA3 AN1 MEMORYID1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2 MEMORYID2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4 MEMORYID3
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1 DDR_CH_SEL
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
CSI2_DN10

Vinafix.com
B27 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3 -TAMPER_SW_DTCT
CSI2_DN11 GPP_F22/EMMC_CLK -TAMPER_SW_DTCT [14]
D27 AP4
CSI2_DP11 GPP_F12/EMMC_CMD
9 OF 20 AT1
EMMC_RCOMP

KBL-RU_BGA1356

B B

TABLE
U125, U126, U127, U128, U129, U130,
MEMORY[3..0] U131, U132 R7 (Rcomp) 2CH 1CH
1111B Samsung K4A8G165WC-BCRC 8Gbit SDP 4GB 200 1% MEMORYID0
1110B Samsung K4AAG165WB-MCRC 16Gbit DDP 8GB 121 1% MEMORYID1
R2331 NC Mount MEMORYID2
MEMORYID3 DDR_CH_SEL
1101B Hynix H5AN8G6NAFR-UHC 8Gbit SDP 4GB 200 1%
1011B Hynix H5ANAG6NAMR-UHC 16Gbit DDP 8GB 121 1%
0111B Micron MT40A512M16JY-083E:B 8Gbit SDP 4GB 200 1%

2
2

2
1100B Micron MT40A1G16WBU-083E:B 16Gbit DDP 8GB 121 1% R2331
R2332 R2333 R2334 R2335 0_0201_5%
0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% X76@
X76@ X76@ X76@ X76@

1
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU : CSI-2/EMMC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 12 of 73
5 4 3 2 1
5 4 3 2 1

D D

XTAL24_IN_U22 R9463 1 U22@ 2 33_0201_5%

2
2 3
2 3 Y5
@EMI@ FLJ20 R308
MCF12102G900-T_4P U22@ 1M_0201_1% 2 3
1 4 G X'tal
1 4

1
2 2
U22@ 1 4 U22@
XTAL24_OUT_U22 R9464 1 2 33_0201_5% C205 X'tal G C206
U22@ 8.2P_0201_25V8D 24MHZ_8PF_8Y24080002 8.2P_0201_25V8D
1 1
U22@
C C

U58J @ SKL_ULT
TXC 8Y24080002
CLOCK SIGNALS

D42
[33] -PCIE0_CLK_100M CLKOUT_PCIE_N0 VCC1R0_SUS
C42
Media Card [33] PCIE0_CLK_100M
AR10 CLKOUT_PCIE_P0
[33] -CLKREQ_PCIE0 GPP_B5/SRCCLKREQ0#
B42
[32] -PCIE11_CLK_100M CLKOUT_PCIE_N1
A42 F43
WWAN [32] PCIE11_CLK_100M
AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43
[32] -CLKREQ_PCIE11 GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
D41 BA17
[32] -PCIE2_CLK_100M CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK_32K [32]
C41
WLAN [32] PCIE2_CLK_100M
AT8 CLKOUT_PCIE_P2 E37 XTAL24_IN_U22
[32] -CLKREQ_PCIE2 GPP_B7/SRCCLKREQ2# XTAL24_IN E35 XTAL24_OUT_U22
XTAL24_OUT

Vinafix.com
D40 2.74K_0201_1%
[52] -PCIE3_CLK_100M CLKOUT_PCIE_N3
C40 E42 1 2
LAN [52] PCIE3_CLK_100M
AT10 CLKOUT_PCIE_P3 XCLK_BIASREF R609 C348
[52] -CLKREQ_PCIE3 GPP_B8/SRCCLKREQ3# AM18 RTCX1 1 2
B40 RTCX1 AM20 RTCX2
[30] -PCIE4_CLK_100M CLKOUT_PCIE_N4 RTCX2
A40 6.8P_0201_25V8B
2280 SSD [30] PCIE4_CLK_100M CLKOUT_PCIE_P4

2
[30] -CLKREQ_PCIE4 AU8 AN18 -SRTCRST [61]
GPP_B9/SRCCLKREQ4# SRTCRST# AM16 R351 Y6
RTCRST# -RTCRST [61]
E40 10M_0402_5% 32.768KHZ_9PF_9H03280012
[49] -PCIE8_CLK_100M CLKOUT_PCIE_N5
E38
TBT [49] PCIE8_CLK_100M

1
AU7 CLKOUT_PCIE_P5
[49] -CLKREQ_PCIE8

1
GPP_B10/SRCCLKREQ5# C326
1 2
10 OF 20
6.8P_0201_25V8B
KBL-RU_BGA1356

TXC 9H03280012
KDS 1TJF090DJ1A000B
B B

U58T @ SKL-U

SPARE

AW69 F6
AW68 RSVD_AW69 RSVD_F6 E3 XTAL24_IN_U42
AU56 RSVD_AW68 RSVD_E3 C11
AW48 RSVD_AU56 RSVD_C11 B11
XTAL24_OUT_U42 C7 RSVD_AW48 RSVD_B11 A11
U12 RSVD_C7 RSVD_A11 D12
U11 RSVD_U12 RSVD_D12 C12
H11 RSVD_U11 RSVD_C12 F52
RSVD_H11 RSVD_F52

2
20 OF 20
Y7
R9569
U42@ 1M_0201_1% 2 3
KBL-RU_BGA1356 G X'tal

1
2 2
XTAL24_IN_U42 R9567 1 U42@ 2 33_0201_5% 1 4 U42@
XTAL24_OUT_U42R9568 1 2 33_0201_5% U42@ C8785 X'tal G C8784
U42@ 8.2P_0201_25V8D 24MHZ_8PF_8Y24080002 8.2P_0201_25V8D
1 1
U42@

TXC 8Y24080002

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU : CLOCK SIGNALS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 13 of 73
5 4 3 2 1
5 4 3 2 1

Change to SN74LVC1G17DRLRG4 (SA00006DR00)


VCC3M

U73
5 1
VCC NC
2 -PLTRST
D
33_0201_5% IN_A D
1 2 4 3
[30,32,33,45,46,49,52,53] -PLTRST_FAR OUT_Y GND
R993

SN74LVC1G17DRLRG4_SOT5

2
C46
100P_0201_25V8J
1

R9505 1 @ 2 0_0201_5%

-RSMRST

2 Removed will cause KB/TP


C8523 can't work after scan 8's
@ESD@ 100P_0201_25V8J
1 code in shell mode

VCC3M VCC3M VCC3B

BPWRG RTCVCC VCC3M


C
Can not remove C

10K_0201_5%
1K_0201_5%
4.7K_0201_5%
2

2
2

10K_0201_5%
C8525 R646

2
@ESD@ 100P_0201_25V8J 1M_0201_5%
1

1
1
R612

R491
R19

1
U58K @ SKL-U

1
R614
SYSTEM POWER MANAGEMENT
AT11 @TP196
GPP_B12/SLP_S0# AP15 PAD
GPD4/SLP_S3# -PCH_SLP_S3 [48,53]
AN10 BA16
GPP_B13/PLTRST# GPD5/SLP_S4# -PCH_SLP_S4 [53]

Vinafix.com
[20] -XDP_DBR B5 AY16
SYS_RESET# GPD10/SLP_S5# -PCH_SLP_S5 [53]
-RSMRST AY17
RSMRST# AN15
A68 SLP_SUS# AW15
PROCPWRGD SLP_LAN# -PCH_SLP_LAN [58]
EC_VCCST_PG B65 BB17 -PCH_SLP_WLAN
VCCST_PWRGD GPD9/SLP_WLAN# -PCH_SLP_WLAN [58]
AN16
GPD6/SLP_A# -PCH_SLP_M [53,58]
[53] BPWRG B6
BA20 SYS_PWROK BA15 -PWRSW_EC_R
[53] PCH_PWROK PCH_PWROK GPD3/PWRBTN#
PCH_DPWROK BB20 AY15 AC_PRESENT_R
DSW_PWROK GPD1/ACPRESENT AU13 -BATLOW
GPD0/BATLOW# -BATLOW [48,53]
-SUSWARN AR13
R1884 1 2 -SUSACK AP11 GPP_A13/SUSWARN#/SUSPWRDNACK
0_0201_5% @ GPP_A15/SUSACK# AU11
BB15 GPP_A11/PME# AP16 -INTRUDER
[32,48] -PCIE_WAKE WAKE# INTRUDER#
[52] -LANWAKE AM15
AW17 GPD2/LAN_WAKE# AM10
[52] LANPHYPC GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE#
AT15 AM11
GPD7/RSVD GPP_B2/VRALERT#
11 OF 20 2
@
VCC3M_PCH C7
KBL-RU_BGA1356
1000P_0201_25V7K
1
B B
R9481 2 @ 1 100K_0201_5% -PWRSW_EC_R

R9487 2 @ 1 10K_0201_5% AC_PRESENT_R

R9587 2 @ 1 8.2K_0201_5% -BATLOW S3


-TAMPER_SW_DTCT 1 3
[12] -TAMPER_SW_DTCT
@
0_0201_5% 1 2 R10
2 4

R9578 2 1 10K_0201_5% AC_PRESENT_R SPVR310100_4P

R9469 2 1 10K_0201_5% -RSMRST

R9470 2 @ 1 100K_0201_5% PCH_DPWROK

@
[53] AC_PRESENT AC_PRESENT R9486 2 1 0_0201_5% AC_PRESENT_R

@
[53] -PWRSW_EC -PWRSW_EC R9480 2 1 0_0201_5% -PWRSW_EC_R

@
[20,53] -RSMRST -RSMRST R9471 2 1 0_0201_5% PCH_DPWROK

VCCST
A From EC(open-drain) A
1

R95
1K_0201_5%
2

R96 1 2 60.4_0201_1% EC_VCCST_PG


[53] VCCST_PG_EC

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU : SYSTEM PM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 14 of 73
5 4 3 2 1
5 4 3 2 1

D D

VCC I (Max) : 32A (Dual Core)


64A (Qual Core)

VCCCPUCORE VCCCPUCORE

VCCST

U58L @ SKL-U
CPU POWER 1 OF 4

A30 G32
A34 VCC_A30 VCC_G32 G33
A39 VCC_A34 VCC_G33 G35
A44 VCC_A39 VCC_G35 G37
AK33 VCC_A44 VCC_G37 G38
AK35 VCC_AK33 VCC_G38 G40 VCCCPUCORE
AK37 VCC_AK35 VCC_G40 G42
VCC_AK37 VCC_G42

2
AK38 J30 @
AK40 VCC_AK38 VCC_J30 J33 R374 R782 R9319
AL33 VCC_AK40 VCC_J33 J37
VCC_AL33 VCC_J37 56_0201_5% 100_0201_5% 100_0201_5%
AL37 J40
VCC_AL37 VCC_J40

1
AL40 K33

1
AM32 VCC_AL40 VCC_K33 K35 R9
C C
AM33 VCC_AM32 VCC_K35 K37 VCCSTG 100_0201_1%
AM35 VCC_AM33 VCC_K37 K38
AM37 VCC_AM35 VCC_K38 K40

2
AM38 VCC_AM37 VCC_K40 K42
G30 VCC_AM38 VCC_K42 K43
VCC_G30 VCC_K43
K32 E32 VCC_SENSE
RSVD_K32 VCC_SENSE VCC_SENSE [64]
E33 VSS_SENSE
VSS_SENSE VSS_SENSE [64]
AK32 220_0201_5%
RSVD_AK32 B63 R781 1 2 -SVID_ALERT
VIDALERT# -SVID_ALERT [64]
AB62 A63 R9387 1 RF@ 2 22_0201_5% SVID_CLK
VCCOPC_AB62 VIDSCK SVID_CLK [64]
P62 D64 SVID_DATA
VCCOPC_P62 VIDSOUT SVID_DATA [64]
V62
VCCOPC_V62 G20
VCCSTG_G20

2
H63 2
VCC_OPC_1P8_H63 R70 @RF@
G61 100_0201_1% C8601
VCC_OPC_1P8_G61

Vinafix.com
12P_0201_25V8J
AC63 1

1
AE63 VCCOPC_SENSE
VSSOPC_SENSE
AE62
AG62 VCCEOPIO
VCCEOPIO
AL63
AJ62 VCCEOPIO_SENSE
VSSEOPIO_SENSE 12 OF 20

KBL-RU_BGA1356

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU : CPU POWER (1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 15 of 73
5 4 3 2 1
5 4 3 2 1

D VCCPLL VCCQC VCCPLL_OC D

VCCGFXCORE_I VCCST VCCSTG VCCST VCC1R2A VCC1R2A VCC1R2A VCC1R2A

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K
2 2 2 2

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K
1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

C8570

C8571

C8572

C8573
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

C8536
C2422

C2423

C2424

C2425

C1184

C1829

C1830

@ C1831

@ C1832

C2426

C2427
C835

@ C838

@ C840

@ C842

@ C844
VCCGT I (Max) :31A
VCCGFXCORE_I_VCCCPUCORE VCCGFXCORE_I VCCGFXCORE_I
VCCCPUIO

U58M @ SKL-U

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CPU POWER 2 OF 4
N70 3400mA
A48 VCCGT N71
2800mA 2 2 2 2
A53 VCCGT VCCGT R63 VCC1R2A VCCCPUIO
C C
A58 VCCGT VCCGT R64
A62 VCCGT VCCGT R65 1 1 1 1
VCCGT VCCGT

C8645

C8646

C8647

C8648
A66 R66
AA63 VCCGT VCCGT R67
AA64 VCCGT VCCGT R68
AA66 VCCGT VCCGT R69 U58N @ SKL-U
AA67 VCCGT VCCGT R70
VCCGT VCCGT CPU POWER 3 OF 4
AA69 R71
AA70 VCCGT VCCGT T62 AU23 AK28
AA71 VCCGT VCCGT U65 AU28 VDDQ_AU23 VCCIO AK30
AC64 VCCGT VCCGT U68 AU35 VDDQ_AU28 VCCIO AL30
VCCGT VCCGT VDDQ_AU35 VCCIO 4000mA
AC65 U71 AU42 AL42
AC66 VCCGT VCCGT W63 BB23 VDDQ_AU42 VCCIO AM28 VCCSA
AC67 VCCGT VCCGT W64 BB32 VDDQ_BB23 VCCIO AM30
AC68 VCCGT VCCGT W65 BB41 VDDQ_BB32 VCCIO AM42
AC69 VCCGT VCCGT W66 BB47 VDDQ_BB41 VCCIO
AC70 VCCGT VCCGT W67 VCCSTG VCCST BB51 VDDQ_BB47 AK23 VCCSA
VCCGT VCCGT VDDQ_BB51 VCCSA

Vinafix.com
AC71 W68 AK25
J43 VCCGT VCCGT W69 VCCSA G23
J45 VCCGT VCCGT W70 AM40 VCCSA G25
J46 VCCGT VCCGT W71 VDDQC VCCSA G27
VCCGT VCCGT VCCGFXCORE_X_VCCCPUCORE
130mA VCCSA
J48 Y62 A18 G28
VCCGT VCCGT VCCST VCCSA

2
J50 20mA J22
J52 VCCGT A22 VCCSA J23 R2154
J53 VCCGT AK42 VCCSTG_A22 VCCSA J27
VCCGT VCCGTX_AK42 VCCSA 100_0201_1%
J55 AK43 AL23 K23
J56 VCCGT VCCGTX_AK43 AK45 VCCPLL_OC VCCSA K25

1
J58 VCCGT VCCGTX_AK45 AK46 K20 VCCSA K27
J60 VCCGT VCCGTX_AK46 AK48 K21 VCCPLL_K20 VCCSA K28
K48 VCCGT VCCGTX_AK48 AK50 VCCPLL_K21 VCCSA K30
K50 VCCGT VCCGTX_AK50 AK52 VCCSA
0_0201_5%2 R9581 1 K52 VCCGT VCCGTX_AK52 AK53 AM23 VCCIO_SENSE
VCCGT VCCGTX_AK53 VCCIO_SENSE @ T101
@ K53 AK55 AM22 VSSIO_SENSE @ T102
K55 VCCGT VCCGTX_AK55 AK56 VSSIO_SENSE
K56 VCCGT VCCGTX_AK56 AK58 H21 VSSSA_SENSE
VCCGT VCCGTX_AK58 VSSSA_SENSE VSSSA_SENSE [64]
K58 AK60 H20 VCCSA_SENSE
VCCGT VCCGTX_AK60 VCCSA_SENSE [64]
K60 AK70 14 OF 20 VCCSA_SENSE
L62 VCCGT VCCGTX_AK70 AL43
L63 VCCGT VCCGTX_AL43 AL46
VCCGT VCCGTX_AL46 KBL-RU_BGA1356

2
B B
L64 AL50
VCCGFXCORE_I L65 VCCGT VCCGTX_AL50 AL53 R2155
L66 VCCGT VCCGTX_AL53 AL56
VCCGT VCCGTX_AL56 100_0201_1%
L67 AL60
L68 VCCGT VCCGTX_AL60 AM48

1
L69 VCCGT VCCGTX_AM48 AM50
L70 VCCGT VCCGTX_AM50 AM52
VCCGT VCCGTX_AM52
2

L71 AM53
R2152 M62 VCCGT VCCGTX_AM53 AM56
N63 VCCGT VCCGTX_AM56 AM58
100_0201_1% VCCGT VCCGTX_AM58
N64 AU58
N66 VCCGT VCCGTX_AU58 AU63
1

N67 VCCGT VCCGTX_AU63 BB57


N69 VCCGT VCCGTX_BB57 BB66
VCCGT VCCGTX_BB66
VCCGT_SENSE J70 AK62
[64] VCCGT_SENSE VCCGT_SENSE VCCGTX_SENSE
VSSGT_SENSE J69 AL61
[64] VSSGT_SENSE VSSGT_SENSE VSSGTX_SENSE
13 OF 20
KBL-RU_BGA1356
2

R2153
100_0201_1%
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU : CPU POWER (2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 16 of 73
5 4 3 2 1
5 4 3 2 1

VCC3M VCC3M_PCH
@ VCC3_SUS VCC1R8_SUS VCC1R0_SUS VCCPCHCORE
D VCCMPHY_GATE VCC1R0_SUS D
0_0603_5% @
R2485 1 2
0_0603_5%
R9325 1 2 2 2 @ 2 2
C2428 C2429 C2430 C2431
47U_0805_6.3V6M 47U_0805_6.3V6M 47U_0805_6.3V6M 47U_0805_6.3V6M
VCC1R0_SUS VCC1R0_SUS_PRIM
@ 1 1 1 1

0_0603_5%
R2486 1 2

VCCMPHY_GATE VCCMPHY_GATE_OUT
@

0_0603_5% VCC3_SUS
R2487 1 2

2 2 2 2
@RF@ @RF@ @RF@ @RF@
696mA C8622 C8623 C8624 C8625
68P_0201_25V8 2200P_0201_50V7K 68P_0201_25V8 2200P_0201_50V7K
VCCPCHCORE VCC1R0_SUS VCC1R0_SUS_PRIM VCC3_SUS 1 1 1 1

U58O @ SKL-U

CPU POWER 4 OF 4 VCC1R8_SUS


AB19
AB20 VCCPRIM_1P0 AK15
VCCPRIM_1P0 VCCPGPPA 20mA VCC3_SUS VCC1R0_SUS
P18 AG15 4mA
VCCPRIM_1P0 VCCPGPPB Y16 @
2574mA VCCPGPPC 6mA
AF18 Y15 8mA 200mA
C
FVT_C_EC013 AF19
V20
VCCPRIM_CORE
VCCPRIM_CORE
VCCPGPPD
VCCPGPPE
T16
AF16
6mA
161mA VCC1R0_SUS_PRIM
2 2 2 29mA R2304 1
0_0603_5%
2 C
VCCMPHY_GATE V21 VCCPRIM_CORE VCCPGPPF AD15 41mA
@
FVT_C_EC017 AL1
VCCPRIM_CORE VCCPGPPG
V19 200mA
C763
0.1U_0201_6.3V6K
C832
0.1U_0201_6.3V6K
C380
1U_0402_6.3V6K 2@ 2@
R2302 DCPDSW_1P0 VCCPRIM_3P3_V19 1 1 1 C2450 C2451
1 2 VCCMPHY_GATE_PLL VCCMPHY_GATE_OUT K17 T1 22U_0603_6.3V6M 22U_0603_6.3V6M
88mA 2 22mA VCCMPHYAON_1P0 VCCPRIM_1P0_T1 696mA
C620 L1
0_0603_5% 1U_0402_6.3V6K VCCMPHYAON_1P0 AA1 VCC1R0_SUS 1 1
VCCATS_1P8 6mA RTCVCC VCC1R0_SUS
2@ 2 1870mA N15
C2447 RF@ 1 N16 VCCMPHYGT_1P0_N15 AK17 @
1U_0402_6.3V6K C2437 N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3
VCC1R0_SUS P15 VCCMPHYGT_1P0_N17 AK19 0_0603_5%
1 1
0.1U_0402_16V4Z VCCMPHYGT_1P0_P15 VCCRTC_AK19 200mA
NEAR K15 P16 BB14 2 33mA R2305 1 2
VCC1R0_SUS VCCMPHYGT_1P0_P16 VCCRTC_BB14
K15 BB10 1 2 C731
RF@ RF@ L15 VCCAMPHYPLL_1P0 DCPRTC C795 1U_0402_6.3V6K
2 VCCAMPHYPLL_1P0 1 2@ 2@
C8615 L1 A14 35mA 0.1U_0201_6.3V6K C2452 C2453
1 2 VCC1R0_SUS_PLL V15 VCCCLK1 22U_0603_6.3V6M 22U_0603_6.3V6M
0.1U_0201_6.3V6K 26mA VCCAPLL_1P0

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K19
1 BLM15EG221SN1D_2P VCC3M_PCH AB17 VCCCLK2 1 1
Y18 VCCPRIM_1P0_AB17 L21 VCC1R0_SUS
2 RF@ VCCPRIM_1P0_Y18 VCCCLK3 24mA
C2449 @
VCC3_SUS VCC3_SUS AD17 N20 R2306
0.1U_0201_6.3V6K 118mA VCCDSW_3P3_AD17 VCCCLK4
AD18 0_0603_5%
Close to L1 L2 1 AJ17 VCCDSW_3P3_AD18 L19 4mA 1 2
VCCDSW_3P3_AJ17 VCCCLK5
1 2 40mA AJ19 A10 39mA
MURATA BLM15EG221SN1D SM01000HC00 VCCHDA VCCCLK6
2@ 2@
11mA AJ16 AN11 C2454 C2455
RF@ 2
C8613
R_0402
2 RF@
C8612 642mA AF20
VCCSPI GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
AN13 22U_0603_6.3V6M 22U_0603_6.3V6M FVT_C_EC013
AF21 VCCSRAM_1P0 1 1
0.1U_0201_6.3V6K 0.1U_0201_6.3V6K VCCSRAM_1P0
T19
1 1 T20 VCCSRAM_1P0
VCCSRAM_1P0
75mA AJ21
VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
33mA N18
B VCCAPLLEBB 15 OF 20 B
2
C8530
KBL-RU_BGA1356
0.1U_0201_6.3V6K
1

VCC1R0_SUS_PRIM VCC1R0_SUS VCCPCHCORE VCC3_SUS VCCMPHY_GATE_OUT VCCMPHY_GATE_OUT VCC3_SUS VCC1R8_SUS VCC1R0_SUS

2@ 2 2@ 2@ 2 2@ 2@ 2 2@ 2@ 2@ 2@ 2 2@
C2432 C2433 C2434 C821 C2435 C2436 C2438 C2439 C2440 C2441 C2442 C2443 C2444 C2445
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 47U_0805_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1
NEAR AB19 NEAR K17 NEAR AF18 NEAR AJ19 NEAR N15 NEAR N15 NEAR AF20 NEAR N18 NEAR AG15 NEAR Y16 NEAR T16 NEAR V19 NEAR AA1 NEAR A10

VCC3M VCC5M VCC3M VCC5M VCC3M VCC5M VCCGFXCORE_I VCC5M


C8808 C8810 C8813 C8815

Reserved for RF 2 1

0.1U_0402_16V4Z
2 1

0.1U_0402_16V4Z
2 1

1U_0402_6.3V6K
2 1

1U_0402_6.3V6K
A RF@ RF@ @RF@ @RF@ A
VCC3B VCC5M VCC3M VCC3M VCC3M VCC1R8_SUS VCC1R8_SUS VCC1R8_SUS VCC1R8_SUS VCC5M
VCC3M VCC5M VCC3M VCC5M VCC3B VCC5M VCC3M VCCGFXCORE_I
C8811 C8812 C8814 C8816

2 2 2 2 @RF@ 2 2 @RF@ 2 @RF@ 2 @RF@ 2 @RF@ 2 2 1 2 1 2 1 2 1


RF@ RF@ RF@ C8802 RF@ C8804 C8805 C8806 C8807 @RF@
C8799 C8800 C8801 1U_0402_6.3V6K C8803 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K C8809
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0201_6.3V6K
1 1 1 1 1 1 1 1 1 1 @RF@ @RF@ @RF@ @RF@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU : PCH POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 17 of 73
5 4 3 2 1
5 4 3 2 1

D D

U58P SKL-U @ U58Q SKL-U @


U58R SKL-U @
GND 1 OF 3 GND 2 OF 3
GND 3 OF 3
A5 AL65 AT63 BA49 F8 L18
A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AB18 VSS VSS AM55 AV68 VSS VSS BB30 G58 VSS VSS N6
AB21 VSS VSS AM60 AV69 VSS VSS BB34 G6 VSS VSS N65
AB8 VSS VSS AM61 AV70 VSS VSS BB38 G60 VSS VSS N68
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
C C
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE65 VSS VSS AN33 AW26 VSS VSS C25 J28 VSS VSS T18
AE66 VSS VSS AN35 AW28 VSS VSS C5 J32 VSS VSS T2
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF2 VSS VSS AP18 AW45 VSS VSS D30 K61 VSS VSS U69
VSS VSS VSS VSS VSS VSS

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AF4 AP20 AW47 D34 K63 U70
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
AG19 VSS VSS AP38 AW57 VSS VSS D48 K68 VSS VSS W6
AG20 VSS VSS AP42 AW6 VSS VSS D53 K70 VSS VSS W9
AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15 18 OF 20
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21
VSS VSS VSS VSS KBL-RU_BGA1356
AJ20 AR28 B22 E46
AJ4 VSS VSS AR35 B30 VSS VSS E50
AK11 VSS VSS AR42 B34 VSS VSS E53
AK16 VSS VSS AR43 B39 VSS VSS E56
AK18 VSS VSS AR45 B44 VSS VSS E6
AK21 VSS VSS AR46 B48 VSS VSS E65
B
AK22 VSS VSS AR48 B53 VSS VSS E71 B
AK27 VSS VSS AR5 B58 VSS VSS F1
AK63 VSS VSS AR50 B62 VSS VSS F13
AK68 VSS VSS AR52 B66 VSS VSS F2
AK69 VSS VSS AR53 B71 VSS VSS F22
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL28 VSS VSS AR63 BA14 VSS VSS F28
AL32 VSS VSS AR8 BA18 VSS VSS F32
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL38 VSS VSS AT20 BA23 VSS VSS F35
AL4 VSS VSS AT23 BA28 VSS VSS F37
AL45 VSS VSS AT28 BA32 VSS VSS F38
AL48 VSS VSS AT35 BA36 VSS VSS F4
AL52 VSS VSS AT4 F68 VSS VSS F40
AL55 VSS VSS AT42 BA45 VSS VSS F42
AL58 VSS VSS AT56 VSS VSS BA41
AL64 VSS VSS AT58 VSS
VSS VSS
16 OF 20 17 OF 20

KBL-RU_BGA1356 KBL-RU_BGA1356

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU : GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 18 of 73
5 4 3 2 1
5 4 3 2 1

D D

TABLE

CFG0 : Stall Reset Sequence


after PCU PLL Lock until de-asserted
1 : No Stall
0 : Stall

CFG3 : MSR Privacy Bit Feature


1 : MSR (C80h) bit[0] setting
0 : MSR (C80h) bit[0] overridden

CFG4 : eDP Enable


1 : Disabled
0 : Enabled

CFG9 : SVID Bus Communication


1 : Enabled
0 : Disabled

U58S @ SKL-U

RESERVED SIGNALS-1

E68 BB68
B67 CFG[0] RSVD_TP_BB68 BB69
C C
D65 CFG[1] RSVD_TP_BB69
D67 CFG[2] AK13
[20] CFG3 CFG[3] RSVD_TP_AK13
E70 AK12
C68 CFG[4] RSVD_TP_AK12
D68 CFG[5] BB2
C67 CFG[6] RSVD_BB2 BA3
F71 CFG[7] RSVD_BA3
G69 CFG[8]
F70 CFG[9] AU5
G68 CFG[10] TP5 AT5
H70 CFG[11] TP6
CFG[12]
1K_0201_5%

1K_0201_5%

1K_0201_5%

G71
CFG[13]
2

H69 D5
G70 CFG[14] RSVD_D5 D4
CFG[15] RSVD_D4 B2
E63 RSVD_B2 C2
F63 CFG[16] RSVD_C2
@ 1

@ 1

CFG[17]

Vinafix.com
R1892

R8965

R1891

B3
E66 RSVD_B3 A3
F66 CFG[18] RSVD_A3
49.9_0201_1% CFG[19] AW1
1 2 E60 RSVD_AW1
R8898 CFG_RCOMP E1
E8 RSVD_E1 E2
[20] ITP_PMODE ITP_PMODE RSVD_E2
AY2 BA4
AY1 RSVD_AY2 RSVD_BA4 BB4
RSVD_AY1 RSVD_BB4
D1 A4
D3 RSVD_D1 RSVD_A4 C4
RSVD_D3 RSVD_C4
K46 BB5
K45 RSVD_K46 TP4
RSVD_K45 A69
AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69 @
RSVD_AL27 AY3 R2287 2 1 0_0201_5%
C71 RSVD_AY3
B70 RSVD_C71 D71
B RSVD_B70 RSVD_D71 C70 B
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54 VCCST
BA70 AY4
BA68 RSVD_TP_BA70 TP1 BB3
RSVD_TP_BA68 TP2 @
J71 AY71 R2288 2 1 0_0201_5%
J68 RSVD_J71 VSS_AY71 AR56
RSVD_J68 ZVM#
F65 AW71
G65 VSS_F65 RSVD_TP_AW71 AW70
VSS_G65 RSVD_TP_AW70
F61 AP56
RSVD_F61 MSM#

@
E61 C64 1 2
RSVD_E61 PROC_SELECT# R2289 100K_0201_5%
19 OF 20

KBL-RU_BGA1356 FVT_C_EC010

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU : CFG/RESERVED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 19 of 73
5 4 3 2 1
5 4 3 2 1

D D

VCC1R0_SUS VCCST VCC1R0_SUS

51_0201_5%
1.5K_0201_5%
2

0.1U_0201_6.3V6K
XDP@
XDP@ XDP@
1

C8320
1

1
R588

R475
JXDP1
28
27 GND
XDP_TCK0 26 GND
[7] XDP_TCK0 26
25
PCH_TCK R9385 1 XDP@ 2 0_0201_5% 24 25
[7] PCH_TCK 24
XDP_TMS 23
[7] XDP_TMS 23
XDP_TDI 22
[7] XDP_TDI 22
-XDP_TRST 21
[7] -XDP_TRST 21
XDP_TDO 20
[7] XDP_TDO 20
19
-XDP_DBR 18 19
[14] -XDP_DBR 18
ITP_PMODE 17
[19] ITP_PMODE 17
16
15 16
14 15
13 14
C C
12 13
XDP@ 11 12
-RSMRST R594 1 2 10 11
[14,53] -RSMRST 10
1K_0201_5% 9
8 9
[19] CFG3 8
7
6 7
5 6
4 5
3 4
-XDP_PRDY 2 3
[11] -XDP_PRDY 2
-XDP_PREQ 1
[11] -XDP_PREQ 1
ACES_51522-02601-001
ME@

Vinafix.com
TABLE

Logic Ref Des Merged DCI 2.0


Page 7 R2559 ASM NO_ASM

Page 18 R1982 ASM NO_ASM


B B
J8 ASM NO_ASM
C8320 ASM NO_ASM
R475 ASM ASM
Page 19 R491 ASM ASM
R588 ASM NO_ASM
R594 ASM NO_ASM

R2494 ASM NO_ASM

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
XDP CONNECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 20 of 73
5 4 3 2 1
5 4 3 2 1

D D

VCC3_SUS

16MB SOIC8
WINBOND W25Q128JVSIQ

2
MACRONIX MX25L12873FM2I-10G

3.3K_0201_5%

3.3K_0201_5%
0.1U_0201_6.3V6K
C C

2
10K_0201_5%
2
@ C629

1
1

R706

R703
1
R2342
U49
-SPI_CS0 R322 1 2 33_0201_5% -SPI_CS0_R 1 8
[8] -SPI_CS0 /CS VCC
SPI_MISO_IO1 R694 1 2 33_0201_5% SPI_MISO_IO1_0_R 2 7 SPI_IO3_0_R R8981 1 2 33_0201_5% SPI_IO3
[8,45] SPI_MISO_IO1 DO(IO1) /HOLD(IO3) SPI_IO3 [8]
3 6 SPI_CLK_0_R R681 2 1 33_0201_5% SPI_CLK SPI_CLK [8,45]
4 /WP(IO2) CLK 5 SPI_MOSI_IO0_0_R R674 2 1 33_0201_5% SPI_MOSI_IO0
GND DI(IO0) SPI_MOSI_IO0 [8,45]
W25Q128JVSIQ_SO8
SPI_IO2_0_R R8980 1 2 33_0201_5% SPI_IO2
SPI_IO2 [8]

Vinafix.com Change to W25Q128JVSIQ (SA00005VV20)

TABLE

SF100 PIN HEADER INTERFACE (TOP VIEW)


B B

1 VCC D12.1 GND GND 2


3 CS# R322.2 R681.2 CLK 4
5 MISO R694.2 R674.2 MOSI 6
7 (KEY) N/A N/A (RESET) 8

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SPI FLASH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 21 of 73
5 4 3 2 1
A B C D E

VCC2R5A M_A_VREF_CA

[5,6] DDR_A_D[63:0]
2 2 2 2 2 2 2 2 2 2 1 1 1 1
[5,6] -DDR_A_DQS[7:0] C2623 C2624
C2552 C2553 C2554 C2555 C2619 C2620 C2621 C2622 C2556 C2557 C2558 C2559
0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 10U_0402_6.3V6M 10U_0402_6.3V6M 0.047U_0201_10V6K 0.047U_0201_10V6K 0.047U_0201_10V6K 0.047U_0201_10V6K
[5,6] DDR_A_DQS[7:0] 1 1 1 1 1 1 1 1 1 1 2 2 2 2

[5,23] DDR_A_MA[16:0]
1 1

M_A_VREF_CA
M_A_VREF_CA M_A_VREF_CA M_A_VREF_CA

VCC1R2A VCC2R5A VCC1R2A


VCC1R2A VCC2R5A VCC1R2A VCC1R2A VCC2R5A VCC1R2A VCC1R2A VCC2R5A VCC1R2A

U125
U126 U127 U128
DDR_A_D18 D7 B1
DDR_A_D17 D3 DQU7 VPP_B1 R9 DDR_A_D24 D7 B1 DDR_A_D52 D7 B1 DDR_A_D59 D7 B1
DDR_A_D23 C8 DQU6 VPP_R9 DDR_A_D26 D3 DQU7 VPP_B1 R9 DDR_A_D55 D3 DQU7 VPP_B1 R9 DDR_A_D57 D3 DQU7 VPP_B1 R9
DDR_A_D16 C2 DQU5 M1 DDR_A_D25 C8 DQU6 VPP_R9 DDR_A_D53 C8 DQU6 VPP_R9 DDR_A_D58 C8 DQU6 VPP_R9
DDR_A_D19 C7 DQU4 VREFCA DDR_A_D30 C2 DQU5 M1 DDR_A_D51 C2 DQU5 M1 DDR_A_D60 C2 DQU5 M1
DDR_A_D21 C3 DQU3 B3 DDR_A_D28 C7 DQU4 VREFCA DDR_A_D49 C7 DQU4 VREFCA DDR_A_D63 C7 DQU4 VREFCA
DDR_A_D22 B8 DQU2 VDD_B3 B9 DDR_A_D29 C3 DQU3 B3 DDR_A_D54 C3 DQU3 B3 DDR_A_D56 C3 DQU3 B3
DDR_A_D20 A3 DQU1 VDD_B9 D1 DDR_A_D31 B8 DQU2 VDD_B3 B9 DDR_A_D48 B8 DQU2 VDD_B3 B9 DDR_A_D62 B8 DQU2 VDD_B3 B9
DQU0 VDD_D1 G7 DDR_A_D27 A3 DQU1 VDD_B9 D1 DDR_A_D50 A3 DQU1 VDD_B9 D1 DDR_A_D61 A3 DQU1 VDD_B9 D1
DDR_A_DQS2 B7 VDD_G7 J1 DQU0 VDD_D1 G7 DQU0 VDD_D1 G7 DQU0 VDD_D1 G7
-DDR_A_DQS2 A7 DQSU_T VDD_J1 J9 DDR_A_DQS3 B7 VDD_G7 J1 DDR_A_DQS6 B7 VDD_G7 J1 DDR_A_DQS7 B7 VDD_G7 J1
DQSU_C VDD_J9 L1 -DDR_A_DQS3 A7 DQSU_T VDD_J1 J9 -DDR_A_DQS6 A7 DQSU_T VDD_J1 J9 -DDR_A_DQS7 A7 DQSU_T VDD_J1 J9
E2 VDD_L1 L9 DQSU_C VDD_J9 L1 DQSU_C VDD_J9 L1 DQSU_C VDD_J9 L1
DMU#/DBIU# VDD_L9 R1 E2 VDD_L1 L9 E2 VDD_L1 L9 E2 VDD_L1 L9
VDD_R1 T9 DMU#/DBIU# VDD_L9 R1 DMU#/DBIU# VDD_L9 R1 DMU#/DBIU# VDD_L9 R1
VDD_T9 VDD_R1 T9 VDD_R1 T9 VDD_R1 T9
DDR_A_D14 J7 A1 VDD_T9 VDD_T9 VDD_T9
DDR_A_D13 J3 DQL7 VDDQ_A1 A9 DDR_A_D5 J7 A1 DDR_A_D32 J7 A1 DDR_A_D46 J7 A1
DDR_A_D15 H8 DQL6 VDDQ_A9 C1 DDR_A_D2 J3 DQL7 VDDQ_A1 A9 DDR_A_D33 J3 DQL7 VDDQ_A1 A9 DDR_A_D40 J3 DQL7 VDDQ_A1 A9
DDR_A_D8 H2 DQL5 VDDQ_C1 D9 DDR_A_D1 H8 DQL6 VDDQ_A9 C1 DDR_A_D35 H8 DQL6 VDDQ_A9 C1 DDR_A_D47 H8 DQL6 VDDQ_A9 C1
DDR_A_D10 H7 DQL4 VDDQ_D9 F2 DDR_A_D3 H2 DQL5 VDDQ_C1 D9 DDR_A_D34 H2 DQL5 VDDQ_C1 D9 DDR_A_D41 H2 DQL5 VDDQ_C1 D9
DDR_A_D9 H3 DQL3 VDDQ_F2 F8 DDR_A_D4 H7 DQL4 VDDQ_D9 F2 DDR_A_D37 H7 DQL4 VDDQ_D9 F2 DDR_A_D43 H7 DQL4 VDDQ_D9 F2
DDR_A_D11 F7 DQL2 VDDQ_F8 G1 DDR_A_D7 H3 DQL3 VDDQ_F2 F8 DDR_A_D39 H3 DQL3 VDDQ_F2 F8 DDR_A_D45 H3 DQL3 VDDQ_F2 F8
DDR_A_D12 G2 DQL1 VDDQ_G1 G9 DDR_A_D0 F7 DQL2 VDDQ_F8 G1 DDR_A_D36 F7 DQL2 VDDQ_F8 G1 DDR_A_D42 F7 DQL2 VDDQ_F8 G1
2 2
DQL0 VDDQ_G9 J2 DDR_A_D6 G2 DQL1 VDDQ_G1 G9 DDR_A_D38 G2 DQL1 VDDQ_G1 G9 DDR_A_D44 G2 DQL1 VDDQ_G1 G9
DDR_A_DQS1 G3 VDDQ_J2 J8 DQL0 VDDQ_G9 J2 DQL0 VDDQ_G9 J2 DQL0 VDDQ_G9 J2
-DDR_A_DQS1 F3 DQSL_T VDDQ_J8 DDR_A_DQS0 G3 VDDQ_J2 J8 DDR_A_DQS4 G3 VDDQ_J2 J8 DDR_A_DQS5 G3 VDDQ_J2 J8
DQSL_C -DDR_A_DQS0 F3 DQSL_T VDDQ_J8 -DDR_A_DQS4 F3 DQSL_T VDDQ_J8 -DDR_A_DQS5 F3 DQSL_T VDDQ_J8
E7 A2 DQSL_C DQSL_C DQSL_C
DML#/DBIL# VSSQ_A2 A8 E7 A2 E7 A2 E7 A2
VSSQ_A8 C9 DML#/DBIL# VSSQ_A2 A8 DML#/DBIL# VSSQ_A2 A8 DML#/DBIL# VSSQ_A2 A8
VSSQ_C9 D2 VSSQ_A8 C9 VSSQ_A8 C9 VSSQ_A8 C9
DDR_A_CLK0 K7 VSSQ_D2 D8 VSSQ_C9 D2 VSSQ_C9 D2 VSSQ_C9 D2
-DDR_A_CLK0 K8 CK_T VSSQ_D8 E3 DDR_A_CLK0 K7 VSSQ_D2 D8 DDR_A_CLK0 K7 VSSQ_D2 D8 DDR_A_CLK0 K7 VSSQ_D2 D8
CK_C VSSQ_E3 E8 -DDR_A_CLK0 K8 CK_T VSSQ_D8 E3 -DDR_A_CLK0 K8 CK_T VSSQ_D8 E3 -DDR_A_CLK0 K8 CK_T VSSQ_D8 E3
DDR_A_CKE0 K2 VSSQ_E8 F1 CK_C VSSQ_E3 E8 CK_C VSSQ_E3 E8 CK_C VSSQ_E3 E8
[5,23] DDR_A_CKE0 CKE VSSQ_F1 VSSQ_E8 VSSQ_E8 VSSQ_E8
H1 DDR_A_CKE0 K2 F1 DDR_A_CKE0 K2 F1 DDR_A_CKE0 K2 F1
-DDR_A_CS0 L7 VSSQ_H1 H9 CKE VSSQ_F1 H1 CKE VSSQ_F1 H1 CKE VSSQ_F1 H1
[5,23] -DDR_A_CS0 CS# VSS_H9 VSSQ_H1 VSSQ_H1 VSSQ_H1
-DDR_A_CS0 L7 H9 -DDR_A_CS0 L7 H9 -DDR_A_CS0 L7 H9
DDR_A_ODT0 K3 B2 CS# VSS_H9 CS# VSS_H9 CS# VSS_H9
[5,23] DDR_A_ODT0 ODT VSS_B2 E1 DDR_A_ODT0 K3 B2 DDR_A_ODT0 K3 B2 DDR_A_ODT0 K3 B2
VSS_E1 ODT VSS_B2 ODT VSS_B2 ODT VSS_B2

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[5,23] -DDR_A_ACT -DDR_A_ACT L3 G8 E1 E1 E1
ACT# VSS_G8 K1 -DDR_A_ACT L3 VSS_E1 G8 -DDR_A_ACT L3 VSS_E1 G8 -DDR_A_ACT L3 VSS_E1 G8
DDR_A_BG1_R M9 VSS_K1 K9 ACT# VSS_G8 K1 ACT# VSS_G8 K1 ACT# VSS_G8 K1
DDR_A_BG0 M2 BG1_VSS VSS_K9 N1 DDR_A_BG1_R M9 VSS_K1 K9 DDR_A_BG1_R M9 VSS_K1 K9 DDR_A_BG1_R M9 VSS_K1 K9
[5,23] DDR_A_BG0 BG0 VSS_N1 BG1_VSS VSS_K9 BG1_VSS VSS_K9 BG1_VSS VSS_K9
T1 DDR_A_BG0 M2 N1 DDR_A_BG0 M2 N1 DDR_A_BG0 M2 N1
DDR_A_BA1 N8 VSS_T1 BG0 VSS_N1 T1 BG0 VSS_N1 T1 BG0 VSS_N1 T1
[5,23] DDR_A_BA1 BA1 VSS_T1 VSS_T1 VSS_T1
[5,23] DDR_A_BA0 DDR_A_BA0 N2 T7 DDR_A_BA1 N8 DDR_A_BA1 N8 DDR_A_BA1 N8
BA0 VSS_NC DDR_A_BA0 N2 BA1 T7 DDR_A_BA0 N2 BA1 T7 DDR_A_BA0 N2 BA1 T7
DDR_A_MA16 L8 BA0 VSS_NC BA0 VSS_NC BA0 VSS_NC
DDR_A_MA15 M8 A16/RAS# DDR_A_MA16 L8 DDR_A_MA16 L8 DDR_A_MA16 L8
DDR_A_MA14 L2 A15/CAS# DDR_A_MA15 M8 A16/RAS# DDR_A_MA15 M8 A16/RAS# DDR_A_MA15 M8 A16/RAS#
A14/WE# DDR_A_MA14 L2 A15/CAS# DDR_A_MA14 L2 A15/CAS# DDR_A_MA14 L2 A15/CAS#
DDR_A_MA13 T8 A14/WE# A14/WE# A14/WE#
DDR_A_MA12 M7 A13 DDR_A_MA13 T8 DDR_A_MA13 T8 DDR_A_MA13 T8
DDR_A_MA11 T2 A12/BC# DDR_A_MA12 M7 A13 DDR_A_MA12 M7 A13 DDR_A_MA12 M7 A13
DDR_A_MA10 M3 A11 P1 -DRAMRST DDR_A_MA11 T2 A12/BC# DDR_A_MA11 T2 A12/BC# DDR_A_MA11 T2 A12/BC#
DDR_A_MA9 R7 A10/AP RESET# DDR_A_MA10 M3 A11 P1 -DRAMRST DDR_A_MA10 M3 A11 P1 -DRAMRST DDR_A_MA10 M3 A11 P1 -DRAMRST
DDR_A_MA8 R2 A9 T3 DDR_A_PAR DDR_A_MA9 R7 A10/AP RESET# DDR_A_MA9 R7 A10/AP RESET# DDR_A_MA9 R7 A10/AP RESET#
DDR_A_MA7 R8 A8 PARITY DDR_A_MA8 R2 A9 T3 DDR_A_PAR DDR_A_MA8 R2 A9 T3 DDR_A_PAR DDR_A_MA8 R2 A9 T3 DDR_A_PAR
DDR_A_MA6 P2 A7 P9 -DDR_A_ALERT DDR_A_MA7 R8 A8 PARITY DDR_A_MA7 R8 A8 PARITY DDR_A_MA7 R8 A8 PARITY
DDR_A_MA5 P8 A6 ALERT# DDR_A_MA6 P2 A7 P9 -DDR_A_ALERT DDR_A_MA6 P2 A7 P9 -DDR_A_ALERT DDR_A_MA6 P2 A7 P9 -DDR_A_ALERT
DDR_A_MA4 N3 A5 E9 DDR_A_MA5 P8 A6 ALERT# DDR_A_MA5 P8 A6 ALERT# DDR_A_MA5 P8 A6 ALERT#
3
DDR_A_MA3 N7 A4 ZQU_VSS DDR_A_MA4 N3 A5 E9 DDR_A_MA4 N3 A5 E9 DDR_A_MA4 N3 A5 E9 3
DDR_A_MA2 R3 A3 F9 DDR_A_MA3 N7 A4 ZQU_VSS DDR_A_MA3 N7 A4 ZQU_VSS DDR_A_MA3 N7 A4 ZQU_VSS
DDR_A_MA1 P7 A2 ZQL_ZQ DDR_A_MA2 R3 A3 F9 DDR_A_MA2 R3 A3 F9 DDR_A_MA2 R3 A3 F9
DDR_A_MA0 P3 A1 N9 DDR_A_MA1 P7 A2 ZQL_ZQ DDR_A_MA1 P7 A2 ZQL_ZQ DDR_A_MA1 P7 A2 ZQL_ZQ
A0 96-BALL TEN DDR_A_MA0 P3 A1 N9 DDR_A_MA0 P3 A1 N9 DDR_A_MA0 P3 A1 N9
SDRAM DDR4 A0 96-BALL TEN A0 96-BALL TEN A0 96-BALL TEN
SDRAM DDR4 SDRAM DDR4 SDRAM DDR4
2

MT40A1G16HBA-083E-A_FBGA96
2

2
X76@ MT40A1G16HBA-083E-A_FBGA96 MT40A1G16HBA-083E-A_FBGA96 MT40A1G16HBA-083E-A_FBGA96
2

R9009 R9010 X76@ X76@ X76@


2

2
R2549 243_0201_1% 243_0201_1% R9011 R9012 R9013 R9014 R9015 R9016
X76@ 0_0201_5% X76@ R2550 243_0201_1% 243_0201_1% R2551 243_0201_1% 243_0201_1% R2552 243_0201_1% 243_0201_1%
1

X76@ 0_0201_5% X76@ X76@ 0_0201_5% X76@ X76@ 0_0201_5% X76@


1

1
1

1
TABLE For RF shielding case
CLIP1 CLIP2 CLIP3 CLIP4 CLIP5 CLIP6 CLIP7 CLIP8 CLIP9 CLIP10 CLIP11 CLIP12
DDR_A_CLK0 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
[5,23] DDR_A_CLK0 SDP DDP

R2549 ASM NA ME@ ME@ ME@ ME@ ME@ ME@ ME@ ME@ ME@ ME@ ME@ ME@

1
-DDR_A_CLK0 R2550 ASM NA
[5,23] -DDR_A_CLK0
R2551 ASM NA
R2552 ASM NA

0_0201_5%
DDR_A_BG1 1 2 DDR_A_BG1_R
[5] DDR_A_BG1
R2553 X76@
DDR_A_BG1_R [23] R2553 NA ASM
CLIP13 CLIP14 CLIP15 CLIP16 CLIP17 CLIP18 CLIP19 CLIP20 CLIP21 CLIP22 CLIP23 CLIP24
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
4 R9041 NA ASM 4

ME@ ME@ ME@ ME@ ME@ ME@ ME@ ME@ ME@ ME@ ME@ ME@

1
[6,24] -DRAMRST -DRAMRST
R9010 0_5% 243_1%
R9012 0_5% 243_1%
[5,23] DDR_A_PAR
DDR_A_PAR 2 R9014 0_5% 243_1%
@ R9016 0_5% 243_1%
C1063
0.1U_0201_6.3V6K
-DDR_A_ALERT 1 Security Classification Compal Secret Data Compal Electronics, Inc.
[5,23] -DDR_A_ALERT
Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4 BASE MEMORY CH-A (1/2)
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 22 of 73
A B C D E
5 4 3 2 1

FVT_C_EC006 VCC1R2A

[5,22] DDR_A_MA[16:0]
VCC0R6B

DDR_A_MA16 1 X76A@ 2

2
R2555 36_0201_1%
DDR_A_MA15 1 X76A@ 2 C428 C242 C534 C537 C540 C425 C426 C427
R9025 36_0201_1% 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

1
DDR_A_MA14 1 X76A@ 2
R9026 36_0201_1%
DDR_A_MA13 1 X76A@ 2
D D
R9027 36_0201_1%
DDR_A_MA12 1 X76A@ 2
R9028 36_0201_1%
DDR_A_MA11 1 X76A@ 2
R9029 36_0201_1%
DDR_A_MA10 1 X76A@ 2
R9030 36_0201_1%
DDR_A_MA9 1 X76A@ 2
R9031 36_0201_1%
DDR_A_MA8 1 X76A@ 2
R9032 36_0201_1%
DDR_A_MA7 1 X76A@ 2 VCC1R2A
R9033 36_0201_1%
DDR_A_MA6 1 X76A@ 2
R9034 36_0201_1%
DDR_A_MA5 1 X76A@ 2
R9035 36_0201_1%
DDR_A_MA4 1 X76A@ 2
R9036 36_0201_1%
DDR_A_MA3 1 X76A@ 2
R9037 36_0201_1%

2
DDR_A_MA2 1 X76A@ 2
R9038 36_0201_1% C2625 C2626 C2627 C2628 C2629 C2630 C2631 C2632
DDR_A_MA1 1 X76A@ 2 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

1
R9039 36_0201_1%
DDR_A_MA0 1 X76A@ 2
R9040 36_0201_1%
DDR_A_BG1_R 1 X76@ 2
[22] DDR_A_BG1_R
R9041 36_0201_1%
DDR_A_BG0 1 X76A@ 2
[5,22] DDR_A_BG0
R9042 36_0201_1%
DDR_A_BA1 1 X76A@ 2
[5,22] DDR_A_BA1
R9043 36_0201_1%
DDR_A_BA0 1 X76A@ 2
[5,22] DDR_A_BA0
R9044 36_0201_1%
-DDR_A_ACT 1 X76A@ 2
[5,22] -DDR_A_ACT
R9045 36_0201_1%
DDR_A_PAR 1 X76A@ 2
[5,22] DDR_A_PAR
R9046 36_0201_1% VCC1R2A
C -DDR_A_CS0 1 X76A@ 2 C
[5,22] -DDR_A_CS0
R9047 36_0201_1%
DDR_A_ODT0 1 X76A@ 2
[5,22] DDR_A_ODT0
R9048 36_0201_1%
DDR_A_CKE0 1 X76A@ 2
[5,22] DDR_A_CKE0
R9049 36_0201_1%

2 2 2 2 2 2 2 2
C479 C481 C485 C489 C497 C503 C517 C524
X76A@ 10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
DDR_A_CLK0 1 2 1 1 1 1 1 1 1 1
[5,22] DDR_A_CLK0
R9050 36_0201_1%

X76A@
-DDR_A_CLK0 1 2
[5,22] -DDR_A_CLK0
R9051 36_0201_1%

[5,22] -DDR_A_ALERT
-DDR_A_ALERT
R2554
1 2
49.9_0201_1%
VCC1R2A

VCC1R2A
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2 2 2 2 2 2 2 2 2 2 2 2
C8544 C8545 C8546 C8547 C8548 C8549 C8550 C8551 C8552 C8553 C8554 C8555
100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J
1 1 1 1 1 1 1 1 1 1 1 1

B B

VCC1R2A

2
R1889
1.82K_0201_1% M_A_VREF_CA

VCC0R6B VCC0R6B X76A@

1
2.7_0201_1%

1 2
[5] +0.6V_A_VREFDQ
R1110
X76A@

2 2 2 2 2 2 2 2 2 2 2 2

2
C8556 C8557 C411 C466 C31 C87 C100 C103 C2633 C2634 C2635 C2636 2
10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K R1890
1 1 1 1 1 1 1 1 1 1 1 1 C1602 1.82K_0201_1%
0.022U_0201_10V6K
1 X76A@

1
X76A@

2
R1111
VCC0R6B VCC0R6B 24.9_0201_1%

1
X76A@
A A

2 2 2 2 2 2 2 2 2 2 2 2
C8569 C8568 C8567 C8566 C8565 C8564 C8563 C8562 C8561 C8560 C8559 C8558
100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4 BASE MEMORY CH-A (2/2)
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 23 of 73
5 4 3 2 1
A B C D E

VCC2R5A M_B_VREF_CA

2 2 2 2 2 2 2 2 2 2 1 1 1 1
[5,6] DDR_B_D[63:0] C8694 C8699
C8691 C8692 C8697 C8693 C8687 C8700 C8696 C8702 C8701 C8688 C8698 C8690
0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 10U_0402_6.3V6M 10U_0402_6.3V6M 0.047U_0201_10V6K 0.047U_0201_10V6K 0.047U_0201_10V6K 0.047U_0201_10V6K
[5,6] -DDR_B_DQS[7:0] 1 1 1 1 1 1 1 1 1 1 2 2 2 2

[5,6] DDR_B_DQS[7:0]

[6,25] DDR_B_MA[16:0]
1 1

M_B_VREF_CA
M_B_VREF_CA M_B_VREF_CA M_B_VREF_CA

VCC1R2A VCC2R5A VCC1R2A


VCC1R2A VCC2R5A VCC1R2A VCC1R2A VCC2R5A VCC1R2A VCC1R2A VCC2R5A VCC1R2A

U129
U130 U131 U132
DDR_B_D8 D7 B1
DDR_B_D10 D3 DQU7 VPP_B1 R9 DDR_B_D35 D7 B1 DDR_B_D41 D7 B1 DDR_B_D62 D7 B1
DDR_B_D13 C8 DQU6 VPP_R9 DDR_B_D37 D3 DQU7 VPP_B1 R9 DDR_B_D47 D3 DQU7 VPP_B1 R9 DDR_B_D57 D3 DQU7 VPP_B1 R9
DDR_B_D14 C2 DQU5 M1 DDR_B_D38 C8 DQU6 VPP_R9 DDR_B_D42 C8 DQU6 VPP_R9 DDR_B_D63 C8 DQU6 VPP_R9
DDR_B_D9 C7 DQU4 VREFCA DDR_B_D33 C2 DQU5 M1 DDR_B_D45 C2 DQU5 M1 DDR_B_D60 C2 DQU5 M1
DDR_B_D15 C3 DQU3 B3 DDR_B_D34 C7 DQU4 VREFCA DDR_B_D43 C7 DQU4 VREFCA DDR_B_D58 C7 DQU4 VREFCA
DDR_B_D12 B8 DQU2 VDD_B3 B9 DDR_B_D32 C3 DQU3 B3 DDR_B_D46 C3 DQU3 B3 DDR_B_D56 C3 DQU3 B3
DDR_B_D11 A3 DQU1 VDD_B9 D1 DDR_B_D39 B8 DQU2 VDD_B3 B9 DDR_B_D40 B8 DQU2 VDD_B3 B9 DDR_B_D59 B8 DQU2 VDD_B3 B9
DQU0 VDD_D1 G7 DDR_B_D36 A3 DQU1 VDD_B9 D1 DDR_B_D44 A3 DQU1 VDD_B9 D1 DDR_B_D61 A3 DQU1 VDD_B9 D1
DDR_B_DQS1 B7 VDD_G7 J1 DQU0 VDD_D1 G7 DQU0 VDD_D1 G7 DQU0 VDD_D1 G7
-DDR_B_DQS1 A7 DQSU_T VDD_J1 J9 DDR_B_DQS4 B7 VDD_G7 J1 DDR_B_DQS5 B7 VDD_G7 J1 DDR_B_DQS7 B7 VDD_G7 J1
DQSU_C VDD_J9 L1 -DDR_B_DQS4 A7 DQSU_T VDD_J1 J9 -DDR_B_DQS5 A7 DQSU_T VDD_J1 J9 -DDR_B_DQS7 A7 DQSU_T VDD_J1 J9
E2 VDD_L1 L9 DQSU_C VDD_J9 L1 DQSU_C VDD_J9 L1 DQSU_C VDD_J9 L1
DMU#/DBIU# VDD_L9 R1 E2 VDD_L1 L9 E2 VDD_L1 L9 E2 VDD_L1 L9
VDD_R1 T9 DMU#/DBIU# VDD_L9 R1 DMU#/DBIU# VDD_L9 R1 DMU#/DBIU# VDD_L9 R1
VDD_T9 VDD_R1 T9 VDD_R1 T9 VDD_R1 T9
DDR_B_D5 J7 A1 VDD_T9 VDD_T9 VDD_T9
DDR_B_D6 J3 DQL7 VDDQ_A1 A9 DDR_B_D18 J7 A1 DDR_B_D25 J7 A1 DDR_B_D50 J7 A1
DDR_B_D1 H8 DQL6 VDDQ_A9 C1 DDR_B_D21 J3 DQL7 VDDQ_A1 A9 DDR_B_D26 J3 DQL7 VDDQ_A1 A9 DDR_B_D48 J3 DQL7 VDDQ_A1 A9
DDR_B_D7 H2 DQL5 VDDQ_C1 D9 DDR_B_D22 H8 DQL6 VDDQ_A9 C1 DDR_B_D29 H8 DQL6 VDDQ_A9 C1 DDR_B_D55 H8 DQL6 VDDQ_A9 C1
DDR_B_D4 H7 DQL4 VDDQ_D9 F2 DDR_B_D17 H2 DQL5 VDDQ_C1 D9 DDR_B_D31 H2 DQL5 VDDQ_C1 D9 DDR_B_D53 H2 DQL5 VDDQ_C1 D9
DDR_B_D2 H3 DQL3 VDDQ_F2 F8 DDR_B_D19 H7 DQL4 VDDQ_D9 F2 DDR_B_D28 H7 DQL4 VDDQ_D9 F2 DDR_B_D51 H7 DQL4 VDDQ_D9 F2
DDR_B_D0 F7 DQL2 VDDQ_F8 G1 DDR_B_D20 H3 DQL3 VDDQ_F2 F8 DDR_B_D27 H3 DQL3 VDDQ_F2 F8 DDR_B_D52 H3 DQL3 VDDQ_F2 F8
DDR_B_D3 G2 DQL1 VDDQ_G1 G9 DDR_B_D23 F7 DQL2 VDDQ_F8 G1 DDR_B_D24 F7 DQL2 VDDQ_F8 G1 DDR_B_D54 F7 DQL2 VDDQ_F8 G1
2 2
DQL0 VDDQ_G9 J2 DDR_B_D16 G2 DQL1 VDDQ_G1 G9 DDR_B_D30 G2 DQL1 VDDQ_G1 G9 DDR_B_D49 G2 DQL1 VDDQ_G1 G9
DDR_B_DQS0 G3 VDDQ_J2 J8 DQL0 VDDQ_G9 J2 DQL0 VDDQ_G9 J2 DQL0 VDDQ_G9 J2
-DDR_B_DQS0 F3 DQSL_T VDDQ_J8 DDR_B_DQS2 G3 VDDQ_J2 J8 DDR_B_DQS3 G3 VDDQ_J2 J8 DDR_B_DQS6 G3 VDDQ_J2 J8
DQSL_C -DDR_B_DQS2 F3 DQSL_T VDDQ_J8 -DDR_B_DQS3 F3 DQSL_T VDDQ_J8 -DDR_B_DQS6 F3 DQSL_T VDDQ_J8
E7 A2 DQSL_C DQSL_C DQSL_C
DML#/DBIL# VSSQ_A2 A8 E7 A2 E7 A2 E7 A2
VSSQ_A8 C9 DML#/DBIL# VSSQ_A2 A8 DML#/DBIL# VSSQ_A2 A8 DML#/DBIL# VSSQ_A2 A8
VSSQ_C9 D2 VSSQ_A8 C9 VSSQ_A8 C9 VSSQ_A8 C9
DDR_B_CLK0 K7 VSSQ_D2 D8 VSSQ_C9 D2 VSSQ_C9 D2 VSSQ_C9 D2
-DDR_B_CLK0 K8 CK_T VSSQ_D8 E3 DDR_B_CLK0 K7 VSSQ_D2 D8 DDR_B_CLK0 K7 VSSQ_D2 D8 DDR_B_CLK0 K7 VSSQ_D2 D8
CK_C VSSQ_E3 E8 -DDR_B_CLK0 K8 CK_T VSSQ_D8 E3 -DDR_B_CLK0 K8 CK_T VSSQ_D8 E3 -DDR_B_CLK0 K8 CK_T VSSQ_D8 E3
DDR_B_CKE0 K2 VSSQ_E8 F1 CK_C VSSQ_E3 E8 CK_C VSSQ_E3 E8 CK_C VSSQ_E3 E8
[6,25] DDR_B_CKE0 CKE VSSQ_F1 VSSQ_E8 VSSQ_E8 VSSQ_E8
H1 DDR_B_CKE0 K2 F1 DDR_B_CKE0 K2 F1 DDR_B_CKE0 K2 F1
-DDR_B_CS0 L7 VSSQ_H1 H9 CKE VSSQ_F1 H1 CKE VSSQ_F1 H1 CKE VSSQ_F1 H1
[6,25] -DDR_B_CS0 CS# VSS_H9 VSSQ_H1 VSSQ_H1 VSSQ_H1
-DDR_B_CS0 L7 H9 -DDR_B_CS0 L7 H9 -DDR_B_CS0 L7 H9
DDR_B_ODT0 K3 B2 CS# VSS_H9 CS# VSS_H9 CS# VSS_H9
[6,25] DDR_B_ODT0 ODT VSS_B2 E1 DDR_B_ODT0 K3 B2 DDR_B_ODT0 K3 B2 DDR_B_ODT0 K3 B2
VSS_E1 ODT VSS_B2 ODT VSS_B2 ODT VSS_B2

Vinafix.com
[6,25] -DDR_B_ACT -DDR_B_ACT L3 G8 E1 E1 E1
ACT# VSS_G8 K1 -DDR_B_ACT L3 VSS_E1 G8 -DDR_B_ACT L3 VSS_E1 G8 -DDR_B_ACT L3 VSS_E1 G8
DDR_B_BG1_R M9 VSS_K1 K9 ACT# VSS_G8 K1 ACT# VSS_G8 K1 ACT# VSS_G8 K1
DDR_B_BG0 M2 BG1_VSS VSS_K9 N1 DDR_B_BG1_R M9 VSS_K1 K9 DDR_B_BG1_R M9 VSS_K1 K9 DDR_B_BG1_R M9 VSS_K1 K9
[6,25] DDR_B_BG0 BG0 VSS_N1 BG1_VSS VSS_K9 BG1_VSS VSS_K9 BG1_VSS VSS_K9
T1 DDR_B_BG0 M2 N1 DDR_B_BG0 M2 N1 DDR_B_BG0 M2 N1
DDR_B_BA1 N8 VSS_T1 BG0 VSS_N1 T1 BG0 VSS_N1 T1 BG0 VSS_N1 T1
[6,25] DDR_B_BA1 BA1 VSS_T1 VSS_T1 VSS_T1
[6,25] DDR_B_BA0 DDR_B_BA0 N2 T7 DDR_B_BA1 N8 DDR_B_BA1 N8 DDR_B_BA1 N8
BA0 VSS_NC DDR_B_BA0 N2 BA1 T7 DDR_B_BA0 N2 BA1 T7 DDR_B_BA0 N2 BA1 T7
DDR_B_MA16 L8 BA0 VSS_NC BA0 VSS_NC BA0 VSS_NC
DDR_B_MA15 M8 A16/RAS# DDR_B_MA16 L8 DDR_B_MA16 L8 DDR_B_MA16 L8
DDR_B_MA14 L2 A15/CAS# DDR_B_MA15 M8 A16/RAS# DDR_B_MA15 M8 A16/RAS# DDR_B_MA15 M8 A16/RAS#
A14/WE# DDR_B_MA14 L2 A15/CAS# DDR_B_MA14 L2 A15/CAS# DDR_B_MA14 L2 A15/CAS#
DDR_B_MA13 T8 A14/WE# A14/WE# A14/WE#
DDR_B_MA12 M7 A13 DDR_B_MA13 T8 DDR_B_MA13 T8 DDR_B_MA13 T8
DDR_B_MA11 T2 A12/BC# DDR_B_MA12 M7 A13 DDR_B_MA12 M7 A13 DDR_B_MA12 M7 A13
DDR_B_MA10 M3 A11 P1 -DRAMRST DDR_B_MA11 T2 A12/BC# DDR_B_MA11 T2 A12/BC# DDR_B_MA11 T2 A12/BC#
DDR_B_MA9 R7 A10/AP RESET# DDR_B_MA10 M3 A11 P1 -DRAMRST DDR_B_MA10 M3 A11 P1 -DRAMRST DDR_B_MA10 M3 A11 P1 -DRAMRST
DDR_B_MA8 R2 A9 T3 DDR_B_PAR DDR_B_MA9 R7 A10/AP RESET# DDR_B_MA9 R7 A10/AP RESET# DDR_B_MA9 R7 A10/AP RESET#
DDR_B_MA7 R8 A8 PARITY DDR_B_MA8 R2 A9 T3 DDR_B_PAR DDR_B_MA8 R2 A9 T3 DDR_B_PAR DDR_B_MA8 R2 A9 T3 DDR_B_PAR
DDR_B_MA6 P2 A7 P9 -DDR_B_ALERT DDR_B_MA7 R8 A8 PARITY DDR_B_MA7 R8 A8 PARITY DDR_B_MA7 R8 A8 PARITY
DDR_B_MA5 P8 A6 ALERT# DDR_B_MA6 P2 A7 P9 -DDR_B_ALERT DDR_B_MA6 P2 A7 P9 -DDR_B_ALERT DDR_B_MA6 P2 A7 P9 -DDR_B_ALERT
DDR_B_MA4 N3 A5 E9 DDR_B_MA5 P8 A6 ALERT# DDR_B_MA5 P8 A6 ALERT# DDR_B_MA5 P8 A6 ALERT#
3
DDR_B_MA3 N7 A4 ZQU_VSS DDR_B_MA4 N3 A5 E9 DDR_B_MA4 N3 A5 E9 DDR_B_MA4 N3 A5 E9 3
DDR_B_MA2 R3 A3 F9 DDR_B_MA3 N7 A4 ZQU_VSS DDR_B_MA3 N7 A4 ZQU_VSS DDR_B_MA3 N7 A4 ZQU_VSS
DDR_B_MA1 P7 A2 ZQL_ZQ DDR_B_MA2 R3 A3 F9 DDR_B_MA2 R3 A3 F9 DDR_B_MA2 R3 A3 F9
DDR_B_MA0 P3 A1 N9 DDR_B_MA1 P7 A2 ZQL_ZQ DDR_B_MA1 P7 A2 ZQL_ZQ DDR_B_MA1 P7 A2 ZQL_ZQ
A0 96-BALL TEN DDR_B_MA0 P3 A1 N9 DDR_B_MA0 P3 A1 N9 DDR_B_MA0 P3 A1 N9
SDRAM DDR4 A0 96-BALL TEN A0 96-BALL TEN A0 96-BALL TEN
SDRAM DDR4 SDRAM DDR4 SDRAM DDR4
2

MT40A1G16HBA-083E-A_FBGA96
2

2
X76@ MT40A1G16HBA-083E-A_FBGA96 MT40A1G16HBA-083E-A_FBGA96 MT40A1G16HBA-083E-A_FBGA96
2

R9518 R9517 X76@ X76@ X76@


2

2
R9516 243_0201_1% 243_0201_1% R9519 R9521 R9522 R9524 R9529 R9530
X76@ 0_0201_5% X76@ R9520 243_0201_1% 243_0201_1% R9523 243_0201_1% 243_0201_1% R9528 243_0201_1% 243_0201_1%
1

X76@ 0_0201_5% X76@ X76@ 0_0201_5% X76@ X76@ 0_0201_5% X76@


1

1
1

1
TABLE
DDR_B_CLK0
[6,25] DDR_B_CLK0 SDP DDP

R9516 ASM NA
-DDR_B_CLK0 R9520 ASM NA
[6,25] -DDR_B_CLK0
R9523 ASM NA
R9528 ASM NA

0_0201_5%
DDR_B_BG1 1 2 DDR_B_BG1_R
[6] DDR_B_BG1
R9515 X76@
DDR_B_BG1_R [25] R9515 NA ASM

4 R9556 NA ASM 4

[6,22] -DRAMRST -DRAMRST


R9517 0_5% 243_1%
R9521 0_5% 243_1%
[6,25] DDR_B_PAR
DDR_B_PAR R9524 0_5% 243_1%
R9530 0_5% 243_1%

-DDR_B_ALERT Security Classification Compal Secret Data Compal Electronics, Inc.


[6,25] -DDR_B_ALERT
Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4 BASE MEMORY CH-B (1/2)
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 24 of 73
A B C D E
5 4 3 2 1

FVT_C_EC006 VCC1R2A

[6,24] DDR_B_MA[16:0]
VCC0R6B

X76B@
DDR_B_MA16 1 2

2
R9549 X76B@ 36_0201_1%
DDR_B_MA15 1 2 C8739 C8715 C8724 C8707 C8735 C8730 C8736 C8714
R9540 X76B@ 36_0201_1% 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

1
DDR_B_MA14 1 2
R9544 X76B@ 36_0201_1%
DDR_B_MA13 1 2
D D
R9559 X76B@ 36_0201_1%
DDR_B_MA12 1 2
R9562 X76B@ 36_0201_1%
DDR_B_MA11 1 2
R9563 X76B@ 36_0201_1%
DDR_B_MA10 1 2
R9538 X76B@ 36_0201_1%
DDR_B_MA9 1 2
R9551 X76B@ 36_0201_1%
DDR_B_MA8 1 2
R9537 X76B@ 36_0201_1%
DDR_B_MA7 1 2 VCC1R2A
R9557 X76B@ 36_0201_1%
DDR_B_MA6 1 2
R9554 X76B@ 36_0201_1%
DDR_B_MA5 1 2
R9547 X76B@ 36_0201_1%
DDR_B_MA4 1 2
R9546 X76B@ 36_0201_1%
DDR_B_MA3 1 2
R9543 X76B@ 36_0201_1%

2
DDR_B_MA2 1 2
R9561 X76B@ 36_0201_1% C8708 C8732 C8711 C8720 C8713 C8710 C8705 C8728
DDR_B_MA1 1 2 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

1
R9542 X76B@ 36_0201_1%
DDR_B_MA0 1 2
R9552 X76@ 36_0201_1%
DDR_B_BG1_R 1 2
[24] DDR_B_BG1_R
R9556 X76B@ 36_0201_1%
DDR_B_BG0 1 2
[6,24] DDR_B_BG0
R9548 X76B@ 36_0201_1%
DDR_B_BA1 1 2
[6,24] DDR_B_BA1
R9558 X76B@ 36_0201_1%
DDR_B_BA0 1 2
[6,24] DDR_B_BA0
R9553 X76B@ 36_0201_1%
-DDR_B_ACT 1 2
[6,24] -DDR_B_ACT
R9541 X76B@ 36_0201_1%
DDR_B_PAR 1 2
[6,24] DDR_B_PAR
R9539 X76B@ 36_0201_1% VCC1R2A
C -DDR_B_CS0 1 2 C
[6,24] -DDR_B_CS0
R9536 X76B@ 36_0201_1%
DDR_B_ODT0 1 2
[6,24] DDR_B_ODT0
R9560 36_0201_1%
DDR_B_CKE0 1 X76B@ 2
[6,24] DDR_B_CKE0
R9535 36_0201_1%

2 2 2 2 2 2 2 2
C8729 C8717 C8722 C8706 C8727 C8733 C8721 C8716
10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
DDR_B_CLK0 1 2 1 1 1 1 1 1 1 1
[6,24] DDR_B_CLK0
R9545 36_0201_1%
X76B@
-DDR_B_CLK0 1 2
[6,24] -DDR_B_CLK0
R9555 36_0201_1%

Vinafix.com
X76B@

VCC1R2A

VCC1R2A

-DDR_B_ALERT 1 2
[6,24] -DDR_B_ALERT
R9550 49.9_0201_1%

2 2 2 2 2 2 2 2 2 2 2 2
C8737 C8734 C8712 C8726 C8723 C8725 C8718 C8731 C8704 C8719 C8738 C8709
100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J
1 1 1 1 1 1 1 1 1 1 1 1

B B

VCC1R2A

2
R9534
1.82K_0201_1% M_B_VREF_CA

VCC0R6B VCC0R6B

1
X76B@
2.7_0201_1%

1 2
[5] +0.6V_B_VREFDQ
R9532
X76B@

2 2 2 2 2 2 2 2 2 2 2 2

2
C8747 C8755 C8743 C8752 C8751 C8745 C8748 C8742 C8741 C8760 C8753 C8750 2
10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K R9533
1 1 1 1 1 1 1 1 1 1 1 1 C8764 1.82K_0201_1%
0.022U_0201_10V6K
1

1
X76B@
X76B@

2
R9531
VCC0R6B VCC0R6B 24.9_0201_1%

1
A X76B@ A

2 2 2 2 2 2 2 2 2 2 2 2
C8754 C8763 C8740 C8756 C8746 C8762 C8749 C8759 C8758 C8757 C8761 C8744
100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 100P_0201_25V8J 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4 BASE MEMORY CH-B (2/2)
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 25 of 73
5 4 3 2 1
5 4 3 2 1

VCC3P

VCC3B VBL12 VINT12


W=60mils U9 W=60mils
1.2A
1
VOUT F7
R361 1 @ 2 0_0805_5% 5
VIN 1 2
1 2
4 GND
D EN 1 C192 1 C193 0438003.WR 3A 32V D
C190

0.1U_0201_10V6K

4.7U_0603_6.3V6K
1U_0402_6.3V6K 3
2 /OC
G524B1T11U_SOT23-5 2 2
1 1
@RF@ C724
C8826 0.01U_0402_25V7K
0.1U_0402_16V4Z
PANEL_POWER_ON 2 2
[4] PANEL_POWER_ON

VCC3M VCC3B

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K
VCC3P
1.5A

0.5A_65V_T0603FF0500TM

0438003.WR 3A 32V
2

2
2 2
@ VBL12
2 2 C311 C308

F24 1
0.1U_0201_6.3V6K 0.01U_0201_6.3V7K

1
1 1
C C
1 1

C321

C319
F34
1

2
VCC3B_TOUCH_CN
VCC3M_SENS_CN
C307 C310 C313
0.01U_0402_25V7K 0.1U_0402_25V7K 1U_0603_25V7K

1
2

LCD CONNECTOR
JEDP1

50
49 50
49

Vinafix.com
48
USBP7- 47 48
[11] USBP7- 47

CAMERA BOARD
USBP7+ 46
[11] USBP7+ 46
45
-INT_MIC_DTCT 44 45
[9,27] -INT_MIC_DTCT 44
MIC_DATA 43
[27,35] MIC_DATA 43

LOGO LED
MIC_CLK 42
[27,35] MIC_CLK 42
41
-LED_LOGO R102 1 2 680_0402_5% 40 41
[27,53] -LED_LOGO 40
39
38 39
ISH_GP0 37 38
[9,27] ISH_GP0 37

SENSOR BOARD
ISH_GP1 36
[9,27] ISH_GP1 36
ISH_GP2 35
[9,27,41] ISH_GP2 35
34
ISH_I2C0_SDA 33 34
[9,27,41] ISH_I2C0_SDA 33
ISH_I2C0_SCL 32
[9,27,41] ISH_I2C0_SCL 32
31
30 31
29 30
29

eDP
28
27 28
B
PANEL_BKLT_CTRL 26 27 B
[4] PANEL_BKLT_CTRL 26
BACKLIGHT_ON 25
[53] BACKLIGHT_ON 25
24
[4] EDP_HPD 24
@ 23
0_0201_5% 1 2 R9374 22 23
[9] -TS_RESET 22
21
21

TOUCH
D6 1 2 RB521CM-30T2R_SOD923-2 20
[9,43,53] -LID_CLOSE 20
19

PANEL
-TOUCH_DISABLE 1 2 -TOUCH_STOP 18 19
[53] -TOUCH_DISABLE 18
D4 RB521CM-30T2R_SOD923-2 17
USBP9- 16 17
[11] USBP9- 16
USBP9+ 15
[11] USBP9+ 15
14
C8766 1 2 0.1U_0201_6.3V6K EDP_AUXN_CONN 13 14
[4] EDP_AUXN 13
C8765 1 2 0.1U_0201_6.3V6K EDP_AUXP_CONN 12
[4] EDP_AUXP 12
11
10 11
10

eDP
9
C8768 1 2 0.1U_0201_6.3V6K EDP_TXP0_C 8 9
[4] EDP_TXP0 8
C8767 1 2 0.1U_0201_6.3V6K EDP_TXN0_C 7
[4] EDP_TXN0 7
C8770 1 2 0.1U_0201_6.3V6K EDP_TXP1_C 6 55
[4] EDP_TXP1 6 GND5
C8769 1 2 0.1U_0201_6.3V6K EDP_TXN1_C 5 54
[4] EDP_TXN1 5 GND4
C8667 1 @ 2 0.1U_0201_6.3V6K EDP_TXP2_C 4 53
[4] EDP_TXP2 4 GND3
C8771 1 @ 2 0.1U_0201_6.3V6K EDP_TXN2_C 3 52
[4] EDP_TXN2 3 GND2
C8669 1 @ 2 0.1U_0201_6.3V6K EDP_TXP3_C 2 51
[4] EDP_TXP3 2 GND1
[4] EDP_TXN3 C8668 1 @ 2 0.1U_0201_6.3V6K EDP_TXN3_C 1
1
100P_0201_25V8J

100P_0201_25V8J

ACES_50398-05071-001
ME@

0828 add -LED_LOGO


ESD@
1000P_0201_25V7K

1000P_0201_25V7K

2 2
2
@EMI@

@EMI@

RF@ 2 2
C8817 2 1 0.1U_0201_6.3V6K ISH_GP0
2

C8532

@ R9472
RF@ 1 1
A 10K_0201_5% A
1 1
C8789

C8790

C8818 2 1 0.1U_0201_6.3V6K ISH_GP1 D28


1
C33

PESD5V0U2BT_SOT23-3
RF@ ESD@
C8819 2 1 0.1U_0201_6.3V6K ISH_GP2
1

For power on screen flash issue

FVT_C_EC015 Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD/LID/MIC/CAMERA
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 26 of 73
5 4 3 2 1
5 4 3 2 1

D D

VCC3B VCC3M VCC5B

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

0.5A_65V_T0603FF0500TM
2A_32V_0438002.WR

0.1U_0201_6.3V6K
2

2
F40
2A_32V_0438002.WR

2 2

F41 1

1
1
2
1 1

C8680
C322

F39
1

C8681
VCC3M_IR
VCC3B_IR

VCC5B_IR
C JIR1 C
1
USBP3- 2 1
[11] USBP3- 2
USBP3+ 3
[11] USBP3+ 3
4
USBP5- 5 4
[11] USBP5- 5
USBP5+ 6
[11] USBP5+ 6
-INT_IR_DTCT 7
[9] -INT_IR_DTCT 7

IR CAMERA BOARD
8
9 8
10 9
-INT_MIC_DTCT 11 10
[9,26] -INT_MIC_DTCT 11
12
13 12
14 13
15 14
MIC_CLK 16 15
[26,35] MIC_CLK 16
MIC_DATA 17
[26,35] MIC_DATA 17

Vinafix.com
18
19 18
20 19
[9,26] ISH_GP0 20

SENSOR BOARD
21
[9,26] ISH_GP1 21
22
[9,26,41] ISH_GP2 22
23
ISH_I2C0_SDA 24 23
[9,26,41] ISH_I2C0_SDA 24

LOGO LED
ISH_I2C0_SCL 25
[9,26,41] ISH_I2C0_SCL 25
-LED_LOGO R9513 1 2 1K_0402_5% 26 31
[26,53] -LED_LOGO 26 G1
27 32
28 27 G2 33
29 28 G3 34
30 29 G4 35
30 G5

100P_0201_25V8J

100P_0201_25V8J
ARGOS_LVDFH-03001-TM00+
ME@

-LED_LOGO

0.1U_0201_6.3V6K
1000P_0201_25V7K
B B
2 2 2 2
2

@EMI@

@EMI@
@ ESD@
D65
1 1 1 1

C8656
PESD5V0U2BT_SOT23-3

C8652

C8653

C8679
ESD@
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IR Camera conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 27 of 73
5 4 3 2 1
5 4 3 2 1

VCC3B

VCC3B_PS8337B

R1876 1 @ 2 4.7K_0201_5% PS8337_TMDS_DDCBUF R1898 1 @ 2 4.7K_0201_5%


D D

R1875 1 @ 2 4.7K_0201_5% PS8337_PEQ R1897 1 @ 2 4.7K_0201_5%

4.7U_0402_6.3V6M

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K
VCC3B VCC3B_PS8337B 2 2 2 2 2
R1877 1 2 4.7K_0201_5% PS8337_TMDS_PRE R1899 1 2 4.7K_0201_5%
@ C993 C1422 C1423 C1424 C1425

0_0603_5% 1 1 1 1 1 R146 1 2 4.7K_0201_5% PS8337_MODE R147 1 2 4.7K_0201_5%


R2463 1 2
TMDS DDCBUF
(INT PD) R1876 R1898
R2509 1 2 4.7K_0201_5% PS8337_TMDS_RT

R2510 1 2 4.7K_0201_5% PS8337_DP_CFG0


DDC Ative Buffer ASM NO_ASM
Place 0.1uF caps near each VDD33 pin of PS8337
@

DDC Pass Through


w/ PU ASM ASM
TABLE : Automatic Switching Mode (MODE = H, M)
DDC Pass Through
SW (DDI_PRIORITY1) NO_ASM NO_ASM LOGIC
w/o PU
L DP Port has higher priority when both ports are plugged
H TMDS Port has higher priority when both ports are plugged

PEQ
(INT PD) R1875 R1897
VCC3B VCC3B_PS8337B
HEQ 15dB ASM NO_ASM
C LLEQ 5dB ASM ASM C

2
U108
R2501 14 40
28 VDD33 DP_D0p 39
4.7K_0201_5%
41 VDD33 DP_D0n LEQ 12dB NO_ASM NO_ASM LOGIC
VCC3B 56 VDD33 37

1
VDD33 DP_D1p 36
PS8337_DP_CFG0 44 DP_D1n
45 DP_CFG0/SCL_CTL 34
38 SW/SDA_CTL DP_D2p 33
I2C_CTL_EN DP_D2n
2.2K_0201_5%

2.2K_0201_5%

C1405 1 2 0.1U_0201_6.3V6K DDIP2_0P_C 3 31


[4] DDIP2_0P IN_D0p DP_D3p
1

C1406 1 2 0.1U_0201_6.3V6K DDIP2_0N_C 4 30


[4] DDIP2_0N IN_D0n DP_D3n TMDS PRE
C1407 1 2 0.1U_0201_6.3V6K DDIP2_1P_C 6 55 (INT PD) R1877 R1899
[4] DDIP2_1P IN_D1p DP_AUXp_SCL
C1408 1 2 0.1U_0201_6.3V6K DDIP2_1N_C 7 54
[4] DDIP2_1N IN_D1n DP_AUXn_SDA 32
R9334 2

R9335 2

C1409 1 2 0.1U_0201_6.3V6K DDIP2_2P_C 9 DP_HPD


[4] DDIP2_2P IN_D2p 1.5dB ASM NO_ASM

Vinafix.com
C1415 1 2 0.1U_0201_6.3V6K DDIP2_2N_C 10
[4] DDIP2_2N IN_D2n 42 R2511 1 2 1M_0201_5%
C1418 1 2 0.1U_0201_6.3V6K DDIP2_3P_C 12 DP_CA_DET
[4] DDIP2_3P
C1419 1 2 0.1U_0201_6.3V6K DDIP2_3N_C 13 IN_D3p 29 PS8337_DP_CFG1 TP918@
3.0dB ASM ASM LOGIC
[4] DDIP2_3N IN_D3n DP_CFG1
52 19 HDMI_DATA0P
FVT_C_EC010 51 IN_AUXp TMDS_CH0p 18 HDMI_DATA0N
HDMI_DATA0P [29] 0dB NO_ASM NO_ASM
IN_AUXn TMDS_CH0n HDMI_DATA0N [29]
50 22 HDMI_DATA1P
[4] DDIP2_CTRLCLK IN_DDC_SCL TMDS_CH1p HDMI_DATA1P [29]
49 21 HDMI_DATA1N
[4] DDIP2_CTRLDATA IN_DDC_SDA TMDS_CH1n HDMI_DATA1N [29]
11 25 HDMI_DATA2P
IN_CA_DET TMDS_CH2p HDMI_DATA2P [29]
24 HDMI_DATA2N
TMDS_CH2n HDMI_DATA2N [29]
5
[4] DDIP2_HPD IN_HPD 16 HDMI_CLKP
TMDS_CLKp HDMI_CLKP [29]
15 HDMI_CLKN
TMDS_CLKn HDMI_CLKN [29] MODE
1 48 HDMI_DDC_CLK (INT PD) R146 R147
CEXT TMDS_SCL HDMI_DDC_CLK [29]
47 HDMI_DDC_DATA
TMDS_SDA HDMI_DDC_DATA [29]
2 PS8337_TMDS_DDCBUF 2
TMDS_DDCBUF 17 HDMI_HPD_CONN
C213 PS8337_PEQ 8 TMDS_HPD HDMI_HPD_CONN [29] Auto
B
2.2U_0402_6.3V6M
R246 PEQ 23 PS8337_TMDS_RT HDMI ID disable ASM NO_ASM B
1 1 2 27 TMDS_RT 20 PS8337_TMDS_PRE
REXT TMDS_PRE
46 26
4.99K_0201_1% PD GND Auto

2
35
PS8337_MODE 53 GND 43 R2512 HDMI ID enable ASM ASM
MODE GND 57 @ 27K_0201_1%
Thermal/GND
PS8337BQFN56GTR2-A1_QFN56_7X7 Control

1
HDMI ID disable NO_ASM NO_ASM LOGIC

Vendor suggest to @

TMDS RT
(INT PD) R2509

OD w/ termination ASM

OD NO_ASM LOGIC

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDI DEMUX/HDMI LEVEL SHIFT
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 28 of 73
5 4 3 2 1
5 4 3 2 1

D D

VCC5B_HDMI

No need diode here because TPS2553 has


reverse voltage protection function.

HDMI CONN

2.2K_0201_5%

2.2K_0201_5%
2

2
R1029 R1030

1
JHDMI1 ME@
HDMI_DATA2P EMI@ FLJ10 2 3 HDMI_DATA2P_CONN 1
[28] HDMI_DATA2P 2 3 D2+
MCF12102G900-T_4P 2
3 D2_shield
HDMI_DATA2N 1 4 HDMI_DATA2N_CONN 4 D2-
[28] HDMI_DATA2N 1 4 D1+
5
HDMI_DATA1P EMI@ FLJ11 2 3 HDMI_DATA1P_CONN 6 D1_shield
[28] HDMI_DATA1P 2 3 D1-
MCF12102G900-T_4P 7
8 D0+ 20
HDMI_DATA1N 1 4 HDMI_DATA1N_CONN 9 D0_shield GND0 21
[28] HDMI_DATA1N 1 4 D0- GND1
10 22
HDMI_DATA0P EMI@ FLJ12 2 3 HDMI_DATA0P_CONN 11 CK+ GND2 23
[28] HDMI_DATA0P 2 3 CK_shield GND3
MCF12102G900-T_4P 12
13 CK-
HDMI_DATA0N 1 4 HDMI_DATA0N_CONN 14 CEC
[28] HDMI_DATA0N 1 4 Reserved
15
HDMI_CLKP EMI@ FLJ13 2 3 HDMI_CLKP_CONN 16 SCL
C C
[28] HDMI_CLKP 2 3 SDA
MCF12102G900-T_4P 17
VCC5B_HDMI 18 DDC/CEC_GND
HDMI_CLKN 1 4 HDMI_CLKN_CONN 19 +5V
[28] HDMI_CLKN 1 4 HP_DET
LCN_AUF05-1967S10-0011

HDMI_DDC_CLK
[28] HDMI_DDC_CLK
HDMI_DDC_DATA
[28] HDMI_DDC_DATA

HDMI_HPD_CONN
[28] HDMI_HPD_CONN

Vinafix.com
D283
HDMI_DATA1N_CONN 1 10 HDMI_DATA1N_CONN
VCC5B_HDMI
HDMI_DATA1P_CONN 2 9 HDMI_DATA1P_CONN

HDMI_DATA2N_CONN 4 7 HDMI_DATA2N_CONN

D227 HDMI_DATA2P_CONN 5 6 HDMI_DATA2P_CONN


HDMI_DDC_CLK 1 6 HDMI_HPD_CONN
V I/O V I/O 3
2 5
Ground V BUS 8
B B
HDMI_DDC_DATA 3 4
V I/O V I/O PUSB3F96_XSON10_2.5X1~D
PUSB2X4D_SO6-6 ESD@
ESD@
Current Limit Target : 400mA
Requirement : 300mA
HDMI Spec : 50mA - 500mA
NEAR HDMI CONN

VCC5B VCC5B_HDMI

U110
1 6
IN OUT
0.1U_0201_6.3V6K

4.7U_0402_6.3V6M
2 2 5
GND ILIM
2
D284 C1426

2
HDMI_CLKP_CONN 1 10 HDMI_CLKP_CONN 3 4 C994
1 EN FAULT# R1119
HDMI_CLKN_CONN 2 9 HDMI_CLKN_CONN 61.9K_0201_1% 1
TPS2553DBVR_SOT23-6
HDMI_DATA0P_CONN 4 7 HDMI_DATA0P_CONN

1
HDMI_DATA0N_CONN 5 6 HDMI_DATA0N_CONN

PUSB3F96_XSON10_2.5X1~D
ESD@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI CONNECTOR
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 29 of 73
5 4 3 2 1
5 4 3 2 1

VCC3B

D
PEDET (PE_DTCT) D
SATA Device GND
PCIe Device Open

2
-PE_DTCT
-PE_DTCT [11]
R2037
10K_0201_5%

1
PE_DTCT 2 Q178
LSK3541G1ET2L_VMT3

3
VCC3B

C C

1
J9239

1
JUMP_43X79

2
JSSD1 ME@

2
@
1 2
3 1_GND 3.3V_2 4
PCIE4_L3_RXN 5 3_GND 3.3V_4 6
[11] PCIE4_L3_RXN 5_PETN3 N/C_6
PCIE4_L3_RXP 7 8
[11] PCIE4_L3_RXP 7_PETP3 N/C_8
9 10
PCIE4_L3_TXN C2166 1 2 0.22U_0201_6.3V6M PCIE4_L3_TXN_CONN 11 9_GND DAS/DSS#_10 12
[11] PCIE4_L3_TXN 11_PERN3 3.3V_12
PCIE4_L3_TXP C2167 1 2 0.22U_0201_6.3V6M PCIE4_L3_TXP_CONN 13 14
[11] PCIE4_L3_TXP 13_PERP3 3.3V_14

Vinafix.com
15 16 VCC3B
PCIE4_L2_RXN 17 15_GND 3.3V_16 18
[11] PCIE4_L2_RXN 17_PETN2 3.3V_18
PCIE4_L2_RXP 19 20
[11] PCIE4_L2_RXP 19_PETP2 N/C_20
-SSD_DTCT 21 22
[53] -SSD_DTCT 21_GND N/C_22

2
PCIE4_L2_TXN C2168 1 2 0.22U_0201_6.3V6M PCIE4_L2_TXN_CONN 23 24
[11] PCIE4_L2_TXN 23_PERN2 N/C_24
PCIE4_L2_TXP C2169 1 2 0.22U_0201_6.3V6M PCIE4_L2_TXP_CONN 25 26 R2038
[11] PCIE4_L2_TXP 25_PERP2 N/C_26
27 28 10K_0201_5%
PCIE4_L1_RXN 29 27_GND N/C_28 30
[11] PCIE4_L1_RXN 29_PETN1 N/C_30
PCIE4_L1_RXP 31 32
[11] PCIE4_L1_RXP

1
33 31_PETP1 N/C_32 34
PCIE4_L1_TXN C2042 1 2 0.22U_0201_6.3V6M PCIE4_L1_TXN_CONN 35 33_GND N/C_34 36
[11] PCIE4_L1_TXN 35_PERN1 N/C_36
PCIE4_L1_TXP C2041 1 2 0.22U_0201_6.3V6M PCIE4_L1_TXP_CONN 37 38
[11] PCIE4_L1_TXP 37_PERP1 DEVSLP_38 SATA1_DEVSLP [11]
39 40
PCIE4_L0_SATA1_RXP 41 39_GND N/C_40 42
[11] PCIE4_L0_SATA1_RXP 41_PETN0/SATA_B+ N/C_42
PCIE4_L0_SATA1_RXN 43 44
[11] PCIE4_L0_SATA1_RXN 43_PETP0/SATA_B- N/C_44
45 46
PCIE4_L0_SATA1_TXN C805 1 2 0.22U_0201_6.3V6M PCIE4_L0_SATA1_TXN_CONN 47 45_GND N/C_46 48
[11] PCIE4_L0_SATA1_TXN 47_PERN0/SATA_A- N/C_48
PCIE4_L0_SATA1_TXP C827 1 2 0.22U_0201_6.3V6M PCIE4_L0_SATA1_TXP_CONN 49 50 -PLTRST_FAR
[11] PCIE4_L0_SATA1_TXP 49_PERP0/SATA_A+ PERST#_50 -PLTRST_FAR [14,32,33,45,46,49,52,53]
51 52
51_GND CLKREQ#_52 -CLKREQ_PCIE4 [13]
-PCIE4_CLK_100M 53 54
[13] -PCIE4_CLK_100M 53_REFCLKN PEWAKE#_54
PCIE4_CLK_100M 55 56
[13] PCIE4_CLK_100M 55_REFCLKP RESERVED_56
57 58
B 57_GND RESERVED_58 B

59 60
PE_DTCT 61 67_N/C_1 SUSCLK_68 62
2 69_PEDET 3.3V_70
63 64
C8657 65 71_GND 3.3V_72 66
@ESD@ 67 73_GND 3.3V_74
100P_0201_25V8J 75_GND
1

69 68
GND GND
2 2 2 2 2
@ RF@ @RF@ RF@
LCN_DAN05_67216-S103 C92 C53 C8606 C8607 C8608
10U_0402_6.3V6M 0.01U_0201_6.3V7K 0.1U_0201_6.3V6K 2200P_0201_50V7K 0.1U_0201_6.3V6K
1 1 1 1 1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M.2 SSD SLOT
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 30 of 73
5 4 3 2 1
5 4 3 2 1

USB_PWR_S1
WIDE PATTERN(MIN 500mA)
PLACE NEAR USB CONN

150U_B2_6.3VM_R35M
D D

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K
JUSB1 ME@ 1
[11] USB3P0_TXP C293 2 1 0.1U_0201_6.3V6K USB3P0_TXP_C 9 2 2
1 SSTX+ +
C263 2 1 0.1U_0201_6.3V6K USB3P0_TXN_C 8 VBUS C771 C773 C1248
[11] USB3P0_TXN SSTX-
USBP0+_CONN 3
7 D+ 1 1 2
USBP0-_CONN 2 GND_DRAIN 10
6 D- GND 11
[11] USB3P0_RXP SSRX+ GND
4 12
5 GND GND 13
[11] USB3P0_RXN SSRX- GND
SINGA_2UB4008-900101F

USB_PWR_S1
FLJ18 EMI@ D231
USBP0+_AOU 2 3 USBP0+_CONN 1 6 D229
2 3 USB3P0_TXP_C 1 10 USB3P0_TXP_C

USBP0-_AOU 1 4 USBP0-_CONN USB3P0_TXN_C 2 9 USB3P0_TXN_C


1 4 2 5
MCF12102G900-T_4P USB3P0_RXP 4 7 USB3P0_RXP

USB3P0_RXN 5 6 USB3P0_RXN
3 4
3
PUSB2X4D_SO6-6
ESD@ 8

PUSB3F96_XSON10_2.5X1~D
ESD@

C C

PLACE NEAR USB CONNECTOR


WIDE PATTERN(MIN 500mA)
USB_PWR_S2

150U_B2_6.3VM_R35M
0.1U_0201_6.3V6K

0.1U_0201_6.3V6K
JUSB2 ME@ 1
[11] USB3P2_TXP C325 2 1 0.1U_0201_6.3V6K USB3P2_TXP_C 9 2 2
SSTX+

Vinafix.com
1 + C1269
C298 2 1 0.1U_0201_6.3V6K USB3P2_TXN_C 8 VBUS C772 C774
[11] USB3P2_TXN SSTX-
USBP2+_CONN 3
7 D+ 1 1 2
USBP2-_CONN 2 GND_DRAIN 10
6 D- GND 11
[11] USB3P2_RXP SSRX+ GND
4 12
5 GND GND 13
[11] USB3P2_RXN SSRX- GND
SINGA_2UB4008-900101F

USB_PWR_S2 D230
D80 USB3P2_TXP_C 1 10 USB3P2_TXP_C
1 6
FLJ19 EMI@ USB3P2_TXN_C 2 9 USB3P2_TXN_C
USBP2+ 2 3 USBP2+_CONN
[11] USBP2+ 2 3 USB3P2_RXP 4 7 USB3P2_RXP
2 5
USBP2- 1 4 USBP2-_CONN USB3P2_RXN 5 6 USB3P2_RXN
B [11] USBP2- 1 4 B
MCF12102G900-T_4P 3
3 4
8
PUSB2X4D_SO6-6
ESD@ PUSB3F96_XSON10_2.5X1~D
ESD@

VCC5M

VCC5M VCC5M
Current Limit Target:
2.3A (2.1 - 2.45A)
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M

0.1U_0201_6.3V6K

1 2

TABLE of USB3.0 Single


2 2 C3
@ @
2

C1291 C257

TI TPS2069CDGN-2
R1152
@ 1 1 0.1U_0201_6.3V6K
10K_0201_5%
1 2

GMT G548A1F51U
C179
1

USB_PWR_S1
USB_PWR_S2

U53
U88 1 9
1 12 2 GND GND 8
9 IN OUT 10 USBP0+_AOU 3 IN#2 OUT#8 7
[53] -AOU_IFLG STATUS# DP_IN IN#3 OUT#7
13 11 USBP0-_AOU USB_ON1 4 6
[11] -USB_PORT0_OC0 FAULT# DM_IN [53] USB_ON1 EN OUT#6
4 2 USBP0- [11] 5 -USB_PORT1_OC1 -USB_PORT1_OC1 [11]
5 ILIM_SEL DM_OUT 3 OC#
[53] AOU_EN EN DP_OUT USBP0+ [11]
6 15 R1114 1 2 2.7M_0201_5% TPS2069DGNR-2_MSOP8
[53] AOU_SEL1 CTL1 ILIM_LO
7 16 R1104 1 2 22.1K_0201_1%
8 CTL2 ILIM_HI 14
A A
[53] AOU_SEL2 CTL3 GND 17
T-PAD
TPS2546RTER_QFN16_3X3

Change to TPS2069D (SA00002Y200)

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB POWER/CONN
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 31 of 73
5 4 3 2 1
5 4 3 2 1

TYPE-B M.2 CARD FOR WWAN


3042S3 CONNECTOR
VCC3B VCC3WAN VCC3B VCC3WAN
J9240
VCC3WAN
1 2
1 2

2
2
R9509 R9511 R1005 ESD@
JUMP_43X79
10K_0201_5% @ 10K_0201_5% 47K_0201_5% C47
JWWAN1 ME@ 100P_0201_25V8J @
D 1 D

1
1 2
[9] WWAN_CFG3 1_COFIG_3 3.3VAUX1_2
3 4
5 3_GND 3.3VAUX2_4 6 R9386 1 @ 2 0_0201_5%
5_GND FULL_CARD_POWER_OFF#_6 -WWAN_PWROFF [9]
USBP1+ 0_0201_5% 1 2 R794 @ USBP1+_CONN 7 8 -WWAN_DISABLE
[11] USBP1+ 7_USB_D+ W_DISABLE1#_8 -WWAN_DISABLE [9]
USBP1- 0_0201_5% 1 2 R793 @ USBP1-_CONN 9 10
[11] USBP1- 9_USB_D- LED#_10
11
11_GND

13 12
[9] WWAN_CFG0 21_CONFIG_0 GPIO_5_20
15 14
17 23_WAKE_ON_WWAN# GPIO_6_22 16
19 25_DPR GPIO_7_24 18 JSIM1 ME@
21 27_GND W_DISABLE2#_26 20 C1 C5
23 29_USB3.0-TX-(PETN1) UIM-RFU_28 22 UIM_RESET C2 VCC GND C6
25 31_USB3.0-TX+(PETP1) UIM-RESET_30 24 R1066 1 RF@ 2 0_0201_5% UIM_CLK C3 RST VPP C7 UIM_DATA
27 33_GND UIM-CLK_32 26 UIM_DATA C4 CLK I/O C8
29 35_USB3.0-RX-(PERN1) UIM-DATA_34 28 UIM_PWR NC NC
31 37_USB3.0-RX+(PERP1) UIM-PWR_36 30 1
PCIE11_RXN 33 39_GND DEVSLP_38 32 DLSW 2
[11] PCIE11_RXN 41_SATA-B+(PETN0) GPIO_0_40 DTSW
PCIE11_RXP 35 34 2
[11] PCIE11_RXP 43_SATA-B-(PETP0) GPIO_1_42
37 36 @RF@ 3 6
PCIE11_TXN C8675 1 2 0.22U_0201_6.3V6K PCIE11_TXN_C 39 45_GND GPIO_2_44 38 C8535 4 GND GND 7
[11] PCIE11_TXN 47_SATA-A-(PERN0) GPIO_3_46 GND GND
PCIE11_TXP C8676 1 2 0.22U_0201_6.3V6K PCIE11_TXP_C 41 40 68P_0201_25V8 5 8
[11] PCIE11_TXP 49_SATA-A+(PERP0) GPIO_4_48 1 GND GND
43 42 -PLTRST_FAR 9
51_GND (PERST#)_50 GND

33P_0201_25V8J

33P_0201_25V8J

33P_0201_25V8J

33P_0201_25V8J
4.7U_0402_6.3V6M

@RF@

@RF@

@RF@

@RF@
-PCIE11_CLK_100M 45 44
[13] -PCIE11_CLK_100M 53_(REFCLKN) (CLKREQ#)_52 -CLKREQ_PCIE11 [13]
PCIE11_CLK_100M 47 46 R9585 2 1 0_0201_5% -PCIE_WAKE 2 2 2 2 2 JAE_SF51S006V4DR1400Q
[13] PCIE11_CLK_100M 55_(REFCLKP) (PEWAKE#)_54
49 48
51 57_GND RESERVED1_56 50 @
53 59_ANTCTRL0 RESERVED2_58 52
61_ANTCTRL1 COEX3_60 1 1 1 1 1

C623

C265

C266

C268

C269
55 54
@ 57 63_ANTCTRL2 COEX2_62 56
65_ANTCTRL3 COEX1_64 R9510
0_0201_5% 1 2 R795 59 58
[9] -WWAN_RESET 67_RESET# SIM DETECT_66
61 60 2 @ 1 SUSCLK_32K
[9] WWAN_CFG1 69_CONFIG_1 SUSCLK_68
63 62
65 71_GND 3.3VAUX3_70 64
67 73_GND 3.3VAUX4_72 66 0_0201_5%
[9] WWAN_CFG2 75_CONFIG_2 3.3VAUX5_74
C VCC3WAN C

2
VCC3WAN
@ 68
D52 GND 69
RCLAMP0502B.TCT_SC75-3 GND
D21
DEREN_40-42258-06711RHF UIM_RESET 1 6 UIM_CLK

1
V I/O V I/O
PLACE NEAR JWWAN1 2
Ground V BUS
5
2
RF@
2
@RF@
2 2 2
@
C8616 C8617 C1118 C1119 C1156
UIM_PWR 3 4 UIM_DATA 0.1U_0201_6.3V6K 2200P_0201_50V7K 0.1U_0201_10V6K 1U_0402_6.3V6K 10U_0402_6.3V6M
V I/O V I/O 1 1 1 1 1
PUSB2X4D_SO6-6
ESD@

TYPE-A M.2 CARD FOR WLAN / Bluetooth


VCC3B
2630S3 CONNECTOR
Vinafix.com VCC3WLAN VCC3WLAN
VCC3WLAN
2

10K_0201_5%
R591
10K_0201_5%
2 2 2 2 2

2
JWLAN1 ME@ RF@ @RF@ @
1

C8618 C8619 C1116 C1117 C1155


0.1U_0201_6.3V6K 2200P_0201_50V7K 0.1U_0201_10V6K 1U_0402_6.3V6K 10U_0402_6.3V6M
1 2 1 1 1 1 1
USBP6+ @ R790 1 2 0_0201_5% USBP6+_CONN 3 1_GND 3.3VAUX1_2 4
[11] USBP6+

1
3_USB_D+ 3.3VAUX2_4

R9512
USBP6- @ R792 1 2 0_0201_5% USBP6-_CONN 5 6
[11] USBP6- 5_USB_D- LED1#_6
7
7_GND
B B

9 8
100_0201_5% 2 1 R9474 11 17_DP_MLDIR LED2#_16 10
[53] EC_TX_P80_DATA 19_DP_ML3N GND_18
100_0201_5% 2 1 R9475 13 12
[53] EC_RX_P80_CLK 21_DP_ML3P DP_AUXN_20
15 14
17 23_GND DP_AUXP_22 16
19 25_DP_ML2N GND_24 18
21 27_DP_ML2P DP_ML1N_26 20
FVT_C_EC003 23
25
29_GND
31_DP_HPD
DP_ML1P_28
GND_30
22
24
PCIE2_TXP C2468 1 2 0.1U_0201_10V6K PCIE2_TXP_C 27 33_GND DP_ML0N_32 26
[11] PCIE2_TXP 35_PERP0 DP_ML0P_34
PCIE2_TXN C2469 1 2 0.1U_0201_10V6K PCIE2_TXN_C 29 28
[11] PCIE2_TXN 37_PERN0 GND_36
31 30 -CL_RST_WLAN
39_GND CLINK RESET#_38 -CL_RST_WLAN [8]
PCIE2_RXP 33 32 CL_DATA_WLAN
[11] PCIE2_RXP 41_PETP0 CLINK DATA_40 CL_DATA_WLAN [8]
PCIE2_RXN 35 34 CL_CLK_WLAN
[11] PCIE2_RXN 43_PETN0 CLINK CLK_42 CL_CLK_WLAN [8]
37 36
PCIE2_CLK_100M 39 45_GND COEX3_44 38
[13] PCIE2_CLK_100M 47_REFCLKP0 COEX2_46
-PCIE2_CLK_100M 41 40
[13] -PCIE2_CLK_100M 49_REFCLKN0 COEX1_48
43 42 R9576 2 @ 1 0_0201_5%
51_GND SUSCLK_50 SUSCLK_32K [13]
-CLKREQ_PCIE2 45 44 -PLTRST_FAR
[13] -CLKREQ_PCIE2 53_CLKREQ0# PERST0#_52 -PLTRST_FAR [14,30,33,45,46,49,52,53]
-PCIE_WAKE 47 46
[14,48] -PCIE_WAKE 55_PEWAKE0# W_DISABLE2#_54 BDC_ON [9]
49 48 -WLAN_RF_KILL
57_GND W_DISABLE1#_56 -WLAN_RF_KILL [53]
51 50
59_PERP1 I2C DATA_58
2

53 52
R9476 55 61_PERN1 I2C CLK_60 54
100K_0201_5% 57 63_GND I2C ALERT#_62 56
59 65_PETP1 RESERVED_64 58
61 67_PETN1 PERST1#_66 60
1

63 69_GND CLKREQ1#_68 62
65 71_REFCLKP1 PEWAKE1#_70 64
67 73_REFCLKN1 3.3VAUX3_72 66
For EC to detect debug card insert. 75_GND 3.3VAUX4_74
3

@ 69 68
D109 GND GND
RCLAMP0502B.TCT_SC75-3

LCN_DAN05-67216-S100
1

A A

PLACE NEAR JWLAN1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIE M.2 CARD SLOT
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 32 of 73
5 4 3 2 1
5 4 3 2 1

TABLE
VCC3B_RTS5236S VCC3B_RTS5236S
Pin name SD/MMC MEMORSTICK

SP1 SD_D1
2 2 2 2 SP2 SD_D0 MS_D1
C1819 C1820 C1821 C1822 SP3 SD_CLK MS_D0
VCC3B VCC3B_RTS5236S 0.1U_0201_10V6K 4.7U_0402_6.3V6M 0.1U_0201_10V6K 10U_0402_6.3V6M
@ 1 1 1 1
SP4 SD_CMD MS_D2
0_0603_5% SP5 SD_D3 MS_D3
R2472 1 2
SP6 SD_D2 MS_CLK
D D
SP7

VCC3B VCC3B VCC3_MC

2
R958 R1865
10K_0201_5% 10K_0201_5%

27
11
U156

3V3AUX
3V3_IN
PCIE0_CLK_100M 5 12
[13] PCIE0_CLK_100M REFCLKP CARD_3V3
-PCIE0_CLK_100M 6 18 DV33_18 C1826 1 2 1U_0402_6.3V6K
[13] -PCIE0_CLK_100M REFCLKN DV33_18
-CLKREQ_PCIE0 2 17 SD_MMC_CLK_R R2466 1 2 33_0201_5% SD_MMC_CLK
[13] -CLKREQ_PCIE0 CLK_REQ# SP3 19 SD_MMC_CMD_R @ R2471 1 2 0_0201_5% SD_MMC_CMD
PCIE0_RXP C441 1 2 0.1U_0201_10V6K PCIE0_RXP_C 7 SP4
[11] PCIE0_RXP HSOP
PCIE0_RXN C258 1 2 0.1U_0201_10V6K PCIE0_RXN_C 8 RTS5232S 16 SD_MMC_D0_R @ R2470 1 2 0_0201_5% SD_MMC_D0
[11] PCIE0_RXN HSON SP2 15 SD_MMC_D1_R @ R2469 1 2 0_0201_5% SD_MMC_D1
PCIE0_TXP C260 1 2 0.1U_0201_10V6K PCIE0_TXP_C 3 SP1 21 SD_MMC_D2_R @ R2468 1 2 0_0201_5% SD_MMC_D2
[11] PCIE0_TXP HSIP SP6
PCIE0_TXN C261 1 2 0.1U_0201_10V6K PCIE0_TXN_C 4 20 SD_MMC_D3_R @ R2467 1 2 0_0201_5% SD_MMC_D3
[11] PCIE0_TXN HSIN SP5
-PLTRST_FAR 1 30 -SD_MMC_CD
[14,30,32,45,46,49,52,53] -PLTRST_FAR PERST# SD_CD# 31
-PCIE_WAKE_MC 32 MS_INS#
C C
WAKE# 29
SP7
22
NC 23
AV12 10 NC 24
AV12 NC 2
1 2 DV12S 14 25 @RF@
DV12S NC 26 C8600
R2437 @ 13 NC R1855 VCC3B
NC 6P_0402_50V8D
0_0201_5% 1

E-PAD
9 28 1 2
RREF GPIO Close to R675
10K_0201_5%
RTS5236S-GR_QFN32_4X4

33
2
2 2 2
R1856

Vinafix.com
C1823 C1824 C1825 6.19K_0201_1%
0.1U_0201_10V6K 0.1U_0201_10V6K 4.7U_0402_6.3V6M
1 1 1
Change to RTS5236 (SA0000AUN00)

B B
VCC3_MC

2 2 2
C8684 C8683 @
0.1U_0201_10V6K 10U_0402_6.3V6M C8682
22U_0603_6.3V6M
1 1 1

JSD1 ME@
6
VSS
7 SD_MMC_D0
DAT0 8 SD_MMC_D1
DAT1 1 SD_MMC_D2
DAT2 2 SD_MMC_D3
DAT3

3 SD_MMC_CMD
CMD 5 SD_MMC_CLK
CLK

10 4
11 GND VDD 9 -SD_MMC_CD
12 GND Detect
13 GND
A A
GND

T-SOL_158-1000902603

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MEDIA CARD CONTROLLER
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 33 of 73
5 4 3 2 1
5 4 3 2 1

D D

VCC5B VCC5B

2
C41
0.1U_0201_10V6K F35
0467001.NRHF 1A 32V
1

VCC5B_CN

1
JSCR1
-SC_DTCT 1
[10] -SC_DTCT 1
2
3 2
USBP4+ 4 3
[11] USBP4+ 4
USBP4- 5
[11] USBP4- 5
VCC5B_CN 6
6 7
GND 8
GND
CVILU_CF61062D0R0-05-NH
ME@

C C

Vinafix.com VCC3B

2
F8
0467.500NRHF 0.5A 32V

1
B B
JFPR1
1
2 1
3 2
3

FPR
4
5 4
USBP8+ @ R800 1 2 0_0201_5% USBP8+_CONN 6 5
[11] USBP8+ 6
USBP8- @ R799 1 2 0_0201_5% USBP8-_CONN 7
[11] USBP8- 7
FUSEVCC3FP 8
8 9
GND 10
2 GND
C208 CVILU_CF5508FD0R1-05-NH
2.2U_0402_6.3V6M ME@
1

USBP8+_CONN

USBP8-_CONN
2

D27
PESD5V0U2BT_SOT23-3
ESD@
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SMART CARD/FPR
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 34 of 73
5 4 3 2 1
5 4 3 2 1

@
VCC1R8_SUS
0_0603_5%
R9344 1 2 VCC1R8_SUS_CODEC

2 2
C105 C82
2.2U_0402_6.3V6M 0.1U_0201_10V6K 2
D 1 1 D
C163
TABLE MIC HW ENABLE/DISABLE 1
1U_0402_6.3V6K

ENABLE DISABLE VCC3B @


AGND
0_0603_5%
R2029 1 2 VCC3B_CODEC
R961 ASM NO ASM
R119 ASM NO ASM 2 2 2
C8587 C116 C154
2.2U_0402_6.3V6M 0.1U_0201_10V6K 1U_0402_6.3V6K
1 1 1

VCC3M
@

LOGIC 0_0603_5% AGND


R2030 1 2 VCC3_SUS_CODEC

2
C28 2 2
1U_0402_6.3V6K @
1 C8506 C8505
Reserve for EMI/ESD 0.47U_0201_6.3V6K 0.1U_0201_10V6K VCC1R8_SUS
1 1
AGND

2
47

46

45

33

32
2

9
U8 R9294
C8594 5.11K_0402_1%

LDO_12

HDA_VDDIO

DVDD_IO

VDD18

LDO_AVDD

VREFP

VREF_DAC
C 1000P_0201_25V7K C
1 @ESD@

1
37
MICBIASE
-HDA_RST 2 38
[10] -HDA_RST RESET# MICBIASB
HDA_BCLK 48 43 HP_JD
[10] HDA_BCLK BCLK JSENSE HP_JD [37]
HDA_SYNC 49
[10] HDA_SYNC SYNC
HDA_SDIN0 R169 1 2 33_0201_5% 50 27
[10] HDA_SDIN0 SDI PORTM_MONO
HDA_SDO 1
[10] HDA_SDO SDO 42
PORTF_R 41
PORTF_L
-SPK_MUTE R9582 2 @ 1 0_0201_5% 7 29
[53] -SPK_MUTE SPKR_MUTE#/GPIO1 PORTE_R 28
PORTE_L
BEEP_MIX_ATT C2503 1 2 0.1U_0201_10V6K 44 40
[40] BEEP_MIX_ATT PC_BEEP PORTB_R
CX11771 39
PORTB_L

Vinafix.com
6 36
MUSIC_REQ/SPDIF/GPIO0 PORTD_B_MIC PORTD_B_MIC [38]
35
PORTD_A_MIC PORTD_A_MIC [38]
EMI@
MIC_CLK R119 1 2 PBY060303T-241Y-N 10 31
[26,27] MIC_CLK DMIC_CLK1/GPIO2 HGNDB HGNDB [36]
MIC_DATA 8
[26,27] MIC_DATA DMIC_DAT1/GPIO3 30
HGNDA HGNDA [36]
22P_0201_25V8
47K_0201_5%

100P_0201_25V8J

100P_0201_25V8J
47P_0201_25V8J

2 10K_0201_5%

PBY060303T-241Y-N 12 26 HP_R_JACK
DMIC_CLK2/GPIO4 PORTA_R HP_R_JACK [36]
13 25 HP_L_JACK
DMIC_DAT2/GPIO5 PORTA_L HP_L_JACK [36]
VCC3M 20
4 CP_VDD18
R9345 HSCL 23
CP_VNEG

SPK_RIGHT+
SPK_RIGHT-
1 2 5 24

SPK_LEFT+

SPK_LEFT-
HSDA CP_VPOS
2

VCC1R8_SUS

PVDD5_R
2 2 2 2

PVDD5_L
@EMI@

@EMI@

10K_0201_5% 11 22

AVDD5
@RF@ @ESD@ @RF@ @ EPAD CP_FLYN 21
CP_FLYP

EP
1 1 1 1
C8620

C324
R124 1

R908 1
C815

C817

CX11771-31Z_QFN50_6X6

34

15

18

14

16

17

19

51
B R9383 2 2 2 2 2 2 2 B
VCC5BA 0_0201_5% C8592 C8591 C8590 C43 C244 C133 C259
1 @ 2

33P_0201_25V8J

33P_0201_25V8J
2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

0.1U_0201_10V6K

4.7U_0402_6.3V6M
VCC3B @ @
1 1 1 1 1 1 1
2

2 AGND

R9363 C8597 See design guide


100K_0201_5% 1U_0402_6.3V6K
1 for ground
R9364
1

connections.
-SPK_MUTE 1 2

10K_0201_5%
AGND

VCC5B
USE SHAPE
@

R2031 0_0603_5%
1 2 VCC5B_CODEC R9413 1 2 SP_OUTR+
SP_OUTR+ [39]
0_0603_5% 0_0603_5%
10U_0402_6.3V6M

10U_0402_6.3V6M
0.1U_0201_10V6K

0.1U_0201_10V6K

R9414 1 2 SP_OUTR-
SP_OUTR- [39]
2 2 2 2
0_0603_5%
C54 C34 C329 C153 R9415 1 2 SP_OUTL-
SP_OUTL- [39]
1 1 1 1 0_0603_5%
R9416 1 2 SP_OUTL+
SP_OUTL+ [39]
VCC5B @ VCC5BA

0_0603_5%
R2015 1 2

1000P_0201_25V7K

1000P_0201_25V7K

1000P_0201_25V7K

1000P_0201_25V7K
PLACE NEAR CODEC 2 2 2 2
10U_0402_6.3V6M
0.1U_0201_10V6K

C122 C127 C117 C243


10U_0402_6.3V6M

0.1U_0201_10V6K

2 C333 2 2 2
A C318 C30 A
@ C535 1 1 1 1

1 1 1 1

@
1 2
PLACE UNDER CX11771-31Z
C36 0.01U_0201_6.3V7K @
C8593 @ 0_0603_5%
AGND 1 2 R9462 1 2

0.01U_0201_6.3V7K Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title
AGND AGND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AUDIO CX11852
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 35 of 73
5 4 3 2 1
5 4 3 2 1

D NEAR AUDIO CONN D

FL3
HP_L_JACK 1 2
[35] HP_L_JACK
34.8_0402_1%

FL5
HP_R_JACK 1 2
[35] HP_R_JACK
34.8_0402_1%

2
@ @ 1 1
R742 R743 C13 C197
220_0201_5% 220_0201_5% 100P_0201_25V8J 100P_0201_25V8J

1
2 2

AGND AGND

VCC3B
C
WIDE AND SHORT PATTERN C
2

R1867
10K_0201_5%
1

Vinafix.com
JAD1
1
1 2
2 3
3 4
4 HGNDA [35]
5 HP_L_JACK_C
5 6
9 6 7
10 GND 7 8
GND 8

CVILU_CI2008M2HRA-NH
HP_JACK_IN
ME@ HP_JACK_IN [37]
HP_R_JACK_C
HGNDB [35]

1 2
MIC_SLEEVE [38]
2

AGND C8507 2.2U_0402_6.3V6M


R139
B B
100K_0201_5% 1 2
MIC_RING2 [38]
C8508 2.2U_0402_6.3V6M
WIDE PATTERN
1

AGND

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AUDIO CONNECTOR
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 36 of 73
5 4 3 2 1
5 4 3 2 1

D D

1 @ 2
R537 0_0201_5%

C AGND C

1 2 HP_JD
HP_JD [35]
R9295 39.2K_0201_1%

1
Vinafix.com
Q50
[36] HP_JACK_IN HP_JACK_IN 1 2 2 LSK3541G1ET2L_VMT3
R257 22K_0201_5%

3
2
@
C9
2.2U_0402_6.3V6M
1

AGND AGND

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AUDIO JACK SENSE
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 37 of 73
5 4 3 2 1
5 4 3 2 1

D D

[36] MIC_SLEEVE MIC_SLEEVE 1 2 PORTD_A_MIC


PORTD_A_MIC [35]
R125 100_0402_5%

@
C1417
100P_0201_25V8J
1

C C

AGND

[36] MIC_RING2 MIC_RING2 1 2 PORTD_B_MIC


PORTD_B_MIC [35]
R126 100_0402_5%

@
C142

Vinafix.com
100P_0201_25V8J
1

AGND

NEAR EXT MIC CONN 1 2


@
R6 0_0201_5%

B B
AGND

1 2

C91 0.01U_0201_6.3V7K

AGND

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AUDIO EXT MIC I/F
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 38 of 73
5 4 3 2 1
5 4 3 2 1

D D

JSPK1
[35] SP_OUTL+ SP_OUTL+ 1
SP_OUTL- 2 1
[35] SP_OUTL- 2
C [35] SP_OUTR+ SP_OUTR+ 3 C
SP_OUTR- 4 3
[35] SP_OUTR- 4
5
6 GND
GND
CVILU_CI4204M2HR0-NH
ME@

2 2 2 2
@EMI@ @EMI@ @EMI@ @EMI@
C166 C168 C169 C175
220P_0201_25V7K 220P_0201_25V7K 220P_0201_25V7K 220P_0201_25V7K
1 1 1 1

Vinafix.com
PLACE, NEAR SPEAKER CONNECTOR

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AUDIO SPEAKER
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 39 of 73
5 4 3 2 1
5 4 3 2 1

D D

D51
[53] EC_SPKR EC_SPKR 2
1
[10] PCH_SPKR PCH_SPKR 3

BAS40CW_SOT323-3

1
R66
10K_0201_5%

2
C C

BEEP_MIX_ATT
BEEP_MIX_ATT [35]

1
R67
10K_0201_5%

2
Vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AUDIO BEEP/DAUGHTER CARD
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 40 of 73
5 4 3 2 1
5 4 3 2 1

Intelligent Cooling G-Sensor Thermal Sensor


TABLE

CS Mode Selection
TABLE
H I2C Mode
ACC2_SA0 Address Selection
D L SPI Mode D

H 32h (W) & 33h (R)


L 30h (W) & 31h (R)
VCC3B
VCC3B
VCC3M BOTTOM UNDER HEAT PIPE
BOTTOM NEAR UP SIDE OUTLINE
VCC3M
VCC3M U31
VCC3M 2 2 U157 @

2
C2170 C2171 1 10 TH_SMB_CK2
R2081 VDD SMCLK 1 10 TH2_SMB_CK2
0.1U_0201_10V6K 10U_0402_6.3V6M VDD SMCLK
2

@ 1 1 REMOTE1+ 2 9 TH_SMB_DA2
10K_0201_5% DP1 SMDATA
R2080 REMOTE_A+ 2 9 TH2_SMB_DA2

14
1 DP1 SMDATA

1
10K_0201_5% U121 C433 REMOTE1- 3 8 @ 1

1
DN1 ALERT#
2.2K_0201_5%

2.2K_0201_5%

0.1U_0201_10V6K C8823 REMOTE_A- 3 8

Vdd_IO

Vdd
8 REMOTE2+ 4 7 0.1U_0201_10V6K DN1 ALERT#
1

SMB_CK2_GS 4 CS 2 DP2/DN3 THERM# REMOTE_B+ 4 7


[53] SMB_CK2_GS SCL/SPC 2 DP2/DN3 THERM#
SMB_DA2_GS 6 REMOTE2- 5 6
[53] SMB_DA2_GS SDA/SDI/SDO DN2/DP3 GND
ACC2_SA0 7 REMOTE_B- 5 6
SDO/SA0 11 DN2/DP3 GND
INT1 GSENSE_INT [53]
2

16 9 ACC2_INT2_1 @ T134 S IC F75303M MSOP 10P SENSOR


ADC1 INT2
1

15 EMC1403-2-AIZL-TR_MSOP10
R2082 13 ADC2 10
10K_0201_5% ADC3 RES
2 Address 1001_101xb
Address 1001_100xb
1

NC
R2418

R2419

3
2nd source

GND

GND
2

NC
SA000029210-->EMC1403-2-AIZL-TR 2nd source
SA000029210-->EMC1403-2-AIZL-TR

12
SMB_CK2_GS KX023-1025 _LGA16_3X3

SMB_DA2_GS

C C

KX023-1025 Address: 0x1Eh REMOTE1,2 (+/-) : REMOTEA,B (+/-) :


Trace width/space:10/10 mil Trace width/space:10/10 mil
Trace length:<8" Trace length:<8"

REMOTE1+ BOTTOM CORE CHOKE REMOTE_A+ TOP NEAR DOWN


Close to U31 Close to U157 SIDE OUTLINE

1
REMOTE1+ C REMOTE_A+ C
1 @ C436 2 Q5 1 @ C8822 2 Q212@
2200P_0402_25V7K B MMBT3904WT1G_SC70-3 @ 2200P_0402_25V7K B MMBT3904WT1G_SC70-3

2
C437 E C8825 E

3
2200P_0402_25V7K REMOTE1- 2200P_0402_25V7K REMOTE_A-
2 REMOTE1- 2 REMOTE_A-

Vinafix.com
REMOTE2+ REMOTE_B+
1 BOTTOM CHARGE 1 BOTTOM JSSD1
G-Sensor C438
REMOTE2+ @
C8824
REMOTE_B+

1
2200P_0402_25V7K C 2200P_0402_25V7K C
2 REMOTE2- @ C439 2 Q6 2 REMOTE_B- @ C8821 2 Q213@
2200P_0402_25V7K B MMBT3904WT1G_SC70-3 2200P_0402_25V7K B MMBT3904WT1G_SC70-3

2
E E

3
REMOTE2- REMOTE_B-

VCC3B VCC3B REMOTE2+ BOTTOM JSSD1

3
E
B
@ C8798 2 @
2200P_0402_25V7K Q208

2
C
MMBT3904WT1G_SC70-3

1
B B
REMOTE2-
2

2
2

R9313 @ R9314 @
R9317 0_0201_5% 0_0201_5%
0_0201_5% @
1

1
1

U152 VCC3B VCC3B

10 1 ACC2_IOVDD
[9,26,27] ISH_I2C0_SDA SDA IO VDD
9 5 ACC2_VDD
[9,26,27] ISH_I2C0_SCL SCL VDD
ACC2_ADDR 8 2
D302 ADDR DNC 3
2 1 ACC2_INT 7 DNC
[9,26,27] ISH_GP2 INT
6 4 2 2
RSVD GND
RB521CM-30T2R_SOD923-2
2

2
C8528 C8529
R9318 KXCJ9-1008_LGA10 1U_0402_6.3V6K 1U_0402_6.3V6K R9594
0_0201_5% 1 1 SMB_CK2 6 1 TH_SMB_CK2 EC_SMB_CK2 2 1 EC_SMB_CK2_R 6 1 TH2_SMB_CK2
[8] SMB_CK2 [8,51,53] EC_SMB_CK2
Q206A 0_0201_5% Q215A
1

SSM6N48FU 2N SC-88-6 ET88 @ SSM6N48FU 2N SC-88-6 ET88


@

5
R9595
SMB_DA2 3 4 TH_SMB_DA2 EC_SMB_DA2 2 1 EC_SMB_DA2_R 3 4 TH2_SMB_DA2
[8] SMB_DA2 [8,51,53] EC_SMB_DA2
Q206B 0_0201_5% Q215B
SSM6N48FU 2N SC-88-6 ET88 @ SSM6N48FU 2N SC-88-6 ET88
KXCJ9 Address: 0x1Ch @

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SENSOR INTERFACE
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 41 of 73
5 4 3 2 1
5 4 3 2 1

D D
VCC3B VCC3M

2
@ F42 F25
0.5A_65V_T0603FF0500TM 0.5A_65V_T0603FF0500TM

1
VCC5_TP VCC5_TP VCC5_TP VCC5B

2
C8482
0.1U_0201_6.3V6K
1

10K_0201_5%
4.7K_0201_5%

4.7K_0201_5%
VCC3M_KEY_CONN

2
F23
2A_32V_0438002.WR

1
2

2
JKB1
34

1
GND

R293

R294

R324
33
GND
32 JTP1
-LED_CAPSLOCK R2450 1 2 200_0201_1% 31 32 14
[53] -LED_CAPSLOCK 31 GND
30 13
-HOTKEY 29 30 GND
C C
[53] -HOTKEY 29
-LED_MICMUTE R994 1 2 200_0201_1% 28 12
[53] -LED_MICMUTE 28 12
-LED_MUTE R41 1 2 200_0201_1% 27 -KBD_BL_DTCT 11
[53] -LED_MUTE 27 [53] -KBD_BL_DTCT 11
-LED_FNLOCK R103 1 2 200_0201_1% 26 KBD_BL_PWM 10
[53] -LED_FNLOCK 26 [53] KBD_BL_PWM 10
25 9
DRV11 24 25 TP4CLK 8 9
24 [43] TP4CLK 8
DRV8 23 7
DRV10 22 23 6 7
DRV12 21 22 5 6
DRV9 20 21 4 5
DRV13 19 20 TP4_RESET 3 4
19 [43,53] TP4_RESET 3
DRV15 18 TP4DATA 2
18 [43] TP4DATA 2
DRV5 17 1
DRV7 16 17 1
DRV6 15 16 JAE_FL10F012HA1R3000-W
DRV3 14 15 ME@
DRV1 13 14
[53] DRV[15:0] 13
SENSE5 12
12

Vinafix.com
DRV2 11
DRV4 10 11
[53] SENSE[7:0] 10
SENSE0 9
SENSE2 8 9
DRV0 7 8
7 1 2
SENSE1 6
SENSE4 5 6 C8308 C8286
DRV14 4 5 220P_0201_25V7K
4 22U_0603_6.3V6M
SENSE6 3 2 1
SENSE7 2 3
SENSE3 1 2
1
JAE_FL10F032HA2R3000
ME@

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KEYBOARD/TRACK POINT
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 42 of 73
5 4 3 2 1
5 4 3 2 1

VCC3SW
TO SUB BOARD

VCC3M VCC3M_PEN

2
F31
1 2 R870
4.7K_0201_1%
D PTC 0.35A_6V_PICOSMDC035S-2 D

1
VCC3M_BUTTON D1
-PWRSWITCH 1 2 -PWRSW -PWRSW [53]
VCC3B VCC5B R9309 1 @ 2 330_0603_5% RB521CM-30T2R_SOD923-2

VCC5M VCC5M_BUTTON

2
F15 R9570 1 2 330_0603_5% VCC3SW VCC3M_BUTTON VCC5M_BUTTON
0.5A_65V_T0603FF0500TM

2
R24 R25
4.7K_0201_5% 4.7K_0201_5%

0467.500NRHF 0.5A 32V


1

2
1

1
JCP1
1
SMB_CLK_3B 2 1
[46] SMB_CLK_3B 2
3
TP4DATA 4 3
[42] TP4DATA

F36 1
TP4CLK 5 4
[42] TP4CLK 5

Clickpad
SMB_DATA_3B 6
[46] SMB_DATA_3B 6
FUSEVCC5B 7 JBTN1
-PAD_RESET 8 7 1
[53] -PAD_RESET 8 1
IPDCLK 9 -LED_PWR 2
[53] IPDCLK 9 [53] -LED_PWR 2
IPDDATA 10 -PWRSWITCH 3
[53] IPDDATA 10 [46] -PWRSWITCH 3
TP4_RESET 11 4
[42,53] TP4_RESET 11 4
BYPASS_PAD 12 5
[53] BYPASS_PAD 12 5
-LID_CLOSE 6
[9,26,53] -LID_CLOSE 6
13 -TABLET_MODE 7 9
GND [9,53] -TABLET_MODE 7 GND
1 1 14 8 10
C8659 C8658 GND 8 GND
100P_0201_25V8J @ @ 100P_0201_25V8J CVILU_CF5512FD0R0-05-NH CVILU_CI2008M2HRA-NH
C ME@ C
2 2 ME@

1000P_0201_25V7K

1000P_0201_25V7K
RF@ 2 RF@ 2
C8654 C8655

1 1

IPDDATA TP4DATA
VCC5B
IPDCLK TP4CLK
2

R9473 1 @ 2 10K_0201_5% -PAD_RESET

D25 D26
PESD5V0U2BT_SOT23-3 PESD5V0U2BT_SOT23-3

Vinafix.com
@ESD@ @ESD@
Follow LIN2
1

VCC3B

2
VCC5B_CN

F17
0.5A_65V_T0603FF0500TM
B B

1
JNFC1
14
13 GND
GND VCC3M_PEN
12
VCC3_SUS VCC3B VCC3B FUSEVCC3B 11 12
I2C0_DATA_NFC 10 11
I2C0_CLK_NFC 9 10
8 9
8

NFC
NFC_INT 7
[11] NFC_INT 7
-NFC_DTCT 6
[9] -NFC_DTCT 6
NFC_ON 5 JPEN1
[11] NFC_ON 5
4 1
[10] NFC_ACTIVE 4 1
3 2
3 2
2

2 3
NFC_DLREQ 1 2 G1 4
[9] NFC_DLREQ 1 G2
R3126 R3127 R9409 R9408
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% CVILU_CF5512FD0R0-05-NH CVILU_CI4202M2HRP-NH
ME@ ME@
1

1
2

100K_0201_5%

100K_0201_5%

100K_0201_5%
2

2
6 1 I2C0_CLK_NFC
[9] I2C0_CLK
Q202A
SSM6N48FU 2N SC-88-6 ET88
R9379 1

R1215 1

R9381 1
5

3 4 I2C0_DATA_NFC
[9] I2C0_DATA
Q202B
SSM6N48FU 2N SC-88-6 ET88

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TOUCH PAD/NFC/BUTTON/PEN J
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 43 of 73
5 4 3 2 1
5 4 3 2 1

D D

VCC5B
FAN CURRENT
IS 0.5A MAX

FUSE 2.0A

2
2
RF@ F4
FVT_C_EC017 C8534
0.1U_0201_6.3V6K
2A_32V_0438002.WR
1

1
JFAN1
VCC5B_F4 1
FAN_ON 2 1
[53] FAN_ON 2
3 6
FAN_FRQ 4 3 G1 7
[53] FAN_FRQ 4 G2
[53] FAN_ID FAN_ID 5
5
CVILU_CI4305M2HR0-NH
ME@

C C

Vinafix.com
VCC5M
VCC5M

2
B B
R9506
100K_0201_5%

LED1
ORANGE

1
ORANGE

2 160_0402_5% 1 2 R9332 -LED_AC_ORANGE

1
3 180_0402_5% 1 2 R9333 -LED_AC_CON
-LED_AC_CON [53]

WHITE Q207 2
LED_AC_CHG [53]
LTW-326DSKF-5A_WHI-ORG LSK3541G1ET2L_VMT3

WHITE
H: LED ON

3
L: LED OFF

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN CONNECTOR
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 44 of 73
5 4 3 2 1
5 4 3 2 1

VCC3_SUS
D D

2
@
R2444
0_0603_5%

1
VCC3_SUS_TPM

2
2 2
@
R2347 C379 C2497
10K_0201_5% 0.1U_0201_10V6K 10U_0402_6.3V6M
1 1

1
U39
-PLTRST_FAR 17 1
[14,30,32,33,46,49,52,53] -PLTRST_FAR RST# VDD 8
-TPM_IRQ 18 VDD 22
[11] -TPM_IRQ PIRQ# VDD
SPI_CLK R2344 1 2 33_0201_5% SPI_CLK_2_R 19 3
[8,21] SPI_CLK SCLK NC 4
-SPI_CS2 R2343 1 2 33_0201_5% -SPI_CS2_R 20 NC 5
[8] -SPI_CS2 CS# NC 10
SPI_MOSI_IO0 R2345 1 2 33_0201_5% SPI_MOSI_IO0_2_R 21 NC 11
[8,21] SPI_MOSI_IO0 MOSI NC 12
SPI_MISO_IO1 R2346 1 2 33_0201_5% SPI_MISO_IO1_2_R 24 NC 13
[8,21] SPI_MISO_IO1 MISO NC 14
6 NC 15
GPIO NC 16
7 NC 25
PP NC R2482
26
2 NC 27 1 2
C C
9 GND NC 28
23 GND NC 29
32 GND NC 30 10K_0201_5%
33 GND NC 31
TABLE
PAD NC
S IC ST33HTPH2E32AHB6 VQFN 32P TPM ST Infineon
Pin No
ST33HTPH2E32AHB6 SLB9670VQ2.0 FW7.61

1 NC VDD
2 GND GND
-Change TPM1.2 to TPM2.0 3 NC NC
-Infineon SLB9670VQ2.0 part number SA00009N230 4 NC NC

Vinafix.com
-ST ST33HTPH2E32AHB6 part number SA00009SO40 5 NC NC
6 NC GPIO
FVT_C_EC001 7 PP PP
8 NC VDD
9 NC GND
10 NC NC
11 NC NC
12 NC NC
13 NC NC
14 NC VDD
B B
15 NC NC
16 NC GND

17 SPI_RST# RST#
18 SPI_PIRQ# PIRQ#
19 SPI_CLK SCLK
20 SPI_CS# CS#
21 MOSI MOSI
22 VDD VDD
23 NC GND
24 MISO MISO

25 NC NC
26 NC NC
27 NC NC
28 NC NC
29 NC NC
30 NC NC
31 NC NC
32 NC GND
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DISCRETE TPM 1.2
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 45 of 73
5 4 3 2 1
5 4 3 2 1

TABLE
REF DES ENABLE DISABLE

JLPC1 ASM NO_ASM


R220 ASM NO_ASM
D D

LOGIC

JLPC1
LPCCLK_DEBUG_24M 1 2 -PWRSWITCH -PWRSWITCH [43]
[8] LPCCLK_DEBUG_24M 1 2
3 4 LPC_AD0
-LPC_FRAME 5 3 4 6 LPC_AD1
[8,53] -LPC_FRAME 5 6
-CLKRUN 7 8 LPC_AD2
[8] -CLKRUN 7 8
IRQSER 9 10 LPC_AD3
[8,53] IRQSER 9 10
-PLTRST_FAR 11 12
[14,30,32,33,45,49,52,53] -PLTRST_FAR 11 12
B_ON 13 14 -SUS_STAT LPC_AD[3:0] [8,53]
[53,56,57] B_ON 13 14 -SUS_STAT [8]
15 16
G1 G2
HRS_DF12-14DP-0P5V
ME@

C C

VCC3B VCC3B VCC3_SUS

Vinafix.com
2

2
R150 R177 R30 R45
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
1

1
2
1 6 SMB_CLK [8]
[43] SMB_CLK_3B
Q199A
SSM6N48FU 2N SC-88-6 ET88

5
4 3 SMB_DATA [8]
[43] SMB_DATA_3B
Q199B
SSM6N48FU 2N SC-88-6 ET88

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SMBUS SWITCH/LPC DEBUG POR
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 46 of 73
5 4 3 2 1
5 4 3 2 1

Alpine Ridge LP - TBT, USB2 & DP Part

Alpine Ridge LP - TBT, USB2 & DP Part U4E

[50] USB3_A_TRX_DTX_P0 B21


TBT PORTS DP
A21 PA_RX0_P AB7 DP_SNK0_ML0_P 0.1U_0201_6.3V6K 2 1 C226
D [50] USB3_A_TRX_DTX_N0 DDIP1_0P [4] D
PA_RX0_N DPSNK0_ML0_P AC7 DP_SNK0_ML0_N 0.1U_0201_6.3V6K 2 1 C218
DPSNK0_ML0_N DDIP1_0N [4]
[50] USB3_A_TTX_C_DRX_P0 CT41 2 1 0.22U_0201_6.3V6MUSB3_A_TTX_DRX_P0 A19
CT42 2 1 0.22U_0201_6.3V6MUSB3_A_TTX_DRX_N0 B19 PA_TX0_P AB9 DP_SNK0_ML1_P 0.1U_0201_6.3V6K 2 1 C276
[50] USB3_A_TTX_C_DRX_N0 PA_TX0_N DPSNK0_ML1_P DDIP1_1P [4]
AC9 DP_SNK0_ML1_N 0.1U_0201_6.3V6K 2 1 C277
DPSNK0_ML1_N DDIP1_1N [4]
CONN

Sink Port 0
[50] USB3_A_TRX_DTX_P1 A15 AB11 DP_SNK0_ML2_P 0.1U_0201_6.3V6K 2 1 C317
PA_RX1_P DPSNK0_ML2_P DDIP1_2P [4]
[50] USB3_A_TRX_DTX_N1 B15 AC11 DP_SNK0_ML2_N 0.1U_0201_6.3V6K 2 1 C312
PA_RX1_N DPSNK0_ML2_N DDIP1_2N [4]
To CPU DDI1

Port A
[50] USB3_A_TTX_C_DRX_P1 CT39 2 1 0.22U_0201_6.3V6MUSB3_A_TTX_DRX_P1 A17 AB13 DP_SNK0_ML3_P 0.1U_0201_6.3V6K 2 1 C323
PA_TX1_P DPSNK0_ML3_P DDIP1_3P [4]
[50] USB3_A_TTX_C_DRX_N1 CT40 2 1 0.22U_0201_6.3V6MUSB3_A_TTX_DRX_N1 B17 AC13 DP_SNK0_ML3_N 0.1U_0201_6.3V6K 2 1 C339
PA_TX1_N DPSNK0_ML3_N DDIP1_3N [4]

[50] TBT_A_AUX_P_C CT43 2 1 0.1U_0201_6.3V6K TBT_A_AUX_P Y15 Y11 DP_SNK0_AUX_P 0.1U_0201_6.3V6K 2 1 C468 DDIP1_AUXP
PA_DPSRC_AUX_P DPSNK0_AUX_P DDIP1_AUXP [4]
[50] TBT_A_AUX_N_C CT44 2 1 0.1U_0201_6.3V6K TBT_A_AUX_N W15 W11 DP_SNK0_AUX_N 0.1U_0201_6.3V6K 2 1 C659 DDIP1_AUXN
PA_DPSRC_AUX_N DPSNK0_AUX_N DDIP1_AUXN [4]

[50,51] TBT_USB2P TBT_USB2P E20 AA2 DDIP1_HPD


PA_USB2_D_P DPSNK0_HPD DDIP1_HPD [4]
[50,51] TBT_USB2N TBT_USB2N D20
PA_USB2_D_N Y5
PD DPSNK0_DDC_CLK

2
R4
TBT_LSTX A5 NC_R4 R1037
[50] TBT_LSTX PA_LSTX
[50] TBT_LSRX TBT_LSRX A4 100K_0201_5%
TBT_HPD M4 PA_LSRX AB15
[51] TBT_HPD PA_DPSRC_HPD NC_AB15 AC15

1
NC_AC15
2 1 AN_PA_USB2_RBIAS H19 AB17
PA_USB2_RBIAS NC_AB17
2

RT43 499_0201_1% AC17


RT41 NC_AC17
100K_0201_5% USB2 Rbias A13 AB19
B13 NC_A13 NC_AB19 AC19
C Place as close as possible NC_B13 NC_AC19 C
1

to pins A11
NC_A11 NC_AB21
AB21
B11 AC21
NC_B11 NC_AC21
Y12
B7 NC_Y12 W12
A7 PB_RX0_N NC_W12
PB_RX0_P Y6
A9 RSV_Y6 Y8
B9 PB_TX0_P NC_Y8 N4
PB_TX0_N NC_N4 Y18 AN_DPSNK_RBIAS RT5 1 2 14K_0402_1%
DPSNK_RBIAS
HW

Vinafix.com
Y16 DPSNK Rbias
NC_Y16
Pull-Up/Pull-Down
1M_0201_1% 2 1 RT42 TBT_LSTX
W16
NC_W16 NC_R2
R2
R1 Place as close
NC_R1
1M_0201_1% 2 1 RT120 TBT_LSRX as possible to
E19 N2 pins
D19 NC_E19 NC_N2 N1
NC_D19 NC_N1
L2
B4 NC_L2 L1
B5 NC_B4 NC_L1
G2 NC_B5 J2
NC_G2 NC_J2 J1
VCC3_TBT F19 NC_J1
NC_F19 W19
NC_W19 Y19
NC_Y19
1

RT70 G1
B 100K_0201_5% NC_G1 B
N6
NC_N6
2

TBT_A_AUX_N_C JHL6240-QSXA-A1_BGA337

TBT_A_AUX_P_C
1

RT73
100K_0201_5%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AR : CIO/DP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A3 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 47 of 73
5 4 3 2 1
5 4 3 2 1

Alpine Ridge LP - Misc Part


Alpine Ridge LP - Misc
Symbol U4A
[51] TBT_EE_DI TBT_EE_DI AB3 U1 TBTA_I2C_SDA [51]
TBT_EE_DO AC4 EE_DI GPIO_0_I2C_DATA
[51] TBT_EE_DO EE_DO
-TBT_EE_CS AC3 U2

EE
[51] -TBT_EE_CS EE_CS_N GPIO_1_I2C_CLK TBTA_I2C_SCL [51]
[51] TBT_EE_CLK TBT_EE_CLK AB4
EE_CLK V1 -TBT_EE_WP

LC GPIO
GPIO_2_EE_WP#

DEBUG
TBT_TDI Y4

MISC &
D D
TBT_TMS V4 TDI V2 TBT_TMU_CLK_OUT
TBT_TCK T4 TMS GPIO_3_Reserved

JTAG
TBT_TDO W4 TCK W1 -PCIE_WAKE From CPU BB15
TDO GPIO_4_PEWAKE# -PCIE_WAKE [14,32]
TBT_XTAL_25_IN D22 W2 -TBT_PLUG_EVENT -TBT_PLUG_EVENT [9]
To CPU pin AD1
XTAL_25_IN GPIO_5_CIO_PLUG_EVENT
TBT_XTAL_25_OUT D23 Y1 DPSRC_CTRLDATA
XTAL_25_OUT GPIO_6_SRC0_DDC_DATA
+/- 0.5% Y2 DPSRC_CTRLCLK @
TBT_RSENSE J6 GPIO_7_SRC0_DDC_CLK
RSENSE R9591
2 1 TBT_RBIAS H6 AA1 TBT_SRC0_CFG1
RT25 4.75K_0402_0.5% RBIAS GPIO_8_SRC0_CFG1 TBTA_I2C_INT 2 1 TBTB_I2C_INT
Place as close J4 TBTA_I2C_INT TBTA_I2C_INT [51]
AC23 POC_GPIO_0_PA_PPS_INT_N 0_0201_5%
as possible to AB23 THERMDA1 E2 TBTB_I2C_INT
THERMDA2 POC_GPIO_1_PB_PPS_INT_N
pins AC1
TEST_EDM
L15 D4 TBT_RTD3_USB_PWR_EN
N15 FUSE_VQPS_64 POC_GPIO_2_RTD3_PWR_EN
NC_N15 H4 TBT_FORCE_PWR From CPU pin AD2
POC_GPIO_3_FORCE_PWR TBT_FORCE_PWR [9]
C23

POC GPIO
DEBUG
C22 MONDC_CIO_0 F2 -BATLOW_TBT D806 1 2 From System
NC_C22 POC_GPIO_4_BATLOW# -BATLOW [14,53]
RB521CM-30T2R_SOD923-2
D6 D2 -PCH_SLP_S3_TBT D807 1 2 -PCH_SLP_S3 [14,53]
From System
W13 MONDC_SVR POC_GPIO_5_DG_SLP_S3# RB521CM-30T2R_SOD923-2
W18 MONDC_DPSNK_0 F1 TBT_RTD3_CIO_PWR_EN
AB2 NC_W18 POC_GPIO_6_RTD3_CIO_PWR_EN
NC_AB2 AB5 TBT_TEST_PWG
A23 TEST_PWR_GOOD
C B23 ATEST_P E1 TBT_TEST_EN C
E18 ATEST_N TEST_EN
V18 USB2_ATEST F4 -TBT_RESET
PCIE_ATEST RESET_N -TBT_RESET [51]
JHL6240-QSXA-A1_BGA337

VCC3_LDO_TBT VCC3_TBT_LC

2
@
8Mbit Flash (Mutual for AR and PD)

Vinafix.com
RT105 RT106
HW Pull-Up/Pull-Down 0_0402_5% 0_0402_5%
DG_SLP_S3#: PU shuold be on the Host side @
VCC3_TBT DG_BATLOW#: PU shuold be on the Host side

1
-PCIE_WAKE RT20 2 @ 1 10K_0201_5%
UT2
-TBT_RESET RT80 2 @ 1 10K_0201_5% TBT_EE_DI 5 2 TBT_EE_DO
1 2
DI SO 3.3K_0402_5% RT49
TBT_FORCE_PWR RT125 2 @ 1 10K_0201_5% TBT_EE_CLK 6
1A CLK 1
VCC3_TBT VCC3M 1 2 -TBT_EE_CS 1 CT45
RT50 3.3K_0402_5% CS
0.1U_0402_10V7K
@ 1 2 -TBT_HOLD 7 2
VCC3_TBT RT51 3.3K_0402_5% HOLD
0_0603_5% 1 2 -TBT_EE_WP 3
B R9406 1 2 RT48 3.3K_0402_5% WP B
-TBT_PLUG_EVENT RT108 2 1 10K_0201_5% 8 4
VCC VSS
TBT_SRC0_CFG1 RT126 2 @ 1 10K_0201_5% W25Q80DVSSIG_SO8

VCC3_TBT_LC VCC3_TBT_LC

VCC3M

25MHZ 10PF +-20PPM


1

1
10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

TBTA_I2C_SDA RT138 2 1 2.2K_0201_5% RT6 RT7 RT8 RT9


@

TBTA_I2C_SCL
TBTA_I2C_INT
RT139 2
RT111 2
1
1
2.2K_0201_5%
10K_0201_5%
Crystal
TBTB_I2C_INT RT112 2 1 10K_0201_5%
R9465
JTAG1 YT1
2

1 TBT_XTAL_25_IN 2 1 TBT_XTAL_25_IN_R 1 2
TBT_TDI 2 1 XTAL0 NC
TBT_TMS 3 2 33_0201_5% 4 3
3 1 NC XTAL1
TBT_TCK 4 CT37
TBT_SRC0_CFG1 RT135 1 2 1M_0201_5% TBT_TDO 5 4 2 3 8.2P_0201_25V8D 25MHZ_10PF_7V25000014
6 5 @EMI@ FLJ21 2 3
6 2 1
TBT_TMU_CLK_OUT RT38 1 2 100K_0201_5% MCF12102G900-T_4P CT38
DPSRC_CTRLDATA RT109 1 2 100K_0201_5% 7 1 4 8.2P_0201_25V8D
DPSRC_CTRLCLK RT110 1 2 100K_0201_5% 8 GND 1 4
GND 2
TBT_TEST_PWG RT136 1 2 100_0201_5% ACES_50228-0067N-001
R9466
TBT_TEST_EN RT137 1 2 100_0201_5% ME@
A
TBT_RTD3_USB_PWR_EN RT115 2 1 10K_0201_5% TBT_XTAL_25_OUT 2 1 TBT_XTAL_25_OUT_R A

TBT_FORCE_PWR RT114 2 1 10K_0201_5% 33_0201_5%


-BATLOW_TBT RT31 2 1 10K_0201_5%
-PCH_SLP_S3_TBT RT30 2 1 10K_0201_5%
TBT_RTD3_CIO_PWR_EN RT116 2 1 10K_0201_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AR : MISC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A3 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 48 of 73
5 4 3 2 1
5 4 3 2 1

Alpine Ridge LP - Power Supply


Alpine Ridge SP - VCC
Symbol

Alpine Ridge SP - GND


Symbol U4D
A6 V5
A8 VSS_ANA VSS_ANA V6
A10 VSS_ANA VSS_ANA V8
A12 VSS_ANA VSS_ANA V9
D
A14 VSS_ANA VSS_ANA V15 D
A16 VSS_ANA VSS_ANA V16
A18 VSS_ANA VSS_ANA V20
VCC3_TBT A20 VSS_ANA VSS_ANA W5
A22 VSS_ANA VSS_ANA W6
VSS_ANA VSS_ANA

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
B6 W8
B8 VSS_ANA VSS_ANA W9
1 1 1 1 1 1 VSS_ANA VSS_ANA
CT137 CT138 CT139 CT140 CT129 CT130 B10 W20
B12 VSS_ANA VSS_ANA W22
VSS_ANA VSS_ANA

6.3V

6.3V

6.3V

6.3V
B14 W23
2 2 2 2 2 2 B16 VSS_ANA VSS_ANA Y9
U4C B18 VSS_ANA VSS_ANA Y13
0.9v @ 700mA VCC0R9_TBT_DP L8 A2
3.3v @ 820mA B20 VSS_ANA VSS_ANA Y20
VCC0P9_DP VCC3P3_SVR VSS_ANA VSS_ANA
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
L11 A3 B22 AA22

MAIN PWR SVR 3.3V


L12 NC_L11 VCC3P3_SVR B3 D8 VSS_ANA VSS_ANA AA23
CT270
1
CT108
1
CT109
1
CT110
1
CT111
1
CT112
1
CT124
1
M8 NC_L12 VCC3P3_SVR H9
3.3v @ 225mA @ D9 VSS_ANA VSS_ANA AB6
T11 VCC0P9_DP VCC3P3A VCC3_TBT_S0 VCC3_TBT D11 VSS_ANA VSS_ANA AB8
@
2 2 2 2 2 2 2
T12 VCC0P9_DP
VCC0P9_DP 3.3v @ 200mA 0_0603_5% D12 VSS_ANA
VSS_ANA GND VSS_ANA
VSS_ANA
AB10

1U_0201_6.3V6M

47U_0603_6.3V6M

47U_0603_6.3V6M
R13 RT121 1 2 D13 AB12
L6 VCC3P3_S0 D15 VSS_ANA VSS_ANA AB14
M6 NC_L6 F8
3.3v @ 185mA CT123
1
CT141
1
CT142
1
D16 VSS_ANA VSS_ANA AB16
V11 NC_M6 VCC3P3_SX VCC3_TBT D18 VSS_ANA VSS_ANA AB18
VCC0P9_ANA_DPSNK 3.3v @ 30mA VSS_ANA VSS_ANA

1U_0201_6.3V6M
V12 R6 E8 AB20
VCC0P9_ANA_DPSNK VCC3P3_LC 2 2 2 SHI0000N600(mount L if needs) VSS_ANA VSS_ANA

LC
V13 1 E9 AB22
VCC0P9_ANA_DPSNK L9 VCC3_TBT_LC CT131 E11 VSS_ANA VSS_ANA AC6
0.9v @ 580mA VCC0R9_TBT_PCIE M13 VCC0P9_SVR M9 E15 VSS_ANA VSS_ANA AC8
VCC0P9_PCIE VCC0P9_SVR VSS_ANA VSS_ANA
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
M15 E12 E16 AC10
VCC0P9_PCIE VCC0P9_SVR_ANA 2 VSS_ANA VSS_ANA

SVR 0.9V
1 1 1 1 1 M16 E13 1 E22 AC12
CT118 CT119 CT120 CT121 CT122 L19 VCC0P9_PCIE VCC0P9_SVR_ANA F11 CT132 E23 VSS_ANA VSS_ANA AC14
N19 NC_L19 VCC0P9_SVR_ANA F12 VCC0R9_TBT_SVR F9 VSS_ANA VSS_ANA AC16
VCC0P9_ANA_PCIE_1 VCC0P9_SVR_ANA VSS_ANA VSS_ANA

PWR OUT 0.9V


L18 F13 F16 AC18
2 2 2 2 2 M18 VCC0P9_ANA_PCIE_2 VCC0P9_SVR_ANA F15 2 F20 VSS_ANA VSS_ANA AC20
N18 VCC0P9_ANA_PCIE_2 VCC0P9_SVR_ANA J9
Share Same GND plane G22 VSS_ANA VSS_ANA AC22
VCC0P9_ANA_PCIE_2 VCC0P9_SVR_SENSE G23 VSS_ANA VSS_ANA P1
0.9v @ 220mA VCC0R9_TBT_USB R15 H1 VSS_ANA VSS_ANA P2
R16 VCC0P9_USB C1 TBT_SVR_IND H2 VSS_ANA VSS_ANA R5
VCC0P9_USB SVR_IND C2 H12 VSS_ANA VSS_ANA R18
SVR_IND VSS_ANA VSS_ANA
1U_0201_6.3V6M

1U_0201_6.3V6M

VCC0R9_TBT_CIO R8 D1 XFL4012-601MEC H13 R19


R9 VCC0P9_CIO SVR_IND LT2 H15 VSS_ANA VSS_ANA R20
1 1 VCC0P9_CIO 0.9v @ 1830mA VSS_ANA VSS_ANA
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

47U_0603_6.3V6M

47U_0603_6.3V6M

47U_0603_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
C CT271 CT115 R11 A1 1 2 VCC0R9_TBT_SVR H16 R22 C
R12 VCC0P9_CIO SVR_VSS B1 0.6UH_MND-04ABIR60M-XGL_20% 1 H20 VSS_ANA VSS_ANA R23
1 1 1 VCC0P9_CIO SVR_VSS 1 1 1 1 1 1 1 1 1 VSS_ANA VSS_ANA
@ CT117 CT116 CT272 0.9v @ 55mAVCC0R9_TBT_LVR B2 CT143 CT144 CT145 CT54 CT125 CT126 CT127 CT128 CT268 CT269 J5 T1
2 2 F18 SVR_VSS J18 VSS_ANA VSS_ANA T2
@ H18 VCC0P9_LVR J16 VCC3_TBT_ANA_USB2
3.3v @ 100mA @ @ J19 VSS_ANA VSS_ANA T5
2 2 2 J11 VCC0P9_LVR VCC3P3_ANA_USB2 L16 VCC3_TBT_ANA_PCIE 2 2 2 2 2 2 2 2 2 2 J20 VSS_ANA VSS_ANA U22
VCC0P9_LVR VCC3P3_ANA_PCIE VSS_ANA VSS_ANA

1U_0201_6.3V6M

1U_0201_6.3V6M
H11 3.3v @ 100mA J22 N23
VCC0P9_LVR_SENSE J23 VSS_ANA VSS_ANA N22
1 1 VSS_ANA VSS_ANA
10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

47U_0603_6.3V6M

JHL6240-QSXA-A1_BGA337 CT134 CT133 K1 N20


K2 VSS_ANA VSS_ANA N5
1 1 1 1 1 VSS_ANA VSS_ANA
CT135 CT136 CT113 CT114 CT146 L5 M20
2 2 L20 VSS_ANA VSS_ANA M19
L22 VSS_ANA VSS_ANA M5
2 2 2 2 2 L23 VSS_ANA VSS_ANA M2
M1 VSS_ANA VSS_ANA T20
VSS_ANA VSS_ANA U23
VSS_ANA

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Vinafix.com
JHL6240-QSXA-A1_BGA337

J12
J8
H8
H5
F6
F5
E6
E5
E4
D5
J13
J15
L13
M11
M12
N8
N9
N11
N12
T8
T9
T13
T15
T16
T18
AB1
AC2
T6
N13
AR-LP Power & GND
AR-LP PCIE

B B

Alpine Ridge LP - PCIe


Symbol
To CPU PCIe RX From CPU PCIe TX
U4B
CT14 1 2 0.22U_0201_6.3V6M PCIE8_L0_RXP_C V23 Y23 PCIE8_L0_TXP_C CT147 1 2 0.22U_0201_6.3V6M
[11] PCIE8_L0_RXP PCIE_TX0_P PCIE_RX0_P PCIE8_L0_TXP [11]
CT16 1 2 0.22U_0201_6.3V6M PCIE8_L0_RXN_C V22 Y22 PCIE8_L0_TXN_C CT148 1 2 0.22U_0201_6.3V6M
[11] PCIE8_L0_RXN PCIE_TX0_N PCIE_RX0_N PCIE8_L0_TXN [11]
CT12 1 2 0.22U_0201_6.3V6M PCIE8_L1_RXP_C P23 T23 PCIE8_L1_TXP_C CT149 1 2 0.22U_0201_6.3V6M
[11]
[11]
PCIE8_L1_RXP
PCIE8_L1_RXN
CT2 1 2 0.22U_0201_6.3V6M PCIE8_L1_RXN_C P22 PCIE_TX1_P
PCIE_TX1_N PCIe PCIE_RX1_P
PCIE_RX1_N
T22 PCIE8_L1_TXN_C CT150 1 2 0.22U_0201_6.3V6M
PCIE8_L1_TXP
PCIE8_L1_TXN
[11]
[11]
K23 M23
K22 NC_K23 NC_M23 M22 VCC3_TBT
NC_K22 NC_M22
F23 H23
F22 NC_F23 NC_H23 H22 RT9352 1 2 10K_0201_5%
-PLTRST_FAR: PU shuold be on the Host side NC_F22 NC_H22
From PCH -PLTRST_FAR L4 AC5 To PCH
[14,30,32,33,45,46,52,53] -PLTRST_FAR PERST_N PCIE_CLKREQ_N -CLKREQ_PCIE8 [13]
PCIE8_CLK_100M V19 N16 AN_PCIE_RBIAS
[13] PCIE8_CLK_100M REFCLK_100_IN_P PCIE_RBIAS
2

-PCIE8_CLK_100M T19 RT140 DG_CLKREQ#:


[13] -PCIE8_CLK_100M REFCLK_100_IN_N * If NOT usingt DG_CLKREQ# to PCH,
3.01K_0201_1%
Add 100K PU to 3v3_Sx.
JHL6240-QSXA-A1_BGA337 * If DG_CLKREQ# is connected to PCH use buffer
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AR : POWER/ GND
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 49 of 73
5 4 3 2 1
5 4 3 2 1

TYPE-C_VBUS TYPE-C_VBUS

ESD for USB2 Lines and Control


JUSBC1
lines
D232
A1 B12 ESD@
GND GND D241
[47] USB3_A_TTX_C_DRX_P0 A2 B11 USB3_A_TRX_DTX_P0 [47] TBT_USB2P_L 1 10 TBT_USB2P_L USB3_A_TTX_C_DRX_P0 1 2
A3 SSTXP1 SSRXP1 B10
[47] USB3_A_TTX_C_DRX_N0 SSTXN1 SSRXN1 USB3_A_TRX_DTX_N0 [47]
TBT_USB2N_L 2 9 TBT_USB2N_L
CT94 1 2 0.47U_0402_25V6K A4 B9 CT96 1 2 0.47U_0402_25V6K
VBUS VBUS 4 7 PESD5V0H1BSF_SOD962-2-2
D233
D TBT_CC1_CONN A5 B8 TBT_SBU2_CONN ESD@ D
CC1 RFU2 5 6
TBT_USB2P_L A6 B7 TBT_USB2N_L USB3_A_TTX_C_DRX_N0 1 2
TBT_USB2N_L A7 DP1 DN2 B6 TBT_USB2P_L 3
DN1 DP2
TBT_SBU1_CONN A8 B5 TBT_CC2_CONN 8

Bottom
RFU1 CC2 PESD5V0H1BSF_SOD962-2-2
D234

TOP
CT95 1 2 0.47U_0402_25V6K A9 B4 CT97 1 2 0.47U_0402_25V6K PUSB3F96_XSON10_2.5X1~D ESD@
VBUS VBUS ESD@
[47] USB3_A_TRX_DTX_N1 A10 B3 USB3_A_TTX_C_DRX_N1 [47] USB3_A_TRX_DTX_P0 1 2
A11 SSRXN2 SSTXN2 B2
[47] USB3_A_TRX_DTX_P1 SSRXP2 SSTXP2 USB3_A_TTX_C_DRX_P1 [47]
A12 B1
GND GND PESD5V0H1BSF_SOD962-2-2
D235
ESD@
1 2 ESD Diode structure should be located
3 GND GND 4 USB3_A_TRX_DTX_N0 1 2
5 GND GND 6 as close as possible to connector
7 GND GND 8
GND GND
DRAPH_UB11249-1600W-1H PESD5V0H1BSF_SOD962-2-2
TYPE-C_VBUS D236
ME@ ESD@

USB3_A_TRX_DTX_P1 1 2

PESD5V0H1BSF_SOD962-2-2

2
D238
D245 ESD@
C PESD24VS2UT_SOT23-3 C
ESD@ USB3_A_TRX_DTX_N1 1 2

1
VCC3M_PD
PESD5V0H1BSF_SOD962-2-2
D239
UT9 ESD@
13 20 TBT_A_AUX_N_C
VCC A1_OUTp 19 TBT_A_AUX_P_C USB3_A_TTX_C_DRX_P1 1 2
TBT_SBU1 1 A1_OUTn
TBT_SBU2 2 A_INp 18 TBT_A_AUX_P_C
A_INn A0_OUTp TBT_A_AUX_P_C [47]
@ 17 TBT_A_AUX_N_C
TBT_A_AUX_N_C [47]

Vinafix.com
RT9366 1 2 0_0201_5% 14 A0_OUTn PESD5V0H1BSF_SOD962-2-2
SAI D240
16 15 TBTA_POL ESD@
[51] TBTA_DP_MODE EN_A SAO TBTA_POL [51]
USB3_A_TTX_C_DRX_N1 1 2
3 6 TBT_LSRX LT3 EMI@
4 B_INp B1_OUTp 7 TBT_LSTX TBT_USB2P 2 3 TBT_USB2P_L
B_INn B1_OUTn [47,51] TBT_USB2P 2 3
12 8 TBT_LSTX PESD5V0H1BSF_SOD962-2-2
10 SBI B0_OUTp 9 TBT_LSRX TBT_LSTX [47] TBT_USB2N 1 4 TBT_USB2N_L
[51] TBTA_TBT_MODE EN_B B0_OUTn TBT_LSRX [47] [47,51] TBT_USB2N 1 4
5 11 MCF12102G900-T_4P
GND SBO
2

21
RT9365 @ Thermal pad
0_0201_5% TS3DS10224RUKR_WQFN20_3X3
UT5
1

7
B RPD_G1 B
TS3DS10224 Function Table 6
RPD_G2

[51] TBT_CC1 TBT_CC1 12 4 TBT_CC1_CONN


CC1 C_CC1
[51] TBT_CC2 TBT_CC2 11 TPD8S300 5 TBT_CC2_CONN
CC2 C_CC2
TBT_SBU1 15 1 TBT_SBU1_CONN
SBU1 C_SBU1
TBT_SBU2 14 2 TBT_SBU2_CONN
SBU2 C_SBU2

20
D1
19
VCC3_LDO_TBT 0.1U_0402_50V7K 2 1 CT154 3 D2
VBIAS 17
10 D3
VPWR 16
D4
RT134
2 1 9 18
FLT GND1 8
1 GND2 13
CT153 10K_0201_5% GND3 21
PAD
0.1U_0201_6.3V6K
2
A A
<BOM Structure>
TPD8S300_QFN20_3X3

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TYPE-C CONNECTOR/PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A3 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 50 of 73
5 4 3 2 1
5 4 3 2 1

VCC3_LDO VCC3_LDO_TBT

D R9592 D
2 1

0_0402_5% 2
VCC3M VCC3M_PD @
@ 10U_0402_6.3V6M
1 @ 2 CT273
RT9369 0_0402_5% Q209 1

1
NTR4101PT1G
RT9368 Remove RT56 for layout routing dat.05/06
0_0402_5% 1 3

S
D
@ VCC3_TBT VCC5M VCC5M_PD
J9237

G
2
2 1 @
2 1
VCC5M_PD 120mil 3A 120mil 3A
JUMP_43X79
1
@
CT88
0.1U_0201_6.3V6K
2
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

2 2
CT225

CT226

VINT20_IN VCC5M_PD

1 1
120mil 3.25A 120mil 3A
TYPE-C_VBUS_F
2 2
CT267 TBT_CC1
place near 16,37 pin CT266 22U_0603_6.3V6M
22U_0805_25V6M
1 1 120mil 3A 1
CT265
220P_0201_25V7K
2

2
C C
VCC3M CT260 CT222
1U_0603_25V6K 0.1U_0402_25V6 2

1
220P_0201_25V7K
CT264
VCC3M_PD U155
1
7 8 Close to UT4 TBT_CC2
PP_HV1 VBUS1
2

1
3.3K_0201_5%

3.3K_0201_5%

@ @
J9241 J9242
RT9370
@ @ 10K_0201_5% 1 2 1 2 1 2
VCC3M_PD PP_HV2 VBUS2 1V8_LDO_TBT VCC3_LDO
1

PAD-OPEN 4x4m PAD-OPEN 4x4m VCC3_LDO_TBT


R9589

R9588

1 5
3 LDO_3V3 26
CT263 VIN_3V3 LDO_1V8
2
10U_0402_6.3V6M 2 10U_0402_6.3V6M

1
2 <BOM Structure>

Vinafix.com
15 TBT_CC1 TBT_CC1 [50] 10U_0402_6.3V6M CT158
C1_CC1 17 TBT_CC2 CT262 RT7060 RT7062
C1_CC2 TBT_CC2 [50] 1
[8,41,53] EC_SMB_CK2 EC_SMB_CK2 18 10K_0201_1% 10K_0201_1%
EC_SMB_DA2 19 I2C1_SCL 36 1
[8,41,53] EC_SMB_DA2 I2C1_SDA C2_CC1
[53] TBT_I2C_IRQ TBT_I2C_IRQ 20 38

2
VCC3M_PD I2C1_IRQ C2_CC2
1

[48] TBTA_I2C_SCL 23 ADCIN1


RT9371 24 I2C2_SCL 4 ADCIN1 ADCIN2
[48] TBTA_I2C_SDA I2C2_SDA ADCIN1 VCC5M_PD
10K_0201_5% [48] TBTA_I2C_INT 25 6 ADCIN2
100K_0201_5% 1 @ 2 RT760 HRESET @ I2C2_IRQ ADCIN2

1
16
2

0_0201_5% 2 @ 1 RT761 PP1_CABLE 37 RT7059 RT7061


PP2_CABLE 1
[48] TBT_EE_DO TBT_EE_DO 27 100K_0201_1% 100K_0201_1%
@ TBT_EE_DI 28 SPI_MISO(GPIO8) 41 TBT_USB2P CT156
[48] TBT_EE_DI SPI_MOSI(GPIO9) C1_USB_P(GPIO18) TBT_USB2P [47,50]
0.01U_0201_6.3V7K 2 1 CT231 [48] TBT_EE_CLK TBT_EE_CLK 29 42 TBT_USB2N TBT_USB2N [47,50] 4.7U_0603_10V6K

2
-TBT_EE_CS 30 SPI_CLK(GPIO10) C1_USB_N(GPIO19) 2
[48] -TBT_EE_CS SPI_SS(GPIO11) 43
C2_USB_P(GPIO20) 44
C2_USB_N(GPIO21)

9 -TBT_RESET
HRESET 35 GPIO0 10 PD_GPIO1 -TBT_RESET [48]
B HRESET GPIO1 11 TP932 @ PD_GPIO1 1M_0201_1% 1 2 RT9367 B
GPIO2 21
HPD1(GPIO3) TBT_HPD [47]
22 TP933 @
45 HPD2(GPIO4) 12 TBTA_DP_MODE TBTA_PPEXT_EN 100K_0201_5% 2 1 RT820
NC GPIO5 TBTA_DP_MODE [50]
46 13 TBTA_POL
NC GPIO6 TBTA_POL [50]
14 TBTA_TBT_MODE
GPIO7 TBTA_TBT_MODE [50]
47 31 SNK_PS_ACK [60]
G-Pad GPIO12 32 TP934 @
GPIO13 SI: Swap TBTA_PPEXT_EN & TBTB_PPEXT_EN
33 TP935 @
A1 GPIO14(PWM) 34 TP936 @
A2 NC1 GPIO15(PWM) 39 TBTA_PPEXT_EN
A3 NC2 GPIO16(PP_EXT1) 40 TP937 @ TBTA_PPEXT_EN [60]
A4 NC3 GPIO17(PP_EXT2)
NC4

PTPS65988CERJTR_QFN48_6X6
SA0000ABQ60

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2015/01/06 Deciphered Date 2016/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PD TPS65988
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 51 of 73
5 4 3 2 1
5 4 3 2 1

D D

VCC3GBE

VCC3B VCC3GBE
TABLE Change from solder
JLAN1 ME@
vPro Capability
short to short pattern
with copper from SVT.

2
@
R29 R166 1
GbE
10K_0201_5% 10K_0201_5% VCC

PHY Yes No
VCC3LAN @ VCC3GBE RJ45_LINKUP R9411 1 2 330_0402_5% 2
Green LED

1
0_0603_5% MDI_0+_CONN 3
U13 Jacksonville-LM Jacksonville-V R2028 1 2 PR1+
MDI_0-_CONN 4
PR1-

22U_0603_6.3V6M

0.1U_0201_6.3V6K
2 2 MDI_1+_CONN 5
PR2+
-CLKREQ_PCIE3 C262 C278 MDI_1-_CONN 6
LOGIC
[13] -CLKREQ_PCIE3 PR2-
1 1 MDI_2+_CONN 7
PR3+
MDI_2-_CONN 8
PR3-
MDI_3+_CONN 9 13
U13 VPRO@ PR4+ GND
MDI_3-_CONN 10 14
48 13 MDI_0+ PR4- GND
-PLTRST_FAR 36 CLK_REQ_N MDI_PLUS0 14 MDI_0- RJ45_ACTIVITY R9412 1 2 330_0402_5% 11 15
C C
[14,30,32,33,45,46,49,53] -PLTRST_FAR PE_RST_N MDI_MINUS0 Yellow LED GND
PCIE3_CLK_100M 44 17 MDI_1+ 12 16
[13] PCIE3_CLK_100M PE_CLKP MDI_PLUS1 GND GND
-PCIE3_CLK_100M 45 18 MDI_1-
[13] -PCIE3_CLK_100M PE_CLKN MDI_MINUS1 VCC3LAN

PCIE
MDI
PCIE3_RXP C49 1 2 0.1U_0201_6.3V6K PCIE3_RXP_C 38 20 MDI_2+
[11] PCIE3_RXP PETp MDI_PLUS2
PCIE3_RXN C209 1 2 0.1U_0201_6.3V6K PCIE3_RXN_C 39 21 MDI_2- BELLW_80070-9022
[11] PCIE3_RXN PETn MDI_MINUS2

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K
PCIE3_TXP C2466 1 2 0.1U_0201_6.3V6K PCIE3_TXP_C 41 23 MDI_3+
[11] PCIE3_TXP PERp MDI_PLUS3 VCC3GBE
PCIE3_TXN C2467 1 2 0.1U_0201_6.3V6K PCIE3_TXN_C 42 24 MDI_3-
SMBUS DEVICE ADDRESSES 0XC8
[11] PCIE3_TXN PERn MDI_MINUS3 2 2
C267 C286
R73 1 2 100_0201_5% 28 6 R1857 1 @ 2 0_0201_5%
[8] SMB0_CLK SMB_CLK SVR_EN_N 1 1

SMBUS
R75 1 2 100_0201_5% 31
[8] SMB0_DATA SMB_DATA 1 R178 1 2 4.7K_0201_5%
RSVD1_VCC3P3
-LANWAKE 2 5
[14] -LANWAKE LANWAKE_N VDD3P3_IN
LANPHYPC 3
[14] LANPHYPC LAN_DISABLE_N

Vinafix.com
4
VDD3P3_4 C212 1 2 1U_0402_6.3V6K
15
RJ45_LINKUP 26 VDD3P3_15 19
[53] RJ45_LINKUP LED0 VDD3P3_19
RJ45_ACTIVITY 27 29
25 LED1 VDD3P3_29

LED
VCC3GBE LED2
47 D244 D287
VDD0P9_47 46 MDI_0-_CONN 1 6 MDI_2-_CONN MDI_1-_CONN 1 6 MDI_3-_CONN
KEEP SHORT AND WIDE
TP902 @ LAN_JTAG_TDI 32 VDD0P9_46 37 V I/O V I/O V I/O V I/O

PATTERN
TP903 @ LAN_JTAG_TDO 34 JTAG_TDI VDD0P9_37 2 5 2 5
R171 1 @ 2 10K_0201_5% 33 JTAG_TDO 43 Ground V BUS Ground V BUS
JTAG

R167 1 @ 2 10K_0201_5% 35 JTAG_TMS VDD0P9_43 MDI_0+_CONN 3 4 MDI_2+_CONN MDI_1+_CONN 3 4 MDI_3+_CONN


JTAG_TCK 11 V I/O V I/O V I/O V I/O
VDD0P9_11 PUSB2X4D_SO6-6 PUSB2X4D_SO6-6
R325 1 2 470_0201_5% 9 40 ESD@ ESD@
10 XTAL_OUT VDD0P9_40 22
XTAL_IN VDD0P9_22 16
25MHz 10pF 30ppm 2016
VDD0P9_16 8
TXC 8Y25000010
30 VDD0P9_8 FLJ14 EMI@
TEST_EN FL40 MDI_0+ 2 3 MDI_0+_CONN
Y2 12 7 1 2 2 3
B Crystal RBIAS CTRL0P9 4.7UH_NRS2012T4R7MGJ_20% B

22U_0603_6.3V6M

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K
4 3 49 MDI_0- 1 4 MDI_0-_CONN
GND OUT VSS_EPAD 1 4
2 2 2 2 2
2

1 2 WGI219LM-QREF-A0_QFN48_6X6 @ MCF12102G900-T_4P
C107 IN GND C48 R172 R176 C231 C255 C1064
12P_0201_50V8J 12P_0201_50V8J 1K_0201_5% 3.01K_0201_1%
1 25MHZ_10PF_8Y25000010 1 1 1 1 FLJ15 EMI@
MDI_1+ 2 3 MDI_1+_CONN
1

2 3

MDI_1- 1 4 MDI_1-_CONN
1 4
MCF12102G900-T_4P

FLJ16 EMI@
MDI_2+ 2 3 MDI_2+_CONN
2 3

MDI_2- 1 4 MDI_2-_CONN
1 4
MCF12102G900-T_4P

FLJ17 EMI@
MDI_3+ 2 3 MDI_3+_CONN
2 3

MDI_3- 1 4 MDI_3-_CONN
1 4
MCF12102G900-T_4P

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GBE JACKSONVILLE
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 52 of 73
5 4 3 2 1
1 2 3 4 5

EC KB9022 Vcc
R370
3.3V +/- 5%
100K +/- 1%
Board ID R372 VAD_BID min V AD_BID typ VAD_BID max EC AD
VCC3SW VCC3_EC +EC_AVCC
@ @ 0K +/- 5%
KB9022 A v.02 SDV 0.000V 0.300V 0x00 - 0x0B
0_0603_5% R369 12K +/- 1%
R368 1 2 1 2
FVT 0.347V 0.354V 0.360V 0x0C - 0x1C
GPIO W/O internal-PH: SIT 15K +/- 1% 0.423V 0.430V 0.438V 0x1D - 0x26
0_0603_5% 1 1
@ 20K +/- 1%
1. GPIO44 6. GPIO4B 1 C549 1 C550 1 C551 1 C552 1 C553 1 C556 C554 C555
SVT 0.541V 0.550V 0.559V 0x27 - 0x30

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1000P_0402_50V7K

1000P_0402_50V7K
@ @ 1000P_0402_50V7K 0.1U_0402_16V4Z 27K +/- 1%
A
2. GPIO45 7. GPIO4E 2 2 TBD 0.691V 0.702V 0.713V 0x31 - 0x3B A

3. GPIO46 8. GPIO4F 2 2 2 2 2 2
ECAGND
TBD 33K +/- 1% 0.807V 0.819V 0.831V 0x3C - 0x46
4. GPIO47 9. GPIO50 TBD 43K +/- 1% 0.978V 0.992V 1.006V 0x47 - 0x54
5. GPIO4A 10.GPIO51

111
125
22
33
96

67
9
U54

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC
EC_VDD0

EC_VDD/AVCC
-LED_AC_CON 1 21 -LED_LOGO
[44] -LED_AC_CON GATEA20/GPIO00 GPIO0F -LED_LOGO [26,27]
-KBRC 2 23 EC_SPKR
[8] -KBRC KBRST#/GPIO01 BEEP#/GPIO10 EC_SPKR [40]
IRQSER 3 26 FAN_ON
[8,46] IRQSER SERIRQ GPIO12 FAN_ON [44]
-LPC_FRAME 4 27 -SSD_DTCT VCC3_EC
[8,46] -LPC_FRAME LPC_FRAME# ACOFF/GPIO13 -SSD_DTCT [30]
LPC_AD3 5
[8,46] LPC_AD3 LPC_AD3
LPC_AD2 7 PWM Output
[8,46] LPC_AD2 LPC_AD2

1
LPC_AD1 8 63 M_TEMP_R
[8,46] LPC_AD1 LPC_AD1 BATT_TEMP/AD0/GPIO38
VCC3M LPC_AD0 10 LPC & MISC 64 -PCH_SLP_M R370
[8,46] LPC_AD0 LPC_AD0 AD1/GPIO39 65 ISYS
-PCH_SLP_M [14,58]
100K_0402_1%
SD028000080 - S RES 1/16W 0 +-5% 0402
ADP_I/AD2/GPIO3A ISYS [62] SD028120280 - S RES 1/16W 12K +-5% 0402
R9584 2 1 100K_0201_5% FAN_ID LPCCLK_EC_24M 12 AD Input 66 USB_ON1
[8] LPCCLK_EC_24M CLK_PCI_EC AD3/GPIO3B USB_ON1 [31]
-PLTRST_FAR 13 75 BRDID
[14,30,32,33,45,46,49,52] -PLTRST_FAR SD028150280 - S RES 1/16W 15K +-5% 0402

2
R9180 1 @ 2 10K_0201_5% ISYS TP43@ 37 PCIRST#/GPIO05 AD4/GPIO42 76 BRDID
PAD -EC_SCI 20 EC_RST# IMON/AD5/GPIO43 SD028200280 - S RES 1/16W 20K +-5% 0402
[9] -EC_SCI EC_SCII#/GPIO0E

1
R9514 1 @ 2 100K_0201_5% EXTPWR_D trace length 40mil [55,71] SUS_ON1 38
SUS_ON1 GPIO1D R372
SD034270280 - S RES 1/16W 27K +-1% 0402
R9580 1 @ 2 10K_0201_5% -BATLOW
DAC_BRIG/GPIO3C
68 AOU_SEL1
AOU_SEL1 [31] 20K_0402_5% SD034330280 - S RES 1/16W 33K +-1% 0402
DA Output 70 FAN_ID
EN_DFAN1/GPIO3D FAN_ID [44]
R387 1 2 10K_0201_5% -KBD_BL_DTCT SENSE0 55 71 AOU_SEL2
AOU_SEL2 [31]

2
SENSE1 56 KSI0/GPIO30 IREF/GPIO3E 72 -DCIN_VBUS_EN
KSI1/GPIO31 CHGVADJ/GPIO3F -DCIN_VBUS_EN [59]
SENSE2 57
SENSE3 58 KSI2/GPIO32 83 I2C_CLK_GSENSE_SH
KSI3/GPIO33 EC_MUTE#/GPIO4A I2C_CLK_GSENSE_SH [9]
VCC3_EC SENSE4 59 84 I2C_DATA_GSENSE_SH
B KSI4/GPIO34 USB_EN#/GPIO4B I2C_DATA_GSENSE_SH [9] B
SENSE5 60 85 SMB_CK2_GS
KSI5/GPIO35 CAP_INT#/GPIO4C SMB_CK2_GS [41]
SENSE6 61 PS2 Interface 86 SMB_DA2_GS
KSI6/GPIO36 EAPD/GPIO4D SMB_DA2_GS [41]
SENSE7 62 87 IPDCLK Power Requset
KSI7/GPIO37 TP_CLK/GPIO4E IPDCLK [43] VCC3M
DRV0 39 88 IPDDATA
DRV[0..15] KSO0/GPIO20 TP_DATA/GPIO4F IPDDATA [43]
DRV1 40
[42] DRV[0..15] KSO1/GPIO21
R9583 1 @ 2 10K_0201_5% -SPK_MUTE DRV2 41
SENSE[0..7] DRV3 42 KSO2/GPIO22 97 VGA_BLON
[42] SENSE[0..7] KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 VGA_BLON [4]

1
R1802 1 2 20K_0201_5% -HOTKEY DRV4 43 98 -TABLET_MODE @
KSO4/GPIO24 WOL_EN/GPXIOA01 -TABLET_MODE [9,43]
DRV5 44 99 ME_FLASH D17
R375 1 @ 2 10K_0201_5% TH_DTCT DRV6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 TH_DTCT
ME_FLASH [10]
KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 TH_DTCT [61] RB520CM-30T2R VMN2
DRV7 46 SPI Device Interface
R376 1 2 100K_0201_5% -SSD_DTCT DRV8 47 KSO7/GPIO27

2
DRV9 48 KSO8/GPIO28 119 -KBD_BL_DTCT ADP_ID_R R400 2 1
KSO9/GPIO29 SPIDI/GPIO5B -KBD_BL_DTCT [42] ADP_ID [59]
R377 1 2 100K_0201_5% -LID_CLOSE DRV10 49 120 VR_ON
KSO10/GPIO2A SPIDO/GPIO5C VR_ON [64]
DRV11 50 126 BYPASS_PAD 10K_0201_5%

Vinafix.com
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 BYPASS_PAD [43]
R2390 2 1 100K_0201_5% -TABLET_MODE DRV12 51 128 -LED_MUTE
KSO12/GPIO2C SPICS#/GPIO5A -LED_MUTE [42]
DRV13 52
R2406 2 1 100K_0201_5% -TOUCH_DISABLE DRV14 53 KSO13/GPIO2D
DRV15 54 KSO14/GPIO2E 73
TBT_I2C_IRQ 81 KSO15/GPIO2F ENBKL/AD6/GPIO40 74 ADP_ID_R
[51] TBT_I2C_IRQ KSO16/GPIO48 PECI_KB930/AD7/GPIO41
-SPK_MUTE 82 89 -HOTKEY
[35] -SPK_MUTE KSO17/GPIO49 FSTCHG/GPIO50 -HOTKEY [42]
90 GSENSE_INT
BATT_CHG_LED#/GPIO52 GSENSE_INT [41]
91 -AOU_IFLG
CAPS_LED#/GPIO53 -AOU_IFLG [31]
Battery/ Charge EC_SMB_CK1 77 GPIO 92 -LED_CAPSLOCK
[61,62] EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 -LED_CAPSLOCK [42]
EC_SMB_DA1 78 93 -DCIN_PWR_DTCT
[61,62] EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 -DCIN_PWR_DTCT [59,60,62]
Thermal sensor/ EC_SMB_CK2 79 SM Bus 95 A_ON
[8,41,51] EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 A_ON [54,69,70]
PD/ PCH EC_SMB_DA2 80 121 BPWRG
[8,41,51] EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 BPWRG [14]
127 -PCH_SLP_S4
PM_SLP_S4#/GPIO59 -PCH_SLP_S4 [14]

VCC3B VCC3_EC
[14,48] -PCH_SLP_S3
-PCH_SLP_S3 6
PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03
100 -RSMRST
-RSMRST [14,20]
*If pin64 used for AD1,
-PCH_SLP_S5 14 101 -EC_WAKE
[14] -PCH_SLP_S5
[31] AOU_EN
AOU_EN 15 PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
102 VGATE
-EC_WAKE [9]
VGATE [64]
pin102 can not used for GPIO.
RP16 -LED_MICMUTE 16 103 -H_PROCHOT_EC
[42] -LED_MICMUTE GPIO0A H_PROCHOT#_EC/GPXIOA06 -H_PROCHOT_EC [62]
C 5 4 EC_SMB_CK1 TP4_RESET 17 104 MOS_OTP C
[42,43] TP4_RESET GPIO0B VCOUT0_PH/GPXIOA07 MOS_OTP [61]
6 3 EC_SMB_DA1 VCCST_PG_EC 18 GPO BKOFF#/GPXIOA08 105 BACKLIGHT_ON
[14] VCCST_PG_EC GPIO0C BACKLIGHT_ON [26]
7 2 EC_SMB_CK2 -WLAN_RF_KILL 19 GPIO 106 -PWRSW_EC
8 1 EC_SMB_DA2
[32] -WLAN_RF_KILL
KBD_BL_PWM 25 GPIO0D PBTN_OUT#/GPXIOA09 107 -TOUCH_DISABLE
-PWRSW_EC [14] Follow ST2
[42] KBD_BL_PWM EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 -TOUCH_DISABLE [26]
FAN_FRQ 28 108 -PAD_RESET
[44] FAN_FRQ FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 -PAD_RESET [43]
2.2K_0804_8P4R_5% -BATLOW 29 M_TEMP_R R9507 1 2 1K_0201_5%
[14,48] -BATLOW EC_PME#/GPIO15 M_TEMP [61]
EC_TX_P80_DATA 30
[32] EC_TX_P80_DATA EC_TX/GPIO16
R9467 1 2 10K_0201_5% -KBRC EC_RX_P80_CLK 31 110 EXTPWR_D 2 1 D811
[32] EC_RX_P80_CLK EC_RX/GPIO17 AC_IN/GPXIOD01 EXTPWR [62]
PCH_PWROK 32 112 EN_3V
[14] PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EN_3V [63,68]
R381 1 @ 2 10K_0201_5% FAN_FRQ -LED_PWR 34 114 -PWRSW RB521CM-30T2R_SOD923-2
[43] -LED_PWR SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 -PWRSW [43]
LED_AC_CHG 36 GPI 115 -LID_CLOSE
[44] LED_AC_CHG NUM_LED#/GPIO1A LID_SW#/GPXIOD04 -LID_CLOSE [9,26,43]
116 B_ON @
SUSP#/GPXIOD05 B_ON [46,56,57]
117 -LED_FNLOCK M_TEMP C558 1 2 100P_0201_25V8J
GPXIOD06 -LED_FNLOCK [42]
118 EC_PECI 1 2 @
PECI_KB9012/GPXIOD07 PECI [7]
AGND/AGND
RJ45_LINKUP 122 R925 43_0201_5% -DCIN_PWR_DTCT C559 1 2 100P_0201_25V8J
[52] RJ45_LINKUP XCLKI/GPIO5D
R9590 1 2 100K_0201_5% -PLTRST_FAR AC_PRESENT 123 124 +V18R R388 1 @ 2 0_0402_5%
GND/GND
GND/GND
GND/GND
GND/GND

[14] AC_PRESENT XCLKO/GPIO5E V18R VCC3_EC


GND0

R9579 1 2 100K_0201_5% BYPASS_PAD For 9022 +V18R, +EC_VCCLPC can be


R9572 1 2 10K_0201_5% USB_ON1 changed to 1.8V if supports 1.8V I/F.
KB9022QA_LQFP128_14X14
11
24
35
94
113

69

R9571 1 2 10K_0201_5% AOU_EN

R9395 1 2 100K_0201_5% -DCIN_VBUS_EN PROCHOT


R390 1 2 10K_0201_5% PCH_PWROK

R391 1 2 100K_0201_5% KBD_BL_PWM


EC SM Bus1 address @
1
L16
2 ECAGND
[64] -VR_HOT
R389 1 @ 2 0_0201_5%
-PROCHOT [7]

Device Address 0_0603_5%

Battery 0X0b -H_PROCHOT_EC R392 1 @ 2 0_0201_5%

Charger 0X12
D D
1

-PWR_RESET
EC SM Bus2 address
-PWR_RESET [63]
Device Address
Thermal Sensor Fintek F75303M 0x9A Security Classification Compal Secret Data Compal Electronics, Inc.
2

Intelligent Cooling G-Sensor 0x1E Issued Date 2015/03/06 Deciphered Date 2016/12/31 Title
Kionix KX023-1025
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE-KB9022
S1 Intel TBT 0x38 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
SKRPABE010_4P DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
Intel KBL-RU PCH 0x4B MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 53 of 73
1 2 3 4 5
5 4 3 2 1

D D

VCC5M

VCCST
2
VCC1R0_SUS C2411
0.1U_0201_6.3V6K
1

1
U143
C C

VDD
3 4
D S

R9577 1 @ 2 0_0201_5% 2 5
[53,69,70] A_ON ON CAP

GND
2 2
C8787 6 SLG5NT1533VTR_STDFN8-6 2
0.1U_0201_6.3V6K @ C2410
10U_0402_6.3V6M C2412
1 1
220P_0201_25V7K
1

Vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LOAD SW VCCST
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 54 of 73
5 4 3 2 1
5 4 3 2 1

D D

C C

0.3A
VCC3M VCC3_SUS

Vinafix.com
R9495 1 @ 2 0_0805_5%

U154

1 7 R9497 1 @ 2 0_0805_5%
2 VIN VOUT 8
VIN VOUT @
R9496 1 @ 2 0_0201_5% 3 6 C8664 2 1
[53,71] SUS_ON1 ON CT 1U_0402_6.3V6K
VCC5M

0.01U_0402_16V7K
4
VBIAS 5
1 GND

0.1U_0201_10V6K
@ 9
C8666 GND
1
@
2 C8665 TPS22967DSGR_SON8_2X2
@
2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LOAD SW PCH SUS/TRACK POIN
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 55 of 73
5 4 3 2 1
5 4 3 2 1

D D

VCC5B_LOAD VCC5B

Change to TPS22976 (SA0000AAF00) J6 @


1 2
160mil
1 2
C C
JUMP_43X79 1 C560 1 C561

10U_0805_10V4Z

10U_0603_6.3V6M
@

VCC3M VCC5M
2 2

U55
1 14
R393 2 VIN1 VOUT1 13
200K_0402_5% VIN1 VOUT1
W=10mils
1 2 5B_GATE 3 12 C563 1 @ 2 1U_0402_6.3V6K
[46,53,57] B_ON ON1 CT1
R9504 4 11
470K_0402_1% VBIAS GND
1 2 3B_GATE 5 10 C565 1 2 1000P_0402_50V7K
ON2 CT2
6 9
VIN2 VOUT2

Vinafix.com
C567 C568 7 8
VIN2 VOUT2

1
0.01U_0402_16V7K

0.01U_0402_16V7K
GPAD
15 0828 revision VCC3B timing

2
TPS22976DPUR_SON14_2X3

VCC3B_LOAD VCC3B

J8 @ 160mil
1 2
VCC3M VCC5M 1 2
JUMP_43X79 1 C570 1 C571 2 C8794 2 C8795 2 C8796 2 C8797

100p_0603_50V6J
@EMI@

10U_0603_6.3V6M

68P_0201_25V8

2200P_0201_50V7K

68P_0201_25V8

2200P_0201_50V7K
@RF@

@RF@

@RF@

@RF@
2 2 1 1 1 1
1 C572 1 C573 2 C8792 2 C8793 1 C574 1 C575
10U_0603_6.3V6M

100P_0603_50V6J

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M
@
@

@RF@

@RF@

@
2 2 1 1 2 2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LOAD SW B
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 56 of 73
5 4 3 2 1
5 4 3 2 1

Imax : 3.6 A

VCC1R0_SUS_P VCC1R0_SUS

D D

Imax : 2.57 A

VCC1R0_SUS_P VCCPCHCORE

VCC5M VCC1R0_SUS_P

1U_0402_6.3V6K
1
C 2 C

C8584
C8586
2 VCCSTG
0.1U_0201_10V6K
1
@ C8786
R9575 1 @ 2 0_0402_5% 2 1

0.1U_0201_10V6K
@

U7
2.73A
1 VCCCPUIO
2 VIN1
VIN2 C8585
7 6 R9574 1 @ 2 0_0805_5% 2 1
VIN thermal VOUT

Vinafix.com
3 @
VBIAS 0.1U_0201_10V6K
4 5
ON GND

TPS22961DNYR_WSON8
R9573
2 1
[46,53,56] B_ON

0_0201_5%

2
C8791
0.1U_0201_10V6K
1
@

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LOAD SW VCCCPUIO
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 57 of 73
5 4 3 2 1
5 4 3 2 1

D D

2.7A

VCC3M VCC3WLAN VCC3B

@ @
R320 1 2 0_0805_5% R459 1 2 0_0805_5%

[14,53] -PCH_SLP_M R9484 1 @ 2 0_0201_5% U19

1 7 R9485 1 @ 2 0_0805_5%
2 VIN VOUT 8
VIN VOUT @
R9483 1 @ 2 0_0201_5% 3 6 C8660 2 1
[14] -PCH_SLP_WLAN ON CT 1U_0402_6.3V6K
VCC5M

0.01U_0402_16V7K
4
VBIAS 5
1 GND

0.1U_0201_10V6K
9
C330 GND
1
2 C331 TPS22967DSGR_SON8_2X2
@
2

C C

Vinafix.com
0.5A
VCC3M VCC3LAN

@
R9490 1 2 0_0805_5%
B B

U153

1 7
2 VIN VOUT 8
VIN VOUT @
R9492 1 @ 2 0_0201_5% 3 6 C8661 2 1
[14] -PCH_SLP_LAN ON CT 1U_0402_6.3V6K
VCC5M
0.01U_0402_16V7K

4
VBIAS 5
1 GND
0.1U_0201_10V6K

9
C8662 GND
1
2 C8663 TPS22967DSGR_SON8_2X2
@
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LOAD SW WWAN & WLAN
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 58 of 73
5 4 3 2 1
5 4 3 2 1

D D

PR258: 750_1% for New AC Adapter

PR258
750_0201_1%
2 1
VCC3M ADP_ID

VINT20_IN
DCIN_PWR20_F
@
PQ9 PQ36
PJDCIN 3.25A max PLACE NEAR CONNECTOR
2 AON7403L_DFN8-5 AON7403L_DFN8-5
POWER 3 PF2 1 CV20 1
DETECT(ID) 4 1 2 5 2 2 5
POWER 1 EMI@ @EMI@ @EMI@ @EMI@ 3 3
GND

1000P_0201_25V7K

1000P_0201_25V7K
0.01U_0402_25V7K

0.01U_0402_25V7K
5 7A_24VDC_429007.WRML
GND 6
GND 2 2

1
PC8681

PC8682

PC8683
PC72
7

4
GND

0.47U_0402_25V6K

0.01U_0402_25V7K
200K_0201_5%
2

100_0201_5%
2
100P_0201_25V8J
DRAPH_PJSS0056-PB21H

2
2

2
1 1

PC1088

2
1

PR78

PC101
PC93
PR77 PR143

1
100_0201_5%

1
C C
2

1
EMI

1
1
EMI 1 2

REGN PC304
Total MLCC capacitance at DCIN connector

2
5600P_0402_25V7K
PR340
is smaller than 1000pF to avoid LC resonance.

2
470K_0201_5%
270_0201_5%

1
PR222

1
PQ61 3 1

2
PR145

1
2 100K_0201_5%
-DCIN_PWR_DTCT 62
DTA014EMT2L_VMT3

470K_0201_5%

1
PQ107

2
Vinafix.com

3
PR9648 LSK3541G1ET2L_VMT3

1
DCIN_PWR20_F

470K_0201_5%
2
PR9600

1
PQ79

1
2

0.01U_0402_25V7K

68K_0201_1%
B B

2
2

3
PC8684
PR9649 LSK3541G1ET2L_VMT3

1
1
PQ78

2
-DCIN_VBUS_EN

LSK3541G1ET2L_VMT3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC-IN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E291P
Date: Monday, October 23, 2017 Sheet 59 of 102

5 4 3 2 1
5 4 3 2 1

D D

TYPE-C_VBUS TYPE-C_VBUS_F VINT20_IN

PF39 @
PU154
2 1 B2 A1
VBUS VINT
FVT_EC011_DCDC C2 B1

4.7U_0603_25V6K
D2 VBUS VINT C1
7A_24VDC_429007.WRML @ VBUS VINT

1
E1 D1

10U_0603_25V6M

10U_0603_25V6M

0.01U_0402_25V7K
VBUS VINT

1U_0603_25V6K
E2

PC10066
VBUS @ @ @
A2 @
SDV_EC001_DCDC

2
ACK

1
2
B3

PC10068

PC10069

PC10070
OVLO

PC10067
C3
GND D3

1
2
A3 GND E3
TBTA_PPEXT_EN VCC3_LDO_TBT
EN GND

(25) NX20P5090UK_WLCSP15
@

1
@ VCC3_LDO_TBT
PR9672 10K_0402_5% PR9675
2 1
@ 100K_0402_1%
1 2
@
PR9677 0_0402_5% NX20P5090_EN#

2
1 2 SNK_PS_ACK

100K_0402_5%
0_0201_5% PR9685

1
C @ SNK_PS_ACK to PD IC GPIO C

PR9673
REGN @ SDV_EC004_DCDC

1
PQ535 D
470K_0201_5%

2
SNK_PS_EN_R 1 @ 2 NX20P5090_EN#_SW2
@
PR9681 PR9682 0_0201_5% G
2

1
6
PR9683 @ S 2N7002KW_SOT323-3

3
@ 0_0201_5%
PQ534A
@ 2 L2N7002DW1T1G_SC88-6
21

2
PQ534B
470K_0201_5%

@
3

L2N7002DW1T1G_SC88-6
PR9684

SDV_EC007_DCDC
1

-DCIN_PWR_DTCT 5
1

Vinafix.com
PR9674
62 100K_0402_5%
4
2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TYPE-C IN
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E291P
Date: Monday, October 23, 2017 Sheet 60 of 102
5 4 3 2 1
5 4 3 2 1

VCC3SW_P

PTC function

540_0402NEW_30%_PRF15BB541NB6RC

540_0402NEW_30%_PRF15BB541NB6RC

540_0402NEW_30%_PRF15BB541NB6RC

540_0402NEW_30%_PRF15BB541NB6RC

540_0402NEW_30%_PRF15BB541NB6RC

540_0402NEW_30%_PRF15BB541NB6RC

540_0402NEW_30%_PRF15BB541NB6RC
2
PR328
TH_DTCT
6.19K_0201_1%
D
MAIN BAT CONN BAT-PWR12 VL D
5A max

1
PR9646
PJBATT WIDE PATTERN PF12
SDV_EC008_DCDC 1 2 TH_DTCT
1 M_BAT_IN 1 2
1 2
2 3 PR273 10A_32V_CC12H10A-TR 140K_0402_1%
3 4 1 2 PR271
4 EC_SMB_CK1
5 1 2
5 EC_SMB_DA1

1
6 100_0201_5%
6

PRT11

PRT13
PRT1

PRT3

PRT5

PRT7

PRT9
7 100_0201_5%

540_0402NEW_30%_PRF15BB541NB6RC

540_0402NEW_30%_PRF15BB541NB6RC

540_0402NEW_30%_PRF15BB541NB6RC

540_0402NEW_30%_PRF15BB541NB6RC

540_0402NEW_30%_PRF15BB541NB6RC

540_0402NEW_30%_PRF15BB541NB6RC
7 8
8 9
9 M_TEMP

2
10
GND 11
GND
FOX_GS73091-10272M-7H
@ @EMI@ EMI@ @EMI@ EMI@

2200P_0201_50V7K
390P_0201_25V7K

2200P_0201_50V7K
390P_0201_25V7K
2 2

2
PC407

PC199

PC203

PC207

1
PRT10

PRT12
PRT2

PRT4

PRT6

PRT8
1

1
1 1

2
EMI
TABLE
VCC3SW_P ID Target
PRT1 VCC5M Switching FET PQ16
PRT2 VCC3M Switching FET PQ18
C C
PRT3 CHARGER SWITCHING FET1 PQ198
PRT4 CHARGER SWITCHING FET2 PQ196

1
PRT5 Charger NVDC MOS PQ525
PR9647 PR9686 PRT6 DDR Power MOS PQ512
100K_0201_1% PRT7 VCCSA MOSFET Drver NCP81382 PU136
100K_0201_1%
PRT8 VCCCPUCORE1 MOSFET Driver NCP81382 PU133
PRT9 VCCCPUCORE2 MOSFET Driver NCP81382 PU153

2
PRT10 VCCCGFXCORE-I MOSFET Driver NCP81382 PU134
MOS_OTP_R PRT11 DCIN_PWR20_F to CV20_FET PQ9
PRT12 TYPE-C_VBUS_F MOS PU154
MOS_OTP PRT13 CPU Die

1
PQ705
SDV_EC006_DCDC
2

Vinafix.com
VCC3SW_P
SDV_EC016_DCDC LSK3541G1ET2L_VMT3

3
RTC Battery VCC3SW_P
2
2

@ PD7
PR237 RB520CM-30T2R_VMN2M2
1.5K_0201_5%
1

RTCVCC
1
2

@
2

PR238
47K_0201_5% PD6
2

RB520CM-30T2R_VMN2M2 @
PC287
1

1U_0402_6.3V6K
1

B PD3 B
2 1

RB520CM-30T2R_VMN2M2
2

PR4
1K_0201_5%

20K_0201_5%
1

1 2
PR620

PJRTC
1
2 1 -RTCRST
2 -RTCRST
3
4 G1
G2
2

CVILU_CI4402M1HRT-NH
@ PC459
1U_0402_6.3V6K
1

20K_0201_5%
1 2 -SRTCRST
-SRTCRST
PR250
2

PC285
1U_0402_6.3V6K
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY INPUT / RTC Battery
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E291P
Date: Monday, October 23, 2017 Sheet 61 of 102
5 4 3 2 1
5 4 3 2 1

VINT20

EMI@ @EMI@ @EMI@ EMI@ @EMI@ EMI@ EMI@ EMI@ EMI@ @EMI@ @EMI@

0.1U_0402_25V6
0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
D D

VINT20_IN

2
2

2
PC10082
PC10074

PC10077

PC10080

PC10081

PC10083

PC10084
PC10075

PC10076

PC10078

PC10079
Max Current = 3.25(A)
Should be placed near ACP, ACN

1
1

1
Keep these two signals as a pair routing
These MLCCs must be placed
DCIN_CURRENT_P_R symmetrically on Top and Bottom. Reserve for RF EMI parts.

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
PR380 2 2 2

PC255

PC291
PC24
0.01_1206_1%

1 1 1
FVT_EC013_DCDC SIT_EC006_DCDC
SIT_EC007_DCDC

4
DCIN_CURRENT_N_R
VINT12
4.99_0201_1%

4.99_0201_1%
1

2
PR264
PR11

PC447
2

1
0.033U_0402_25V7K

0.033U_0402_25V7K

1 2
VINT20
2

1
PC444

PC138

7.5A max These MLCCs must be placed


0.1U_0402_25V6 symmetrically on Top and Bottom.
PL5
1

EMI@ EMI@ EMI@ @EMI@ @EMI@ @EMI@ EMI@ EMI@


PQ198 1 2

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

AON6994 2N DFN5X6D PQ196


0.1U_0402_25V6

0.1U_0402_25V6

0.01U_0402_25V7K

1000P_0201_25V7K

2200P_0201_25V7K

1U_0402_25V6
@EMI@ @EMI@

7
2.2_0805_5% 330P_0201_50V7M

2.2_0805_5% 330P_0201_50V7M
68P_0402_50V8J

10U_0805_25V6K

10U_0805_25V6K
68P_0402_50V8J

68P_0402_50V8J
2.2UH +-20% MPLCG0630L2R2 7.8A AON6994 2N DFN5X6D 2 2 2 2 2 2

S1/D2
@ @EMI@

2
PC8618
PC194

PC221

PC424

PC425

PC426

PC431

PC810
2 2 2 3

S1/D2
2

S2
2

2
PC10019

PC10018

PC10017

PC10014

PC10013

PC2336
PC747
PC10016

PC10015

PC2337
2 4 2 2 3
D1 S2 S2

2
PC440

PC436
5 @EMI@ 4 2

1
S2 PC197 PC195 5 S2 D1 1 1 1 1 1 1
C C
1

1
1 1 1 0.047U_0402_25V7K 0.047U_0402_25V7K S2

1
1 1

G1

G2

G2

G1
Reserve for RF EMI parts. @EMI@ @EMI@

2
EMI

1
PR963

PR959
EMI
@ PQ525

2
@
PR217 PR216 AON7409_DFN8-5
DCIN_PWR20_F 0_0402_5% 0_0402_5% 1
PR728
BAT-PWR12

1
2 Max Current = 3.5(A)
3 5 1 2

1
RB521CM-30T2R_SOD923-2

RB521CM-30T2R_SOD923-2
0.01_1206_1%
2

EMI PU1
PC2499 EMI PC390

4
1U_0603_25V6K 1 2
1

2
@ 30 25
BTST1 BTST2

PD313

PD312

0.1U_0402_25V6
0.1U_0402_25V7K
REGN VDDA

10U_0805_25V6K
Vinafix.com

0.1U_0402_25V6
32 23
SW1 SW2

2
PC806
2

PC10071
10_0402_1%

10_0402_1%

PC2504
29 26
VDDA
1

1
LODRV1 LODRV2

PR2358

PR2359
1
2 1 31 24 2 1
PC10072

1
HIDRV1 HIDRV2 1
@ PR9327 0_0201_5% @ PR2356 0_0201_5%
2

1 2 1 22

1
PR9246 VBUS VSYS
SIT_EC001_DCDC @
1

10_0201_1% 0.47U_0402_25V6 2 21 2 1
PR720 ACN /BATDRV
VINT12 165K_0201_1% 3 20
PR9625 0_0402_5%
PC451
1

ACP SRP
1 2 7 19
2

VDDA SRN
BZT52-B20S_SOD323-2

@
1U_0402_25V6 REGN
VDDA
1

6
ILIM_HIZ 28 2 1
PD316

REGN

2
1 2 2 1 PC16 2.2U_0402_10V6M
PC2338 1800P_0402_50V7K PR9510 40.2K_0201_1% 16 2 1 2 1 PR9514
1

1 2 COMP1 17 PC8622 680P_0201_25V7K


COMP2 PR9513 10K_0201_1% 43.2K_0201_1%
2

PC8620 33P_0201_25V8J 1 2
-H_PROCHOT_EC 64 2 1 11 PC8621 15P_0201_25V8J
B /PROCHOT B

1
PR2207 75_0201_5%
# of CELL VCELL_PRES PR9514
2

2
1 2
PR211 18
@ 100K_0201_1% REGN EC_SMB_CK1 2 1 13 CELL_BATPRES PR9626
2 1
137K_0402_1% 1-CELL 1.2V 402K
SCL

2
PQ42 @ PR9326 0_0201_5% PC8623 100P_0201_50V8J
EC_SMB_DA1 2 1 12 8 ISYS PR2353 2-CELL 2.7V 121K
3

DTC015EMT2L_VMT3
1

SDA IADPT
@ PR9325 0_0201_5% 100K_0201_1%
4 9 3-CELL 3.9V 53.6K
CHRG_OK IBAT 2 1
4-CELL 4.2V 43.2K
100K_0201_1%

1
1 2 5 10 PC8624 100P_0201_50V8J
2

VDDA PR9590 10K_0201_5% ENZ_OTG PSYS


PR9611

@ 15 27
CMPOUT PGND PSYS
64
2

14 33
PR9594 CMPIN PAD
1

10K_0201_5%
1

BQ25700ARSNR_WQFN32_4X4

IDPM V(ILIM) PR720 EXTPWR DCIN_PWR20_F


500mA 1.2V 402K SDV_EC015_DCDC
1.0A 1.6V 280K
100K_0201_1%
2

-DCIN_PWR_DTCT 2
2.0A 1.8V 237K 591
PR9687

@ PR9609 0_0201_5%
3.0A 2.2V 174K 2 PR9607
100K_0201_1%
3.25A 2.3V 162K
1

2
1

PR9608
PC10002 14.3K_0201_1%
A 0.1U_0402_25V7K A
2

SIT_EC002_DCDC
SIT_EC003_DCDC

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2016/01/ Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CHARGER(BQ25700)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E291P
Date: Monday, October 23, 2017 Sheet 62 of 102
5 4 3 2 1
5 4 3 2 1

D
These MLCCs must be placed VINT12 D

symmetrically on Top and Bottom. These MLCCs must be placed


VINT12 symmetrically on Top and Bottom. 9A
SDV_EC008_DCDC (TDC 7A)

2
PJ9224
PAD-OPEN 4x4m
VCC3M
VCC5M VINT12

2
9A Max Current = 4.5(A) Max Current = 3(A) @
(TDC 7A) PJ9223
PAD-OPEN 4x4m Max Current = 9(A)
VL

1
VCC5M Max Current = 9(A)
@

0.01UF_0402_25V7K
EMI@

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
0.01UF_0402_25V7K
2 2 2 2

2
EMI@

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

4.7U_0402_6.3V6M

PC495

PC217

PC232

PC240

PC314
0.1U_0201_6.3V6K
2
PC2456
2 2 2 2

2
PC502

PC145

PC392

PC393

PC340

1
2
1 1 1 1

PC225
1

2
VINT12_5M

VINT12_3M
1
1 1 1 1 PJ2019 PJ2020

1
EMI
2

PAD-OPEN 4x4m PAD-OPEN 4x4m


PJ2016 PJ2017 @ @
PAD-OPEN 4x4m PAD-OPEN 4x4m
EMI
@ @

1
1

0.01UF_0402_25V7K
@

NEC TOKIN MPLCG0630L2R2 2 NEC TOKIN MPLCG0630L2R2

2
PC227
TDK SPM6530T-2R2M TDK SPM6530T-2R2M
@ PR2309

D1

D1
AON6994 2N DFN5X6D
FVT_EC005_DCDC
PL3
SDV_EC012_DCDC G1
1 1 2 1 1
G1
PL4
1 2 7 7 1 2
0_0402_5%
1000P_0201_25V7K

1000P_0201_25V7K
220U_B2_6.3VM_R25M

220U_B2_6.3VM_R25M

220U_B2_6.3VM_R25M

220U_B2_6.3VM_R25M

220U_B2_6.3VM_R25M
2.2UH +-20% MPLCG0630L2R2 7.8A S1/D2 S1/D2 2.2UH +-20% MPLCG0630L2R2 7.8A @EMI@ EMI@
0.01U_0201_6.3V7K

0.01U_0201_6.3V7K
0.1U_0402_25V6

C 1 1 1 EMI@ PQ16 PQ18 1 1 C

470P_0201_25V7K
@EMI@2 @ 6 6 @
2 2
2

@ G2 G2
PC2420

PC2153

+ + +

PC2421

PC1306

PC2457
+ +
PC140

PC511

PC216
2

S2
S2
S2

S2
S2
S2
2

PC1304

@EMI@

2
PR221

2
PC10086

PC768
0_0402_5%
AON6994 2N DFN5X6D

PR2310
0_0201_5% PC769 EMI@

3
4
5

5
4
3

1
1 2 2 2 @ 1 1 2 2
470P_0201_25V7K
1

1
1

1
PR386
1

0_0201_5%

VCC5M_DH
@EMI@
2

1
@

VCC5M_DL
PR912

2
2.2_0603_5%

2
VCC3M_DH

VCC3M_DL

2.2_0603_5%
EMI
2

PR895
EMI @ 2 EMI
1

PC2402 PR1603 EMI@


154K_0201_1%
6TPE220MAPB Panasonic 1000P_0201_25V7K

1
1
TEPSLB20J227M(25)BR NEC-TOKIN EMI
1

2
Vinafix.com
PR1604 2@
133K_0201_1% PC2409
2

@ 2
PC2408 PR525 EMI 1000P_0201_25V7K

1
PU41 1

15

14

13

12

11
100K_0201_1%
1000P_0201_25V7K
1 6TPE220MAPB Panasonic

DRVL1

VO1

VREG5

VIN

DRVL2
1

TEPSLB20J227M(25)BR NEC-TOKIN
16 10
DRVH1 DRVH2
@ PR392 @PR112 PC229 2@
PC2410
GND_51285 1 2 1 2 17 9 2 1 2 1
PC483 VBST1 VBST2 1000P_0201_25V7K
0.1U_0402_25V7K 0_0402_5% 0_0402_5% 0.1U_0402_25V7K 1
18 TPS51285BRUKR_QFN20_3X3 8
SW1 SW2
SDV_EC002_DCDC PR2308
1 2 19 7
VCLK PGOOD

2
200_0201_1% PR402
20 6 EN_3V 200K _0201_1%
B
GND_51285 EN1 EN2 B

VREG3
EN_3V

VFB1

VFB2

1
CS1

CS2
21
TP
Fsw=470kHz

5
FVT_EC006_DCDC PD317
Fsw=400kHz
PR364 locp = 14.8Atyp
(10.0 - 23.7A) GND_51285
PR299
1 2 locp = 15.7Atyp 1 2
MOS_OTP_R 1 2
(10.6 - 25.1A)
10K_0201_1%
RB521CM-30T2R_SOD923-2
SDV_EC017_DCDC 10K_0201_1%
GND_51285
SDV_EC009_DCDC GND_51285
VCC3SW_P

2
PC406
VCC3SW_P PQ100 VCC3SW 4.7U_0402_6.3V6M
1

AO3413_SOT23-3
@ PR191
S

3 1 1 2
0.47U_0402_25V6K
200K_0201_5%

2 0_0402_5%
2

G
PC10073

2
PR9645

GND_51285
SDV_EC010_DCDC 1
@ FVT_EC008_DCDC
1

200K_0201_5%
2

PR9650
VCC3SW_P
1

A A
SIT_EC002_DCDC
2

PR9212
SIT_EC003_DCDC
1

470K_0201_5%PQ533
1

-PWR_RESET 2

LSK3541G1ET2L_VMT3 Security Classification Compal Secret Data Compal Electronics, Inc.


3

PWR_RESET Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

DC/DC VCC5M/VCC3M
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E291P
Date: Monday, October 23, 2017 Sheet 63 of 102
5 4 3 2 1
5 4 3 2 1

U22/U42 co-lay KBL-R U42: PR9657 / PR9658


KBL-U 22: PR9655
VCCCPUCORE VCCGFXCORE_I_VCCCPUCORE
U42@
1 2
1 2
PR9657 SOLDER_PREFORMS_0402
VCCGFXCORE_I
U22@
1 2
1 2
PR9655 SOLDER_PREFORMS_0402
VCCCPUCORE U42@
VCCGFXCORE_X_VCCCPUCORE
D D
1 2 @
PSYS:
1 2
SOLDER_PREFORMS_0402 1
PR235
2 PSYS Please confirm charger pull low resistance.
PR9658 Charger side should be unpop.
FVT_EC004_DCDC 0_0201_5%
62

OCP for VCCSA PC2319 PR2176


SDV_EC005_DCDC 1 2 1 2
1.5K_0201_1%
SDV_EC0014_DCDC PC2315
1000P_0201_25V7K
8200P_0201_25V7K
COMP_1b_CPU1 2
15P_0201_25V8J PC2318
SDV_EC0018_DCDC 1 2
PR9642

1000P_0201_25V8J
10_0201_1%
CSN_1b_VCCSA_R 1 2

19.1K_0402_1%
1

PC2507
2
CSN_1b_VCCSA

1
2200P_0402_50V7K
VCCSA_SENSE VCCSA_SENSE 2 1 VSPP_1b_CPU_R 2 1 VSP_1b_CPU PLACE CLOSE TO <11>
PRT20

PR2177
<> @ PR229 0_0201_5% 2 PR2426 1.69K_0402_1% VCCSA PL32

5600P_0201_10V7K
2

PCI108
6800P_0201_25V6K
RDRPSP

1
PC2317 PR2175 100K_0201_1%_NCP03WF104F05RL

1
1000P_0201_25V7K 1K_0201_1% IoutSA:
VCCST

2 2
1

2
1

PC2411
PC2331
VSSSA_SENSE VSSSA_SENSE 2 1 VSNN_1b_CPU_R 1 2 VSN_1b_CPU CSN_1b_VCCSA_NTC For U22: PR2178=63.4K

2
<> @ PR228 0_0201_5% For U42: PR2178=63.4K
1 2 PR2204

1
2200P_0201_25V7K PC2316 12K_0201_1%
VCC3B

0.1U_0201_6.3V6K
CSP_1b_VCCSA_R
2 1 CSP_1b_VCCSA

1
PR2178

10K_0201_5%
PR2163 20K_0201_5% 1 2
SDV_EC003_DCDC

1
PC10042
63.4K_0402_1% <11>
7.5K_0603_1%

PR2188
VCC_SENSE VCC_SENSE 2 1 VSP_2ph_CPU 1 2 PR2206
<> @ PR232 0_0201_5% 2

2
2 1
VSS_SENSE PC2310
VSS_SENSE PR2169 PC2320 470P_0201_25V7K

1
1000P_0201_25V7K VGATE
<> 1K_0201_1% VGATE
2 1 1 VSN_2ph_CPU_R 1 2 VSN_2ph_CPU
@ PR233 0_0201_5%
1 2 VR_ON VCC5M confirm with power sequence,
3300P_0201_25V7K PC2309 Upper Threshold > 0.8V VCCST it need behind VCC5M.
C Lower Threshold < 0.3V C

1
PR2172 RIOUT@VCORE: @ VCCSTG PRI2160 and PR2159 pull high resistor are pop at the end of VR SVID.

CPUCORE_VR_ON_R
FVT_EC007_DCDC

0_0201_5%
49.9_0201_1% PR9173 @
PR2171
U22 = 26.1K -PR9663 U42@ PR9663
0_0201_5%VR_ON Other VR is unpop.
23.7K_0402_1%

PR2424
U42 = 23.7K -PR9663

110_0402_1%
47_0201_5%
2 1

100_0201_5%
IOUT_1b_CPU
1 2
1K_0201_1%

ILIM_1b_CPU

2
@
IoutGT:

470P_0201_25V7K
67 PR2157

2
PC2314

1
PWM_1B_SA For U22: PR2168=39.2K
470P_0201_25V7K 510_0201_5%
CSCOMP_2ph_CPU_R

Close to VCORE1 choke PLACE CLOSE TO 1 For U42: PR2168=39.2K

PC2311
PWM_1B_SA

2
VCCCPUCORE1 PL29

1
U22@ PR9663 Part Reference = PU137

1
RPH@VCORE:

3.48K_0402_1%
PRT18 VCORE OCP 26.1K_0402_1% NCP81218MNTXG_QFN48_6X6 PC10058 PR2190
U22 = 84.5K PR9660,PR9659(De-pop) U42@ DRVON

1
2

2
7.5K_0603_1%

49

48
47
46
45
44
43
42
41
40
39
38
37
0.1U_0201_10V6

0_0201_5%
U42 = 84.5K PR9660,PR9659 PR9661 @

2
NCP03WL224E05RL

PR2425
65,66,67 @ 1 2 CSP_1a_GT

PR2173
U22 PR9661-9.76K 16.9K_0402_1% 62

1
1
2 1 -VR_HOT 66

TAB

VSN_2ph
VSP_2ph
PSYS
VSP_1b
VSN_1b
COMP_1b
ILIM_1b
CSN_1b
CSP_1b
IOUT_1b
VR_RDY
EN

PR2160

PR2159
1

PC2412 0.01U_0201_25V6
U42 PR9661-16.9K

PRI27
PC2313 PR2191
33P_0201_25V8J 12K_0201_1%

0.015u_0201_16V6K
2

1 2
PC2308

1
Vinafix.com
IOUT_2ph_CPU 1 36 1 2CSN1_VGT_NTC
PR2199 PR2198 IOUT_2ph PWM_1b 470P_0201_25V7K
DIFFOUT_2ph_CPU 2 35

2200P_0201_25V7K
75K_0201_1% DIFFOUT_2ph DRVON

2
CSP_1a_VCORE_R 1 2 2 1 2 1 1 1 PC2312 FB_2ph_CPU 3 34 SVID_CLK_R1PR21612 1 51_0201_5% SVID_CLK 2 1
84.5K_0603_1% U22@ PR9661 9.76K_0402_1% COMP_2ph_CPU 4 FB_2ph SCLK 33 -SVID_ALERT_R1
PR23631 @ 2 0_0201_5% PRT16 PLACE CLOSE TO
<> PR9660 165K_0201_1% 2200P_0201_25V7K -SVID_ALERT 2

PC10057
2
1 2 PC2329 PC2328 1 2 ILIM_2ph_CPU 5 COMP_2ph ALERT# 32 SVID_DATA_R1 1 10_0201_5%
PR21622 PR2168 100K_0201_1%_NCP03WF104F05RL VCCGT PL30

PC2323
CSP_2a_VCORE_R ILIM_2ph SDIO SVID_DATA

1
PR9659 U42@ 84.5K_0603_1% 330P_0201_50V7K 470P_0201_25V7K CSCOMP_2ph_CPU 6 31 VR_HOTL# 1 2
<> CSCOMP_2ph VR_HOT# 39.2K_0402_1%
2 2 CSSUM_2ph_CPU 7 30 PR2189 75_0201_5% IOUT_1a_GT 1 2
PR9639

1
2 1 CSREF_2ph_CPU 8 CSSUM_2ph IOUT_1a 29 CSP_1a_GT_R 1
CSN_2a_VCORE 10_0201_1%

2
CSP2_2ph_CPU 9 CSREF_2ph CSP_1a 28 CSN_1a_GT_R 1 2 CSN_1a_GT
<> PR9637 U42@ 10_0201_1% 1 1
0.022U_0201_16V6K

0.022U_0201_16V6K

2 1 CSP1_2ph_CPU 10 CSP2_2ph CSN_1a 27 ILIM_1a_GT 66

ROSC_COREGT
CSN_1a_VCORE CSP1_2ph ILIM_1a
TSENSE_2ph_CPU_R 1 2 TSENSE_2ph_CPU 11 26 COMP_1a_GT
100K_0201_1%_NCP03WF104F05RL
PC2700

U42@ PC2325

PR2196 10_0201_1%

ADDR_VBOOT
<> TSENSE_2ph COMP_1a 1
1

TSENSE_1ph
RSOC_SAUS

ICCMAX_2ph
PR2192 0_0201_5% 2 1 12 25 1

ICCMAX_1a
ICCMAX_1b
@ VRMP VSN_1a PC2304 2200P_0201_25V7K

PWM1_2ph
PWM2_2ph

2
2 2
PC2327 VINT12 PC2506

VRMP_CPU
PR2186 PC2306
61.9K_0201_1%
2

PWM_1a
2

1 2 VSN_1a_CPU_R PC2307

VSP_1a
1K_0402_5% 150P_0402_50V8J 1000P_0201_25V7K
2

2
PR2203

0.01UF_0402_25V7K
0.1U_0201_10V6 2 0.015U_0201_16V6K

VCC

1
2
For U22: PRT17 PR2165

1
PC2324 @
PR9637=De-pop 1K_0201_1% PR231

2
PC2321
CSP_1a_VCORE_R 1 2 1000P_0201_25V7K VSN_1a_CPU
1 2 1 2 PR2166 PR2167
1

For U42:
1

13
14
1ROSC_SAUS_CPU 15
16
17
ICCMAX_2ph_CPU 18
19
20
21
22
23
24
1
PR2194 7.5K_0402_1% 1 2.15K_0201_1% 39.2K_0201_1%
PR9637,PR9659=Pop CSP_2a_VCORE_R 1 2 0_0201_5%
PC2305 VSSGT_SENSE

ADDR_VBOOT_CPU
PR9638 U42@ 7.5K_0402_1%

ICCMAX_1a_CPU
ICCMAX_1b_CPU
VCC_CPU
1000P_0201_25V7K

2
B PRT17 PLACE CLOSE TO VCC5M PR2187 2
OCP for VGT B
2_0201_5% @
2 1 VCCCPUCORE1 PU133 PR2436 PR230
For U22: VCC5M U22@ PR2195 2 1 1 2VSP_1a_CPU_R 1 2 VCCGT_SENSE SIT_EC008_DCDC
3.32K_0201_1%

1ROSC_COREGT_CPU
PR2194=7.5K, PR9638=De-pop 1K_0201_1% 0_0201_5%

1U_0402_6.3V6K
VSP_1a_CPU1 2 1 2
For U42: For U22: PR2164 1.82K_0201_1%

24K_0201_5%
2
PR2194, PR9638=7.5K PC2322
PC2303
PC2325=De-pop 472mV/120uA=3.933K 1000P_0201_25V7K SDV_EC013_DCDC

PR2181
For U42: Active Point110 degreeC = 4.206K @ PR2202
PC2325=0.022U 0_0201_5%
1
TSENSE_1ph_CPU 2 1 TSENSE_1ph_CPU_R

2
PWM_1a_GT

1000P_0201_25V7K
2
29.4K_0402_1% 65

PC2330

61.9K_0201_1%
2

2
PR2180

PR2193
PRT19
Fsw for SA 1 100K_0201_1%_NCP03WF104F05RL

PR2183 U22@ 51.1K_0201_1%

97.6K_0201_1%

35.7K_0201_1%
PR2184 U22@ 15.8K_0402_1%
Fsw for CORE & GT
PLACE CLOSE TO
2

1
VCCGT PU134
NCP81218 Operating Frequency
I/A and GT are 450KHz and SA is 600KHz 1

1
RIccMAX2ph: 472mV/120uA=3.933K
For U22: Active Point110 degreeC = 4.206K

PR2185
PR2183=51.1K
2

2
PR2182

For U42:
PR2183=100K
VBOOT:
PR2183 U42@
100K_0201_1%
51.1K for debuge setting.

U42@
For U22: PR2184=15.8K PR2184
For U42: PR2184=19.1K 19.1K_0402_1%
RIccMAX1a:
PWM2_2ph_IA2 <34>
For U22 & U42:
PR2182=97.6K PWM1_2ph_IA1
A <34> A

FVT_EC010_DCDC
SIT_EC003_DCDC
SIT_EC010_DCDC

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC IMVP8 CONTROLLER
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E291P
Date: Monday, October 23, 2017 Sheet 64 of 102
5 4 3 2 1
5 4 3 2 1

VCCCPUCORE
SIT_EC005_DCDC
These MLCCs must be placed
symmetrically on Top and Bottom. 1pcs 22uF / 4pcs 10uF
VINT12 Max Current = 3.50(A)
for VCCCPUCORE<U42>

330U_B_2.5VM_R9M

330U_B_2.5VM_R9M
U42@
1 1
PFL41 VCCCPUCORE

10U_0402_6.3V6M

10U_0402_6.3V6M
PC10041
+ +

PC77
1 2 VINT12_CPUCORE EMI@ EMI@ 2 2

PC8571

PC8572
BLM18KG300TN1D_2P

33U_D2_25VM_R60M

33U_D2_25VM_R60M
2 2

1000P_0201_25V7K
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
EMI@ EMI@ 1 1

2
D TABLE for PC77, P10041<U42> U42@ U42@ U42@ U42@ U42@ D
1 1 2 2 2 2 2

2
PC2263

PC2264

PC2265

PC2266

PC2267

PC2326

10U_0402_6.3V6M

10U_0402_6.3V6M
@ PC8483

10U_0402_6.3V6M

10U_0402_6.3V6M
@

22U_0603_6.3V6M
PC8674
+

PC8675
+ 0.1U_0402_25V6 Panasonic, ETPE330MA9GB
VCC5M 2 2 2 2

PC10049

PC10051
2

PC10050

PC10052
NEC TOKIN PSGB20E337M9

PC10043
1
1 1 1 1 1
2 2
PR2133 1 1 1 1

1
1 2

2_0201_5%
EMI EMI
2

PC2261
1U_0402_6.3V6K
1
2

PC2260
2.2U_0402_6.3V6M
PR2135 SIT_EC009_DCDC 2pcs 22uF 3pcs 22uF / 4pcs 1uF
1

TABLE PL29
PU133
2 1
for VCCGFXCORE_X_VCCCPUCORE<U42> for VCCGFXCORE_I_VCCCPUCORE<U42>
3.9_0603_1% CYNTEC. PCME063T-R15MS0R907
3
VCC VIN
8 2 VCCCPUCORE VCCGFXCORE_X_VCCCPUCORE VCCGFXCORE_I_VCCCPUCORE
15 9
@ PR223 VCCD VIN PC2268
17 5 0.22UF_0402_25V6K
0_0201_5% 1
DRVON 64,66,67 2 1
DRVON 16 THWN BOOT 7 0.15UH 20% PCME063T-R15MS0R907 37A
DISB# PHASE PL29 U42@ U42@ U42@ U42@ U42@ U42@ U42@ U42@ U42@
PWM1_2ph_IA1 1
PWM

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
PWM1_2ph_IA1 2 11 1 4

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
64
VCC5M SMOD# SW 12 2 2 2 2
SW

PC10053

PC10054

PC10055

PC10056
2 3

PC10044

PC10045

PC10046

PC10047

PC10048
Max Current = 28(A) @EMI@
4 PC2422
10 CGND
PGND 0.1U_0201_6.3V6K

1
1 1 1 1

1
14
13 PGND 6
GL NC 2
19 18 EMI@
GL AGND
PC2269
1000P_0402_50V7K EMI
NCP302045MNTXG_PQFN33_5X5 1 CSN_1a_VCORE
64 CSN_1a_VCORE

C C

2
EMI@ CSP_1a_VCORE_R
64 CSP_1a_VCORE_R
PR2136
2.2_0603_5%
VCCCPUCORE
12pcs 22uF for VCCCPUCORE

22U_0603_6.3V6M

22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
EMI

2
2

PC10060

PC10059

PC10061

PC10062
PC6387

PC6396

PC6397

PC6398

PC6399

PC6400

PC6401

PC6402

1
1

1
Vinafix.com
These MLCCs must be placed
symmetrically on Top and Bottom.
Max Current = 3.50(A)
VINT12
PFL45 U42_EMI@
1 2 VINT12_CPUCORE_R U42_EMI@ U42_EMI@

BLM18KG300TN1D_2P
U42@ U42@ U42@ U42@

1000P_0201_25V7K
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
VCCCPUCORE
18pcs (+2pcs) 10uF for VCCCPUCORE
2

2 2 2 2 2

2
PC10036

PC10035

PC10038

PC10037

PC10030

PC10029
PC10034 U42_EMI@
VCC5M 0.1U_0402_25V6
1

1
1 1 1 1 1

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
2 2 2 2 2 2 2 2 2

PC8553

PC8554

PC8555

PC8556

PC8557

PC8558

PC8559

PC8560

PC8561
B U42@ B
PR9633 EMI 1 1 1 1 1 1 1 1 1
EMI
1 2

2_0201_5%
2

U42@
PC10032
1U_0402_6.3V6K
1

U42@
2

U42@ PR9635
PC10033 2 1 VCCCPUCORE
2.2U_0402_6.3V6M
SIT_EC009_DCDC
1

3.9_0603_1% TABLE PL46


U42@ PU153 2 U42@
3
15 VCC VIN
8
CYNTEC. PCME063T-R15MS0R907 VCCCPUCORE

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
9 PC10040
@U42@PR9643 VCCD VIN
0.22UF_0402_25V6K 2 2 2 2 2 2 2 2 2
1

PC8562

PC8563

PC8564

PC8565

PC8566

PC8567

PC8568

PC8569

PC8570
0_0201_5% 17 5
DRVON 2 1 16 THWN BOOT 7 U42@
DISB# PHASE 0.15UH 20% PCME063T-R15MS0R907 37A
PWM2_2ph_IA2 PWM2_2ph_IA2 64 1 PL46
2 PWM 11 1 1 1 1 1 1 1 1 1
VCC5M SMOD# SW
SW
12
1 4

2
2 3 Max Current = 28(A) @U42_EMI@
4
CGND PC10027
10
14 PGND 0.1U_0201_6.3V6K

1
PGND
SIT_EC003_DCDC 13
19 GL NC
6
18 2
GL AGND U42_EMI@
PC10031
NCP302045MNTXG_PQFN33_5X5 1000P_0402_50V7K EMI
1 4pcs 1uF for VCCCPUCORE
CSN_2a_VCORE
64 CSN_2a_VCORE VCCCPUCORE

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
64 CSP_2a_VCORE_R CSP_2a_VCORE_R
2

U42_EMI@ 2 2 2 2

PC8604

PC8605

PC8606

PC8607
PR9634
A 2.2_0603_5% A
1 1 1 1
1

FVT_EC001_DCDC

EMI
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC VCCCPUCORE
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E291P
Date: Monday, October 23, 2017 Sheet 65 of 102
5 4 3 2 1

Main Func = CPUcore IA/GT/SA


5 4 3 2 1

D D

TABLE for PC2508, PC2516

Panasonic, ETPE330MA9GB
VCCGFXCORE_I 9pcs 22uF for VCCGFXCORE_I
NEC TOKIN PSGB20E337M9

330U_B_2.5VM_R9M

330U_B_2.5VM_R9M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1 1

2
PC2516
+

PC2508
+

PC2107

PC2108

PC2509

PC2510

PC2511

PC2512

PC2513

PC2514

PC2515
1

1
2 2

These MLCCs must be placed


symmetrically on Top and Bottom.
Max Current = 3.88(A)
VINT12
PFL42
1 2 VINT12_GFXCORE_IA EMI@ EMI@

C
BLM18KG300TN1D_2P 20pcs (+3pcs) 10uF for VCCGFXCORE_I C

1000P_0201_25V7K
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

0.1U_0402_25V6
EMI@ EMI@ 2

2
2

2
VCCGFXCORE_I

PC2277

PC2332
PC2300

PC2272

PC2273

PC2274
VCC5M PC8484
0.1U_0402_25V6

1
1

1
1

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
PR2138 2 2 2 2 2 2 2 2 2 2
EMI

PC8573

PC8574

PC8575

PC8576

PC8577

PC8578

PC8579

PC8580

PC8581

PC8582
1 2
EMI 1 1 1 1 1 1 1 1 1 1
2_0201_5% SIT_EC004_DCDC
2

Vinafix.com
PC2271
1U_0402_6.3V6K
1

Max Current = 31(A)


2

PC2270
2.2U_0402_6.3V6M
PU134
PR2140 VCCGFXCORE_I
1

1 2 TABLE PL30
3 8
15 VCC VIN 9 2
@ PR225 VCCD VIN 3.9_0603_1%
PC2280
CYNTEC. PCME063T-R15MS0R907 VCCGFXCORE_I
0_0201_5% 17 5 0.22UF_0402_25V6K
DRVON 64,65,67 2 1 16 THWN BOOT 7 1
DRVON DISB# PHASE PL30 0.15UH 20% PCME063T-R15MS0R907 37A
PWM_1a_GT PWM_1a_GT
64 1
2 PWM 11 1 4
SMOD# SW 12
SW 2 3

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
4 @EMI@
10 CGND PC2423
PGND 2 2 2 2 2 2 2 2 2 2

PC8583

PC8584

PC8585

PC8586

PC8587

PC8588

PC8589

PC8590

PC8591

PC8592
14 0.1U_0201_6.3V6K

1
13 PGND 6 2
B
SIT_EC003_DCDC 19 GL
GL
NC
AGND
18 EMI@
PC2279 1 1 1 1 1 1 1 1 1 1 B
EMI
1000P_0402_50V7K
NCP302045MNTXG_PQFN33_5X5 1 CSN_1a_GT
64 CSN_1a_GT

64 CSP_1a_GT CSP_1a_GT
2

EMI@
PR2141
2.2_0603_5%

VCCGFXCORE_I
1

VCCGFXCORE_I
6pcs 1uF for VCCGFXCORE-I

EMI

FVT_EC002_DCDC

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
2 2 2 2 2 2 2 2 2

PC8593

PC8594

PC8597

PC8598

PC8599

PC8600

PC8601

PC8602

PC8603
1 1 1 1 1 1 1 1 1
@ @ @

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC VCCGFXCORE_I
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E291P
Date: Monday, October 23, 2017 Sheet 66 of 102
5 4 3 2 1
5 4 3 2 1

D D

These MLCCs must be placed


symmetrically on Top and Bottom.
Max Current = 0.49(A)
VINT12
PFL44
1 2 VINT12_SA EMI@ EMI@

BLM18KG300TN1D_2P

1000P_0201_25V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
EMI@ 2 2 2

2
PC2292

PC2295

PC2296

PC2301
PC8486 6pcs (+2pcs) 22uF for VCCSA
0.1U_0402_25V6

1
1 1 1
EMI@
VCC5M

C
EMI
VCCSA C

EMI
PR2148

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1 2
@ @

2
PC2224

PC2225

PC2226

PC2227

PC2228

PC2229
2_0201_5%
2

1
PC2291
1U_0402_6.3V6K
1
2

PR2150 Max Current = 5(A)


PC2290 TABLE PL32
1 2
2.2U_0402_6.3V6M
VCCSA
1

PU136 MAG. LAYERS MMD05CZR47M


3.9_0603_1% 2

Vinafix.com
3 8
15 VCC VIN 9
VCCD VIN PC2297
@ PR226 0.22UF_0402_25V6K
0_0201_5% 17 5 1
DRVON DRVON 64,65,66 2 1 16 THWN BOOT 7 VCCSA
PWM_1B_SA 1 DISB# PHASE PL32 0.47UH_MMD05CZR47M_12A_20%
PWM_1B_SA 64 PWM
2 11 1 4
SMOD# SW 12
SW 2 3

22U_0603_6.3V6M

22U_0603_6.3V6M
4 EMI@
10 CGND PC2424
PGND

2
PC2232

PC2233
14 0.1U_0201_6.3V6K

1
13 PGND 6
GL NC 2
19 18 EMI@
SIT_EC003_DCDC

1
GL AGND PC2298
NCP302035MNTXG_PQFN33_5X5 EMI
1000P_0402_50V7K
1
CSN_1b_VCCSA
64 CSN_1b_VCCSA

CSP_1b_VCCSA64 CSP_1b_VCCSA

2
EMI@
B B
PR2151
2.2_0603_5%

1
EMI

FVT_EC003_DCDC

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC VCCSA(NCP81382)
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E291P
Date: Monday, October 23, 2017 Sheet 67 of 102
5 4 3 2 1
5 4 3 2 1

D D

VL PQ704
AO3413_SOT23-3

D
3 1

G
1

1 2
PC10063 PR9667
0.1U_0402_10V6K 100K_0402_5% PR9666
2
100_0402_1%

2
VCC5M

1 2

2
PR9668 10K_0402_5% PC2354

2
0.01U_0402_16V7K @
PR2479
1

PR9665

1
PQ703 D
EN_3V 2 0_0402_5% 0_0402_5%
G

1
VCC1R0

1
S 2N7002KW_SOT323-3 @

SLEW_VCC1R0
3

2.2U_0402_10V6M VINT12

TRIP_VCC1R0
PC6336
2 1 2

C
SDV_EC002_DCDC PR703 C
@EMI@ @EMI@ @EMI@
200K_0402_1%

23

22

21

20

19

18

17

16

15

2200P_0402_50V7K
PU32
1

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

68P_0402_50V8J
0.1U_0402_25V6
GSNS

VSNS

SLEW

TRIP

GND

V5

VIN

VIN

VIN
REFIN_VCC1R0

1
PC2353

PC8596
PC493
24
REFIN2
1

PC2352

PC646

PC647

PC482
14
PR716 PR704 PGND

2
100K_0402_1% 200K_0402_1% 25
1 2 REFIN 13
EN_3V PGND
1.0VS OCL = 8A (Trip = GND)
2

2 1 VREF_VCC1R0 26
VREF TPS51362RVER_QFN28_4P5X3P5 12 1.0VS OCL = 12A (Trip = 5V)
PGND
PC2355 VREF = 2V EMI
0.1U_0402_10V7K 27
RA 11
PGND VCC1R0_SUS_P
EN_VCC1R0 28
EN +1.0 V +/- 5%

Vinafix.com
10
PGND
TDC:7.12 A
PGOOD

MODE
29
TP Peak Current:8.9 A

BST
LP#

SW

SW

SW

SW
VCC3SW_P NC

2
PL7 PJ9236 PJ9235
OCP Current:12 A
1

9
.68UH_PCMC063T-R68MN_15.5A_20% PAD-OPEN 4x4m PAD-OPEN 4x4m
SW_VCC1R0 1 2 @ @
BST_VCC1R0
2

1
@ PR707 Output Volttage = 1.05V (REFIN Voltage = GND)

2.2_0805_1% 1000P_0402_50V7K
100K_0402_5% @ Output Volttage = 1.2V (REFIN Voltage = FLOAT)
1

PC2357
PC2356
PR2244
PC709 0.1U_0603_25V7K VCC1R0 Output Volttage Adi between = 0.6V~2V (REFIN Voltage = Resistor divider)
EMI@
0.1U_0402_10V7K 1 2 1 2
1
2

2
PGOOD_VCC1R0
0_0402_5%

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
PR2245

1
B EMI@ B

PC889

PC881

PC880

PC878

PC520

PC572

PC592

PC594
2

2
EMI

FVT_EC012_DCDC
SIT_EC002_DCDC

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC VCC1R0_SUS_P(TPS51362)
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E291P
Date: Monday, October 23, 2017 Sheet 68 of 102
5 4 3 2 1
5 4 3 2 1

D D

0.6Volt +/- 5%
PJ2033 TDC: 0.8 A
1
1 2
2 +VCC1R2A Peak Current 1 A
1 2 BOOT_VCC1R2A
OCP Current
VINT12 PR2453 2.2_0402_5% JUMP_43X39 1.6A(min)
@
2.6A(typ)

2
@EMI@ @EMI@ EMI@ EMI@ EMI@ @EMI@ @EMI@ PC2564 VLDOIN_VCC1R2A 3.6A(max)
0.1U_0603_50V_X7R

1
0.1U_0402_25V6

0.1U_0402_25V6
68P_0402_50V8J

68P_0402_50V8J

2200P_0402_50V7K
0.1U_0402_25V6

0.1U_0402_25V6
+VCC0R6B

10U_0603_25V6M

10U_0603_25V6M
DH_VCC1R2A

5
PC10021

PC10020
PC10023

PC10022

AON7408L_DFN8-5
1

1 1 1

10U_0603_6.3V6M
PC2358

PC8679

PC2359

PC2360

PC2361
SW_VCC1R2A

10U_0603_6.3V6M
@
2

PJ9228
2

1
2 2

PC404

PC423
16

17

18

19

20
4 PU118 1 2

PHASE

UGATE

BOOT

VLDOIN

VTT

2
Reserve for RF EMI parts. EMI 21 CONNECT TO
PQ512 PAD +VCC1R2A @ PAD-OPEN 4x4m VCC1R2A
DL_VCC1R2A 15 1
PJ9226 DIMM CONNECTOR

1
2
3
LGATE VTTGND 1 2
C C
14 2
1UH_PCMB063T-1R0MS_12A_20% PR502 PGND VTTSNS PAD-OPEN 4x4m
PL34 13.7K_0402_1%
1 2 1 2 CS_VCC1R2A 13 3
PJP505
+VCC1R2A CS RT8207PGQW_WQFN20_3X3 GND
CONNECT TO

1000P_0603_50V7K
1 2
+VCC0R6B
@ 1 2 VCC0R6B DIMM CONNECTOR

5
PC8678
EMI@ 12 4 VTTREF_VCC1R2A
PR9593 VDDP VTTREF
VCC5M 5.1_0402_1% JUMP_43X39

SNUB_VCC1R2A
2

1
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

0.1U_0201_6.3V6K

1 2 VDD_VCC1R2A 11 5
VDD VDDQ +VCC1R2A

PGOOD
PC510
2

1
PC10012

PC10011

PC2362

PC2363

PC2364

PC2098

PC2099

PC2415

4 0.033U_0402_16V7K

TON

2
PC8638 220P_0402_50V8J

FB
S5

S3
1U_0402_16V6K
1

2
PQ513 AON7752_DFN3X3EP8-5 @ PC512

10

FB_VCC1R2A 6
1 2

1
2
3
EMI@
1

Vinafix.com
2.2_1206_1%

1 2
VCC5M
PR9592

1
PR511 PD318 PR9535

2
2.2_0402_5% RB751V40_SC76-2 4.64K_0201_1%
PC514 0.75V 1 2
+VCC1R2A
2

PR506
+1.2V +/- 5% 1U_0603_10V6K

1
EMI Pull high resistor 619k_0201_1%

2
TDC:6.4 A FVT_EC012_DCDC @ must be less than 2Mohm VINT12 1 2

1
PR507
Peak Current:8 A 0_0402_5% S5_VCC1R2A PR508 PC515
OCP Current: 10.83 A 1 2 70 @ 7.5K_0201_1% @.1U_0402_16V7K

2
1
2R5A_PWRGD @ PC516 PR509
H/S Rds(on): 30 mΩ DDR_VTT_PG_CTRL 0_0402_5%

2
1U_0402_6.3V6K 1 2 S3_VCC0R6B
L/S Rds(on): 14.5 mΩ PD297

2
Freq=400kHz A_ON

0.1U_0402_10V7K
1 702

PC517
1
RB521CM-30T2R_SOD923-2 FVT_EC009_DCDC @

2
B
SIT_EC002_DCDC B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC VCC1R2A(RT8207P)
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E291P
Date: Monday, October 23, 2017 Sheet 69 of 102
5 4 3 2 1
5 4 3 2 1

D D

+2.5V +/- 5%
TDC:0.8A
VCC3M Peak Current:1 A
@
Current Limit :4 A (MIN)
PJ18

100K_0201_5%
1 2 VCC2R5A_VIN
VCC5M 1 2

PR2546
22U_0603_6.3V6M

22U_0603_6.3V6M
JUMP_43X39
@
+VCC2R5A PJ11

PC2601
1

PC2602
C C
PU151

1
TABLE PL704 +VCC2R5A 1 2 VCC2R5A
10 1 2

2
PVIN
9 PGOOD
4
69 2R5A_PWRGD TOKO, DFE201612R-H-1R0M JUMP_43X39
PVIN CYNTEC, PIFE20161B-1R0MS
1
8 NC PL42
SVIN 2 LX_VCC2R5A 1 2
7 LX 1UH_DFE201612R-H-1R0M-P2_2.6A_20%
NC

68P_0402_50V8J

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
3
LX

1
EN_VCC2R5A 5

2.2_1206_1%
EN

1
@

PC8651

PC2603

PC2604

PC8671
6 PR2547
PR9564 FB

PR9539
11 32.4K_0402_1%
0_0402_5% TP EMI@

2
A_ON

0.1U_0402_25V6
1 2
69

2
RT8061AZQW_WDFN10_3X3

1
PC8645
0.6V

1000P_0402_50V7K
2

1
Vinafix.com

PC8650
EMI@

1
@
SIT_EC002_DCDC PR2548

2
10K_0201_1%

2
EMI
FB_VCC2R5A

FVT_EC012_DCDC

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC VCC2R5A(RT8061)
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E291P
Date: Monday, October 23, 2017 Sheet 70 of 102
5 4 3 2 1
5 4 3 2 1

D D

+1.8 V +/- 5%
@
PJ9232 TDC:0.8 A
1 2 VCC1R8_VIN Peak Current:1 A
VCC5M 1 2
Current Limit :4 A (MIN)

22U_0603_6.3V6M
22U_0603_6.3V6M
JUMP_43X39

1
PC2416

PC2417
C C
PU145
10 VCC1R8_PRIM

2
PVIN 4
9 PGOOD
PVIN 1
NC PJ9240
8 PL39
SVIN 2 LX_VCC1R8 1 2 1 2
7 LX VCC1R8_PRIM @ 1 2 VCC1R8_SUS
NC

68P_0402_50V8J
3 2.2UH_MLV-YT12N2R2M-O1L_2A_20%
LX JUMP_43X39

22U_0603_6.3V6M

22U_0603_6.3V6M
EN_VCC1R8 5

2.2_1206_1%
EN

1
@

PC8654
6 PR9567
FB

1
PR9565

PR9542

PC2418

PC2419
11 20K_0201_1%
TP EMI@
SUS_ON1 0_0402_5%

2
0.1U_0402_25V6
1 2

2
RT8061AZQW_WDFN10_3X3

1
PC8652
0.6V

SIT_EC002_DCDC
2

1000P_0402_50V7K
Vinafix.com
@

PC8653

1
EMI@
PR9545

2
10K_0201_1%

2
EMI
FB_VCC1R8

FVT_EC012_DCDC

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC VCC1R8_SUS(RT8061)
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E291P
Date: Monday, October 23, 2017 Sheet 71 of 102
5 4 3 2 1
5 4 3 2 1

PTH FOR SCREW HOLE

Pad Dia
Value Hola Dia QTY
TOP BOTTOM
D D
TESTPIN_2P5_01 2.5 6 6 10
TP_A1 TP_B1 TP_C1 TP_D1 TP_F1 TP_H1 TP_I1 TP_K1
TESTPIN_2P5_01 TESTPIN_2P5_01 TESTPIN_2P5_01 TESTPIN_2P5_01 TESTPIN_2P5_01 TESTPIN_2P5_01 TESTPIN_2P5_01 TESTPIN_2P5_01
TESTPIN_2P5_02 2.5 7.4 7.4 2
@ @ @ @ @ @ @ @

1
TESTPIN_2P5_03 2.5 Square 0 1

TESTPIN_2P5_06 2.5 5 5 2

TESTPIN_2P8_01 2.8 0 Square 1

TESTPIN_4P3_01 4.3 6.5 6.5 3

TESTPIN_4P0_01 4.0 6.1 6.1 4

TP_L1 TP_M1 TP_O1 TP_P1 TP_Q1 TP_R1 TP_S1 TP_T1 TP_U1 TP_V1 TP_W1 TP_X1
TESTPIN_2P5_02 TESTPIN_2P5_02 TESTPIN_2P5_06 TESTPIN_2P5_06 TESTPIN_2P8_01 TESTPIN_4P2_01 TESTPIN_4P2_01 TESTPIN_4P2_01 TESTPIN_4P0_01 TESTPIN_4P0_01 TESTPIN_4P0_01 TESTPIN_4P0_01

@ @ @ @ @ @ @ @ @ @ @ @
1

1
C C

TP_Y1 TP_E1 TP_Z1

Vinafix.com
H_2P5N H_4P0X2P5N H_5P6N
H_2P5N @ @ H_4P0X2P5N H_5P6N @
1

FD1 FD4
@ @
1 1
NC, NO CONNECT TO ANY. NC, NO CONNECT TO ANY.

FID FD2
@
1
B Board Area NC, NO CONNECT TO ANY. B

FD3
@
1
NC, NO CONNECT TO ANY.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PTH FOR SCREW HOLES
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 72 of 73
5 4 3 2 1
5 4 3 2 1

ZZZ

DA8001C9000

BOM Structure Table


U58 U58 U58 U58 U58 U58 U58 U58
BTO Item BOM Structure Remark
D D
vPRO LAN chip VPRO@ WGI219LM
non vPRO LAN chip NVPRO@ WGI219V
KBL QLYK 2.4G KBL-R QN5C KBL-R QN5D KBL-R QNBE KBL-R QNEF KBL-R QNBF KBL-R QNEE KBL-R QNB1 Thunderbolt requirement TBT@
CPU1@ CPU2@ CPU3@ CPU4@ CPU5@ CPU6@ CPU7@ CPU8@
SA0000A38N0 SA0000AQZ20 SA0000AR020 SA0000AWR00 SA0000AWB00 SA0000AWC00 SA0000AWS00 SA0000B2Y40
Thunderbolt reserve @TBT@
ESD requirement ESD@
U13
ESD reserve @ESD@
EMI requirement EMI@
EMI reserve @EMI@
Jacksonville WGI219V RF requirement RF@
NVPRO@
SA000093410
RF reserve @RF@
XDP XDP@
ZZZ ZZZ ZZZ ZZZ ZZZ ZZZ
On board RAM X76@
2+2 CPU U22@
4+2 CPU U42@
Samsung 1G Samsung 2G MIcron 1G Micron 2G Hynix 1G Hynix 2G
S1G@ S2G@ M1G@ M2G@ H1G@ H2G@
X7666239L24 X7666239L23 X7666239L22 X7666239L24 X7666239L22 X7666239L23

C C

Vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/11/04 Deciphered Date 2016/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCB CPU PN
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F421P
Date: Monday, October 23, 2017 Sheet 73 of 73
5 4 3 2 1

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