Lenovo B41-35 Compal LA-C293P AAWBC - BD Rev 1.0 PDF

A B C D E
1 1
Compal LA-C293P
2 2
B/N series AMD

Carrizo/Carrizo-L
DIS M/B Schematics Document
AMD Exo Pro
3
REV：
：1.0 3
2015-03-06
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/03/06 Deciphered Date 2016/03/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-C293P
Date: Monday, March 09, 2015 Sheet 1 of 48
A B C D E
A B C D E
Carrizo only
AMD Carrizo/Carrizo-L 1
Memory BUS(DDR3L)
AMD Exo Pro S3 18W 204pin DDR3L SO-DIMM X2
GFX PCIe x 4
VRAM 1GB(reserved)/2GB GFX Single Channel BANK 0, 1, 2
DDR3L x4
1.35V DDRIIIL 1600MHz
eDP Conn. DP0
Right USB 2.0

CMOS WLAN/BT Touch screen Conn.
DP1 (reserved) (USB Charger reserved)
CRT Conn. DP to CRT Translator DP Swich Camera Combo In IO/B
Realtek Parade AMD FP4 APU
RTD2168 PS8339B Port 3 Port 5 Port 1 Port 0
2
USB USB2.0 2
Port 8 Port 9 Port 7
HDMI Conn. DP2
BGA 968-balls MB MB Finger Print
(reserved)
GPP 3.0 Conn. LP1 3.0 Conn. LP2
GPP0 GPP2 GPP1
USB
LAN 10/100/1G
Card Reader NGFF
Realtek
Realtek (WLAN/BT)
8111H HD Audio
RTS5220
8107E(reserved)
SATA
Transformer Gen3 Port 0 Port 1
RJ45 Audio
HDD ODD
Realtek
Conn. Conn.
SPI ROM (8MB) SPI ALC3248
3
LPC 3
TCM Int. MIC Int. Speaker Conn. Audio Combo Jacks

Nuvoton
Z32H320TC In IO/B
NPCE388NB0DX (reserved)
14" Sub-borad 15" Sub-borad
IO/B Int.KBD Touch Pad Thermal Sensor

USB2.0 x 1 IO/B (reserved)
Combo Jack USB2.0 x 1 ODD/B
Novo button Combo Jack
Novo button
LED/B
LED/B
4 Battery/B 4
14" Power/B
15" Power/B
BLOCK DIAGRAMS
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
LA-C293P
A B C D E
A B C D E
Voltage Rails
SIGNAL
STATE SLP_S3# SLP_S5# +VALW +V +VS Clock
Power Plane Description S0 S3 S5 USB OC MAPPING
VIN Adapter power supply (19V) ON ON ON Full ON HIGH HIGH ON ON ON ON
OC# USB Port
B+ AC or battery power rail for power circuit. ON ON ON
S3 (Suspend to RAM) HIGH HIGH ON ON OFF OFF
+APU_CORE Core voltage for APU ON OFF OFF 0 USB2 port0
+APU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF 1 USB2 port6,7 USB3 port2,3 S4 (Suspend to Disk) LOW HIGH ON OFF OFF OFF
1
+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF 2 1
S5 (Soft OFF) LOW LOW ON OFF OFF OFF
+3VALW 3.3V always on power rail ON ON OFF
+3VS 3.3V switched power rail ON OFF OFF
+1.8VALW 1.8V always on power rail ON ON ON*
+1.8VS 1.8V switched power rail ON OFF OFF
+0.95VALW 0.95V always on power rail ON OFF OFF
BOM Structure Table
+1.35V 1.35V power rail for APU and DDR ON ON OFF
BOM Structure BTO Item
+3VGS 3.3V switched power rail for VGA ON OFF OFF 45@ for HDMI Logo
+1.8VGS 1.8V switched power rail for VGA ON OFF OFF 14@ for 14" componect
+1.35VGS 1.35V switched power rail for VGA ON OFF OFF 15@ for 15" componect
+0.95VGS 0.95V switched power rail for VGA ON OFF OFF PX_CZL@ GFX GEN2 caps for PX CZL
+5VALW 5V always on power rail ON ON ON PX_CZ@ GFX GEN3 caps for PX CZ
+5VS 5V switched power rail ON OFF OFF CZ@ For CZ APU BOM
CZL@ For CZL APU BOM
+RTC_APU RTC power ON ON ON
2 2
A8@
+0.675VS 0.675V switched power rail for DDR terminator ON OFF OFF
A6@
A4@
SMBUS Control APU PCIE PORT LIST
Port Device E1@
SOURC UMA@ UMA part
1 LAN
EXO@
EC_SMB_CK1
EC_SMB_DA1
EC 388N
+3VLP
X V
+3VLP
X X X X 2
3
WLAN
MESO@
CMOS@
HDMI@
APU_SCLK0
APU_SDATA0
APU
+3VS
X X V X X X 8107E_LDO@
+3VS 8107E_SW@
3 EC_SMB_CK2 EC 388N V X X X V V 8111H_LDO@

8111H_SW@ 3
EC_SMB_DA2 +3VS +3VS +3VS +3VS Touch Screen

TS@
ZODD@ Zero Power ODD part
NOZODD@ Non-Zero Power ODD part
USB Port Table
CHG@ USB Charger function
3 External NOCHG@ Non-USB Charger function
EC SM Bus1 address EC SM Bus2 address USB 2.0 USB 3.0 Port USB Port FHD@ Full HD Panel
Device Address HEX Device Address HEX 0 RIGHT USB CRT@ CRT BOM
Smart Battery 0001 011X b 16H Thermal Sensor 1001 101X b 9AH 1 Touch Screen USB3@ USB 3.0
SB-TSI (APU) 1001 100X b 98H 2 Finger Print EX_THM@ External Thermal sensor
3 Camera NOTCM@ NOTCM componets
EHCI TCM componets
VGA Internal Thermal 1000 001X b 82H 4 TCM@
5 WLAN/BT Combo ME@ ME part
2 6 LEFT USB3.0 EMIP@ EMI pop component
XHCI EMI Un pop component
APU 3 7 LEFT USB3.0 EMIU@
ESDP@ ESD pop component
4 SM Bus address ESDU@ ESD Un pop component 4
Device Address HEX @ Unpop

DDR DIMM2 1010 000Xb A0H
DDR DIMM1 1010 001Xb A2H
NOTES LIST
Size
Document Number Rev
B 1.0
LA-C293P
A B C D E
5 4 3 2 1
EXO Pro VRAM STRAP Power-Up/Down Sequence

X76@ X76@ "EXO" has the following requirements with regards to power-supply
Vendor
UV5, UV6, UV7, UV8
ID PS_3[ 3 ] PS_3[ 2 ] PS_3[ 1 ]
R_pu
RV21
R_pd
RV24 ‧
sequencing to avoid damaging the ASIC:
All the ASIC supplies must reach their respective nominal voltages within 20ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred.
Hynix 2048Mbits
D
ZZZ09
1GBytes JH1G@
SA00006H400
128Mx16 H5TC2G63FFR-11C 0 0 0 0 NC 4.75K ‧‧The maximum slew rate on all rails is 50 mV/µs.
It is recommended that the 3.3-V rail ramp up frist.
It is recommended that the 0.95-V rail reach at least 90% of its nominal value no later
D
Micron 2048Mbits
ZZZ10
1GBytes JM1G@
SA000067500
128Mx16 MT41J128M16JT-093G:K
Samsung 2048Mbits
1 0 0 1 8.45K 2K
‧than 2ms from the start of VDDC ramping up.
The power rails that are shared with other components on the system should be gated for
the dGPU so that when dGPU is powered down (for example AMD PowerXpressTM idle state),
≦
ZZZ11 SA000068U40 all the power rails are removed from the dGPU.
1GBytes JS1G@ 2 0 1 0 4.53K 2K
‧
128Mx16 K4W2G1646Q-BC1A The gate circuits must meet the slew rate requirement (such as 50mV/us)
Hynix 4096Mbits VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
‧
ZZZ12 SA00006E800 should reach 90% before VDD_CT starts to ramp up (or vice versa).
2GBytes JH2G@ 256Mx16 H5TC4G63AFR-11C 3 0 1 1 6.98K 4.99K
For power down, reversing the ramp-up sequence is recommended.
Samsung 4096Mbits
ZZZ13 SA000076P00
2GBytes JS2G@ 256Mx16 K4W4G1646D-BC1A 4 1 0 0 4.53K 4.99K
Micron 4096Mbits
ZZZ14 SA000077K00
2GBytes JM2G@ 256Mx16 MT41J256M16HA-093G:E 5 1 0 1 3.24K 5.62K
Micron 4096Mbits
ZZZ08 SA000065D00
2GBytes JM2G2@ 256Mx16 MT41K256M16HA-107G:E 6 1 1 0 3.4K 10K
Micron 2048Mbits
ZZZ16 SA00005XB00 VDDR3(+3VGS)
1GBytes JM1G2@ 128Mx16 MT41K128M16JT-107G:K 7 1 1 1 4.75K NC
C
PCIE_VDDC(+0.95VGS)
ZZZ ZZZ ZZZ ZZZ
VDD_CT(+1.8VGS)
JH1G@ JM1G@ JS1G@ JH2G@
1G HYNIX 1G MICRON 1G SAMSUNG 2G HYNIX
X7653638L07 X7653638L08 X7653638L09 X7653638L04 VDDR1(+1.35VGS)
VDDC/VDDCI(+VGA_CORE)
DGPU_PW C
PERSTb
R
REFCLK
Straps Reset
B B
DGPU_PW
Straps Valid
Global ASIC Reset
A A

VGA Notes List
C 1.0
LA-C293P
5 4 3 2 1
5 4 3 2 1
UAPU1B
PCIE
D U10 R1 PCIE_ATX_DRX_P0 CC15 1 2 0.1U_0201_10V7K D

P_GPP_RXP[0] P_GPP_TXP[0]
<25> PCIE_DTX_C_ARX_P0 U9 R2 1 2 PCIE_ATX_C_DRX_P0 <25>
Card Reader P_GPP_RXN[0] P_GPP_TXN[0] PCIE_ATX_DRX_N0 CC16 0.1U_0201_10V7K Card Reader
<25> PCIE_DTX_C_ARX_N0 PCIE_ATX_C_DRX_N0 <25>
T6 P_GPP_RXP[1] P_GPP_TXP[1] R4 PCIE_ATX_DRX_P1 CC17 1 2 0.1U_0201_10V7K
<26> PCIE_DTX_C_ARX_P1 T5 R3 1 2 PCIE_ATX_C_DRX_P1 <26>
LAN P_GPP_RXN[1] P_GPP_TXN[1] PCIE_ATX_DRX_N1 CC18 0.1U_0201_10V7K LAN
T9 P_GPP_RXP[2] P_GPP_TXP[2] N1 PCIE_ATX_DRX_P2 CC19 1 2 0.1U_0201_10V7K
<27> PCIE_DTX_C_ARX_P2 T8 N2 1 2 PCIE_ATX_C_DRX_P2 <27>
WLAN P_GPP_RXN[2] P_GPP_TXN[2] PCIE_ATX_DRX_N2 CC20 0.1U_0201_10V7K WLAN
P7 P_GPP_RXP[3] P_GPP_TXP[3] N4
P6 P_GPP_RXN[3] P_GPP_TXN[3] N3
RC1 1 CZ@ 2 196_0402_1% P_ZVDDP U7 P_ZVDDP P_ZVSS/P_RX_ZVDDP U6 P_ZVSS RC2 1 CZL@ 2 1K_0402_1%
+0.95VS +0.95VS
RC3 1 CZ@ 2 196_0402_1%
RC1 S RES 1/16W 1.69K +-1% 0402
CZL@
P10 P_GFX_RXP[0] P_GFX_TXP[0] M2 PCIE_ATX_GRX_P0 CC7 PX_CZL@ 1 2 0.1U_0402_16V7K
<14> PCIE_GTX_C_ARX_P0 P9 M1 PCIE_ATX_C_GRX_P0 <14>
P_GFX_RXN[0] P_GFX_TXN[0] PCIE_ATX_GRX_N0 CC8 PX_CZL@ 1 2 0.1U_0402_16V7K
<14> PCIE_GTX_C_ARX_N0 PCIE_ATX_C_GRX_N0 <14>
N6 P_GFX_RXP[1] P_GFX_TXP[1] L1 PCIE_ATX_GRX_P1 CC9 PX_CZL@ 1 2 0.1U_0402_16V7K
<14> PCIE_GTX_C_ARX_P1 PCIE_ATX_C_GRX_P1 <14>
N5 P_GFX_RXN[1] P_GFX_TXN[1] L2 PCIE_ATX_GRX_N1 CC10 PX_CZL@ 1 2 0.1U_0402_16V7K
VGA VGA
N9 P_GFX_RXP[2] P_GFX_TXP[2] L4 PCIE_ATX_GRX_P2 CC11 PX_CZL@ 1 2 0.1U_0402_16V7K
<14> PCIE_GTX_C_ARX_P2 PCIE_ATX_C_GRX_P2 <14>
N8 P_GFX_RXN[2] P_GFX_TXN[2] L3 PCIE_ATX_GRX_N2 CC12 PX_CZL@ 1 2 0.1U_0402_16V7K
C <14> PCIE_GTX_C_ARX_N2 PCIE_ATX_C_GRX_N2 <14> C
L7 P_GFX_RXP[3] P_GFX_TXP[3] J1 PCIE_ATX_GRX_P3 CC13 PX_CZL@ 1 2 0.1U_0402_16V7K

<14> PCIE_GTX_C_ARX_P3 L6 J2 PCIE_ATX_C_GRX_P3 <14>
P_GFX_RXN[3] P_GFX_TXN[3] PCIE_ATX_GRX_N3 CC14 PX_CZL@ 1 2 0.1U_0402_16V7K
L10 P_GFX_RXP[4] P_GFX_TXP[4] J4
L9 P_GFX_RXN[4] P_GFX_TXN[4] J3 CC7 CC9 CC11 CC13
PX_CZ@ PX_CZ@ PX_CZ@ PX_CZ@ S CER CAP 0.22U 10V K X5R 0402
K6 P_GFX_RXP[5] P_GFX_TXP[5] H2
K5 P_GFX_RXN[5] P_GFX_TXN[5] H1 CC8 CC10 CC12 CC14
ZZZ ZZZ PX_CZ@ PX_CZ@ PX_CZ@ PX_CZ@
K9 P_GFX_RXP[6] P_GFX_TXP[6] G1
K8 P_GFX_RXN[6] P_GFX_TXN[6] G2
J7 P_GFX_RXP[7] P_GFX_TXP[7] G4 UAPU1

J6 P_GFX_RXN[7] P_GFX_TXN[7] G3 UAPU1 AMD E2-7110 1.8G 2M 4cBGA APU
LAC293P 14@ LAC293P 15@ AMD A8-7410 2.2G 2M 4cBGA APU E2@
A8@ SA00008KW20
DA6001BC010 DA6001BC110 SA00008PS10
FP4 REV 0.93
A6@ FP4_BGA968
S IC CARRIZO-L AM7310JBY44JB 2G BGA 968P UAPU1 UAPU1
SA00008KX20 AMD A4-7210 1.8G 2M 4cBGA APU AMD E1-7010 1.5G 1M 2cBGA APU
A4@ E1@
SA00008J520
B
Carrizo: SA00008KY20 B
PCIe GPP: Four x1 Gen2

PCIe Discrete Graphics Port: PCI Gen3 x8
Carrizo-L:
PCIe GPP: Four x1 Gen2
PCIe Discrete Graphics Port: PCI Gen2 x4
A A

FP4 PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 1.0
LA-C293P
5 4 3 2 1
5 4 3 2 1
UAPU1A UAPU1I
<12,13> DDRAB_SMA[15..0] DDRAB_SDQ[63..0] <12,13>
MEMORY A MEMORY B
AE28 MA_ADD[0] MA_DATA[0] H17 DDRAB_SMA0 AG31 MB_ADD[0] MB_DATA[0] A25 DDRAB_SDQ0
Y27 MA_ADD[1] MA_DATA[1] J17 DDRAB_SMA1 AC30 MB_ADD[1] MB_DATA[1] C25 DDRAB_SDQ1
Y29 MA_ADD[2] MA_DATA[2] F20 DDRAB_SMA2 AC31 MB_ADD[2] MB_DATA[2] C27 DDRAB_SDQ2
Y26 MA_ADD[3] MA_DATA[3] H20 DDRAB_SMA3 AB32 MB_ADD[3] MB_DATA[3] D27 DDRAB_SDQ3
W 28 MA_ADD[4] MA_DATA[4] E17 DDRAB_SMA4 AA32 MB_ADD[4] MB_DATA[4] B24 DDRAB_SDQ4
W 29 MA_ADD[5] MA_DATA[5] F17 DDRAB_SMA5 AA33 MB_ADD[5] MB_DATA[5] B25 DDRAB_SDQ5
W 26 MA_ADD[6] MA_DATA[6] K18 DDRAB_SMA6 AA31 MB_ADD[6] MB_DATA[6] B27 DDRAB_SDQ6
U29 MA_ADD[7] MA_DATA[7] E20 DDRAB_SMA7 Y33 MB_ADD[7] MB_DATA[7] A27 DDRAB_SDQ7
W 25 MA_ADD[8] DDRAB_SMA8 AA30 MB_ADD[8]
U26 MA_ADD[9] MA_DATA[8] A21 DDRAB_SMA9 W 32 MB_ADD[9] MB_DATA[8] A29 DDRAB_SDQ8
AG29 MA_ADD[10] MA_DATA[9] C21 DDRAB_SMA10 AG32 MB_ADD[10] MB_DATA[9] C29 DDRAB_SDQ9
U27 MA_ADD[11] MA_DATA[10] C23 DDRAB_SMA11 Y32 MB_ADD[11] MB_DATA[10] B32 DDRAB_SDQ10
D D
T28 MA_ADD[12] MA_DATA[11] D23 DDRAB_SMA12 W 33 MB_ADD[12] MB_DATA[11] D32 DDRAB_SDQ11
AK26 MA_ADD[13] MA_DATA[12] B20 DDRAB_SMA13 AL31 MB_ADD[13] MB_DATA[12] B28 DDRAB_SDQ12
T26 MA_ADD[14]/MA_BG[1] MA_DATA[13] B21 DDRAB_SMA14 W 30 MB_ADD[14]/MB_BG[1] MB_DATA[13] B29 DDRAB_SDQ13
T25 MA_ADD[15]/MA_ACT_L MA_DATA[14] B23 DDRAB_SMA15 V32 MB_ADD[15]/MB_ACT_L MB_DATA[14] A31 DDRAB_SDQ14
MA_DATA[15] A23 MB_DATA[15] C31 DDRAB_SDQ15
MA_DATA[16] G22 MB_DATA[16] E30 DDRAB_SDQ16

AG26 MA_BANK[0] MA_DATA[17] H22 AH32 MB_BANK[0] MB_DATA[17] E31 DDRAB_SDQ17
<12,13> DDRAB_SBS0#
AG27 MA_BANK[1] MA_DATA[18] E25 AG33 MB_BANK[1] MB_DATA[18] G33 DDRAB_SDQ18
<12,13> DDRAB_SBS1#
T29 MA_BANK[2]/MA_BG[0] MA_DATA[19] G25 W 31 MB_BANK[2]/MB_BG[0] MB_DATA[19] G32 DDRAB_SDQ19
<12,13> DDRAB_SBS2#
MA_DATA[20] J20 MB_DATA[20] C33 DDRAB_SDQ20
<12,13> DDRAB_SDM[7..0]
E19 MA_DM[0] MA_DATA[21] E22 DDRAB_SDM0 D25 MB_DM[0] MB_DATA[21] D33 DDRAB_SDQ21
D21 MA_DM[1] MA_DATA[22] H23 DDRAB_SDM1 D29 MB_DM[1] MB_DATA[22] G30 DDRAB_SDQ22
K21 MA_DM[2] MA_DATA[23] J23 DDRAB_SDM2 E33 MB_DM[2] MB_DATA[23] G31 DDRAB_SDQ23
F29 MA_DM[3] DDRAB_SDM3 J33 MB_DM[3]
AP28 MA_DM[4] MA_DATA[24] F26 DDRAB_SDM4 AR30 MB_DM[4] MB_DATA[24] J30 DDRAB_SDQ24
AV26 MA_DM[5] MA_DATA[25] E27 DDRAB_SDM5 AW 30 MB_DM[5] MB_DATA[25] J31 DDRAB_SDQ25
AR22 MA_DM[6] MA_DATA[26] J26 DDRAB_SDM6 BC30 MB_DM[6] MB_DATA[26] L33 DDRAB_SDQ26
BC22 MA_DM[7] MA_DATA[27] J27 DDRAB_SDM7 BC26 MB_DM[7] MB_DATA[27] L32 DDRAB_SDQ27
K29 MA_DM[8] MA_DATA[28] H25 N33 MB_DM[8] MB_DATA[28] H32 DDRAB_SDQ28
MA_DATA[29] E26 MB_DATA[29] H33 DDRAB_SDQ29
H19 MA_DQS_H[0] MA_DATA[30] G28 B26 MB_DQS_H[0] MB_DATA[30] L30 DDRAB_SDQ30
<12,13> DDRAB_SDQS0
G19 MA_DQS_L[0] MA_DATA[31] G29 A26 MB_DQS_L[0] MB_DATA[31] L31 DDRAB_SDQ31
<12,13> DDRAB_SDQS0#
B22 MA_DQS_H[1] B30 MB_DQS_H[1]
<12,13> DDRAB_SDQS1
A22 MA_DQS_L[1] MA_DATA[32] AN26 A30 MB_DQS_L[1] MB_DATA[32] AN31 DDRAB_SDQ32
F23 MA_DQS_H[2] MA_DATA[33] AP29 F32 MB_DQS_H[2] MB_DATA[33] AP32 DDRAB_SDQ33
<12,13> DDRAB_SDQS2
E23 MA_DQS_L[2] MA_DATA[34] AR26 E32 MB_DQS_L[2] MB_DATA[34] AT32 DDRAB_SDQ34
G27 MA_DQS_H[3] MA_DATA[35] AP24 K32 MB_DQS_H[3] MB_DATA[35] AU32 DDRAB_SDQ35
<12,13> DDRAB_SDQS3
F27 MA_DQS_L[3] MA_DATA[36] AN29 J32 MB_DQS_L[3] MB_DATA[36] AN33 DDRAB_SDQ36
C AP25 MA_DQS_H[4] MA_DATA[37] AN27 AR32 MB_DQS_H[4] MB_DATA[37] AN32 DDRAB_SDQ37 C
<12,13> DDRAB_SDQS4
AP26 MA_DQS_L[4] MA_DATA[38] AR29 AR33 MB_DQS_L[4] MB_DATA[38] AR31 DDRAB_SDQ38
AW 27 MA_DQS_H[5] MA_DATA[39] AR27 AW 32 MB_DQS_H[5] MB_DATA[39] AT33 DDRAB_SDQ39
<12,13> DDRAB_SDQS5
AV27 MA_DQS_L[5] AW 33 MB_DQS_L[5]
AV22 MA_DQS_H[6] MA_DATA[40] AU26 BA29 MB_DQS_H[6] MB_DATA[40] AU30 DDRAB_SDQ40
<12,13> DDRAB_SDQS6
AU22 MA_DQS_L[6] MA_DATA[41] AV29 AY29 MB_DQS_L[6] MB_DATA[41] AV32 DDRAB_SDQ41
BA21 MA_DQS_H[7] MA_DATA[42] AU25 BA25 MB_DQS_H[7] MB_DATA[42] BA33 DDRAB_SDQ42
<12,13> DDRAB_SDQS7
AY21 MA_DQS_L[7] MA_DATA[43] AW 25 AY25 MB_DQS_L[7] MB_DATA[43] AY32 DDRAB_SDQ43
L27 MA_DQS_H[8] MA_DATA[44] AU29 P32 MB_DQS_H[8] MB_DATA[44] AU33 DDRAB_SDQ44
L26 MA_DQS_L[8] MA_DATA[45] AU28 N32 MB_DQS_L[8] MB_DATA[45] AU31 DDRAB_SDQ45
MA_DATA[46] AW 26 MB_DATA[46] AW 31 DDRAB_SDQ46
AE25 MA_CLK_H[0] MA_DATA[47] AT25 AE33 MB_CLK_H[0] MB_DATA[47] AY33 DDRAB_SDQ47
<12> DDRA_CLK0
AE26 MA_CLK_L[0] AE32 MB_CLK_L[0]
<12> DDRA_CLK0#
AD26 MA_CLK_H[1] MA_DATA[48] AV23 AE30 MB_CLK_H[1] MB_DATA[48] BC31 DDRAB_SDQ48
<12> DDRA_CLK1
AD27 MA_CLK_L[1] MA_DATA[49] AW 23 AE31 MB_CLK_L[1] MB_DATA[49] BB30 DDRAB_SDQ49
<12> DDRA_CLK1#
AB28 MA_DATA[50] AV20 MB_DATA[50] BB28
AB29 MA_DATA[51] AW 20 AD33 MB_DATA[51] AY27 DDRAB_SDQ51
<13> DDRB_CLK0#
AB25 MA_DATA[52] AR23 AC33 MB_DATA[52] BB32 DDRAB_SDQ52
<13> DDRB_CLK1
AB26 MA_DATA[53] AT23 AC32 MB_DATA[53] BA31 DDRAB_SDQ53
<13> DDRB_CLK1#
MA_DATA[54] AR20 MB_DATA[54] BC29 DDRAB_SDQ54
N29 MA_DATA[55] AT20 T33 MB_DATA[55] BB29 DDRAB_SDQ55
<12,13> MEM_MAB_RST#
AE29 AG30
<12,13> MEM_MAB_EVENT#
MA_DATA[56] BB23 MB_DATA[56] BB27 DDRAB_SDQ56
P27 MA_DATA[57] BB22 DDRAB_CKE0 U32 MB_DATA[57] BB26 DDRAB_SDQ57
<12,13> DDRAB_CKE0
P29 MA_DATA[58] BB20 DDRAB_CKE1 U33 MB_DATA[58] BB24 DDRAB_SDQ58
<12,13> DDRAB_CKE1
MA_DATA[59] AY19 MB_DATA[59] AY23 DDRAB_SDQ59
MA_DATA[60] BA23 MB_DATA[60] BA27 DDRAB_SDQ60
MA_DATA[61] BC23 MB_DATA[61] BC27 DDRAB_SDQ61
AK27 MA_DATA[62] BC21 AL30 MB_DATA[62] BC25 DDRAB_SDQ62
<12> DDRA_ODT0
AL26 MA_DATA[63] BB21 AM32 MB_DATA[63] BB25 DDRAB_SDQ63
B <12> DDRA_ODT1 B
AH25 AJ32
<13> DDRB_ODT0
AL25 MA1_ODT[1] MA_CHECK[0] K26 AM33 MB1_ODT[1] MB_CHECK[0] N30
<13> DDRB_ODT1
MA_CHECK[1] K28 MB_CHECK[1] N31
AH26 MA0_CS_L[0] MA_CHECK[2] N26 AJ33 MB0_CS_L[0] MB_CHECK[2] R33
<12> DDRA_SCS0#
AL29 MA0_CS_L[1] MA_CHECK[3] N28 AL32 MB0_CS_L[1] MB_CHECK[3] R32
<12> DDRA_SCS1#
AH29 MA1_CS_L[0] MA_CHECK[4] J29 AJ30 MB1_CS_L[0] MB_CHECK[4] M32
<13> DDRB_SCS0#
AL28 MA1_CS_L[1] MA_CHECK[5] K25 AL33 MB1_CS_L[1] MB_CHECK[5] M33
<13> DDRB_SCS1#
MA_CHECK[6] L29 MB_CHECK[6] R30
MA_CHECK[7] N25 MB_CHECK[7] R31
AG24 MA_RAS_L/MA_RAS_L_ADD[16] AH33 MB_RAS_L/MB_RAS_L_ADD[16]
<12,13> DDRAB_SRAS#
AK29 MA_CAS_L/MA_CAS_L_ADD[15] AK32 MB_CAS_L/MB_CAS_L_ADD[15]
<12,13> DDRAB_SCAS#
AH28 MA_WE_L/MA_WE_L_ADD[14] AJ31 MB_WE_L/MB_WE_L_ADD[14]
<12,13> DDRAB_SWE#
B19 MA_VREFDQ MA_ZVDDIO_MEM_S AD29 +MB_VREFDQ A19 MB_VREFDQ MB_ZVDDIO_MEM_S AF32 MEM_MB_ZVDDIO 1 2
+1.35V
+MEM_VREF
T32 M_VREF RC4
39.2_0402_1%
FP4 REV 0.93 FP4 REV 0.93
A6@
FP4_BGA968 FP4_BGA968
A6@ +1.35V RPC1 +MEM_VREF
1 8
2 7
CLOSE TO APU
3 6 MEM_MAB_EVENT# 1 1
4 5
CC21 CC22
1K_0804_8P4R_1% 0.1U_0201_10V7K 1000P_0402_50V7K
A 2 2 A
MEMORY VREF
Vinafix.com Security Classification
Issued Date 2015/03/06
Compal Secret Data
Deciphered Date 2016/03/06 Title
Compal Electronics, Inc.
FP4 MEMORY INTERFACE
Size Document Number Rev
Custom 1.0
LA-C293P
5 4 3 2 1
A B C D E
UAPU1C +1.8VS +3VS

DP2 is not supported by
2
DISPLAY/SVI2/JTAG/TEST
CZ@ CZ@
Carrizo-L
5
UC5
B6 A9 DP_ZVSS RC6 1 2 2K_0402_1% 1 RC7
DP2: HDMI
P
DP2_TXP[0] DP_ZVSS
<22> DP2_P0 NC
A6 DP2_TXN[0] DP_AUX_ZVSS B9 DP_AUX_ZVSS RC8 1 2 150_0402_1% 4 2.2K_0402_5%
DP1: CRT Translator <22> DP2_N0 G5 2 Y
DP_BLON ENBKL_R
1
A
G
D7 G6 ENVDD_R
DP0: eDP <22> DP2_P1
C7
DP2_TXP[1]
DP2_TXN[1]
DP_DIGON
DP_VARY_BL F11 INVT_PWM_R NL17SZ07DFT2G_SC70-5
ENBKL <21,31>
<22> DP2_N1
3
SA00004BV00
HDMI for CZ only A7 0_0402_5%
For SIC, SID, ALERT_L, <22> DP2_P2 B7
DP2_TXP[2]
DP2_TXN[2] DP2_AUXP H9 ENBKL_R RC9 1 2
<22> DP2_N2 DP2_HDMI_CLK <24>
PROCHOT_L DP2_AUXN G9
DP2_HDMI_DAT <24>
D9 E9 For DP_VARY_BL, DP_BLON, DP_DIGON
Carrizo: Each are pulled <22> DP2_P3 C9
DP2_TXP[3]
DP2_TXN[3]
DP2_HPD
DP2_HDMI_HPD <24>
RC10 1 @ 2 0_0402_5%
<22> DP2_N3 Carrizo: VDD_18 level at the APU
up to VDD_18 DP1_AUXP F7
DP1_DDC_SCL <22>
A2 E7
Carrizo-L: Each are pulled <22> DP1_P0 DP1_TXP[0] DP1_AUXN
DP1_DDC_SDA <22> Carrizo-L: VDD_33 level at the APU
D
A3 DP1_TXN[0] DP1_HPD F5 EDP_HPD_APU 3 1
1 <22> DP1_N0 DP1_HPD <22> EDP_HPD <21> 1
up to VDD_33 B4 F8
@
QC2 MESS138W-G_SOT323-3
DP1_TXP[1] DP0_AUXP
<22> DP1_P1 EDP_AUXP <21>
A4 E8
G
DP1_TXN[1] DP0_AUXN
<22> DP1_N1
2
G8 EDP_HPD_APU EDP_AUXN <21> +3VALW RPC2
DP-to-CRT Translator D5 DP1_TXP[2]
DP0_HPD +1.8VS
ENBKL_R 8 1
<22> DP1_P2 +1.8VS
C5 K24 CORETYPE 1 2 ENVDD_R 7 2
or DP Switch <22> DP1_N2 DP1_TXN[2] RSVD_1
E15 TEMPIN0
@
EDP_HPD_APU 6 3
TEMPIN0 TPC2 RC11 +3VS
A5 DP1_TXP[3] TEMPIN1 E14 TEMPIN1 TPC3 100K_0402_5% CZ@ 5 4
<22> DP1_P3
5
B5 DP1_TXN[3] TEMPIN2 E12 TEMPIN2 UC4
<22> DP1_N3 TPC4
F14 TEMPINRETURN 1 100K_0804_8P4R_5%
P
TEMPINRETURN TPC5
E2 TEST410 AK24 APU_TEST410 NC 4
DP0_TXP[0] TPC6
<21> EDP_TXP0 Y
2
E1 DP0_TXN[0] TEST411 AL24 APU_TEST411 2 CZ@
<21> EDP_TXN0 TPC7 A
G
TEST4 P24 APU_TEST4 TPC8 RC14
E3 DP0_TXP[1] TEST5 N24 APU_TEST5 NL17SZ07DFT2G_SC70-5 4.7K_0402_5%
<21> EDP_TXP1 TPC9
3
E4 DP0_TXN[1] TEST6 AN24 APU_TEST6 TPC10 SA00004BV00
<21> EDP_TXN1
TEST9 AB8 APU_TEST9 TPC11
1
D1 DP0_TXP[2] TEST10 Y9 APU_TEST10 CZL@
+1.8VS TPC12
D2 DP0_TXN[2] TEST14 B10 APU_TEST14 ENVDD_R RC13 1 2 0_0402_5%
D11 SOC_ENVDD <21,31>
@ RPC3 TEST15 APU_TEST15 TPC13
8 1 APU_SVT C1 DP0_TXP[3] TEST16 A10 APU_TEST16
7 2 GFX_SVT Place resistor(0ohm) for SVT in PWR side B1 DP0_TXN[3] TEST17 C11 APU_TEST17
6 3 GFX_SVC TEST11 B11 APU_TEST11
5 4 APU_SVC APU_SVT C15 SVT0 TEST18 A14 APU_TEST18 INVT_PWM_R RC15 1 CZL@ 2 0_0402_5% INVT_PWM
<42> APU_SVT 1 2 0_0402_5% D17 B14 INVT_PWM <21>
RC110 APU_SVC_R SVC0 TEST19 APU_TEST19
<42> APU_SVC
1K_0804_8P4R_5% RC16 1 2 0_0402_5% APU_SVD_R D19 SVD0
<42> APU_SVD
2
+3VS
GFX_SVT B15 SVT1 TEST28_H A13 APU_TEST28_H RC17
<44> GFX_SVT TPC14
RC18 1 CZ@ 2 0_0402_5% GFX_SVC_R B16 SVC1 TEST28_L B13 APU_TEST28_L TPC15 10K_0402_5%
<44> GFX_SVC
2
RC19 1 CZ@ 2 0_0402_5% GFX_SVD_R A18 SVD1 TEST31 P26 APU_TEST31
<44> GFX_SVD TPC16 +1.8VS
DP_STEREOSYNC/TEST36 E11 DP_STEREOSYNC CZ@
1
APU_SIC B18 SIC TEST37 A17 APU_TEST37 RC20
RC108 2 @ 1 APU_SVD APU_SID C17 SID CZ@ 4.7K_0402_5%
5
1K_0402_5% UC2
1
RC115 2 @ 1 GFX_SVD RC21 1 2 300_0402_5% APU_RST# D15 1
P
+1.8VS RESET_L
1K_0402_5% RC22 1 2 300_0402_5% APU_PWRGD C19 NC 4 INVT_PWM
+1.8VS PWROK
INVT_PWM_R 2 Y
<42,44> APU_PWRGD A
G
A15 PROCHOT_L
<31> H_PROCHOT# TPC29
2 APU_ALERT# B17 ALERT_L TPC28 NL17SZ07DFT2G_SC70-5 2
3
+1.8VS +3VS VDDCR_GFX_SENSE H11 SA00004BV00
APU_GFX_SEN_H <44>
APU_TDI H15 TDI VDDCR_NB_SENSE J12
APU_VDDNB_SEN <42>
RC116
RC117
APU_TDO H14 TDO VDDCR_CPU_SENSE G12

D13 AY18 APU_VDD_SEN <42>
APU_TCK TCK VDDP_SENSE VDDP_SENSE TPC21 TPC27
APU_TMS G15 TMS
APU_RST# APU_TRST# J14 TRST_L VSS_SENSE H12
APU_VDD_RUN_FB_L <42>
2
+1.8VS +3VS APU_DBRDY C13 DBRDY

RC25
CZ@ APU_PWRGD APU_DBREQ# A11 DBREQ_L

RC26
CZL@
2
RC118 1 @ 2 0_0402_5%
APU_GFX_SEN_L <44>
1
1
1K_0402_5%
CZ@ CZL@ CC126 CC127 FP4 REV 0.93

1K_0402_5%
ESDP@ ESDP@ FP4_BGA968

33P_0402_50V8J 33P_0402_50V8J
1
2
0_0402_5%
0_0402_5%
H_PROCHOT# A6@
RPC5 @ RPC6
8 1 APU_SID 1
7 2 APU_ALERT# APU_TEST11 7 2 For DP_STEREOSYNC/TEST36
6 3 APU_SIC +1.8VS APU_TEST16 6 3
5 4 APU_TEST14 5 4 Carrizo: Pulled up to VDD_18
1K_0804_8P4R_5% 1K_0804_8P4R_5%
Carrizo-L: Pulled up to VDD_33
2
G
CZ@
+3VS EC_SMB_CK2 1 3 APU_SIC DP_STEREOSYNC 1 CZ@ 2
+1.8VS RC27
+1.8VS CZ
D
MESS138W-G_SOT323-3 1K_0402_5%
QC4 APU_TEST37 1 @ 2 1 CZL@ 2 +3VS CZ-L
2
RC109 1 CZ@ 2 2.2K_0402_5% EC_SMB_CK2

G
RC28 RC29
RC111 1 CZ@ 2 2.2K_0402_5% EC_SMB_DA2 CZ@ 1K_0402_5% 1K_0402_5%
EC_SMB_DA2 1 3 APU_SID 1 @ 2 1 @ 2
RC30 RC31
D
1K_0402_5% 1K_0402_5%
QC5 MESS138W-G_SOT323-3
3 3
1 CZL@ 2 APU_SIC
<15,23,31,32> EC_SMB_CK2
RC32
0_0402_5%
1 CZL@ 2 APU_SID
<15,23,31,32> EC_SMB_DA2
RC33
0_0402_5%
+1.8VS
HDT+
JHDT1 @
1 2 APU_TCK
1 2 +1.8VS
3 4 APU_TMS RPC8
3 4 APU_DBREQ# 1 8
5 6 APU_TDI APU_TDI 2 7
5 6 APU_TCK 3 6
7 8 APU_TDO APU_TMS 4 5
@ 7 8
APU_TRST# 1 2 APU_TRST#_R 9 10 APU_PWRGD 1K_0804_8P4R_5%
RC34 33_0402_5% 9 10
@ RPC9 HDT_P11 11 12 APU_RST# +1.8VS
1 8 11 12 RPC10
2 7 HDT_P13 13 14 APU_DBRDY 1 8
3 6 13 14 APU_TRST# 2 7
4 5 HDT_P15 15 16 APU_DBREQ# APU_TEST18 3 6
15 16 APU_TEST19 4 5
10K_0804_8P4R_5% 17 18 APU_TEST19
17 18 1K_0804_8P4R_5%
19 20 APU_TEST18 APU_TRST# 1 2
19 20
@ CC23
4 0.01U_0402_16V7K 4
SAMTE_ASP-136446-07-B

FP4 DISP/MISC/HDT
C 1.0
LA-C293P
A B C D E
A B C D E
1 2 UAPU1D
CC24 150P_0402_50V8J +3VS
ACPI/SD/AZ/GPIO/RTC/I2C/UART/MISC
RC36 1 2 33_0402_5% LPC_RST_A# BB12 LPC_RST_L SD0_WP/EGPIO101 BB2
<31,32> LPC_RST#
2
RC38 1 2 33_0402_5%APU_PCIE_RST#_R AN7 PCIE_RST_L/EGPIO26 SD0_PWR_CTRL/AGPIO102 BB5
<14,25,26,27> APU_PCIE_RST#
SD0_CD/AGPIO25 BC2 RC39
1 2 EC_RSMRST#_R AE4 RSMRST_L SD0_CLK/EGPIO95 BB4 UMA@ 10K_0402_5%
CC25 150P_0402_50V8J SD0_CMD/EGPIO96 AY5
AE1 PWR_BTN_L/AGPIO0 UMA: HIGH
<31> PBTN_OUT#
1
PW R_GOOD_APU BC9 PWR_GOOD SD no used can NC
SYS_RST# AF2 SYS_RESET_L/AGPIO1 DIS_ID# DIS: LOW
APU_PCIE_W AKE# AG2 WAKE_L/AGPIO2 SD0_DATA0/EGPIO97 BC3
<27> APU_PCIE_W AKE#
2
SD0_DATA1/EGPIO98 BA3
1 AK7 SLP_S3_L SD0_DATA2/EGPIO99 BC5 RC40 1
<31> PM_SLP_S3#
AH5 SLP_S5_L SD0_DATA3/EGPIO100 BA5 PX@ 10K_0402_5%
<31> PM_SLP_S5#
SD0_LED/EGPIO93 BB6 DGPU_PE_GPIO1 TPC18
S0A3_GPIO AE8 S0A3_GPIO/AGPIO10
1
RPC15 AH8 S5_MUX_CTRL/EGPIO42 SCL0/I2C2_SCL/EGPIO113 BA15 APU_SCLK0
<10> S5_MUX_CTRL APU_SCLK0 <12,13>
1 8 SDA0/I2C2_SDA/EGPIO114 AY17 APU_SDATA0
APU_SDATA0 <12,13>
2 7 APU_TEST0 AH6 TEST0
3 6 APU_TEST1 AK8 TEST1/TMS SCL1/I2C3_SCL/AGPIO19 AG5APU_SCLK1
4 5 APU_TEST2 AE3 TEST2 SDA1/I2C3_SDA/AGPIO20 AG4 APU_SDATA1
15K_0804_8P4R_5% AY15 ESPI_RESET_L/KBRST_L/AGPIO129

<31> KBRST# +3VALW
BC19 GA20IN/AGPIO126
<31> GATEA20
AD7 LPC_PME_L/AGPIO22 AGPIO3 AL5 MEM_VOLT_SEL1 NOZODD@
<31> EC_SCI#
BB13 LPC_SMI_L/AGPIO86 AGPIO4 AL6 MEM_VOLT_SEL0 ODD_DA#_APU 10K_0402_5% 2 1 RC44
AGPIO5 AJ1 MEM_VOLT_SEL0 10K_0402_5% 2 CZL@ 1 RC46
ODD_DA#_APU <29>
AG3 AC_PRES/USB_OC4_L/IR_RX0/AGPIO23 AGPIO6/LDT_RST AJ3 AGPIO8 10K_0402_5% 2 CZ@ 1 RC47
<29> ODD_PLUGIN#
AD5 IR_TX0/USB_OC5_L/AGPIO13 AGPIO7/LDT_PWROK AH1
AL8 IR_TX1/USB_OC6_L/AGPIO14 AGPIO8 AJ4 AGPIO8 +3VS
<27> BT_OFF#
AN8 IR_RX1/AGPIO15 AGPIO9 AK5 EC_LID_OUT# TPC30
AE2 IR_LED_L/LLB_L/AGPIO12 VDDGFX_PD/AGPIO39 AD8 VDDGFX_PD BT_OFF#_AGPIO64 10K_0402_5% 2 1 RC48
VDDGFX_PD <44>
BC15 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92 AGPIO40 AG8 APU_VRM_GFX_PW RGD TCM_ID 10K_0402_5% 2 TCM@ 1 RC49
<25> CR_CLKREQ# APU_VRM_GFX_PW RGD <44>
BB17 CLK_REQ1_L/AGPIO115 AGPIO64 AW15 10K_0402_5% 2 1 RC50
<26> LAN_CLKREQ# BT_OFF#_AGPIO64 <27>
BC17 CLK_REQ2_L/AGPIO116 AGPIO65 AU15 NOTCM@
<27> W LAN_CLKREQ#
BB18 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131 DGPU_PW R_EN 10K_0402_5% 2 1 RC121
<29> ODD_EN
RC51 1 @ 2 0_0402_5% VGA_CLKREQ#_R BB16 CLK_REQG_L/OSCIN/EGPIO132 AGPIO66/SHUTDOWN_L AT15 TCM_ID
<15> VGA_CLKREQ#
AH9 USB_OC0_L/TRST_L/AGPIO16 AGPIO68/SGPIO_CLK AU12 CR_CLKREQ# RC52 1 @ 2 10K_0402_5%
<30> USB_OC0#
AG1 USB_OC1_L/TDI/AGPIO17 AGPIO69/SGPIO_LOAD AT14 DIS_ID# W LAN_CLKREQ# RC53 1 @ 2 10K_0402_5%
<30> USB_OC1#
AH2 USB_OC2_L/TCK/AGPIO18 AGPIO71/SGPIO_DATAOUT AR14 AND Gate, as before LAN_CLKREQ# RC54 1 @ 2 10K_0402_5%
PXS_RST# <14>
AL9 USB_OC3_L/TDO/AGPIO24 AGPIO72/SGPIO_DATAIN BC13 VGA_CLKREQ#_R RC55 1 UMA@ 2 10K_0402_5%
DGPU_PW R_EN <16,31,45>
2 2
HDA_BITCLK AU6 BA17 RC1201 PX@ 2 10K_0402_5%
APU_SPKR <28>
HDA_SDIN0 AR8
<28> HDA_SDIN0
HDA_SDIN1 AP6 AN5 AGPIO11
EMIP@RPC11
EMIP@RPC11 HDA_SDIN2 AR5
1 8 HDA_RST# AU9 BB14 RC101 1 @ 2 0_0402_5%
<28> HDA_RST#_AUDIO
2 7 HDA_SYNC AT9
AZ_RST_L/I2S_LR_MIC
AZ_SYNC/I2S_BCLK_PLAYBACK
GENINT1_L/AGPIO89
GENINT2_L/AGPIO90 BA19
CZ only for Secure boot enable before PR sample
<28> HDA_SYNC_AUDIO DGPU_PW ROK <45>
3 6 HDA_SDOUT AR7 AZ_SDOUT/I2S_DATA_PLAYBACK
<28> HDA_SDOUT_AUDIO
4 5HDA_BITCLK RPC16 CZ@ FANIN0/AGPIO84 BC18
<28> HDA_BITCLK_AUDIO
1 8 I2C0_SCLBB10 I2C0_SCL/EGPIO145 FANOUT0/AGPIO85 BB19
RPC17 33_0804_8P4R_5% 2 7 I2C0_SDA BB9 I2C0_SDA/EGPIO146
1 8 3 6 I2C1_SCL BB7 I2C1_SCL/EGPIO147 UART0_CTS_L/EGPIO135 AY9
2 7 4 5 I2C1_SDA BC7 I2C1_SDA/EGPIO148 UART0_RXD/EGPIO136 AW8
3 6 UART0_RTS_L/EGPIO137 AV5 UART no used can NC
4 5 UART0_TXD/EGPIO138 AV8
UART0_INTR/AGPIO139 AW9
1K_0804_8P4R_1%
CZ@ 32K_X1 AT1 X32K_X1 UART1_CTS_L/BT_I2S_BCLK/EGPIO140AV11
HDA_SDIN1 RC122 1 2 10K_0402_5% AU7
AT11
CZ@ AR11
HDA_SDIN2 RC123 1 2 10K_0402_5% 32K_X2 AT2 AP9
FP4 REV 0.93
FP4_BGA968
+3VALW
RC60 1 2 10K_0402_5% APU_PCIE_W AKE# A6@ MEM_VOLT_SEL1/AGPIO3 RTC_CLK BLINK/AGPIO11 SYS_RST#

RC61 1 2 100K_0402_5% USB_OC0# LPC_CLK0_EC LPC_CLK1 LPC_FRAME#
RC99 1 2 100K_0402_5% USB_OC1# <INT PU> <INT PU> <INT PU> <INT PU>
3 3
CZL CZ LDT_RST#/PG
BOOT FAIL CLKGEN SPI ROM COIN BATT OUTPUT TO NORMAL
+3VS H TIMER
ENABLED
ENABLE
(DEFAULT)
(DEFAULT) 1.8V SPI ROM ENHANCED RESET
LOGIC (quick S5) ON BOARD
(DEFAULT)
APU
(DEFAULT)
RESET MODE
(DEFAULT)
RC62 1 2 2.2K_0402_5% APU_SCLK0
RC63 1 2 2.2K_0402_5% APU_SDATA0 BOOT FAIL
RC64 1 2 10K_0402_5% GATEA20 TIMER CLKGEN TRADITION AL COIN BATT OUTPUT SHORT RST
+3VALW
RC65 1 2 10K_0402_5% KBRST#
+1.8VALW
+1.8VS
+3VS
L DISABLED
(DEFAULT)
DISABLED LPC ROM 3.3V SPI ROM RESET LOGIC NOT ON
BOARD
TO PADS MODE
RC66 1 CZL@ 2 10K_0402_5% APU_SCLK1 +3VS +3VALW

RC67 1 CZL@ 2 10K_0402_5% APU_SDATA1
2
1
RC37 1 CZL@ 2 10K_0402_5% S0A3_GPIO RC68 CZL@ CZ@ @ CZ@
47K_0402_5% RC69 RC100 4.7K_0402_5% RC70 RC71 RC72 RC73 RC74 RC75 RC76
SCS00005C00 4.7K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
DC1
1
2
1 2EC_RSMRST#_R
<31> EC_RSMRST# <31,32,9> LPC_FRAME#
<31,32,9> LPC_CLK0_EC
RB751V-40TE17_SOD323-2
<9> LPC_CLK1
MEM_VOLT_SEL1
32.768KMHz CRYSTAL 32K_X1 1
DC2
SCS00005C00
2PW R_GOOD_APU
RTC_CLK
SYS_RST#
<31> SYS_PW RGD_EC
1 AGPIO11
1
YC1 RB751V-40TE17_SOD323-2 1
1
1
CC26
4 32.768KHZ_12.5P_1TJF125DP1A000D 1U_0402_6.3V6K CC27 @ @ CZL@ @ @ @ 4
2 1U_0402_6.3V6K RC77 RC78 RC79 RC80 RC81 RC82 RC83
2
2 1 32K_X2 2 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5%

RC84
2
2
20M_0402_5% SJ10000HW 00
1 1
CC28 CC29 Security Classification Compal Secret Data Compal Electronics, Inc.
18P_0402_50V8J 18P_0402_50V8J 2015/03/06 2016/03/06 Title
2 2 Issued Date Deciphered Date
FP4 GPIO/AZ/MISC/STRAPS
Custom 1.0
LA-C293P
A B C D E
A B C D E
UAPU1E
AU3 SATA_TX0P
CLK/SATA/USB/SPI/LPC
USBCLK/25M_48M_OSC AP8
48MHz CRYSTAL
<29> SATA_ATX_DRX_P0
AU4 SATA_TX0N 48M_X2
<29> SATA_ATX_DRX_N0 AP5 USB_ZVSS
USB_ZVSS RC85 1 2 11.8K_0402_1%
HDD AV1 SATA_RX0N 1 RC86 2 48M_X1
<29> SATA_DTX_C_ARX_N0 AV2 AR2
SATA_RX0P USB_HSD0P 1M_0402_5%
<29> SATA_DTX_C_ARX_P0 AR1 USB20_P0 <30>
USB_HSD0N
USB20_N0 <30> Right USB port
AY2 SATA_TX1P
<29> SATA_ATX_DRX_P1 AY1 AR3
SATA_TX1N USB_HSD1P
1 <29> SATA_ATX_DRX_N1 USB20_P1 <21> 1
ODD AR4 2 1
AW4
USB_HSD1N
USB20_N1 <21> Touch Screen (reserved) 2 1
SATA_RX1N
<29> SATA_DTX_C_ARX_N1 AW3 AN2
SATA_RX1P USB_HSD2P
<29> SATA_DTX_C_ARX_P1 USB20_P2 <30>
USB_HSD2N AN1 Finger Print
2 1 AW1 USB20_N2 <30>
RC87 1K_0402_1% SATA_ZVSS SATA_ZVSS
+0.95VS RC88 2 1 1K_0402_1% SATA_ZVDD AW2 SATA_ZVDDP USB_HSD3P AN3 YC2

2 USB20_P3 <21>
+3VS RC89 CZ@ 1 10K_0402_5% DEVSLP0 AT17 DEVSLP[0]/EGPIO67 USB_HSD3N AN4 CAMERA
2 USB20_N3 <21>
RC90 CZ@ 1 10K_0402_5% DEVSLP1 AT12 DEVSLP[1]/EGPIO70
SATALED# BB15 SATA_ACT_L/AGPIO130 USB_HSD4P AM1
<33> SATALED# AM2
USB_HSD4N
AU2 SATA_X1 3 4
AL2 3 4
USB_HSD5P
USB20_P5 <27>
1
USB_HSD5N AL1 WLAN/BT combo
USB20_N5 <27>
CC30 CC31
AU1 SATA_X2 USB_HSD6P AL3 5.6P_0402_50V8D 5.6P_0402_50V8D
USB30_P6 <30>
2
USB_HSD6N AL4 MB USB3.0 port0
USB30_N6 <30>
U4 GFX_CLKP USB_HSD7P AK2 Part Number = SJ10000AF00
<14> CLK_PCIE_GPU USB30_P7 <30>
2 CZ@ 1 APU_SPI_CS2# U3 GFX_CLKN USB_HSD7N AJ2 MB USB3.0 port1 48MHZ_8PF_X3S048000D81H-W
<14> CLK_PCIE_GPU# USB30_N7 <30>
RC91
10K_0402_5% U1 GPP_CLK0P
2 <25> CLK_PCIE_CR
CZ@ 1 APU_SPI_TPMCS# U2 GPP_CLK0N
<25> CLK_PCIE_CR#
RC92
10K_0402_5% W4 GPP_CLK1P
2 <26> CLK_PCIE_LAN W3
2
GPP_CLK1N
<26> CLK_PCIE_LAN#
W1 GPP_CLK2P
<27> CLK_PCIE_WLAN W2 GPP_CLK2N
<27> CLK_PCIE_WLAN#
Y2 GPP_CLK3P
Y1 GPP_CLK3N
RPC13
1 8 APU_SPI_AISO_U BC10
<31> EC_SPI_AISO
2 7 APU_SPI_CS1#_U USB_SS_ZVSS AD2 USBSS_ZVSS RC93 1 2 1K_0402_1%
<31> EC_SPI_CS1# 3 6 AD1 USBSS_ZVDD RC96 1 2 1K_0402_1%
APU_SPI_CLK_U USB_SS_ZVDDP +0.95VALW
<31> EC_SPI_CLK
4 5 APU_SPI_AOSI_U 48M_X1 T2 X48M_X1
<31> EC_SPI_AOSI AA3
USB_SS_0TXP
33_0804_8P4R_5% USB_SS_0TXN AA4
EMIP@
48M_X2 T1 X48M_X2 USB_SS_0RXP W9
USB_SS_0RXN W8
APU_SPI_AOSI_U 1 8 APU_SPI_AOSI 2 EMIP@ 1 LPC_CLK0_APU AW14 USB_SS_1TXP AA2

<31,32,8> LPC_CLK0_EC
APU_SPI_CLK_U 2 7 APU_SPI_CLK 2 EMIP@ 1 LPC_CLK1_APU AY13 USB_SS_1TXN AA1
3 6 <8> LPC_CLK1
APU_SPI_CS1#_U APU_SPI_CS1# RC98 33_0402_5%
APU_SPI_AISO_U 4 5 APU_SPI_AISO BB11 USB_SS_1RXP W5
<31,32> LPC_AD0 BA11 W6
USB_SS_1RXN
<31,32> LPC_AD1 AY11
3 33_0804_8P4R_5% 3
<31,32> LPC_AD2
EMIP@ BA13 USB_SS_2TXP AC1
<31,32> LPC_AD3 AV14 AC2 USB30_MTX_C_DRX_P2 <30>
USB_SS_2TXN
<31,32,8> LPC_FRAME# USB30_MTX_C_DRX_N2 <30>
BA1
BC14 USB_SS_2RXP Y6
<31,32> SERIRQ BC11 Y7 USB30_MRX_DTX_P2 <30>
RPC12 USB_SS_2RXN
USB30_MRX_DTX_N2 <30>
TPC19 LPC_PD# AE9
APU_SPI_HOLD# 1 8 USB_SS_3TXP AC4
USB30_MTX_C_DRX_P3 <30>
APU_SPI_CS1#_U2 7 +SPI_VCC USB_SS_3TXN AC3
3 6 USB30_MTX_C_DRX_N3 <30>
APU_SPI_WP# APU_SPI_CLK BC6 SPI_CLK/ESPI_CLK/EGPIO117
4 5 APU_SPI_CS1# BB8 SPI_CS1_L/EGPIO118 USB_SS_3RXP AB5
USB30_MRX_DTX_P3 <30>
TPC20 APU_SPI_CS2# AW7 SPI_CS2_L/ESPI_CS_L/EGPIO119 USB_SS_3RXN AB6
USB30_MRX_DTX_N3 <30>
10K_0804_8P4R_5% APU_SPI_AISO BA9 SPI_DI/ESPI_DATA/EGPIO120
APU_SPI_AOSI AY7 SPI_DO/EGPIO121
APU_SPI_WP# AW11 SPI_WP_L/EGPIO122
APU_SPI_HOLD# BA7
+1.8VS +3VALW 8MB SPI ROM APU_SPI_TPMCS# AW12
SPI_HOLD_L/EGPIO133
SPI_TPM_CS_L/AGPIO76
FP4 REV 0.93

1 CZL@ 2
RC103 0_0402_5% UC1 CZ@ FP4_BGA968
1 2
RC104 0_0402_5%
CZ@ A6@
4 UC1 CZL@ 4
APU_SPI_CS1#_U1 8 +SPI_VCC SPI ROM
APU_SPI_AISO_U 2 /CS VCC 7 APU_SPI_HOLD# Part Number = SA00007JS00
APU_SPI_WP# 3 DO(IO1) /HOLD(IO3) 6 APU_SPI_CLK_U GD25LQ64CSIGR_SO8
4 /WP(IO2)
GND
CLK
DI(IO0)
5 APU_SPI_AOSI_U 1
@ 2015/03/06 2016/03/06 Title
W25Q64FVSSIQ_SO8 CC32
Issued Date Deciphered Date
0.1U_0201_10V7K THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP4 SATA/CLK/USB/SPI
APU_SPI_CLK_U 1 2 1 2 2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
RC105 EMIU@ CC33 EMIU@ B 1.0
10_0402_5% 10P_0402_50V8J
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-C293P
close to UC1 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D E
A B C D E
+APU_CORE
CC56
CC57
CC58
CC52
CC59
CC60
CC61
CC62
CC63
+1.35V
1 1 1 1 1 1 1 1 1
CC34
CC35
CC36
CC37
CC38
CC39
CC40
CC41
CC42
CC43
CC44
CC45
CC46
CC47
CC48
CC49
CC50
CC51
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
180P_0402_50V8J
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
2 2 2 2 2 2 2 2 2
22U_0603_6.3V6M
0.1U_0201_10V7K
0.1U_0201_10V7K
22U_0603_6.3V6M
0.1U_0201_10V7K
0.1U_0201_10V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
0.1U_0201_10V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
180P_0402_50V8J
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 Under APU UAPU1F 1
POWER +APU_CORE_NB
+1.35V +1.35V P25 VDDIO_MEM_S3_1 VDDCR_CPU_1 U8 +APU_CORE
CC74
CC75
CC76
CC77
CC78
CC79
CC80
CC81
CC82
P28 VDDIO_MEM_S3_2 VDDCR_CPU_2 W7
CC53
CC54
CC64
CC65
CC55
CC66
T24 VDDIO_MEM_S3_3 VDDCR_CPU_3 W12 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 T27 VDDIO_MEM_S3_4 VDDCR_CPU_4 W15
U25 VDDIO_MEM_S3_5 VDDCR_CPU_5 W18
180P_0402_50V8J
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
U28 W21
VDDIO_MEM_S3_6 VDDCR_CPU_6
2 2 2 2 2 2 2 2 2 Under APU
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
180P_0402_50V8J
180P_0402_50V8J
V30 VDDIO_MEM_S3_7 VDDCR_CPU_7 Y8
2 2 2 2 2 2 V33 VDDIO_MEM_S3_8 VDDCR_CPU_8 Y10
W24 VDDIO_MEM_S3_9 VDDCR_CPU_9 Y13
W27 VDDIO_MEM_S3_10 VDDCR_CPU_10 Y16
Y25 VDDIO_MEM_S3_11 VDDCR_CPU_11 Y19
Y28 VDDIO_MEM_S3_12 VDDCR_CPU_12 Y22
Y30 VDDIO_MEM_S3_13 VDDCR_CPU_13 AB7
AB24 VDDIO_MEM_S3_14 VDDCR_CPU_14 AB9
AB27 AB12
DIMMS/GND AB30
VDDIO_MEM_S3_15
VDDIO_MEM_S3_16
VDDCR_CPU_15
VDDCR_CPU_16 AB15
AB33 VDDIO_MEM_S3_17 VDDCR_CPU_17 AB18
AD25 VDDIO_MEM_S3_18 VDDCR_CPU_18 AB21 CZ@ CZ@
AD28 VDDIO_MEM_S3_19 VDDCR_CPU_19 AD6 +APU_CORE_NB QC8 QC9
AD30 VDDIO_MEM_S3_20 VDDCR_CPU_20 AD10 AO3416L_SOT23-3 AO3416L_SOT23-3 +APU_FCH_ALW
AE24 AD13
FOR DEBUG ONLY VDDIO_MEM_S3_21 VDDCR_CPU_21
D
AE27 AD16 CZ@ 1 3 +APU_CORE_NB_Q 3 1
S
VDDIO_MEM_S3_22 VDDCR_CPU_22 1
AF30 VDDIO_MEM_S3_23 VDDCR_CPU_23 AD19 CC120 1 1
22U_0603_6.3V6M
22U_0603_6.3V6M
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
1
RC106 1 2 0_0402_5% AF33 AD22 4.7U_0603_6.3V6K
CZ@ CC123
CZ@ CC124
+3VS +3VS_APU +1.8VS +1.5VS VDDIO_MEM_S3_24 VDDCR_CPU_24
AG25 AE7
CZ@ CC121
CZ@ CC122
G
G
VDDIO_MEM_S3_25 VDDCR_CPU_25
2
2
CC67
CC68
CC69
CC70
AG28 VDDIO_MEM_S3_26 VDDCR_CPU_26 AE12
2
2 2
CC71
CC72
CC73
1 1 1 1 AH24 VDDIO_MEM_S3_27 VDDCR_CPU_42 AK9
1 1 1 AH27 VDDIO_MEM_S3_28 VDDCR_CPU_31 AG10
@ AH30 VDDIO_MEM_S3_29 VDDCR_CPU_43 AK10 CORE_NB_GATE
10U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
0.22U_0402_10V6K
AK25 VDDIO_MEM_S3_30 VDDCR_CPU_32 AG13

2 2 2 2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
AK28 VDDIO_MEM_S3_31 VDDCR_CPU_44 AK13
2 2 2 AK30 VDDIO_MEM_S3_32 VDDCR_CPU_33 AG16
AK33 VDDIO_MEM_S3_33 VDDCR_CPU_45 AK16 +0.775VALW CZ@ CZ@
AL27 VDDIO_MEM_S3_34 VDDCR_CPU_34 AG19 QC10 QC11
AM30 VDDIO_MEM_S3_35 VDDCR_CPU_46 AK19 AO3416L_SOT23-3 AO3416L_SOT23-3
2 VDDCR_CPU_35 AG22 2
D
AR19 AK22 CZ@ 1 3 +0.775VALW_Q 3 1
S
+1.5VS VDDIO_AUDIO VDDCR_CPU_47 1
VDDCR_CPU_36 AH7 CC128
AE6 VDDP_GFX_2 VDDCR_CPU_28 AE18 4.7U_0603_6.3V6K 1
+0.95VS_APU_GFX
AE5 AE21 CC125
G
G
VDDP_GFX_1 VDDCR_CPU_29
2
VDDCR_CPU_40 AH21 2 4.7U_0603_6.3V6K
AP19 VDD_33_1 VDDCR_CPU_30 AG6 CZ@
+3VALW +1.8VALW +0.95VALW +3VS_APU 2
AP21 VDD_33_2 VDDCR_CPU_37 AH12
CC83
CC84
CC85
CC86
CC87
CC88
VDDCR_CPU_49 AN6 0.775VALW_GATE

1 1 1 1 1 AP16 VDD_18_1 VDDCR_CPU_38 AH15
+1.8VS
AP18 VDD_18_2 VDDCR_CPU_39 AH18
VDDCR_CPU_48 AL7
10U_0603_6.3V6M
0.22U_0402_10V6K
10U_0603_6.3V6M
0.22U_0402_10V6K
10U_0603_6.3V6M
0.22U_0402_10V6K
+1.8VALW AP10 VDD_18_S5_1 VDDCR_CPU_41 AK6

2 2 AR9 VDD_18_S5_2 VDDCR_CPU_27 AE15 +5VALW
AP15 VDD_33_S5_1
+APU_CORE_NB CZ@ +5VALW
+3VALW
AR15 VDD_33_S5_2 VDDCR_GFX_14 L8
+APU_GFX
8
VDDCR_GFX_15 L13
AN12 L16
P
+0.95VALW VDDP_S5_1 VDDCR_GFX_16
AP12 VDDP_S5_2 VDDCR_GFX_17 L19
VDDCR_GFX_18 L22
-
G
AP13 VDDCR_FCH_S5_1 VDDCR_GFX_19 N7 +5VALW
+APU_FCH_ALW AR12 VDDCR_FCH_S5_2 VDDCR_GFX_20 N12
4
N15 CZ@
+0.95VALW/+0.95VS OF APU VDDCR_GFX_21
8
AW19 VDDP_6 VDDCR_GFX_22 N18 UC1103B
+0.95VS
AU17 N21 5 LM393DR_SO8
P
VDDP_1 VDDCR_GFX_23
AU19 P8 + 7 0.775VALW_GATE RC127 1 CZ@ 2 1K_0402_1%
VDD_095 VDD_095_GFX AV17
VDDP_2
VDDP_3
VDDCR_GFX_24
VDDCR_GFX_25 P13 6 O
-
G
+0.95VS +0.95VS_APU_GFX AV19 VDDP_4 VDDCR_GFX_26 P16
LC1 AW17 VDDP_5 VDDCR_GFX_27 P19
4
2 1 VDDCR_GFX_28 P22
FBMA-L11-201209-121LMA50T_0805 AL12 VDDCR_NB_1 VDDCR_GFX_29 T7
+APU_CORE_NB
CC99
CC100
CC101
CC102
CC94
CC95
CC103
CC104
CC96
CC97
AL13 VDDCR_NB_2 VDDCR_GFX_1 F12

1 1 1 1 1 1 1 1 1 1 AL15 VDDCR_NB_3 VDDCR_GFX_2 F15
AL18 VDDCR_NB_4 VDDCR_GFX_3 G11
AL21 VDDCR_NB_5 VDDCR_GFX_4 G14
+3VALW +5VALW +0.775VALW
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.22U_0402_10V6K
180P_0402_50V8J
10U_0603_6.3V6M
1U_0402_6.3V6K
AN13 VDDCR_NB_6 VDDCR_GFX_5 J8

2 2 2 2 2 2 2 2 2 2 AN16 VDDCR_NB_7 VDDCR_GFX_6 J9
3 3
AN19 VDDCR_NB_8 VDDCR_GFX_7 J11
AN22 VDDCR_NB_9 VDDCR_GFX_8 K7
2
VDDCR_GFX_9 K12
K13 RC113
RTC OF APU VDDCR_GFX_10
2
+RTCBATT_R +RTCBATT_R AR17 VDDBT_RTC_G VDDCR_GFX_11 K15 CZ@
6
VDDCR_GFX_12 K16 RC114 100K_0402_5%
CC98
VDDCR_GFX_30 T12 CZ@ QC7A
1
1 VDDCR_GFX_31 T15 100K_0402_5% ME2N7002D1KW-G 2N_SOT363-6
VDDCR_GFX_32 T18 2
CZ@
1
@ VDDCR_GFX_33 T21
3
0.22U_0402_10V6K
PX@ PX@ VDDCR_GFX_34 U13

+0.95VS_APU_GFX
1
2 VDDCR_GFX_35 U16 QC7B 0.775MOS
CC105
CC106
VDDCR_GFX_36 U19 ME2N7002D1KW-G 2N_SOT363-6

1 1 VDDCR_GFX_37 U22 5
<8> S5_MUX_CTRL CZ@
2
VDDCR_GFX_13 K19
RC112
4
10U_0603_6.3V6M
0.22U_0402_10V6K
FP4 REV 0.93 CZ@

2 2 FP4_BGA968 100K_0402_5%
1
A6@
+RTCBATT_3V
RTC OF APU VDDBT_RTC_G UC3
Close AE6, AE5 VDDBT_RTC_G +RTCBATT 3
+RTCBATT Vout 1
2 Vin
0.1U_0603_25V7K
+RTCBATT_R RC107 1 2 1K_0402_1% GND
W=20mils
680P_0603_50VK
1
CC107
2
1
CZ@
CZ@
CZ@
CZ@
CZ@
CZ@
CZ@
CZ@
CZ@
CZ@
AP2138N-1.5TRG1_SOT23-3
CC108
1
+APU_CORE_NB RC119
2
1
+APU_GFX CC109 @ 0_0402_5%
2
CC89
CC90
CC91
CC92
CC93
0.22U_0402_10V6K CLRP1 @
Need OPEN
1
2 D
CC110
CC111
CC112
CC113
CC114
CC115
CC116
CC117
CC118
CC119
1 1 1 1 1 SHORT PADS
1
1 1 1 1 1 1 1 1 1 1 2
<31> EC_CLEAR_CMOS
4 G QC12 4
2
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
S 2N7002H_SOT23-3 for Clear CMOS

3
2 2 2 2 2
180P_0402_50V8J
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
RC102
2 2 2 2 2 2 2 2 2 2 10K_0402_5%
1
pop or unpop?
ACROSS VDDNB AND VSS SPLIT Security Classification Compal Secret Data Compal Electronics, Inc.
FP4 PWR
C 1.0
LA-C293P
A B C D E
5 4 3 2 1
UAPU1G UAPU1H
UAPU1J
GND GND
A8 VSS_1 VSS_63 L28 AE10 VSS_125 VSS_187 AV30
A12 VSS_2 VSS_64 M4 AE13 VSS_126 VSS_188 AV33 TPC23 U30 RSVD_2
A16 VSS_3 VSS_65 M30 AE16 VSS_127 VSS_189 AW22 TPC22 U31 RSVD_3
A20 VSS_4 VSS_66 N10 AE19 VSS_128 VSS_190 AY4 TPC24 AN30 RSVD_4
A24 VSS_5 VSS_67 N13 AE22 VSS_129 VSS_191 AY6
A28 VSS_6 VSS_68 N16 AF1 VSS_130 VSS_192 AY8
A32 VSS_7 VSS_69 N19 AF4 VSS_131 VSS_193 AY10
B2 VSS_8 VSS_70 N22 AG9 VSS_132 VSS_194 AY12
B8 VSS_9 VSS_71 N27 AG12 VSS_133 VSS_195 AY14
B12 VSS_10 VSS_72 P1 AG15 VSS_134 VSS_196 AY16
D B33 VSS_11 VSS_73 P2 AG18 VSS_135 VSS_197 AY20 D
C3 VSS_12 VSS_74 P4 AG21 VSS_136 VSS_198 AY22 FP4 REV 0.93
D4 VSS_13 VSS_75 P5 AH4 VSS_137 VSS_199 AY24
D6 VSS_14 VSS_76 P12 AH10 VSS_138 VSS_200 AY26 FP4_BGA968
D12 VSS_17 VSS_79 P21 AH19 VSS_141 VSS_203 BB1 A6@
D14 VSS_18 VSS_80 P30 AH22 VSS_142 VSS_204 BB33
D16 VSS_19 VSS_81 P33 AK1 VSS_143 VSS_205 BC4
D18 VSS_20 VSS_82 T4 AK4 VSS_144 VSS_206 BC8
D26 VSS_24 VSS_86 T19 AL16 VSS_148 VSS_210 BC24
F1 VSS_27 VSS_89 U5 AM4 VSS_151
F2 VSS_28 VSS_90 U12 AN9 VSS_152
F4 VSS_29 VSS_91 U15 AN10 VSS_153
F9 VSS_30 VSS_92 U18 AN15 VSS_154
F19 VSS_31 VSS_93 U21 AN18 VSS_155
F22 VSS_32 VSS_94 U24 AN21 VSS_156
F25 VSS_33 VSS_95 V1 AN25 VSS_157
F30 VSS_34 VSS_96 V2 AN28 VSS_158
F33 VSS_35 VSS_97 V4 AP1 VSS_159
G7 VSS_36 VSS_98 W10 AP2 VSS_160
G17 VSS_37 VSS_99 W13 AP4 VSS_161
G20 VSS_38 VSS_100 W16 AP7 VSS_162
G23 VSS_39 VSS_101 W19 AP22 VSS_163
G26
L15 VSS_40 VSS_102 W22 AP27 VSS_164
H4 VSS_41 VSS_103 Y4 AP30 VSS_165
H30 VSS_42 VSS_104 Y5 AP33 VSS_166
C J5 Y12 AR6 C
VSS_43 VSS_105 VSS_167
J15 VSS_44 VSS_106 Y15 AR25 VSS_168
J19 VSS_45 VSS_107 Y18 AR28 VSS_169
J22 VSS_46 VSS_108 Y21 AT4 VSS_170
J25 VSS_47 VSS_109 Y24 AT19 VSS_171
J28 VSS_48 VSS_110 AB1 AT22 VSS_172
K1 VSS_49 VSS_111 AB2 AT30 VSS_173
K2 VSS_50 VSS_112 AB4 AU5 VSS_174
K4 VSS_51 VSS_113 AB10 AU8 VSS_175
K10 VSS_52 VSS_114 AB13 AU11 VSS_176
K22 VSS_53 VSS_115 AB16 AU14 VSS_177
K27 VSS_54 VSS_116 AB19 AU20 VSS_178
K30 VSS_55 VSS_117 AB22 AU23 VSS_179
K33 VSS_56 VSS_118 AD4 AU27 VSS_180
L5 VSS_57 VSS_119 AD9 AV4 VSS_181
L12 VSS_58 VSS_120 AD12 AV7 VSS_182
VSS_59 VSS_121 AD15 AV9 VSS_183
L18 VSS_60 VSS_122 AD18 AV12 VSS_184 VSS_213 L24
L21 VSS_61 VSS_123 AD21 AV15 VSS_185 VSS_215 AL10
L25 VSS_62 VSS_124 AD24 AV25 VSS_186 VSS_214 AK21
FP4 REV 0.93 FP4 REV 0.93
FP4_BGA968 FP4_BGA968
A6@ A6@
B B
A A

FP4 GND
Size Document Number
Rev
Custom 1.0
LA-C293P
5 4 3 2 1
A B C D E
+VREF_DQ_R R187 2 1 0_0402_5%

+VREF_DQ
+1.35V +1.35V
JDIMM2
+MB_VREFDQ
2
R195
@ 1
0_0402_5%
1
JDIMM2
2
Reverse Type
3 VREF_DQ VSS 4 DDRAB_SDQ4 DDRAB_SDQ[0..63]
VSS DQ4
Near CPU DDRAB_SDQ[0..63] <13,6>
1000P_0402_50V7K
DDRAB_SDQ0 5 6 DDRAB_SDQ5
DQ0 DQ5
0.1U_0402_25V6K
1 DDRAB_SDQ1 7 8 DDRAB_SDM[0..7]
DQ1 VSS DDRAB_SDM[0..7] <13,6>
C1142
1 9 10 DDRAB_SDQS0#
VSS DQS0# DDRAB_SDQS0# <13,6>
C1176
DDRAB_SMA[0..15]
DDRAB_SDM0 11
13 DM0 DQS0
12
14
DDRAB_SDQS0
DDRAB_SDQS0 <13,6> DDRAB_SMA[0..15] <13,6> +EC_VCCA
2 DDRAB_SDQ2 15 VSS VSS 16 DDRAB_SDQ6
2 DDRAB_SDQ3 17 DQ2 DQ6 18 DDRAB_SDQ7
19 DQ3 DQ7 20
VSS VSS
16.5K_0402_1%
1 DDRAB_SDQ8 21 22 DDRAB_SDQ12 1
DQ8 DQ12
1
DQ9 DQ13
R1648
25 26
DDRAB_SDQS1# 27 VSS VSS 28 DDRAB_SDM1
<13,6> DDRAB_SDQS1# DDRAB_SDQS1 29 DQS1# DM1 30 MEM_MAB_RST#
<13,6> DDRAB_SDQS1 31 DQS1 RESET# 32 MEM_MAB_RST# <13,6>
+1.35V/+0.675VS OF DIMM2
2
DDRAB_SDQ10 33 VSS VSS 34 DDRAB_SDQ14
DDRAB_SDQ11 35 DQ10 DQ14 36 DDRAB_SDQ15 <31> DDR_TEMP
37 DQ11 DQ15 38
DDRAB_SDQ16 39 VSS VSS 40 DDRAB_SDQ20 +1.35V +0.675VS
DQ16 DQ20
1
43 DQ17 DQ21 44 PH202
DDRAB_SDQS2# 45 VSS VSS 46 DDRAB_SDM2 100K_0402_1%_TSM0B104F4251RZ
<13,6> DDRAB_SDQS2# DQS2# DM2
C1122
C1115
C1114
C1116
C1117
C1118
C1119
C1120
C1121
C1123
C1126
C1127
DDRAB_SDQS2 47 48
<13,6> DDRAB_SDQS2 49 DQS2 VSS 50 DDRAB_SDQ22 1 1 1 1 1 1 1 1 1 1 1 1
2
DDRAB_SDQ18 51 VSS DQ22 52 DDRAB_SDQ23
DDRAB_SDQ19 53 DQ18 DQ23 54
DQ19 VSS
22U_0603_6.3V6M
22U_0603_6.3V6M
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
4.7U_0603_6.3V6K
55 56 DDRAB_SDQ28
DDRAB_SDQ24 57 VSS DQ28 58 DDRAB_SDQ29 2 2 2 2 2 2 2 2 2 2 2 2
61 DQ25 VSS 62 DDRAB_SDQS3#
DDRAB_SDM3 63 VSS DQS3# 64 DDRAB_SDQS3 DDRAB_SDQS3# <13,6>
65 DM3 DQS3 66 DDRAB_SDQS3 <13,6>
DDRAB_SDQ26 67 VSS VSS 68 DDRAB_SDQ30 ECAGND
DDRAB_SDQ27 69 DQ26 DQ30 70 DDRAB_SDQ31
71 DQ27 DQ31 72 @ @ @ @ @
VSS VSS
DDRAB_CKE0 73 74 DDRAB_CKE1
<13,6> DDRAB_CKE0 75 CKE0 CKE1 76 DDRAB_CKE1 <13,6>
77 VDD VDD 78 DDRAB_SMA15
DDRAB_SBS2# 79 NC A15 80 DDRAB_SMA14
2 <13,6> DDRAB_SBS2#
DDRAB_SMA12
81
83
BA2
VDD
A14
VDD
82
84 DDRAB_SMA11
VREF for DIMM1,DIMM2 2
DDRAB_SMA9 85 A12/BC# A11 86 DDRAB_SMA7

87 A9 A7 88 +1.35V +1.35V
DDRAB_SMA8 89 VDD VDD 90 DDRAB_SMA6
DDRAB_SMA5 91 A8 A6 92 DDRAB_SMA4
A5 A4
2
93 94
DDRAB_SMA3 95 VDD VDD 96 DDRAB_SMA2 R65 R66
DDRAB_SMA1 97 A3 A2 98 DDRAB_SMA0 1K_0402_1% 1K_0402_1%
99 A1 A0 100
DDRA_CLK0 101 VDD VDD 102 DDRA_CLK1
DDRA_CLK1 <6>
1
<6> DDRA_CLK0 DDRA_CLK0# 103 CK0 CK1 104 DDRA_CLK1# +VREF_CA
<6> DDRA_CLK0# 105 CK0# CK1# 106 DDRA_CLK1# <6>
+VREF_DQ_R
DDRAB_SMA10 107 VDD VDD 108 DDRAB_SBS1#
DDRAB_SBS0# 109 A10/AP BA1 110 DDRAB_SRAS# DDRAB_SBS1# <13,6>
<13,6> DDRAB_SBS0# BA0 RAS# DDRAB_SRAS# <13,6>
2
111 112
VDD VDD
2
R68
<13,6> DDRAB_SWE# DDRAB_SCAS# 115 WE# S0# 116 DDRA_ODT0 DDRA_SCS0# <6>
R67 1K_0402_1%
<13,6> DDRAB_SCAS# 117 CAS# ODT0 118 DDRA_ODT0 <6>
1K_0402_1%
DDRAB_SMA13 119 VDD VDD 120 DDRA_ODT1
DDRA_ODT1 <6>
1
DDRA_SCS1# 121 A13 ODT1 122
1
<6> DDRA_SCS1# 123 S1# NC 124
125 VDD VDD 126
TEST VREF_CA +VREF_CA
127 128
VSS VSS
1000P_0402_50V7K
0.1U_0402_25V6K
DQ33 DQ37 1 1
C1134
C1167
133 134
<13,6> DDRAB_SDQS4# DDRAB_SDQS4 137 DQS4# DM4 138
<13,6> DDRAB_SDQS4 139 DQS4 VSS 140 DDRAB_SDQ38 2 2
3 145 DQ35 VSS 146 DDRAB_SDQ44 3
153 VSS DQS5# 154 DDRAB_SDQS5# <13,6>
DDRAB_SDM5 DDRAB_SDQS5
161 DQ43 DQ47 162
167 DQ49 DQ53 168
<13,6> DDRAB_SDQS6 173 DQS6 VSS 174 DDRAB_SDQ54
179 DQ51 VSS 180 DDRAB_SDQ60
195 DQ59 DQ63 196
R69 1 2 10K_0402_5%197 VSS VSS 198 MEM_MAB_EVENT#
SA0 EVENT# MEM_MAB_EVENT# <13,6>
199 200
+3VS 201 VDDSPD SDA 202 APU_SDATA0 <13,8>
203 SA1 SCL 204 APU_SCLK0 <13,8>
+0.675VS VTT VTT +0.675VS
1
205 206
4 R70 GND1 GND2 4
+3VS 10K_0402_5%
ARGOS_DS2RK-20401-TP4B
2
ME@ SP070014D00
1 1
C1135 C1136 Security Classification Compal Secret Data Compal Electronics, Inc.
2.2U_0603_6.3V6K 0.1U_0201_10V7K 2015/03/06 2016/03/06 Title
2 2
DIMM_2 H:4mm Issued Date Deciphered Date
DDR3 SODIMM-I Socket
<Address: 00> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
LA-C293P
A B C D E
A B C D E
+VREF_DQ +1.35V +1.35V

JDIMM1
1
JDIMM1
2
Standard Type
3 VREF_DQ VSS 4 DDRAB_SDQ4 DDRAB_SDQ[0..63]
0.1U_0402_25V6K
VSS DQ4
Near User DDRAB_SDQ[0..63] <12,6>
1000P_0402_50V7K
DDRAB_SDQ1 7 DQ0 DQ5 8 DDRAB_SDM[0..7]
1 1 DQ1 VSS DDRAB_SDM[0..7] <12,6>
C1177
C1143
9 10 DDRAB_SDQS0#
DDRAB_SDM0 11 VSS DQS0# 12 DDRAB_SDQS0 DDRAB_SDQS0# <12,6> DDRAB_SMA[0..15]
DM0 DQS0 DDRAB_SDQS0 <12,6> DDRAB_SMA[0..15] <12,6>
13 14
2 2 DDRAB_SDQ2 15 VSS VSS 16 DDRAB_SDQ6
19 DQ3 DQ7 20
1 DDRAB_SDQ8 21 VSS VSS 22 DDRAB_SDQ12 1
25 DQ9 DQ13 26
<12,6> DDRAB_SDQS1# DDRAB_SDQS1 29 DQS1# DM1 30 MEM_MAB_RST#
<12,6> DDRAB_SDQS1 31 DQS1 RESET# 32 MEM_MAB_RST# <12,6>
DDRAB_SDQ10 33
35
VSS
DQ10
VSS
DQ14
34
36
DDRAB_SDQ14 2 2 +1.35V/+0.675VS OF DIMM1
DDRAB_SDQ11 DDRAB_SDQ15 ESDP@ ESDP@
37 DQ11 DQ15 38 C1381 C1382
VSS VSS
100P_0402_50V8J
DDRAB_SDQ16 39 40 DDRAB_SDQ20 +1.35V +0.675VS +1.35V
100P_0402_50V8J
DDRAB_SDQ17 41 DQ16 DQ20 42 DDRAB_SDQ21 1 1
43 DQ17 DQ21 44
<12,6> DDRAB_SDQS2# DQS2# DM2
C1162
C1170
C1172
C1169
C1133
C1155
C1132
C1165
C1168
C1171
C1175
C1158
DDRAB_SDQS2 47 48
VSS DQ22 1 1 1 1 1 1 1 1 1 1 1 1 1
DDRAB_SDQ18 51 52 DDRAB_SDQ23 @
DDRAB_SDQ19 53 DQ18 DQ23 54 + C250
DQ19 VSS
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
4.7U_0603_6.3V6K
55 56 DDRAB_SDQ28 330U_D3_2.5VY_R6M
DDRAB_SDQ24 57 VSS DQ28 58 DDRAB_SDQ29 2 2 2 2 2 2 2 2 2 2 2 2
DDRAB_SDQ25 59 DQ24 DQ29 60 2
DDRAB_SDM3 63 VSS DQS3# 64 DDRAB_SDQS3 DDRAB_SDQS3# <12,6>
71 DQ27 DQ31 72 @ @ @
VSS VSS
DDRAB_CKE0 73 74 DDRAB_CKE1
<12,6> DDRAB_CKE0 75 CKE0 CKE1 76 DDRAB_CKE1 <12,6>
77 VDD VDD 78 DDRAB_SMA15
DDRAB_SBS2# 79 NC A15 80 DDRAB_SMA14
2 <12,6> DDRAB_SBS2# 81 BA2 A14 82 2
DDRAB_SMA9 85 A12/BC# A11 86 DDRAB_SMA7
87 A9 A7 88
93 A5 A4 94
99 A1 A0 100
DDRB_CLK0 101 VDD VDD 102 DDRB_CLK1
<6> DDRB_CLK0 103 CK0 CK1 104 DDRB_CLK1 <6>
DDRB_CLK0# DDRB_CLK1#
<6> DDRB_CLK0# 105 CK0# CK1# 106 DDRB_CLK1# <6>
DDRAB_SMA10 107 VDD VDD 108 DDRAB_SBS1#
DDRAB_SBS0# 109 A10/AP BA1 110 DDRAB_SRAS# DDRAB_SBS1# <12,6>
<12,6> DDRAB_SBS0# 111 BA0 RAS# 112 DDRAB_SRAS# <12,6>
VDD VDD
<12,6> DDRAB_SWE# DDRAB_SCAS# 115 WE# S0# 116 DDRB_ODT0 DDRB_SCS0# <6>
<12,6> DDRAB_SCAS# 117 CAS# ODT0 118 DDRB_ODT0 <6>
DDRAB_SMA13 119 VDD VDD 120 DDRB_ODT1
A13 ODT1
<6> DDRB_SCS1# 123 S1# NC 124
125 VDD VDD 126
TEST VREF_CA +VREF_CA
127 128
VSS VSS 1000P_0402_50V7K
0.1U_0402_25V6K
DQ33 DQ37 1 1
C1139
C1174
133 134
<12,6> DDRAB_SDQS4 139 DQS4 VSS 140 DDRAB_SDQ38 2 2
3 145 DQ35 VSS 146 DDRAB_SDQ44 3
161 DQ43 DQ47 162
167 DQ49 DQ53 168
179 DQ51 VSS 180 DDRAB_SDQ60
195 DQ59 DQ63 196
R71 1 2 10K_0402_5% 197 VSS VSS 198
SA0 EVENT# MEM_MAB_EVENT# <12,6>
199 200
+3VS 1 2 10K_0402_5% 201 VDDSPD SDA 202 APU_SDATA0 <12,8>
203 SA1 SCL 204 APU_SCLK0 <12,8>
+0.675VS VTT VTT +0.675VS
R72
205 206
4 207 GND1 GND2 208 4
BOSS1 BOSS2
ARGOS_DS2SK-20401-TP4B
ME@
SP070014E00

2015/03/06 2016/03/06 Title
DIMM_1 H:4mm Issued Date Deciphered Date
DDR3 SODIMM-II Socket
<Address: 01> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
LA-C293P
A B C D E
1 2 3 4 5
UV1A
A
AC Coupling Capacitor A
PCIe Gen3: Recommended value is 220 nF
PCIe Gen1 and Gen2 only: Recommended value is 100 nF
AF30 AH30 PCIE_GTX_ARX_P0
AE31 PCIE_RX0P PCIE_TX0P AG31 PCIE_GTX_ARX_N0 CV1 2 1 PX_CZL@ 0.1U_0402_16V7K
<5> PCIE_ATX_C_GRX_P0 PCIE_RX0N PCIE_TX0N PCIE_GTX_C_ARX_P0 <5>
CV2 2 1 PX_CZL@ 0.1U_0402_16V7K
<5> PCIE_ATX_C_GRX_N0 PCIE_GTX_C_ARX_N0 <5>
AE29 AG29 PCIE_GTX_ARX_P1
AD28 PCIE_RX1P PCIE_TX1P AF28 PCIE_GTX_ARX_N1 CV3 2 1 PX_CZL@ 0.1U_0402_16V7K
CV4 2 1 PX_CZL@ 0.1U_0402_16V7K
AD30 AF27
AC31 PCIE_RX2P PCIE_TX2P AF26 PCIE_GTX_ARX_P2 CV5 2 1 PX_CZL@ 0.1U_0402_16V7K
PCIE_GTX_ARX_N2 CV6 2 1 PX_CZL@ 0.1U_0402_16V7K
AC29 AD27
AB28 PCIE_RX3P PCIE_TX3P AD26 PCIE_GTX_ARX_P3 CV7 2 1 PX_CZL@ 0.1U_0402_16V7K
PCIE_GTX_ARX_N3 CV8 2 1 PX_CZL@ 0.1U_0402_16V7K
AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_RX4N PCIE_TX4N CV1 CV2 CV3 CV4
PX_CZ@ PX_CZ@ PX_CZ@ PX_CZ@ S CER CAP 0.22U 10V K X5R 0402
AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24 CV5 CV6 CV7 CV8
PCIE_RX5N PCIE_TX5N PX_CZ@ PX_CZ@ PX_CZ@ PX_CZ@
Y30 AB27
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N
W29 Y27
V28 PCIE_RX7P PCIE_TX7P Y26
B PCIE_RX7N PCIE_TX7N B
V30 W24
U31 NC#V30 NC#W24 W23
NC#U31 NC#W23
U29 V27
T28 NC#U29 NC#V27 U26
NC#T28 NC#U26
PCI EXPRESS INTERFACE

T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23
R29 T26 No Use GPU Display Port outpud

P28 NC#R29 NC#T26 T27
NC#P28 NC#T27
UV1F EXO@
P30 T24
N31 NC#P30 NC#T24 T23
NC#N31 NC#T23
AB11 0_0402_5% 2 MESO@ 1 RV177
N29 P27 VARY_BL AB12 0_0402_5% 2 MESO@ 1 RV176 FOR TOPAS CORE POWER USE
M28 NC#N29 NC#P27 P26 DIGON
NC#M28 NC#P26
M30 P24
L31 NC#M30 NC#P24 P23 AL15
NC#L31 NC#P23 TXCAP_DPA3P AK14
TXCAM_DPA3N
L29 M27 AH16
K30 NC#L29 NC#M27 N26 TX0P_DPA2P AJ15
NC#K30 NC#N26 TX0M_DPA2N
AL17
TX1P_DPA1P AK16
C C
TX1M_DPA1N
CLOCK
AK30 AH18
CLK_PCIE_GPU AK32 PCIE_REFCLKP TX2P_DPA0P AJ17
<9> CLK_PCIE_GPU PCIE_REFCLKN TX2M_DPA0N
CLK_PCIE_GPU#
<9> CLK_PCIE_GPU# +0.95VGS AL19
+3VGS CALIBRATION NC_TXOUT_L3P AK18
Y22 NC_TXOUT_L3N
PCIE_CALR_TX RV1 1 PX@ 2 1.69K_0402_1%
N10 AA22 TMDP
RV2 1 PX@ 2 1K_0402_5% TEST_PG PCIE_CALR_RX RV3 1 PX@ 2 1K_0402_1%
5
UV2 PX@ AH20

APU_PCIE_RST# 2 AL27 TXCBP_DPB3P AJ19
P
<25,26,27,8> APU_PCIE_RST# B PERSTB TXCBM_DPB3N

4 GPU_RST#
PXS_RST# 1 Y AL21
<8> PXS_RST# A TX3P_DPB2P
G
AK20
TX3M_DPB2N
1
216-0841018 A0 SUN PRO S3 EXO@

3
RV4 AH22
MC74VHC1G08DFT2G_SC70-5 100K_0402_5% TX4P_DPB1P AJ21
<15> GPU_RST# TX4M_DPB1N
PX@
AL23
2
TX5P_DPB0P AK22
TX5M_DPB0N
AK24
NC_TXOUT_U3P AJ23
NC_TXOUT_U3N
216-0841018 A0 SUN?PRO S3
D D

EXO/MESO(1/5)_PCIE/DP
Custom 1.0
LA-C293P
1 2 3 4 5
1 2 3 4 5
+3VGS
RV375 1 @ 2 0_0402_5%
+1.8VGS
PS_0[3:1]=001 Strap Name :
1
GPU_RST# 1 @ 2 PX@ PX@ UV1B EXO@ U?
<14> GPU_RST#
RV112 0_0402_5% RV157 RV158 PS_0[5:4]=11
1
47K_0402_5% 47K_0402_5% PS_0[1] ROM_CONFIG[0]
2
PX@
AF2 RV12 PS_0[2] ROM_CONFIG[1]
2
6 1 VGA_SMB_DA2 NC#AF2 AF4 8.45K_0402_1%
<23,31,32,7> EC_SMB_DA2 NC#AF4
PS_0[3] ROM_CONFIG[2]
2
PX@ QV9A N9 AG3 PS_0
DBG_DATA16 NC#AG3
5
ME2N7002D1KW-G 2N_SOT363-6 L9 AG5 Resistor Divider Lookup Lable PS_0[4] N/A
DBG_DATA15 NC#AG5
1
AE9 1
0.68U_0402_10V
DPA
3 4 VGA_SMB_CK2 Y11 DBG_DATA14 AH3 PX@
<23,31,32,7> EC_SMB_CK2 AE8 DBG_DATA13 NC#AH3 AH1 CV30 RV7
PS_0[5] AUD_PORT_CONN_PINSTRAP[0]
PX@ QV9B AD9 DBG_DATA12 NC#AH1 R_pu (ohm) R_pd (ohm) Bitd [3:1] 2K_0402_1%
A ME2N7002D1KW-G 2N_SOT363-6 AC10 DBG_DATA11 AK3 @ 2 A
2
AD7 DBG_DATA10 NC#AK3 AK1
AC8 DBG_DATA9 NC#AK1 NC 4.75k 000
DVO
AC7 DBG_DATA8 AK5
AB9 DBG_DATA7 NC#AK5 AM3
8.45k 2k 001
AB8 DBG_DATA6 NC#AM3
+3VGS +3VGS +3VGS +1.8VGS AB7 DBG_DATA5 AK6
4.53k 2k 010
AB4 DBG_DATA4 NC#AK6 AM5
AB2 DBG_DATA3 NC#AM5 6.98k 4.99k 011 +1.8VGS
DBG_DATA2 DPB PS_1[3:1]=000 Strap Name :
2
2 2 @ Y8 AJ7 4.53k 4.99k 100

CV195 RV71 RV161 Y7 DBG_DATA1 NC#AJ7 AH6
DBG_DATA0 NC#AH6 PS_1[5:4]=11
1
10K_0402_5% 10K_0402_5% CV182 3.24k 5.62k 101 PS_1[1] STRAP_BIF_GEN3_EN_A
0.1U_0201_10V7K @ @ 0.1U_0201_10V7K AK8 @
@ 1 1 NC#AK8 AL7 RV9
3.4k 10k 110 PS_1[2] TRAP_BIF_CLK_PM_EN
1
@ FOR MESO only NC#AL7 8.45K_0402_1%

UV13 @ 4.75k NC 111 PS_1[3] N/A
2
@ 33_0402_5% 1 8 33_0402_5% +1.8VGS W6 PS_1
GPU_VID3 RV162 1 2GPU_VID3_GPIO_15 2 VCCA VCCB 7 GPU_SVD_R RV131 1 2 GPU_SVD V6 NC#W6
A1 B1 NC#V6 0402 1% resistors are equired PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING
1
GPU_VID1 RV81 1 2GPU_VID1_GPIO_20 3 6 GPU_SVC_R RV130 1 2 GPU_SVC V4 1
0.68U_0402_10V
@ 33_0402_5%DIR 5 A2 B2 4 AC6 NC#V4 U5 PX@
DIR GND 33_0402_5% @ AC5 NC#AC5 NC#U5 CV31 RV14
PS_1[5] STRAP_TX_DEEMPH_EN
NC#AC6
2
W3 4.75K_0402_1%
NC#W3
2
SN74LVC2T45DCTR_SM8 AA5 V2 @ 2
Capacitor Divider Lookup Lable
2
@ @ RV16 RV11 AA6 NC#AA5 NC#V2
DPC
RV135 RV134 4.7K_0402_5% 4.7K_0402_5% NC#AA6 Y4
10K_0402_5% 10K_0402_5% MESO@ MESO@ NC#Y4 W5 Cap (nF) Bitd [5:4]
1
NC#W5
1
GPU_VID3 RV182 1 EXO@ 2 0_0402_5% GPU_SVD U1 AA3 PLL_ANALOG_OUT 1 PX@ 2
GPU_VID1 RV183 1 EXO@ 2 0_0402_5% GPU_SVC 1 FB_VDDCI W1 NC#U1 NC#AA3 Y2 RV17
@
TV23
U3 NC#W1 NC#Y2 16.2K_0402_1%
680nF 00
+3VGS 10K_0402_5% CV180 10U_0603_6.3V6M Y6 NC#U3 J8 +1.8VGS
RV136 2 1 DIR 2 1 1 PLL_ANALOG_IN AA1 NC#Y6 NC#J8 82nF 01 PS_2[3:1]=000 Strap Name :
TV18 NC#AA1
10nF 10 PS_2[5:4]=11
1
@ CV196 PS_2[1] N/A
2 1 0.1U_0201_10V7K NC 11 AMD recommend 09/25 @
RV57 PS_2[2] N/A
@ I2C 8.45K_0402_1%
PS_2[3] STRAP_BIOS_ROM_EN
2
B R1 PS_2 B
R3 SCL
SDA PS_2[4] STRAP_BIF_VGA_DIS
1
+3VGS
1
0.68U_0402_10V
+3VGS AM26 @ PX@
REAK CURRENT CONTROL ( MESO only ) +VGA_CORE R AK26 CV32 RV19
PS_2[5] N/A
GENERAL PURPOSE I/O AVSSN#AK26
2
U6 +3VGS 4.75K_0402_1%
GPIO_0
2
RV170 1 MESO@ 2 0_0402_5% U10 AL25 2
2
RV10 RV174 1 MESO@ 2 0_0402_5% T10 GPIO_1 G AJ25 @ RV373
GPIO_2 AVSSN#AJ25
2
10K_0402_5% VGA_SMB_DA2 U8 4.7K_0402_5%
VGA_SMB_CK2 U7 SMBDATA AH24 RV371
MESO@
2 1
RV15 @ DV1 1 2 GPU_GPIO5 T9 SMBCLK B AG25
<31,33,37> VCIN1_AC_IN 4.7K_0402_5%
1
GPIO_5_AC_BATT AVSSN#AG25
G
1K_0402_5% GPU_GPIO6 T8 @
GPU_GPIO6 1 2 GPU_PROCHOT# RB751V_SOD323 T7 GPIO_6 DAC1 AH26
GPU_PROCHOT# <45>
1
MESO@ P10 GPIO_7_BLON HSYNC AJ27 3 1 GPU_WAKEB
1 GPIO_8_ROMSO VSYNC
P4 +1.8VGS
D
GPIO_9_ROMSI PS_3[3:1]=000 Strap Name :
2
CV17 P2
+VGA_CORE N6 GPIO_10_ROMSCK AD22 RV372 2N7002H_SOT23-3
0.1U_0201_10V7K GPIO_11 RSET PS_3[5:4]=11
1
2 N5 @ QV20
MESO@
N3 GPIO_12 AG24
4.7K_0402_5%
PX@ X76@
PS_3[1] BOARD_CONFIG[0] (Memory ID)
Y9 GPIO_13 AVDD AE22
OBFF OPTION: RV21 PS_3[2] BOARD_CONFIG[1] (Memory ID)
1
GPU_VID3 N1 GPIO_14_HPD2 AVSSQ reserved for AMD request 8.45K_0402_1%
M4 GPIO_15_PWRCNTL_0 AE23 Pull down for none OBFF design
PS_3[3] BOARD_CONFIG[2] (Memory ID)
2
THM_ALERT# RV194 0_0402_5% THM_ALERT#_R R6 GPIO_16 AD23 PS_3
<32> THM_ALERT# GPIO_17_THERMAL_INT VSS1DI
RV173 1 2 0_0402_5% W10 PS_3[4] AUD_PORT_CONN_PINSTRAP[1]
GPIO_18
1
MESO@ GPIO19_CTF M2 1
0.68U_0402_10V
GPIO_19_CTF FutureASIC/SEYMOUR/PARK
GPU_VID1 P8 AM12
CV33
X76@ PS_3[5] AUD_PORT_CONN_PINSTRAP[2]
+1.8VGS P7 GPIO_20_PWRCNTL_1 CEC_1 @ RV24
N8 GPIO_21 2K_0402_1%
1 RV13 2 GPIO19_CTF AK10 GPIO_22_ROMCSB AK12 SVI2_SVD RV166 1 MESO@ 2 0_0402_5% GPU_SVD 2
GPU_SVD <45>
2
10K_0402_5% AM10 GPIO_29 RSVD#AK12 AL11 SVI2_SVT RV167 1 MESO@ 2 0_0402_5% GPU_SVT
GPIO_30 RSVD#AL11 GPU_SVT <45>
@ N7 AJ11 SVI2_SVC RV168 1 MESO@ 2 0_0402_5% GPU_SVC GPU_SVC <45>
<8> VGA_CLKREQ# CLKREQB RSVD#AJ11
2
RV22 JTAG_TRSTB L6 FOR MESO

JTAG_TDI L5 JTAG_TRSTB EXO doesn't have native SVI2
10K_0402_5% JTAG_TDI
@ JTAG_TCK L3
2 L1 JTAG_TCK AL13
1
RV26 5.11K_0402_5% 1 JTAG_TDO K4 JTAG_TMS GENLK_CLK AJ13

TV24 JTAG_TDO GENLK_VSYNC
+3VGS 1 PX@ 2 TESTEN K7
C RV27 1K_0402_5% AF24 TESTEN C
RV18 2 PX@ 1 4.7K_0402_5% THM_ALERT# +VGA_CORE NC#AF24 AG13
SWAPLOCKA AH12
RV169 1 MESO@ 2 0_0402_5% AB13 SWAPLOCKB
W8 GENERICA
RV171 1 MESO@ 2 0_0402_5% W9 GENERICB
W7 GENERICC AC19 PS_0
AD10 GENERICD PS_0
AJ9 GENERICE AD19 PS_1
+3VGS 1 AL9 NC#AJ9 PS_1
TV22 NC#AL9 AE17 PS_2
RV175 1 MESO@ 2 0_0402_5% AC14 PS_2
1 PX_EN AB16 HPD1 AE20 PS_3
TV25 PX_EN PS_3
RV58 1 @ 2 GPU_GPIO5
10K_0402_5%
RV20 1 @ 2 JTAG_TDO AE19
10K_0402_5% AC16 TS_A
DBG_VREFG
VGA_AC_BATT
pull up DDC/AUX
+3VGS AE6
PLL/CLOCK DDC1CLK AE5
DDC1DATA OPTIAN FOR 3.3V tolerance VR,
RPV1 @ AD2 Check with VR vendor
1 8 JTAG_TRSTB AUX1P AD4 +VGA_CORE +1.8VGS +3VGS
2 7 JTAG_TDI AUX1N RV185 RV186
3 6 JTAG_TMS AC11 RV178 1 MESO@ 2 0_0402_5% 1 MESO@ 2 1 EXO@ 2
4 5 JTAG_TCK DDC2CLK AC13 RV179 1 MESO@ 2 0_0402_5% FOR MESO CORE POWER USE 0_0402_5% 0_0402_5%
DDC2DATA
2
10K_8P4R_5% XTALIN AM28 AD13 RV164 RV163
XTALOUT AK28 XTALIN AUX2P AD11 10K_0402_5% PX@ 10K_0402_5%
XTALOUT AUX2N @
RV28 RV29 1 PX@ 2 10K_0402_5% AC22 AD20 FB_GND RV37 1 MESO@ 2 0_0402_5%
1
XTALIN 1M_0402_5% XTALOUT RV31 1 PX@ 2 10K_0402_5% AB22 XO_IN NC#AD20 AC20 FB_VDDC RV51 1 MESO@ 2 0_0402_5% GPU_VDD_RUN_FB_L <45> GPU_SVD
PX@ TO EXTERNAL THERMAL SENSOR XO_IN2 NC#AC20 ONLY AVAILABLE ON TOPAZ, NC BALLS ON JET/SUN GPU_VDD_SEN <45> GPU_SVC
AE16
NC#AE16
2
AD16
D YV1 PX@ NC#AD16 D
4 3 SEYMOUR/FutureASIC AC1 @ PX@
NC OSC REMOTE1+ T4 DDCVGACLK AC3 RV165 RV184
<32> REMOTE1+ DPLUS THERMAL DDCVGADATA
1 2 REMOTE1- T2 GPU_VDD_RUN_FB_L RV30 1 @ 2 0_0402_5% 10K_0402_5% 10K_0402_5%
<32> REMOTE1-
1
OSC NC DMINUS
27MHZ 10PF +-10PPM 7V27000050 +1.8VGS GPU_VDD_SEN RV32 1 @ 2 0_0402_5%
2 2 +VGA_CORE
SJ10000GI00 Enable MLPS RV33 1 EXO@ 2 10K_0402_5% GPIO28 R5
PX@ CV19 PX@ CV20 AD17 GPIO28_FDO
LV4 1 2 0_0402_5% +TSVDD AC17 TSVDD
10P_0402_50V8J 10P_0402_50V8J TSVSS
1 1
1
CV21
1U_0402_6.3V6K Security Classification Compal Secret Data Compal Electronics, Inc.
PX@ 2015/03/06 2016/03/06 Title
2 216-0841018 A0 SUN PRO ?S3
EXO/MESO(2/5)_MSIC
Custom 1.0
LA-C293P
1 2 3 4 5
1 2 3 4 5
+1.35VS to +1.35VGS UV1E EXO@ U?
+1.35V +1.35VGS
UV14 PX@ AA27 A3
AP4800BGM-HF 1N SO-8 No Use GPU Display Port outpud AB24 GND GND A30
8 1 +1.8VGS AB32 GND GND AA13
7 2 AC24 GND GND AA16
GND GND
2
0.1U_0201_10V7K
6 3 UV1G EXO@ U? AC26 AB10
GND GND
10U_0603_6.3V6M
1U_0402_6.3V6K
1 5 1 1 RV34 AC27 AB15
GND GND
CV25
CV26
CV22
AD25 AB6
CV23
CV24
470_0603_5% DP POWER NC/DP POWER
AD32 GND GND AC9
@ 1 1
4
AG15 AE11 AE27 GND GND AD6
A A
3 1
2 PX@ 2 PX@ 2 PX@ AG16 DP_VDDR#AG15 NC#AE11 AF11 AF32 GND GND AD8
AF16 DP_VDDR#AG16 NC#AF11 AE13 AG27 GND GND AE7
1U_0402_6.3V6K
10U_0603_6.3V6M
2 2 AG17 DP_VDDR#AF16 NC#AE13 AF13 AH32 GND GND AG12
DP_VDDR#AG17 NC#AF13 GND GND
PX@
PX@
AG18 AG8 K28 AH10
PX@ 220K_0402_5% 5 DGPU_PWR_EN# AG19 DP_VDDR#AG18 NC#AG8 AG10 K32 GND GND AH28
1 2 1.35VSG_GATE 1 PX@ 2 AF14 DP_VDDR#AG19 NC#AG10 L27 GND GND B10
B+ DP_VDDR#AF14 GND GND
RV35 1M_0402_5% RV36 QV10B M32 B12
4
GND GND
6
ME2N7002D1KW-G 2N_SOT363-6 N25 B14
PX@ @ N27 GND GND B16
P25 GND GND B18
1 GND GND
DGPU_PWR_EN# 2 QV10A PX@ AG20 AF6 P32 B20
ME2N7002D1KW-G 2N_SOT363-6 CV27 AG21 DP_VDDC#AG20 NC#AF6 AF7 R27 GND GND B22
0.022U_0402_25V7K +0.95VGS AF22 DP_VDDC#AG21 NC#AF7 AF8 T25 GND GND B24
1
2 AG22 DP_VDDC#AF22 NC#AF8 AF9 T32 GND GND B26
AD14 DP_VDDC#AG22 NC#AF9 U25 GND GND B6
DP_VDDC#AD14 U27 GND GND B8
V32 GND GND C1
CV28
CV29
W25 GND GND C32
1 1 GND GND
AG14 AE1 W26 E28
AH14 DP_VSSR NC#AE1 AE3 W27 GND GND F10
AM14 DP_VSSR NC#AE3 AG1 Y25 GND GND F12
1U_0402_6.3V6K
0.1U_0201_10V7K
2 2 AM16 DP_VSSR NC#AG1 AG6 Y32 GND GND F14
DP_VSSR NC#AG6 GND GND
PX@
PX@
AM18 AH5 F16
AF23 DP_VSSR NC#AH5 AF10 GND F18
AG23 DP_VSSR NC#AF10 AG9 GND F2
AM20 DP_VSSR NC#AG9 AH8 GND F20
AM22 DP_VSSR NC#AH8 AM6 M6 GND F22
AM24 DP_VSSR NC#AM6 AM8 N13 GND GND F24
AF19 DP_VSSR NC#AM8 AG7 N16 GND GND F26
AF20 DP_VSSR NC#AG7 AG11 N18 GND GND F6
AE14 DP_VSSR NC#AG11 N21 GND GND
GND F8
DP_VSSR P6 GND GND G10
+1.8VALW TO +1.8VGS P9
R12
GND
GND
GND
GND
G27
G31
B +0.95VALW GND GND B
+0.95VALW TO +0.95VGS AF17
DPAB_CALR NC#AE10
AE10 R15
R17
R20
GND
GND
GND
GND
G8
H14
H17
GND GND
C29
Load switch T13
T16 GND
GND
GND
GND
H2
H20
1U_0402_6.3V6K
1 216-0841018 A0 SUN PRO S3 T18 H6

@ T21 GND GND J27
T6 GND GND J31
+0.95VGS U15 GND GND K11
2 U1895V U17 GND GND K2
1 14 +0.95VGS_LS RV5 1 @ 2 0_0805_5% U20 GND GND K22
PX@ 2 VIN1 VOUT1 13 U9 GND GND K6
R1642 VIN1 VOUT1 V13 GND GND
GND
2
DGPU_PWR_EN 2 1 DGPU_PWR_EN_R 3 12 @ 1 2 PX@ V16
150K_0402_5% ON1 CT1 2200P_0402_50V7K C28 C32 V18 GND
4 11 Y10 GND
VL 0.1U_0201_10V7K
1
VBIAS GND GND
C1380
Y15
5 10 @ 1 2 Y17 GND
GND
1
2200P_0402_50V7K Y20
R11 GND A32
VIN2 VOUT2 GND VSS_MECH
0.1U_0402_16V7K
7 8 +1.8VGS_LS RV6 1 @ 2 0_0805_5% T11 AM1

2
VIN2 VOUT2 AA11 GND VSS_MECH AM32

15 M12 GND VSS_MECH
GPAD GND
2
PX@ N11
APE8990GN3B DFN 14P C31 V11 GND
GND
0.1U_0201_10V7K
1
1 PX@
@ C30
?
216-0841018 A0 SUN PRO S3
SA00007PM00
1U_0402_6.3V6K
C C
+3VS to +3VGS
+VGA_CORE +1.8VGS +0.95VGS
+3VALW +3VGS
2
PX@
RV39 RV53 RV56
3 1 4.7U_0603_6.3V6K 1U_0603_10V6K 470_0603_5% 470_0603_5% 470_0603_5%
PX@ @ @
1
ME2N7002D1KW-G 2N_SOT363-6
ME2N7002D1KW-G 2N_SOT363-6
QV16 1 1 @
1 1
6 1
3 1
LP2301ALT1G_SOT23-3 CV36 CV37 RV40
D
680_0603_5%
2
PX@ @ DGPU_PWR_EN# 2 PX@

2 2 QV11
3VGS_EN#
G
2
+5VALW S 2N7002H_SOT23-3 2 DGPU_PWR_EN# 5 DGPU_PWR_EN#
3
@
1
D QV21A QV21B
4
2 @ @
PX@ QV17 G
RV42 PX@ DGPU_PWR_EN# 1 2 S 2N7002H_SOT23-3
3
RV43 10K_0402_5%
20K_0402_5%
D D
1
D
1 PX@
R1640 2 1 0_0402_5% DGPU_PWR_EN_3VGS 2 PX@ DGPU_PWR_EN#
<31,45,8> DGPU_PWR_EN CV38
G QV18
0.1U_0201_10V7K
1
S 2N7002H_SOT23-3
3
RV41 2
@
100K_0402_5%
2
EXO/MESO(3/5)_PWR/GND
Custom 1.0
LA-C293P
1 2 3 4 5
1 2 3 4 5
A A
+1.35VGS
UV1D EXO@ +1.8VGS
U?
AM30
MEM I/O PCIE_PVDD
PCIE
CV47
CV48
+1.35VGS H13 AB23 1 1
H16 VDDR1 NC#AB23 AC23
H19 VDDR1 NC#AC23 AD24
CV75
CV88
CV74
CV80
CV83
CV87
CV76
CV77
CV78
CV79
CV81
CV82
CV89
CV86
CV85
CV84
1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
220U_B2_2.5VM_R35
J10 VDDR1 NC#AD24 AE24
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10U_0603_6.3V6M
1U_0402_6.3V6K
+ J23 VDDR1 NC#AE24 AE25 2 2
VDDR1 NC#AE25
PX@
PX@
@ J24 AE26
J9 VDDR1 NC#AE26 AF25
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VDDR1 NC#AF25
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
@
@
K10 AG26
K23 VDDR1 NC#AG26
K24 VDDR1
K9 VDDR1 L23
L11 VDDR1 PCIE_VDDC L24
L20 VDDR1 PCIE_VDDC M22 +0.95VGS
L21 VDDR1 PCIE_VDDC N22
L22 VDDR1 PCIE_VDDC N23
VDDR1 PCIE_VDDC N24
PCIE_VDDC R22
PCIE_VDDC T22
CV49
CV50
CV51
CV52
CV53
CV54
+1.8VGS LEVEL PCIE_VDDC U22
TRANSLATION PCIE_VDDC 1 1 1 1 1 1
V22
AA20 PCIE_VDDC
AA21 VDD_CT
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
AB20 VDD_CT AA15 2 2 2 2 2 2
CV55
B VDD_CT CORE VDDC B
PX@
PX@
PX@
PX@
PX@
@
1 AB21 N15
VDD_CT VDDC N17
+3VGS VDDC R13
I/O VDDC R16
1U_0402_6.3V6K
2 AA17 VDDC R18
VDDR3 VDDC
PX@
AA18 Y21
AB17 VDDR3 VDDC T12
CV56
AB18 VDDR3 VDDC T15 +VGA_CORE
VDDC T17
V12 VDDC T20
Y12 VDDR4 VDDC U13
1U_0402_6.3V6K
2 U12 VDDR4 VDDC U16
VDDR4 VDDC
PX@
U18
VDDC V21 VGA_CORE Caps in power side sheet
VDDC V15
VDDC V17
VDDC V20
VDDC
POWER
Y13
VDDC Y16
VDDC Y18
VDDC AA12
VDDC M11
VDDC N12
VDDC U11
VDDC
+1.8VGS
@ PLL
LV1 1 2 0_0603_5% +MPLL_PVDD
+0.95VGS
R21
CV39
CV40
CV41
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
BIF_VDDC U21
1 1 1 BIF_VDDC
L8
+1.8VGS MPLL_PVDD
C C
+VGA_CORE
PX@
PX@
PX@
CV62
ISOLATED
LV2 1 2 +SPLL_PVDD CORE I/O 1
M13
H7 VDDCI M15
CV42
CV43
10U_0603_6.3V6M
1U_0402_6.3V6K
SPLL_PVDD VDDCI M16
1 1
1U_0402_6.3V6K
VDDCI M17 2
+0.95VGS VDDCI
@
M18
0_0402_5% VDDCI M20
2 2 VDDCI
PX@
PX@ LV3 1 2 +SPLL_VDDC H8 M21

SPLL_VDDC VDDCI N20
J7 VDDCI
SPLL_PVSS
CV46
CV90
VGA_CORE Caps in power side sheet
1U_0402_6.3V6K
0.1U_0201_10V7K
1 1
216-0841018 A0 SUN PRO S3?

2 2
PX@
PX@
D D

EXO/MESO(4/5)_PWR
Custom 1.0
LA-C293P
1 2 3 4 5
1 2 3 4 5
EXO@
M_DA[63..0] UV1C U?
<19,20> M_DA[63..0]
M_MA[15..0] GDDR5/DDR3 GDDR5/DDR3
<19,20> M_MA[15..0]
A M_DA0 K27 K17 M_MA0 A
M_DQM[7..0] M_DA1 J29 DQA0_0 MAA0_0/MAA_0 J20 M_MA1
<19,20> M_DQM[7..0] DQA0_1 MAA0_1/MAA_1
M_DA2 H30 H23 M_MA2
M_DQS[7..0] M_DA3 H32 DQA0_2 MAA0_2/MAA_2 G23 M_MA3
<19,20> M_DQS[7..0] DQA0_3 MAA0_3/MAA_3
M_DA4 G29 G24 M_MA4
M_DQS#[7..0] M_DA5 F28 DQA0_4 MAA0_4/MAA_4 H24 M_MA5
<19,20> M_DQS#[7..0] DQA0_5 MAA0_5/MAA_5
M_DA6 F32 J19 M_MA6
M_DA7 F30 DQA0_6 MAA0_6/MAA_6 K19 M_MA7
M_DA8 C30 DQA0_7 MAA0_7/MAA_7 G20 M_MA13
M_DA9 F27 DQA0_8 MAA0_8/MAA_13 L17 M_MA15
M_DA10 A28 DQA0_9 MAA0_9/MAA_15
M_DA11 C28 DQA0_10 J14 M_MA8
M_DA12 E27 DQA0_11 MAA1_0/MAA_8 K14 M_MA9
M_DA13 G26 DQA0_12 MAA1_1/MAA_9 J11 M_MA10
M_DA14 D26 DQA0_13 MAA1_2/MAA_10 J13 M_MA11
M_DA15 F25 DQA0_14 MAA1_3/MAA_11 H11 M_MA12
M_DA16 A25 DQA0_15 MAA1_4/MAA_12 G11 M_BA2
DQA0_16 MAA1_5/MAA_BA2 M_BA2 <19,20>
M_DA17 C25 J16 M_BA0
DQA0_17 MAA1_6/MAA_BA0 M_BA0 <19,20>
M_DA18 E25 L15 M_BA1
DQA0_18 MAA1_7/MAA_BA1 M_BA1 <19,20>
M_DA19 D24 G14 M_MA14
M_DA20 E23 DQA0_19 MAA1_8/MAA_14 L16
MEMORY INTERFACE
M_DA21 F23 DQA0_20 MAA1_9/RSVD
M_DA22 D22 DQA0_21 E32 M_DQM0
+1.35VGS M_DA23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 M_DQM1
M_DA24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 M_DQM2
M_DA25 D20 DQA0_24 WCKA0_1/DQMA0_2 C21 M_DQM3
M_DA26 F19 DQA0_25 WCKA0B_1/DQMA0_3 E13 M_DQM4
DQA0_26 WCKA1_0/DQMA1_0
1
M_DA27 A19 D12 M_DQM5

PX@ M_DA28 D18 DQA0_27 WCKA1B_0/DQMA1_1 E3 M_DQM6
RV44 M_DA29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 M_DQM7
40.2_0402_1% M_DA30 A17 DQA0_29 WCKA1B_1/DQMA1_3
M_DA31 C17 DQA0_30 H28 M_DQS0
2
M_DA32 E17 DQA0_31 EDCA0_0/QSA0_0 C27 M_DQS1

M_DA33 D16 DQA1_0 EDCA0_1/QSA0_1 A23 M_DQS2
M_DA34 F15 DQA1_1 EDCA0_2/QSA0_2 E19 M_DQS3
B
M_DA35 A15 DQA1_2 EDCA0_3/QSA0_3 E15 M_DQS4 B
DQA1_3 EDCA1_0/QSA1_0
1
1 M_DA36 D14 D10 M_DQS5

PX@ PX@ M_DA37 F13 DQA1_4 EDCA1_1/QSA1_1 D6 M_DQS6
RV46 CV65 M_DA38 A13 DQA1_5 EDCA1_2/QSA1_2 G5 M_DQS7
100_0402_1% 1U_0402_6.3V6K M_DA39 C13 DQA1_6 EDCA1_3/QSA1_3
2 M_DA40 E11 DQA1_7 H27 M_DQS#0
2
M_DA41 A11 DQA1_8 DDBIA0_0/QSA0_0B A27 M_DQS#1

M_DA42 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 M_DQS#2
M_DA43 F11 DQA1_10 DDBIA0_2/QSA0_2B C19 M_DQS#3
M_DA44 A9 DQA1_11 DDBIA0_3/QSA0_3B C15 M_DQS#4
M_DA45 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 M_DQS#5
M_DA46 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 M_DQS#6
M_DA47 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 M_DQS#7
+1.35VGS M_DA48 E7 DQA1_15 DDBIA1_3/QSA1_3B
M_DA49 A7 DQA1_16 L18 VRAM_ODT0
DQA1_17 ADBIA0/ODTA0 VRAM_ODT0 <19>
M_DA50 C7 K16 VRAM_ODT1
DQA1_18 ADBIA1/ODTA1 VRAM_ODT1 <20>
M_DA51 F7
DQA1_19
1
M_DA52 A5 H26 M_CLK0

DQA1_20 CLKA0 M_CLK0 <19>
PX@ E5 H25
DQA1_21 CLKA0B M_CLK#0 <19>
RV45 M_DA54 C3
40.2_0402_1% M_DA55 E1 DQA1_22 G9 M_CLK1
DQA1_23 CLKA1 M_CLK1 <20>
M_DA56 G7 H9 M_CLK#1
M_CLK#1 <20>
2
M_DA57 G6 DQA1_24 CLKA1B

M_DA58 G1 DQA1_25 G22 M_RAS#0
DQA1_26 RASA0B M_RAS#0 <19>
M_DA59 G3 G17 M_RAS#1
DQA1_27 RASA1B M_RAS#1 <20>
M_DA60 J6
DQA1_28
1
J1 G19
DQA1_29 CASA0B M_CAS#0 <19>
PX@ PX@ M_DA62 J3 G16 M_CAS#1
DQA1_30 CASA1B M_CAS#1 <20>
RV47 CV66 M_DA63 J5
100_0402_1% 1U_0402_6.3V6K DQA1_31 H22 M_CS0B#0
2 CSA0B_0 M_CS0B#0 <19>
+MVREFDA K26 J22
2
+MVREFSA J26 MVREFDA CSA0B_1

MVREFSA G13 M_CS1B#0
CSA1B_0 M_CS1B#0 <20>
J25 K13
RV52 1 PX@ 2 120_0402_1% K25 NC#J25 CSA1B_1
C C
MEM_CALRP0 K20 M_CKE0
CKEA0 M_CKE0 <19>
PX@ PX@ J17 M_CKE1
CKEA1 M_CKE1 <20>
RV48 RV49
49.9_0402_1% 10_0402_1% G25 M_WE#0
WEA0B M_WE#0 <19>
1 2 2 1 DRST L10 H10 M_WE#1
<19,20> DRAM_RST DRAM_RST WEA1B M_WE#1 <20>
1 RV54 @ 1 2 51.1_0402_1% CV69 @1

@ 2 0.1U_0201_10V7K K8
CLKTESTA
1
1 @ RV55 @ 1 2 51.1_0402_1% CV70 @

@1 2 L7
PX@ PX@ CV67 0.1U_0201_10V7K CLKTESTB
CV68 RV50 68P_0402_50V8J
120P_0402_50V8J 5.1K_0402_1% 2 Route 50ohms single-ended/100ohm diff and keep short
216-0841018 A0 SUN PRO S3
2 debug only, for clock observation,if not need, DNI. ?
2
Place close to GPU (within 25mm)

and place componment close to each other
D D

EXO/MESO(5/5)_MEM
Custom 1.0
LA-C293P
1 2 3 4 5
1 2 3 4 5
DDR3L Memory Channel Rank 0:A0

M_DA[63..0]
<18,20> M_DA[63..0]
M_MA[15..0]
<18,20> M_MA[15..0]
M_DQM[7..0] +1.35VGS +1.35VGS
<18,20> M_DQM[7..0]
M_DQS[7..0]
<18,20> M_DQS[7..0]
1
A M_DQS#[7..0] PX@ PX@ A
<18,20> M_DQS#[7..0]
RV63 RV62
4.99K_0402_1% UV5 4.99K_0402_1% UV6
2
+FBA_VREF0 M8 E3 M_DA8 +FBA_VREF1 M8 E3 M_DA18
H1 VREFCA DQL0 F7 M_DA14 H1 VREFCA DQL0 F7 M_DA19
VREFDQ DQL1 F2 M_DA10 VREFDQ DQL1 F2 M_DA16
DQL2 DQL2
1
PX@
1
PX@
M_MA0
M_MA1
N3
P7 A0 DQL3
F8
H3
M_DA13
M_DA9 PX@
1
PX@
M_MA0
M_MA1
N3
P7 A0 DQL3
F8
H3
M_DA20
M_DA21
+EC_VCCA
RV75 CV72 M_MA2 P3 A1 DQL4 H8 M_DA12 RV66 CV71 M_MA2 P3 A1 DQL4 H8 M_DA23
4.99K_0402_1% 0.1U_0201_10V7K M_MA3 N2 A2 DQL5 G2 M_DA11 4.99K_0402_1% 0.1U_0201_10V7K M_MA3 N2 A2 DQL5 G2 M_DA17
2 M_MA4 P8 A3 DQL6 H7 M_DA15 2 M_MA4 P8 A3 DQL6 H7 M_DA22
2
M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7
16.5K_0402_1%
A5 A5
1
M_MA6 R8 M_MA6 R8
M_MA7 R2 A6 D7 M_DA5 M_MA7 R2 A6 D7 M_DA31
RV374
M_MA8 T8 A7 DQU0 C3 M_DA3 M_MA8 T8 A7 DQU0 C3 M_DA27 PX@
M_MA9 R3 A8 DQU1 C8 M_DA6 M_MA9 R3 A8 DQU1 C8 M_DA30
M_MA10 L7 A9 DQU2 C2 M_DA2 M_MA10 L7 A9 DQU2 C2 M_DA24
2
M_MA11 R7 A10/AP DQU3 A7 M_DA4 M_MA11 R7 A10/AP DQU3 A7 M_DA28
M_MA12 N7 A11 DQU4 A2 M_DA1 M_MA12 N7 A11 DQU4 A2 M_DA25 <31> VRAM_TEMP
M_MA13 T3 A12 DQU5 B8 M_DA7 M_MA13 T3 A12 DQU5 B8 M_DA29
M_MA14 T7 A13 DQU6 A3 M_DA0 M_MA14 T7 A13 DQU6 A3 M_DA26
A14 DQU7 A14 DQU7
1
M_MA15 M7 M_MA15 M7
A15/BA3 +1.35VGS A15/BA3 +1.35VGS PHV1
PX@ 100K_0402_1%_TSM0B104F4251RZ
M_BA0 M2 B2 M_BA0 M2 B2
<18,20> M_BA0 BA0 VDD BA0 VDD
M_BA1 N8 D9 M_BA1 N8 D9
<18,20> M_BA1
2
M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7
K2 K2
VDD K8 VDD K8
VDD N1 VDD N1
M_CLK0 M_CLK0 J7 VDD N9 M_CLK0 J7 VDD N9
<18> M_CLK0 CK VDD CK VDD
M_CLK#0 M_CLK#0 K7 R1 M_CLK#0 K7 R1
<18> M_CLK#0 CK VDD CK VDD
M_CKE0 K9 R9 M_CKE0 K9 R9
<18> M_CKE0 CKE/CKE0 VDD +1.35VGS CKE/CKE0 VDD +1.35VGS
1
B B
PX@ PX@ ECAGND
RV102 RV103 VRAM_ODT0 K1 A1 VRAM_ODT0 K1 A1
<18> VRAM_ODT0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
40.2_0402_1% 40.2_0402_1% M_CS0B#0 L2 A8 M_CS0B#0 L2 A8
<18> M_CS0B#0 CS/CS0 VDDQ CS/CS0 VDDQ
M_RAS#0 J3 C1 M_RAS#0 J3 C1
<18> M_RAS#0 RAS VDDQ RAS VDDQ
M_CAS#0 K3 C9 M_CAS#0 K3 C9
<18> M_CAS#0
2
M_WE#0 L3 CAS VDDQ D2 M_WE#0 L3 CAS VDDQ D2

<18> M_WE#0 WE VDDQ WE VDDQ
E9 E9
VDDQ F1 VDDQ F1
M_DQS1 F3 VDDQ H2 M_DQS2 F3 VDDQ H2
1 DQSL VDDQ DQSL VDDQ
PX@ M_DQS0 C7 H9 M_DQS3 C7 H9
CV73 DQSU VDDQ DQSU VDDQ
0.01U_0402_16V7K
2 M_DQM1 E7 A9 M_DQM2 E7 A9
M_DQM0 D3 DML VSS B3 M_DQM3 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS G8 VSS G8
M_DQS#1 G3 VSS J2 M_DQS#2 G3 VSS J2
VSS J8 M_DQS#3 B7 DQSL VSS J8
VSS VSS
VSS M9 VSS M9
VSS P1 VSS P1
DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9
<18,20> DRAM_RST RESET VSS VSS
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
J1 B1 J1 B1
PX@ L1 NC/ODT1 VSSQ B9 PX@ L1 NC/ODT1 VSSQ B9
RV111 J9 NC/CS1 VSSQ D1 RV110 J9 NC/CS1 VSSQ D1
243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
SINGLE RANK:RV102,RV103 install 40.2 ohms
2
2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
C C
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96
X76@ X76@
+1.35VGS +1.35VGS +1.35VGS

10U_0603_6.3V6M
CV105
1U_0402_6.3V6K
CV106
1U_0402_6.3V6K
CV107
1U_0402_6.3V6K
CV108
1U_0402_6.3V6K
CV109
1U_0402_6.3V6K
CV112
1U_0402_6.3V6K
CV113
0.1U_0201_10V7K
CV125
10U_0603_6.3V6M
CV115
10U_0603_6.3V6M
CV116
1U_0402_6.3V6K
CV117
1U_0402_6.3V6K
CV120
1U_0402_6.3V6K
CV121
1U_0402_6.3V6K
CV126
1U_0402_6.3V6K
CV123
1U_0402_6.3V6K
CV122
1U_0402_6.3V6K
CV124
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
@
D D

EXO/MESO_DDR3L_A1 Rank 0
Custom 1.0
LA-C293P
1 2 3 4 5
1 2 3 4 5
DDR3L Memory Channel Rank 0:A1

+1.35VGS
+1.35VGS
1
1
PX@
PX@ RV119
RV118 4.99K_0402_1% UV4
4.99K_0402_1% UV3
2
A M_DA[63..0] +FBA_VREF3 M8 E3 M_DA34 A
<18,19> M_DA[63..0]
2
+FBA_VREF2 M8 E3 M_DA58 H1 VREFCA DQL0 F7 M_DA38
M_MA[15..0] H1 VREFCA DQL0 F7 M_DA61 VREFDQ DQL1 F2 M_DA35
<18,19> M_MA[15..0] VREFDQ DQL1 DQL2
1
F2 M_DA59 1 M_MA0 N3 F8 M_DA39
DQL2 A0 DQL3
1
M_DQM[7..0] 1 M_MA0 N3 F8 M_DA62 PX@ PX@ M_MA1 P7 H3 M_DA32
<18,19> M_DQM[7..0] A0 DQL3 A1 DQL4
PX@ PX@ M_MA1 P7 H3 M_DA56 RV127 CV118 M_MA2 P3 H8 M_DA37
M_DQS[7..0] RV126 CV119 M_MA2 P3 A1 DQL4 H8 M_DA63 4.99K_0402_1% 0.1U_0201_10V7K M_MA3 N2 A2 DQL5 G2 M_DA33
<18,19> M_DQS[7..0] A2 DQL5 2 A3 DQL6
4.99K_0402_1% 0.1U_0201_10V7K M_MA3 N2 G2 M_DA57 M_MA4 P8 H7 M_DA36
2
M_DQS#[7..0] 2 M_MA4 P8 A3 DQL6 H7 M_DA60 M_MA5 P2 A4 DQL7
<18,19> M_DQS#[7..0]
2
M_MA5 P2 A4 DQL7 M_MA6 R8 A5
M_MA6 R8 A5 M_MA7 R2 A6 D7 M_DA47
M_MA7 R2 A6 D7 M_DA52 M_MA8 T8 A7 DQU0 C3 M_DA43
M_MA8 T8 A7 DQU0 C3 M_DA51 M_MA9 R3 A8 DQU1 C8 M_DA46
M_MA9 R3 A8 DQU1 C8 M_DA55 M_MA10 L7 A9 DQU2 C2 M_DA42
M_MA10 L7 A9 DQU2 C2 M_DA50 M_MA11 R7 A10/AP DQU3 A7 M_DA44
M_MA11 R7 A10/AP DQU3 A7 M_DA54 M_MA12 N7 A11 DQU4 A2 M_DA41
M_MA12 N7 A11 DQU4 A2 M_DA49 M_MA13 T3 A12 DQU5 B8 M_DA45
M_MA13 T3 A12 DQU5 B8 M_DA53 M_MA14 T7 A13 DQU6 A3 M_DA40
M_MA14 T7 A13 DQU6 A3 M_DA48 M_MA15 M7 A14 DQU7
M_MA15 M7 A14 DQU7 A15/BA3 +1.35VGS
A15/BA3 +1.35VGS
M_BA0 M2 B2
M_BA0 M2 B2 M_BA1 N8 BA0 VDD D9
M_BA1 N8 D9 M_BA2 M3 G7
M_BA2 M3 G7 K2
<18,19> M_BA2 BA2 VDD VDD
M_CLK1 K2 K8
M_CLK#1 VDD K8 VDD N1
VDD N1 M_CLK1 J7 VDD N9
M_CLK1 J7 VDD N9 M_CLK#1 K7 CK VDD R1
<18> M_CLK1 CK VDD CK VDD
1
PX@ PX@ M_CLK#1 K7 R1 M_CKE1 K9 R9

<18> M_CLK#1 CK VDD CKE/CKE0 VDD +1.35VGS
RV139 RV140 M_CKE1 K9 R9
<18> M_CKE1 CKE/CKE0 VDD +1.35VGS
40.2_0402_1% 40.2_0402_1%
VRAM_ODT1 K1 A1
VRAM_ODT1 K1 A1 M_CS1B#0 L2 ODT/ODT0 VDDQ A8
<18> VRAM_ODT1
2
M_CS1B#0 L2 ODT/ODT0 VDDQ A8 M_RAS#1 J3 CS/CS0 VDDQ C1

B <18> M_CS1B#0 CS/CS0 VDDQ RAS VDDQ B
M_RAS#1 J3 C1 M_CAS#1 K3 C9
<18> M_RAS#1 RAS VDDQ CAS VDDQ
M_CAS#1 K3 C9 M_WE#1 L3 D2
<18> M_CAS#1 CAS VDDQ WE VDDQ
1 M_WE#1 L3 D2 E9
<18> M_WE#1 WE VDDQ VDDQ
PX@ E9 F1
CV154 VDDQ F1 M_DQS4 F3 VDDQ H2
0.01U_0402_16V7K M_DQS7 F3 VDDQ H2 M_DQS5 C7 DQSL VDDQ H9
2 M_DQS6 C7 DQSL VDDQ H9 DQSU VDDQ
DQSU VDDQ
M_DQM4 E7 A9
M_DQM7 E7 A9 M_DQM5 D3 DML VSS B3
FOR PE Bruce
M_DQM6 D3 DML VSS B3 DMU VSS E1
DMU VSS E1 VSS G8
VSS G8 M_DQS#4 G3 VSS J2
M_DQS#7 G3 VSS J2 M_DQS#5 B7 DQSL VSS J8
M_DQS#6 B7 DQSL VSS J8 DQSU VSS M1
DQSU VSS M1 VSS M9
VSS M9 VSS P1
VSS P1 DRAM_RST T2 VSS P9
DRAM_RST T2 VSS P9 RESET VSS T1
<18,19> DRAM_RST RESET VSS VSS
T1 L8 T9
L8 VSS T9 ZQ/ZQ0 VSS
ZQ/ZQ0 VSS
1
J1 B1
NC/ODT1 VSSQ
1
J1 B1 PX@ L1 B9
PX@ L1 NC/ODT1 VSSQ B9 RV138 J9 NC/CS1 VSSQ D1
RV137 J9 NC/CS1 VSSQ D1 243_0402_1% L9 NC/CE1 VSSQ D8
243_0402_1% L9 NC/CE1 VSSQ D8 NCZQ1 VSSQ E2
2
NCZQ1 VSSQ E2 VSSQ E8
SINGLE RANK:RV139,RV140 install 40.2 ohms
2
VSSQ E8 VSSQ F9
VSSQ F9 VSSQ G1
VSSQ G1 VSSQ G9
VSSQ G9 VSSQ
VSSQ 96-BALL
96-BALL SDRAM DDR3
C SDRAM DDR3 H5TC2G63FFR-11C_FBGA96 C
H5TC2G63FFR-11C_FBGA96 X76@
X76@
+1.35VGS +1.35VGS +1.35VGS

10U_0603_6.3V6M
CV128
1U_0402_6.3V6K
CV152
1U_0402_6.3V6K
CV158
1U_0402_6.3V6K
CV132
1U_0402_6.3V6K
CV164
0.1U_0201_10V7K
CV134
1U_0402_6.3V6K
CV135
1U_0402_6.3V6K
CV136
10U_0603_6.3V6M
CV138
10U_0603_6.3V6M
CV139
1U_0402_6.3V6K
CV141
1U_0402_6.3V6K
CV144
1U_0402_6.3V6K
CV145
1U_0402_6.3V6K
CV146
0.1U_0201_10V7K
CV147
1U_0402_6.3V6K
CV193
1U_0402_6.3V6K
CV148
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
D D

EXO/MESO_DDR3L_A2 Rank 0
Custom 1.0
LA-C293P
1 2 3 4 5
5 4 3 2 1
LCD POWER CIRCUIT

CMOS Camera
+3VS
@
+3VS R190 1 2 0_0603_5%
+LCDVDD_CONN
D U5 D
5 1 +LCDVDD_CONN_R R139 2 @ 1 0_0603_5% +3VS_CMOS
IN OUT Q4
4.7U_0603_6.3V6K
2 PMV65XP_SOT23-3
GND
C128
1
R132 1 2 0_0402_5% 4 3 3 1
D
@ ENVDD 10U
<31,7> SOC_ENVDD EN OC
1
R134 1 2 G524B1T11U SOT-23 5P CMOS@ C129 @
<31> EC_ENVDD
2
1
@ 0_0402_5% 2 C130
G
2
R120 SA00006Y800 CMOS@ 10U_0603_6.3V6M
@ 100K_0402_5% R119 CMOS@ 0.1U_0201_10V7K 2
2
150K_0402_5%
<31> CMOS_ON#
1
C132
1
CMOS@
0.1U_0201_10V7K
2
C C
VGA LCD/PANEL BD. Conn.

+LEDVDD B+
5
U15
2
From APU
P
<31,7> ENBKL B 4 1 2 0_0805_5%

DISPOFF# R121 @
From EC
G
2
C133
3
2
R124 4.7U_0805_25V6-K
R211 10K_0402_5%
100K_0402_5%
1
1
JLVDS1
R123 1 @ 2 0_0402_5% 1
2 1 41
3 2 G1 42
4 3 G2 43
5 4 G3 44
5 G4
6 G5
1
7 46
DISPOFF# 8 7 G6
R126 1 2 0_0402_5% EDP_HPD_R R826 @ EDP_HPD_R 9 8
<7> EDP_HPD 100K_0402_5% 10 9
B 11 10 B
+LCDVDD_CONN
2
12 11
eDP (60 MIL) 12
13
14 13
C134 1 2 0.1U_0201_10V7K EDP_AUXN_C 15 14
<7> EDP_AUXN 15
<7> EDP_AUXP C135 1 2 0.1U_0201_10V7K EDP_AUXP_C 16
17 16
C136 1 2 0.1U_0201_10V7K EDP_TXP0_C 18 17
<7> EDP_TXP0 18
<7> EDP_TXN0 C137 1 2 0.1U_0201_10V7K EDP_TXN0_C 19
20 19
FHD@ C138 1 2 0.1U_0201_10V7K EDP_TXP1_C 21 20
<7> EDP_TXP1 21
<7> EDP_TXN1 FHD@ C139 1 2 0.1U_0201_10V7K EDP_TXN1_C 22
23 22
24 23
R125 1 2 0_0201_5% 25 24
26 25
27 26
L6 EMIU@ 28 27
2 3 USB20_P3_R
Touch Screen (reserved) USB20_P1_R 29 28
<9> USB20_P3 2 3 29
USB20_N1_R 30
31 30
1 4 USB20_N3_R R122 1 2 0_0402_5% TS_RST# 32 31
Camera <9> USB20_N3 1 4 <31> TS_DISABLE#
R270 2 @ 1 0_0603_5% +3VS_TS 33 32
PANASONIC EXC24CQ900U +3VS 33
34
+3VS_CMOS 34
SM070004400 USB20_N3_R 35
USB20_P3_R 36 35
CMOS 36
R127 1 2 0_0201_5%
Camera 37
38 37
<28> DMIC_CLK 38
DMIC <28> DMIC_DAT
39
39
40
+3VS 40
E-T_0871K-F40N-00L
A ME@ A
R129 1 TS@ 2 0_0201_5% SP010011Z00
SM070004400
PANASONIC EXC24CQ900U
1 4 USB20_P1_R
<9> USB20_P1 1 4
Touch Screen
<9> USB20_N1
2
2 3
3 USB20_N1_R Security Classification Compal Secret Data Compal Electronics, Inc.
L7 EMIU@
EDP CONN / Camera
Size
Document Number Rev
R130 2 1 0_0201_5% B 1.0
TS@
LA-C293P
5 4 3 2 1
5 4 3 2 1
+3VS_DP
Hybrid DDC/AUX
+3VS +3VS_DP
R77
@
R81
R79
RD22 2 1 0_0603_5%
1
+3VS_DP
4.7K_0402_5%
CZL@ CZL@ CZL@
10K_0402_5%
10K_0402_5%
+3VS_DP
1 CD1 1 CD2 1 CD3 1 CD4
0.1U_0201_10V7K
CZL@
0.01U_0402_16V7K
CZL@
0.1U_0201_10V7K
CZL@
0.01U_0402_16V7K
CZL@
IN_CA_DET#
2
D 2 2 2 2
2 IN_CA_DET RD25
3
D S S D
G CRT@ 100K_0402_5%
PMV65XP_SOT23-3
G G
2 2 S 2N7002H_SOT23-3
3
Q10 Q102
1
CZL@ D D PMV65XP_SOT23-3
1
Q11 CZL@
CZL@
Pin14 Pin28 Pin41 Pin56 DP_CRT_AUXN
CZL@
C157 1 2 0.1U_0201_10V7K DP1_MUX_AUXP DP_CRT_AUXP
<7> DP1_DDC_SCL
C174 1 2 0.1U_0201_10V7K DP1_MUX_AUXN
<7> DP1_DDC_SDA
CZL@
2
+3VS_DP +3VS_DP RD26
DP_Switching Function (For Automatic Switching) UD1 CRT@ 100K_0402_5%
14 40
H TMDS output has higher priority DP_CRT_P0 <23>
＊L
+3VS_DP 28 VDD33 DP_D0p 39
DP_CRT_N0 <23>
1
VDD33 DP_D0n
2
DP output has higher priority 41
@ 56 VDD33 37
VDD33 DP_D1p DP_CRT_P1 <23>
2
RD2 36 DP_CRT_N1 <23>

@ 4.7K_0402_5% DP_CFG0 44 DP_D1n
RD14 DP_Switching 45 DP_CFG0/SCL_CTL 34
1
4.7K_0402_5% I2C_CTL_EN 38 SW/SDA_CTL DP_D2p 33
I2C_CTL_EN DP_D2n To CRT Translator
TMDS_DDCBUF Function
1
2
TMDS_DDCBUF CZL@ CZL@ <7> DP1_P0 CZL@ CD6 1 2 0.1U_0201_10V7K CPU_DP1_P0_C 3 31
CZL@ CD7 1 2 0.1U_0201_10V7K CPU_DP1_N0_C 4 IN_D0p DP_D3p 30
H DDC active buffer <7> DP1_N0 IN_D0n DP_D3n
2
RD4
RD1
CZL@ M DDC pass through with 40 kohm pull up resistor <7> DP1_P1 CZL@ CD5 1 2 0.1U_0201_10V7K CPU_DP1_P1_C 6 55
1 2 7 IN_D1p DP_AUXp_SCL 54 DP_CRT_AUXP <23>
RD17 <7> DP1_N1 CZL@ CD8 0.1U_0201_10V7K CPU_DP1_N1_C
DP_CRT_AUXN <23>
1
4.7K_0402_5% IN_D1n DP_AUXn_SDA 32
L DDC pass through DP_HPD DP_CRT_HPD <23>
4.7K_0402_5%
4.7K_0402_5%
<7> DP1_P2 CZL@ CD9 1 2 0.1U_0201_10V7K CPU_DP1_P2_C 9
1
CZL@ CD10 1 2 0.1U_0201_10V7K CPU_DP1_N2_C 10 IN_D2p

<7> DP1_N2 IN_D2n 42 RD20 1CZL@ 2 1M_0402_5%
CZL@ CD11 1 2 0.1U_0201_10V7K CPU_DP1_P3_C 12 DP_CA_DET
<7> DP1_P3 IN_D3p
From CPU <7> DP1_N3 CZL@ CD12 1 2 0.1U_0201_10V7K CPU_DP1_N3_C 13 29 DP_CFG1
+3VS_DP IN_D3n DP_CFG1
DP1_MUX_AUXP 52 19
IN_AUXp TMDS_CH0p HDMI_TX0+ <24>
C DP1_MUX_AUXN 51 18 HDMI_TX0- <24> C
IN_AUXn TMDS_CH0n
2
DP1_DDC_SCL 50 22 HDMI_TX1+ <24>

RD15 DP1_DDC_SDA 49 IN_DDC_SCL TMDS_CH1p 21
IN_DDC_SDA TMDS_CH1n HDMI_TX1- <24>
4.7K_0402_5% TMDS_RT Function IN_CA_DET 11 25 HDMI_TX2+ <24>
1
TMDS_RT IN_CA_DET TMDS_CH2p 24

H Open drain driver with termination resistors 5 TMDS_CH2n HDMI_TX2- <24> To HDMI
<7> DP1_HPD IN_HPD
2
16
@
L Standard open drain driver TMDS_CLKp 15
HDMI_CLK+ <24>
TMDS_CLKn HDMI_CLK- <24>
RD18
4.7K_0402_5% 1 48
CEXT TMDS_SCL HDMICLK_R <24>
2.2U_0402_6.3V6M
CD15
CZL@
1 47
HDMIDAT_R <24>
1
TMDS_DDCBUF 2 TMDS_SDA
17
TMDS_HPD HDMI_DET_R <24>
DPSW_PEQ 8
+3VS_DP 27 TMDS_RT 20 TMDS_PRE

REXT TMDS_PRE
4.42K_0402_1%
1
RD5
CZL@
GND
2
2 1 DP_MODE 53 GND 43
+3VS_DP MODE GND
RD16 TMDS_PRE
2
4.7K_0402_5%
RD7
CZL@
4.7K_0402_5% 4.7K_0402_5%
2
H 1.5dB pre-emphasis CZL@
1
TMDS_PRE CZL@
M 3.0dB pre-emphasis
2
1
@ L no pre-emphasis
RD19
4.7K_0402_5%
1
DP_MODE Function
H Automatic Switching Mode, HDMI ID disable
＊M (VDD33/2)
+3VS_DP
B Automatic Switching Mode, HDMI ID enable B
2
@
L Control Switching Mode, HDMI ID disable
RD10 DPSW_PEQ Function
4.7K_0402_5%
H HEQ, compensate channel loss up to 15dB @ HBR2
1
DPSW_PEQ
M LLEQ, compensate channel loss up to 5dB @ HBR2
2
@ RP37
RD13
L default, LEQ, compensate channel loss up to 12dB @ HBR2 For CZ only <7> DP2_N1 DP2_N1 1 8 HDMI_TX1-
4.7K_0402_5% DP2_P1 2 7 HDMI_TX1+
<7> DP2_P1
RP41 RP43 <7> DP2_N0 DP2_N0 3 6 HDMI_TX2-
1
DP1_N1 1 8 DP1_N1_R 1 8 DP_CRT_N1 DP2_P0 4 5 HDMI_TX2+

<7> DP2_P0
DP1_P1 2 7 DP1_P1_R 2 7 DP_CRT_P1
DP1_N0 3 6 DP1_N0_R 3 6 DP_CRT_N0 0_0804_8P4R_5%
DP1_P0 4 5 DP1_P0_R 4 5 DP_CRT_P0 CZ@
+3VS_DP From CPU
0_0804_8P4R_5% 0_0804_8P4R_5% RP38
CZ@ CZ@ <7> DP2_N3 DP2_N3 1 8 HDMI_CLK-
2
DP2_P3 2 7 HDMI_CLK+
<7> DP2_P3
@ DP1_DDC_SCL RD23 1 CZ@ 2 0_0402_5% DP_CRT_AUXP <7> DP2_N2 DP2_N2 3 6 HDMI_TX0-
RD8 DP_CFG0 Function DP1_DDC_SDA RD24 1 CZ@ 2 0_0402_5% DP_CRT_AUXN <7> DP2_P2 DP2_P2 4 5 HDMI_TX0+
4.7K_0402_5%
H automatic EQ disable & AUX interception enable 0_0804_8P4R_5%
1
DP_CFG0 DP1_HPD RD27 1 CZ@ 2 0_0402_5% DP_CRT_HPD CZ@

M automatic EQ disable & AUX interception disable, no pre-emphasis, 800mVpp swing
2
@ L default, automatic EQ enable & AUX interception enable

RD11
4.7K_0402_5%
1
+3VS_DP
A A
2
@
RD9
4.7K_0402_5% DP_CFG1 Function
1
DP_CFG1
H auto test enable & input offset cancellation enable
M auto test disable & input offset cancellation disable
2
@ L default, auto test disable & input offset cancellation enable

RD12
4.7K_0402_5% 2015/03/06 2016/03/06 Title
DP Switch
1
C 1.0
LA-C293P
5 4 3 2 1
5 4 3 2 1
D D
+3VS
RT5 CRT@
2 1 +3VS_CRT
BLM15BD121SN1D_0402
10U_0805_25V6K
CRT@
CRT@
CRT@
CRT@
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
2 2 2
CT4 1 2
1 1 1
CT1
CT2
CT3
+5VS
@ RT1
1 2
20
UT1
9
1
@ 0_0402_5%
DVCC_33
DVCC_33
VDD_DAC_33
<22> DP_CRT_HPD DP_CRT_HPD 1 CT7
HPD
0.1U_0201_10V7K
CT5 1 2 0.1U_0201_10V7K DP_CRT_AUXN_C 27 6 CRT_DATA 2
<22> DP_CRT_AUXN AUX_N VGA_SDA
1
CT6 1 2 0.1U_0201_10V7K DP_CRT_AUXP_C 26 4 CRT_CLK
<22> DP_CRT_AUXP AUX_P VGA_SCL 8 HSYNC
OE#
P
CT22 1 2 0.1U_0201_10V7K DP_CRT_P0_C 29 HSYNC 7 VSYNC VSYNC 2 4 CRT_VSYNC_1 RT2 @ 1 2 36_0402_5% CRT_VSYNC_2
<22> DP_CRT_P0 LANE0P VSYNC A Y
CT23 1 2 0.1U_0201_10V7K DP_CRT_N0_C 30
<22> DP_CRT_N0 LANE0N
G
15 CRT_R UT2 @ 1
CT24 1 2 0.1U_0201_10V7K DP_CRT_P1_C 31 RED_P SN74AHCT1G125DCKR_SC70-5
<22> DP_CRT_P1
3
CT25 1 2 0.1U_0201_10V7K DP_CRT_N1_C 32 LANE1P 12 CRT_G @ CT8
<22> DP_CRT_N1 LANE1N GREEN_P
C RT7 CRT@ 10P_0402_50V8J C
2 1 10 CRT_B
+3VS BLUE_P
BLM15BD121SN1D_0402
22 POL1_SDA
CT9 CRT@ 2 1 2.2U_0402_6.3V6M POL1_SDA 23 POL2_SCL +5VS
POL2_SCL
8
7
6
5
CRT@ @ RT3
CT10 CRT@ 2 1 0.1U_0201_10V7K VCCK_12 19 2 RT19 1 @ 2 0_0402_5% RPT1 1 2
VCCK_12 SMB_SCL EC_SMB_CK2 <15,31,32,7>
3 RT20 1 @ 2 0_0402_5% 75_0804_8P4R_1% 1
SMB_SDA EC_SMB_DA2 <15,31,32,7>
CT11 CRT@ 2 1 0.1U_0201_10V7K AVCC_33 24 @ 0_0402_5%
AVCC_33 CT12
1
2
3
4
CT13 CRT@ 2 1 0.1U_0201_10V7K VCCK_12 25 0.1U_0201_10V7K
AVCC_12 21 LDO_EN 2
1
DP_CRT_HPD RRX
OE#
P
18 HSYNC 2 4 CRT_HSYNC_1 RT4 @ 1 2 33_0402_5% CRT_HSYNC_2
A Y
BLUE_N
G
13 17 UT3 @
GREEN_N XI/CKIN
1
14 SN74AHCT1G125DCKR_SC70-5 1
3
CZ@ 16 GND_DAC @
RT18 RED_N CT14
100K_0402_5% EPAD_GND 10P_0402_50V8J
2
2
RT8 CRT@ 1 2 36_0402_5%

10U_0805_25V6K
CRT@
RTD2168-CG_QFN32_5X5
21
CT15
+3VS +3VS +3VS

4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
1
1
CRT@RT12
RT12
CRT@RT10
CRT@RT10
@RT11
RT11
CRT@
B B
@
+5V_Display
2
POL2_SCL POL1_SDA LDO_EN

4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
1
1
@RT15
RT15
@RT13
RT13
CRT@RT14
CRT@RT14
CRT@ RT16
CRT@ RT17
@
@
2
EMI
1
2.2K_0402_5%
2.2K_0402_5%
CRT
2
SM01000LU00 +5V_Display
ESD SM01000LU00
SM01000LU00
LT1 EMIP@ TP1 6
JCRT1
BLM15BA220SN1D 0402 1JCRT_PIN11_TEST 11

+5VS CRT_R 1 2 CRT_R_2 1
LT2 EMIP@ 7
BLM15BA220SN1D 0402 CRT_DATA 12
DT1 ESDU@ CRT_G 1 2 CRT_G_2 2
CRT_CLK 6 3 CRT_HSYNC_2 LT3 EMIP@ 8
I/O4 I/O2 BLM15BA220SN1D 0402 CRT_HSYNC_2 13
CRT_B 1 2 CRT_B_2 3
9
CT16
CT17
CT18
CT19
CT20
CT21
5 2 CRT_VSYNC_2 14 16
VDD GND G
1 1 1 1 1 1 4 17
G
EMIP@
EMIP@
EMIP@
EMIP@
EMIP@
EMIP@
10
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J
CRT_CLK 15
CRT_VSYNC_2 4 1 CRT_DATA 5
I/O3 I/O1 2 2 2 2 2 2
AZC099-04S.R7G_SOT23-6 C-H_13-12201557CP
A DC060006G00 A
+5VS DT2 ESDU@ ME@
CRT_R_2 6 3 CRT_B_2
I/O4 I/O2
5 2
VDD GND
CRT_G_2 4 1
I/O3 I/O1 Security Classification Compal Secret Data Compal Electronics, Inc.
AZC099-04S.R7G_SOT23-6 2015/03/06 2016/03/06 Title
DP to VGA - RTD2168
C 1.0
LA-C293P
5 4 3 2 1
5 4 3 2 1
ZZZ1 45@
HDMI Logo
RO0000003HM
D D
+5V_Display
Near HDMI CONN EMI +5VS
U6
3
C229 CZ@ EMIP@ L8 SM070002R00 OUT
1
CZL@ <22> HDMI_CLK- C229 1 2 0.1U_0201_10V7K HDMI_CLKN 2 3 HDMI_CLK-_CONN 1
S RES 1/20W 0 +-5% 0201 2 3 IN C140
1
CZ@ 2
C230 C230 1 2 0.1U_0201_10V7K HDMI_CLKP 1 4 HDMI_CLK+_CONN C141 GND 0.1U_0201_10V7K 2
<22> HDMI_CLK+ 1 4
CZL@
S RES 1/20W 0 +-5% 0201 PANASONIC EXC24CG900U 0.1U_0201_10V7K 2 AP2330W-7_SC59-3
C231 CZ@ EMIP@ L9 SM070002R00

CZL@ C231 1 2 0.1U_0201_10V7K HDMI_TX0N 2 3 HDMI_TX0-_CONN +3VS
<22> HDMI_TX0- 2 3
S RES 1/20W 0 +-5% 0201
CZ@ For CRT and HDMI
C232 <22> HDMI_TX0+ C232 1 2 0.1U_0201_10V7K HDMI_TX0P 1 4 HDMI_TX0+_CONN
CZL@ 1 4
S RES 1/20W 0 +-5% 0201 PANASONIC EXC24CG900U
EMIP@ L10 SM070002R00

EMIP@L10 <22> HDMI_DET_R
C233 CZ@
CZL@ <22> HDMI_TX1+ C233 1 2 0.1U_0201_10V7K HDMI_TX1P 2 3 HDMI_TX1+_CONN
S RES 1/20W 0 +-5% 0201 2 3
CZ@ CZ@
1
C234 <22> HDMI_TX1- C234 1 2 0.1U_0201_10V7K HDMI_TX1N 1 4 HDMI_TX1-_CONN CZ@ C R133 JHDMI1
CZL@ 1 4 Q5 2 1 2 HDMI_DET_R 19
S RES 1/20W 0 +-5% 0201 PANASONIC EXC24CG900U MMBT3904_NL_SOT23-3 B 150K_0402_5% 18 HP_DET
+5V_Display +5V
E 17
3
DDC/CEC_GND
2
C235 CZ@ EMIP@ L11 SM070002R00
EMIP@L11 HDMI_DET HDMIDAT_R 16
CZL@ C235 1 2 0.1U_0201_10V7K HDMI_TX2P 2 3 HDMI_TX2+_CONN @ HDMICLK_R 15 SDA
<22> HDMI_TX2+ 2 3 SCL
1
S RES 1/20W 0 +-5% 0201 R138 14
CZ@ CZ@ 200K_0402_5% 13 Reserved
C236 C236 1 2 0.1U_0201_10V7K HDMI_TX2N 1 4 HDMI_TX2-_CONN R137 HDMI_CLK-_CONN 12 CEC 20
C <22> HDMI_TX2- C
1
CZL@ 1 4 100K_0402_5% 11 CK- G1 21
S RES 1/20W 0 +-5% 0201 PANASONIC EXC24CG900U HDMI_CLK+_CONN 10 CK_shield G2 22
2
HDMI_TX0-_CONN 9 CK+ G3 23
8 D0- G4
RP39 HDMI_TX0+_CONN 7 D0_shield
1 8 HDMIDAT_DP2 HDMI_TX1-_CONN 6 D0+
<7> DP2_HDMI_DAT D1-
<7> DP2_HDMI_CLK 2 7 HDMICLK_DP2 5
3 6 HDMI_DET HDMI_TX1+_CONN 4 D1_shield
<7> DP2_HDMI_HPD D1+
4 5 HDMI_TX2-_CONN 3
<22> HDMICLK_R D2-
2
0_0804_8P4R_5% HDMI_TX2+_CONN 1 D2_shield
<22> HDMIDAT_R D2+
CZ@
+5V_Display CONCR_099ATAC19NBLCNF
ME@
+3VS DC232001K00
R675 1 2 2.2K_0402_5% HDMIDAT_R
Q6A RP29
R676 1 2 2.2K_0402_5% CZ@
2
ME2N7002D1KW-G 2N_SOT363-6 HDMI_TX1N 6 3

HDMI_TX2P 7 2
HDMICLK_DP2 1 6 HDMICLK_R HDMI_TX2N 8 1
+3VS
5
499 +-1% 8P4R

CZ@
R657 2 CZ@ 1 4.7K_0402_5% HDMIDAT_DP2 HDMIDAT_DP2 4 3 HDMIDAT_R
RP30
Q6B HDMI_CLKN 5 4
R660 2 CZ@ 1 4.7K_0402_5% HDMICLK_DP2 CZ@ HDMI_CLKP 6 3
ME2N7002D1KW-G 2N_SOT363-6 HDMI_TX0N 7 2
HDMI_TX0P 8 1
ESD 499 +-1% 8P4R
CZ@
ESDU@ D1 ESDU@ D2 ESDU@ D3
HDMIDAT_R 9 1 HDMIDAT_R HDMI_TX0+_CONN 9 1 HDMI_TX0+_CONN HDMI_TX1+_CONN 9 1 HDMI_TX1+_CONN
B B
HDMICLK_R 8 9 2 2 HDMICLK_R HDMI_TX0-_CONN 8 9 2 2 HDMI_TX0-_CONN HDMI_TX1-_CONN 8 9 2 2 HDMI_TX1-_CONN
+3VS
HDMI_DET_R 7 7 4 4 HDMI_DET_R HDMI_CLK+_CONN 7 7 4 4 HDMI_CLK+_CONN HDMI_TX2+_CONN 7 7 4 4 HDMI_TX2+_CONN
1
D
6 6 5 5 HDMI_CLK-_CONN 6 6 5 5 HDMI_CLK-_CONN HDMI_TX2-_CONN 6 6 5 5 HDMI_TX2-_CONN Q7 2
CZ@ G
3 3 3 3 3 3 2N7002H_SOT23-3 S
3
8 8 8
YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9
ESD protection needs to be placed near connector side
A A

HDMI CONN
C 1.0
LA-C293P
5 4 3 2 1
5 4 3 2 1
D D
+AV12 +DV12S
+3VS
1 1 1 1
CR1 CR2 CR3 CR4
CR5 1 2 4.7U_0603_6.3V6K
2 2 2 2
0.1U_0201_10V7K
0.1U_0201_10V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
CR6 1 2 0.1U_0201_10V7K UCR1
9
+DV33_18 15 3V3_IN
+AV12 7 DV33_18
+Card_3V3 300 ohm bead +DV12S 11 AV12
LR1 EMIP@ DV12_S
+Card_3V3 1 2 +Card_3V3_R 10
PBY160808T-301Y-N_0603 Card_3V3 25
1 2 8 GND
RR1 6.2K_0402_1% RREF
1 12 SD_D1_R RR2 1 2 0_0402_5% SD_D1

<5> PCIE_ATX_C_DRX_P0 HSIP SP1
<5> PCIE_ATX_C_DRX_N0 2 13 SD_D0_R RR3 1 2 0_0402_5% SD_D0
CR7 1 2 0.1U_0201_10V7K PCIE_DTX_ARX_P0 5 HSIN SP2 14 SD_CLK_R RR9 1 EMIP@ 2 33_0402_5% SD_CLK
<5> PCIE_DTX_C_ARX_P0 1 2 0.1U_0201_10V7K 6 HSOP SP3 16
CR8 PCIE_DTX_ARX_N0 SD_CMD_R RR5 1 2 0_0402_5% SD_CMD
C
<5> PCIE_DTX_C_ARX_N0
3
HSON SP4
SP5
SP6
17
18
SD_D3_R
SD_D2_R
RR6 1
RR7 1
2 0_0402_5%
2 0_0402_5%
SD_D3
SD_D2 1
EMIU@
EMI C
<9> CLK_PCIE_CR REFCLKP

4 CR13
<9> CLK_PCIE_CR# REFCLKN
+DV33_18 5.6P 50V D NPO 0402
23 20 SD_WP 2
<14,26,27,8> APU_PCIE_RST# PERST# SD_WP
2 24 21 SD_CD#
1U_0402_6.3V6K
<8> CR_CLKREQ# CLK_REQ# SD_CD#

CR10
2 1 SD_GPIO1 19 22
+3VS GPIO MS_INS#
RR8 10K_0402_5%
+Card_3V3
JSD1
SD_D0 7 4
D0 VDD
B B
SD_D1 8
D1
SD_D2 9 10 SD_WP CR11 1 1
0.1U_0201_10V7K
D2 WP CR12
4.7U_0603_6.3V6K
SD_D3 1 11 SD_CD#
D3 CD
3 2 2
SD_CLK 5 VSS1 6
CLK VSS2 12
SD_CMD 2 Shading 13
CMD Shading
TAITW_PSDBTC-09GLBS1N14H0
ME@
SP07000LN00
A A

Card Reader RTS5220
C 1.0
LA-C293P
5 4 3 2 1
5 4 3 2 1
+3VALW +3V_LAN
RL11
RL18 1 @ 2 0_0603_5% 1 2
0_0603_5%
8111H_LDO@
+LAN_VDD
LL1
2 +LAN_SROUT1.05 1 2
0.1U_0201_10V7K
2.2UH +-5% NLC252018T-2R2J-N
0.1U_0201_10V7K
CL1 1 8111H_SW@
4.7U_0603_6.3V6K
1U_0402_6.3V6K 1 1
1 CL15 LL1 CL16 CL17
8111H_LDO@ 8107E_SW@
2
8111H_SW@
8111H_SW@
D 2 2 D
CL16
8107E_SW@
CL17
8107E_SW@
LL1, CL16, and CL17 close to Pin24

( Should be place within 200 mils )
+LAN_VDD
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
1 1 1 1 1
1U_0402_6.3V6K
CL8
CL4 CL5 CL6 CL7
2 2 2 2 2 RJ-45 CONN.
+3V_LAN JLAN1
LED0 1 2 12
RL15 510_0402_5% Yellow LED-
+3V_LAN @ 11
1 2+LAN_VDDREG Yellow LED+
+3V_LAN RL1 0_0603_5% Pin3 Pin8 Pin22 Pin30 Pin22 RJ45_TX3- 8
0.1U_0201_10V7K
4.7U_0603_6.3V6K
PR4-
1 1
CL9 CL10 RJ45_TX3+ 7
0.1U_0201_10V7K
PR4+
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1 1 1 1 RJ45_RX1- 6
8111H_SW@
0.1U_0201_10V7K
@ @ 2 2 PR2-
CL2 CL3 CL20 CL21 CL9 RJ45_TX2- 5
8107E_SW@ PR3-
2 2 2 2 RJ45_TX2+ 4
2014/12/16 PR3+
RJ45_RX1+ 3
PR2+
C Close to Pin23 RJ45_TX0- 2
C
PR1- 13
RJ45_TX0+ 1 SHLD2 14
+3V_LAN PR1+ SHLD1
LED2 1 2 10
RL16 510_0402_5% Green LED-
CL2 close to Pin 11 9
CL3 close to Pin 32 Green LED+
SANTA_130452-0P
ME@
DC234007O00
LANGAN1 LANGAN
+LAN_VDD +LAN_VDD
+3VS
MDIP0 HSOP
1
LAN_MDIN0 2 18 PCIE_DTX_ARX_N1 1 2 PCIE_DTX_C_ARX_N1 <5>
3 MDIN0 HSON 19 APU_PCIE_RST# CL12 0.1U_0201_10V7K RL8
LAN_MDIP1 4 AVDD10 PERSTB 20 ISOLATE# APU_PCIE_RST# <14,25,27,8> 1K_0402_5%
LAN_MDIN1 5 MDIP1 ISOLATEB 21 PCIE_WAKE#
LAN_MDIP2 6 MDIN1 LANWAKEB 22 PCIE_WAKE# <27>
EMI
2
LAN_MDIN2 7 MDIP2 DVDD10 23 +LAN_VDDREG ISOLATE#
8 MDIN2 VDDREG 24 +LAN_SROUT1.05 +3V_LAN
LAN_MDIP3 9 AVDD10 REGOUT 25 LED2 TPL1
RL4 1 @ 2 0_0402_5% LAN_MDIN3 10 MDIP3 LED2 26 LED1_GPIO 1 @ 2
11 MDIN3 LED1/GPIO 27 LED0 RL17 10K_0402_5% RL10
+3V_LAN AVDD33 LED0
RL5 1 @ 2 0_0402_5% 12 28 XTLO TPL2 15K_0402_5%
<8> LAN_CLKREQ# 13 CLKREQB CKXTAL1 29 XTLI
<5> PCIE_ATX_C_DRX_P1 14 HSIP CKXTAL2 30 reserved GPIO pin
<5> PCIE_ATX_C_DRX_N1 15 HSIN AVDD10 31 2.49K_0402_1% 2 1 RL9
LANGAN <9> CLK_PCIE_LAN 16 REFCLK_P RSET 32
<9> CLK_PCIE_LAN# REFCLK_N AVDD33 +3V_LAN
33
GND
RL6 1 EMIU@ 2 0_0402_5%
B B
RL7 1 EMIU@ 2 0_0402_5%
UL2
LANGAN1
RTL8111GS-CG_QFN32_4X4
8111H_LDO@
+V_DAC 1
TL1
24 MCT
EMI
TCT1 MCT1 RL19 CL19
CL13
EMI LAN_MDIP3
LAN_MDIN3
2
3
TD1+ MX1+
23
22
RJ45_TX3+
RJ45_TX3-
1
75_0805_5%
2 1 2
10P_0603_50V
1 2 RL20 2 @ 1 0_0402_5% XTLO CL18 TD1- MX1- EMIP@ EMIP@
1 2 +V_DAC 4 21
10P_0402_50V8J TCT2 MCT2 LANGAN
0.01U_0402_16V7K LAN_MDIP2 5 20 RJ45_TX2+
TD2 MX2+
1
EMIP@
YL1 LAN_MDIN2 6 19 RJ45_TX2-
OSC
NC
25MHZ_10PF_7V25000014
EMI +V_DAC 7
TD2-
TCT3 MCT3
MX2-
18 2 1
OSC
DL1 LAN_MDIP1 8 17 RJ45_RX1+ DL3

NC
LAN_MDIN2 1 10 TD3+ MX3+ BS4200N-C-LV_SMB-F2

2 1 10 9 LAN_MDIP3 LAN_MDIN1 9 16 RJ45_RX1- EMIP@
2
LAN_MDIP2 3 2 9 8 TD3- MX3-

CL14 3 8
4 7 LAN_MDIN3 +V_DAC 10 15
GND
10P_0402_50V8J
2 XTLI 5 4
5
7
6
6
RCLAMP3304N.TCT_SLP2626P10-10
LAN_MDIP0 11
TCT4
TD4+
MCT4
MX4+
14 RJ45_TX0+ EMI
11
GIGAEMIU@ LAN_MDIN0 12 13 RJ45_TX0-

SC300001J00 TD4- MX4-
TL1
S0 X'FORM_ HH-065 10/100 350UH_IH-160
8107E_LDO@ 8111H_LDO@
DL2
A LAN_MDIN0 1 10 A
2 1 10 9 LAN_MDIP1
LAN_MDIP0 3 2 9 8 FOR 10/100 data transferring 2013/08/27
4 3 8 7 LAN_MDIN1
GND
5 4 7 6 TL1 TL1
5 6 S0 X'FORM_ HH-065 10/100 S0 X'FORM_ 350UH_IH-160
RCLAMP3304N.TCT_SLP2626P10-10 8107E_SW@ 8111H_SW@
11
EMIU@
SC300001J00

LAN_RTL8111H/RTL8107E
C 1.0
LA-C293P
5 4 3 2 1
A B C D E
1 1
NGFF for WLAN / BT(Key E) +3VS +3VS_WLAN
R153 1 @ 2 0_0805_5%
+3VS_WLAN
JWLAN1
1 2 1 1
3 GND 3.3VAUX 4 C155 C156
<9> USB20_P5 USB_D+ 3.3VAUX
BT 5 6
<9> USB20_N5 7 USB_D- LED1# 8 4.7U_0603_6.3V6K @ 0.1U_0201_10V7K
9 GND PCM_CLK 10 2 2
11 SIDO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDO_DAT0 PCM_OUT 16
2 2
17 SDO_DAT1 LED2# 18
19 SDO_DAT2 GND 20
21 SDO_DAT3 UART_WAKE# 22
23 SDIO_WAKE# UART_RX
SDIO_RESET#
24
25 UART_TX 26
27 GND UART_CTS 28
<5> PCIE_ATX_C_DRX_P2 29 PETP0 UART_RTS 30 R155 1 2 0_0402_5%
<5> PCIE_ATX_C_DRX_N2 PETN0 RESERVED EC_TX <31>
31 32 R156 1 2 0_0402_5%
GND RESERVED EC_RX <31>
33 34
<5> PCIE_DTX_C_ARX_P2 35 PERP0 RESERVED 36
WLAN 37 PERN0 COEX3 38
39 GND COEX2 40
<9> CLK_PCIE_WLAN REFCLKP0 COEX1
41 42 SUSCLK_R R78 1 2 0_0402_5%
<9> CLK_PCIE_WLAN# REFCLKN0 SUSCLK RTC_CLK <8>
43 44 APU_PCIE_RST#
GND PERST0# APU_PCIE_RST#
2 0_0402_5%
<8> WLAN_CLKREQ# CLKEQ0# W_DISABLE2# BT_OFF# <8>
<8> APU_PCIE_WAKE# R160 1 @ 2 0_0402_5% R163 1 @ 2 0_0402_5% 47 48 R161 1 2 0_0402_5%
49 PEWAKE0# W_DISABLE1# 50 EC_WL_OFF# <31>
R1649 1 2 0_0402_5%
GND I2C_DATA BT_OFF#_AGPIO64 <8>
<31> EC_PCIE_WAKE# R162 1 @ 2 0_0402_5% 51 52
53 RSRVD/PETP1 I2C_CLK 54
55 RSRVD/PETN1 ALERT 56
Note: The real behavior of BT_DISABLE are
57 GND RESERVED 58 BT_DISABLE=LOW, BT=OFF
59 RSRVD/PERP1 RESERVED 60
<26> PCIE_WAKE#
61 RSRVD/PERN1 RESERVED 62 BT_DISABLE=HIGH, BT=ON
63 GND RESERVED 64
65 RESERVED 3.3VAUX 66
67 RESERVED 3.3VAUX
GND
69 68
MTG77 MTG76
LCN_DAN05-67306-0102
2
ME@
3 3
SP070013F00 R1647
100K_0402_5%
4 4

NGFF WLAN/BT
C 1.0
LA-C293P
A B C D E
5 4 3 2 1
+IOVDD_CODEC
+3VS +3VDD_CODEC +1.5VS
RA2 0_0603_5% RA3

1 2 2 1 0_0603_5%
CA4
CA6
1U_0402_6.3V6K
SIV
1 1
1
CA5
0.1U_0201_10V7K
0.1U_0201_10V7K
2
2 2
D
Place near Pin1 Place near Pin9 D
+5VDDA_CODEC +5VS
RA1 RA4 0_0603_5%

1 2 +5VS_PVDD 1 2
+5VS
CA1
CA2
CA3
0_0805_5% +1.5VS
2 1 1
4.7U_0603_6.3V6K
0.1U_0201_10V7K
0.1U_0201_10V7K
1
1 2 2
Place near Pin26
RA49
+IOVDD_CODEC
CA7
CA11 4.7U_0603_6.3V6K
0_0402_5%
1 1
2
+3VDD_CODEC
0.1U_0201_10V7K
+1.5VS_AVDD2
2 2 2
CA38
1U_0402_6.3V6K
1
41
46
26
40
1
9
UA1 Place near Pin40
PVDD1
PVDD2
AVDD1
AVDD2
DVDD
DVDD-IO
LINE1-L 22
LINE1-R 21 LINE1-L(PORT-C-L) 43 SPK_L1-
LINE1-R(PORT-C-R) SPK-OUT-L- 42 SPK_L2+
24 SPK-OUT-L+
+MIC2-VREFO
wide 100MIL 23 LINE2-L(PORT-E-L)
LINE2-R(PORT-E-R) SPK-OUT-R+
SPK-OUT-R-
45
44
SPK_R2+
SPK_R1-
C RA6 1 2 2.2K_0402_5% EXT_MIC_RING2 17 C
1 2 2.2K_0402_5% EXT_MIC_SLEEVE 18 MIC2-L(PORT-F-L) /RING2
RA7 MIC2-R(PORT-F-R) /SLEEVE 32 HP_L
31 HPOUT-L(PORT-I-L) 33 HP_R
+LINE1-VREFO-L LINE1-VREFO-L HPOUT-R(PORT-I-R)
30
+LINE1-VREFO-R LINE1-VREFO-R 10 HDA_SYNC_AUDIO HDA_SYNC_AUDIO <8>
2 SYNC 6 HDA_BITCLK_AUDIO
<21> DMIC_DAT GPIO0/DMIC-DATA BCLK HDA_BITCLK_AUDIO <8>
LA1 1 EMIP@ 2 BY100505T-301Y-N 0402 DMIC_CLK_R 3
<21> DMIC_CLK GPIO1/DMIC-CLK
SM01000I000 RA10 1 EMIU@ 2 33_0402_5% CA12 EMIU@ 22P_0402_50V8J
RA11 2 1 0_0402_5% PDB 47 5 HDA_SDOUT_AUDIO

<31> EC_MUTE#
<8> HDA_RST#_AUDIO
11 PDB
RESETB
ALC3248-CG SDATA-OUT
SDATA-IN
8 HDA_SDIN0_R RA12 1 2 33_0402_5%
HDA_SDOUT_AUDIO
HDA_SDIN0 <8>
<8>
+3VDD_CODEC 48
PC_BEEP 12 SPDIF-OUT/GPIO2
16
RA13 2 1 200K_0402_1% PLUG_IN#_R 13 MONO-OUT
<30> PLUG_IN# SENSE A
14
RA4 close to chip SENSE B 29
MIC2-VREFO
CA15 1 2 2.2U_0402_6.3V6M CBN 35 CBP 7 LDO3 CA13 2 1 4.7U_0603_6.3V6K
PDB CBN LDO3-CAP 39 LDO2 CA16 2 1 4.7U_0603_6.3V6K
LDO2-CAP 27 LDO1 CA26 2 1 4.7U_0603_6.3V6K
LDO1-CAP
2
36
+3VS CPVDD
CA17 2 1 4.7U_0603_6.3V6K RA45 1 2 100K_0402_5%
RA50
10K_0402_5%
@ 28 VREF 1 2
RA46 1 @ 2100K_0402_5% CRVREF 20 VREF CA27 1U_0402_6.3V6K
+3VLP CPVREF 15 JDREF
1
CA19 2 1 4.7U_0603_6.3V6K MIC-CAP 19 JDREF 34 CPVEE 1 @ 2 20K_0402_1%

MIC-CAP CPVEE RA47
close to chip SM01000N000
RA48 1 @ 2 0_0402_5% DVSS 4
49 DVSS 25 1 EXT_MIC_SLEEVE
SM01000N000
RA19 2 EMIP@ 1 BLM15PD800SN1D 0402
EMI
Thermal PAD AVSS1 HGNDB <30>
38 EXT_MIC_RING2 RA20 2 1 BLM15PD800SN1D 0402
AVSS2 1 EMIP@ 2 47_0402_5% HGNDA <30>
CA20 HP_L EMIP@ RA22
HPOUT_L <30>
2.2U_0402_6.3V6M HP_R RA23 1 EMIP@ 2 47_0402_5%
2 HPOUT_R <30>
ALC3248-CG_MQFN48_6X6
B B
For Universal Audio Jack
2
1 1 1 1
LINE1-L CA21 2 1 1U_0402_6.3V6K CA33 CA34 CA35 CA36
RA26
RA27
10K_0402_5%
10K_0402_5%
@ @ EMIP@ EMIP@ EMIP@ EMIP@
LINE1-R CA22 2 1 1U_0402_6.3V6K
470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K
2 2 2 2
1
ESD protection needs to be placed near connector side +LINE1-VREFO-L RA29 1 2 4.7K_0402_5%
ESD +LINE1-VREFO-R RA32 1 2 4.7K_0402_5%
+5VS EMI
ESDU@ DA3
SPK_R1-_CONN 6 3 SPK_L2+_CONN
I/O4 I/O2 JSPK1
SPK_R1- LA5 1 @ 2 0_0603_5% SPK_R1-_CONN 1
SPK_R2+ LA6 1 @ 2 0_0603_5% SPK_R2+_CONN 2 1
5 2 SPK_L1- LA7 1 @ 2 0_0603_5% SPK_L1-_CONN 3 2
VDD GND SPK_L2+ LA8 1 @ 2 0_0603_5% SPK_L2+_CONN 4 3
5 4
6 G5
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
SPK_R2+_CONN 4 1 SPK_L1-_CONN G6
I/O3 I/O1 ACES_85205-04001
1 1 1 1
AZC099-04S.R7G_SOT23-6 ME@
EMIP@ CA28
EMIP@ CA29
EMIP@ CA30
EMIP@ CA31
SP020008X00
2 2 2 2
EMI
PC Beep
place close audio codec
A RA21 1 2 0_0402_5% A
RA51 1 2 47K_0402_5% PC_BEEP_R

RA24 1 2 0_0402_5% EC Beep <31> BEEP# CA25
RA52 1 2 47K_0402_5% 1 2 PC_BEEP
APU Beep <8> APU_SPKR
RA25 1 2 0_0402_5%
1U_0402_6.3V6K
1
EMIU@ 1
RA28 1 2 EMIU@ RA36
0_0402_5% C1383 27K_0402_5%
100P_0402_50V8J
2
2
GND GNDA ALC3248 CODEC

C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C293P
5 4 3 2 1
A B C D E F G H
HDD
SATA HDD Conn.
Near Connector
JHDD1
1
C142 2 1 0.01U_0402_16V7K SATA_ATX_C_DRX_P0 2 GND
<9> SATA_ATX_DRX_P0 RX+
C143 2 1 0.01U_0402_16V7K SATA_ATX_C_DRX_N0 3
<9> SATA_ATX_DRX_N0 RX-
4
C144 1 2 0.01U_0402_16V7K SATA_DTX_ARX_N0 5 GND
<9> SATA_DTX_C_ARX_N0 C145 1 2 0.01U_0402_16V7K SATA_DTX_ARX_P0 6 TX-
<9> SATA_DTX_C_ARX_P0 7 TX+
GND
R141 1 @ 2 0_0805_5% +3V_HDD 8
1 +3VS 3.3V 1
9
10 3.3V
11 3.3V
12 GND
13 GND
14 GND
2 5V
ESDU@ 15
C1374 0.1U_0201_10V7K R142 1 @ 2 0_0805_5% +5V_HDD 16 5V
+5VS 17 5V
1 18 GND 23
19 Reserved GND1 24
20 GND GND2
Near HDD 21 12V
22 12V
+5V_HDD 12V
ALLTO_C166KH-122H9-L
ME@
1 1 1 SP011310171
@
C146 C147 C148
1000P_0402_50V7K 0.1U_0201_10V7K 10U_0603_6.3V6M
2 2 2
ODD
2 2
+3VALW
ODD Power Control FOR 15"
2
R151
100K_0402_5%
SATA ODD FFC Conn.
ZODD@
JODD1
1
1
2 1
+5VALW +5VS +5V_ODD <9> SATA_ATX_DRX_P1 2
NOZODD@ 3
<9> SATA_ATX_DRX_N1 3
R147 1 2 0_0805_5% 5 4
5
6
1
ZODD@ 7
+5V_ODD 8
S
R149 3 1 9
10K_0402_5% ODD_DA# 10 9
ZODD@ Q8 10 11
2
R150 LP2301ALT1G_SOT23-3
G
2
100K_0402_5% ZODD@ GND

1 2 ACES_88058-100N
1 1 ME@
1
SP010016C00
C149 C150
OUT
0.01U_0402_16V7K 10U_0603_6.3V6M
2 ZODD@ 2
2
<8> ODD_EN IN
GND
3 3
Q9
DTC124EKAT146_SC59-3
3
ZODD@
FOR 14"
SATA ODD Conn.
Near Connector JODD2
1
SATA_ATX_DRX_P1 14@ C151 1 2 0.01U_0402_16V7K SATA_ATX_C_DRX_P1_14 2 GND
SATA_ATX_DRX_N1 14@ C152 1 2 0.01U_0402_16V7K SATA_ATX_C_DRX_N1_14 3 A+
4 A-
SATA_DTX_C_ARX_N1 14@ C153 1 2 0.01U_0402_16V7K SATA_DTX_ARX_N1_14 5 GND
SATA_DTX_C_ARX_P1 14@ C154 1 2 0.01U_0402_16V7K SATA_DTX_ARX_P1_14 6 B-
7 B+
GND
+3VS
ODD_DETECT# 8
9 DP
+5V_ODD +5V
10
+5V
2
ZODD@ ODD_DA# 11
RC23 12 MD 14
10K_0402_5% 13 GND GND 15
GND GND
2
G
1
1 3 ALLTO_C185S1-113H9-L
<8> ODD_DA#_APU
ME@
D
ZODD@ Q103 SP011312061

2N7002H_SOT23-3
4 4

HDD/ODD
C 1.0
LA-C293P
A B C D E F G H
5 4 3 2 1
ESD ESDP@ D6
Finger Print U3RXDN0 9 10
U3RXDP0 8 9
1 1 U3RXDN0
2 2 U3RXDP0
U3RXDP1 8
ESDP@
U3RXDN1 9 10
9
D7
1 1U3RXDN1
2 2U3RXDP1
U2DN0 3
ESDP@
I/O2
D8
I/O4
6 U2DP1 3
ESDP@
I/O2
D9
I/O4
6
U3TXDN0 7 7 4 4 U3TXDN0
U3TXDN1 7 7 4 4U3TXDN1 2 5 +USB3_VCCA 2 5 +USB3_VCCA
U3TXDP0 6 5 U3TXDP0 GND VDD GND VDD
6 5
U3TXDP1 6 6 5 5U3TXDP1
+3VS 3 3
3 3 1 4 U2DP0 1 4 U2DN1
JFP1 8 I/O1 I/O3 I/O1 I/O3
R291 1 2 0_0402_5% +3VS_FP 1 8
2 1 AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6
<9> USB20_P2 2
Finger Print 3 YSCLAMP0524P_SLP2510P8-10-9
<9> USB20_N2 3
D
4 YSCLAMP0524P_SLP2510P8-10-9 D
(For B14/E14/B15) 5 4
6 5
6
2
1 7
GND
ESD protection needs to be placed near connector side
ESDP@ 8
GND
USB3.0_Port
0.1U_0201_10V7K
C247
D25
L30ESD24VC3-2 3P C/A SOT23 ESD
2
ACES_88058-060N
ME@ EMI
1
SCA00000U10 SP010010T00
L12 EMIP@
2 3 U2DN1
ESD <9> USB30_N6 2 3
EMI FP@ <9> USB30_P6

1
1 4
4 U2DP1
PANASONIC EXC24CQ900U
SM070004400
Left USB CONN

L13 EMIP@ +USB3_VCCA
2 3 U3RXDN1
<9> USB30_MRX_DTX_N2 2 3
USB2.0_Port +USB_VCCB <9> USB30_MRX_DTX_P2

1
1 4
4
PANASONIC EXC24CH900U
SM070004300
U3RXDP1
U3TXDP1
U3TXDN1
9
1
8
JUSB1
SSTX+
VBUS
U2DP1 3 SSTX-
7 D+
1
R191 2
CHG@
1 0_0402_5% USB20_N0_U
EMI +3VALW +3VLP C170
220U_6.3V_M
+
C168 USB3@
U2DN1
U3RXDP1
2
6
4
GND
D-
SSRX+
GND 11
GND 12
10
C GND GND 13 C
0.1U_0201_10V7K L15 EMIP@ U3RXDN1 5
SSRX- GND
2
2
100K_0402_5%
100K_0402_5%
1 2 U3TXDN1_L 2 3 U3TXDN1
<9> USB30_MTX_C_DRX_N2 2 3
R177 2 EMIU@ 1 0_0201_5% @ J-L_TNBNRAC70010009
R275 R169 ME@
SM070004400 1 2 U3TXDP1_L 1 4 U3TXDP1 DC23300ET10
<9> USB30_MTX_C_DRX_P2 1 4
NOCHG@ PANASONIC EXC24CQ900U Near HDMI CONN
1
R180 2 1 0_0402_5% USB20_N0_R 1 4 USB20_N0_C C169 USB3@ PANASONIC EXC24CH900U
<9> USB20_N0 1 4 0.1U_0201_10V7K SM070004300
Right USB2__I/O Port NOCHG@ JIO1
R183 2 1 0_0402_5% USB20_P0_R 2 3 USB20_P0_C 12 14
<9> USB20_P0 2 3 <28> HGNDB 12 G2 13
11
<28> HGNDA 11 G1
<28> HPOUT_L 10
9
8 9
<28> HPOUT_R 8
R178 2 EMIU@ 1 0_0201_5% 7
<28> PLUG_IN# 7
CHG@ 6
R193 2 1 0_0402_5% USB20_P0_U USB20_N0_C 5 6
USB20_P0_C 4 5 L16 EMIP@
Right USB2__I/O Port 3 4 2 3 U2DN0
3 <9> USB30_N7 2 3
2
1 2
<31> NOVO# 1 1 4 U2DP0
+5VALW +USB_VCCB <9> USB30_P7 1 4
ACES_88058-120N
ME@ PANASONIC EXC24CQ900U
U8 SP010015H00 SM070004400
1
4 @
Left USB CONN
<31> USB_EN# EN 3 USB_OC0#_U8 1 R179 2 USB_OC0#
OCB 0_0402_5% L17 EMIP@ +USB3_VCCA
1
1
NOCHG@ SY6288D20AAC_SOT23-5 @ 2 3 U3RXDN0

C195 C171
0.1U_0201_10V7K 470P_0402_50V7K
2
2 1 4 U3RXDP0 JUSB2
9
PANASONIC EXC24CH900U 1 SSTX+
B VBUS B
U3TXDN0 8
U2DP0 3 SSTX-
7 D+
U2DN0 2 GND 10
0 6 D- GND 11
USB3@ C172 4 SSRX+ GND 12
+5VALW_USBCH +USB_VCCB 0.1U_0201_10V7K L18 EMIP@ U3RXDN0 5 GND GND 13
1 2 U3TXDN0_L 2 3 U3TXDN0 SSRX- GND
<9> USB30_MTX_C_DRX_N3 2 3 J-L_TNBNRAC70010009
USB Charger ME@

2
1 2 U3TXDP0_L 1 4 U3TXDP0 DC23300ET10

<9> USB30_MTX_C_DRX_P3 1 4
CHG@ Near End User
R297 USB3@ C173 PANASONIC EXC24CH900U
10K_0402_5% 0.1U_0201_10V7K SM070004300
U9
1
1 12
9 IN OUT 10 USB20_P0_R
<31> USB_CHG_STATUS#
R181 1 @ 2 0_0402_5% USB_OC0#_U9 13 STATUS# DP_IN 11 USB20_N0_R
Place TX AC coupling Cap (C843~C850). Close to connector
<8> USB_OC0# FAULT# DM_IN
4 2 USB20_N0_U
5 ILIM_SEL DM_OUT 3 USB20_P0_U
Right USB2__I/O Port
<31> USB_CHG_EN# EN DP_OUT
<31> USB_CHG_CTL1
6 15 R182 1 @ 2 20K_0402_1% (For E14)
7 CTL1 ILIM_LO 16 R184 1 CHG@ 2 20K_0402_1%
<31> USB_CHG_CTL2 CTL2 ILIM_HI +5VALW_USBCH
8 14 +5VALW
<31> USB_CHG_CTL3 CTL3 GND 17
T-PAD
1
CHG@ R196 @ 0_0603_5% +5VALW +USB3_VCCA

1
C186 TPS2544RTER WQFN 16P @ VL 1 2 U10
0.1U_0201_10V7K CHG@ C188 1
D30
2
5 OUT
470P_0402_50V7K
2 2 1 3 1 IN 2
1 GND
LP2301ALT1G_SOT23-3
1 Q28 USB_EN# 4 @
CHG@ RB751V-40TE17_SOD323-2 CHG@ C453 CHG@ EN 3 USB_OC1#_R 1 R185 2
4.7U_0603_6.3V6K OCB USB_OC1# <8>
C454 CHG@ 0_0402_5%
1
4.7U_0603_6.3V6K SCS00005C00 2 SY6288D20AAC_SOT23-5
2
2 C196 1
0.1U_0201_10V7K 1
2
+ @
A
VL C178 C177 A
R131 CHG@ 220U_6.3V_M 470P_0402_50V7K
1 2 2 2
100K_0402_5%
1
1
D
2 C90 CHG@
<31,38> EC_ON
G Q29 CHG@ 0.1U_0201_10V7K
2N7002H_SOT23-3 2
S
3
2015/03/06 2016/03/06 Title

USB Port/FP
Custom 1.0
LA-C293P
5 4 3 2 1
5 4 3 2 1
+3VALW_EC +3VLP
+3VALW
L20
FBM-11-160808-601-T_0603 +3VLP
1 2
+EC_VCCA
R188 1 @ 2 0_0603_5% +3VALW_EC
C179
1 1 1 +3VALW_EC
C185 @ +5VALW
C184 @ R189 1 2 0_0603_5% @
0.1U_0201_10V7K 1000P_0402_50V7K 100P_0402_50V8J
1 2 2 ECAGND 2 2
L21 1 1 1 1
0.1U_0201_10V7K
C180
0.1U_0201_10V7K
C181
1000P_0402_50V7K
C182
1000P_0402_50V7K
C183
FBM-11-160808-601-T_0603 R194
+EC_VCCA USB_EN# 1 2
D ECAGND D
2 2 @ 2 @ 2 10K_0402_5%
111
125
+3VALW
22
33
96
67
9
VCC1/LPC
VCC2
VCC3
VCC4
VSBY
AVCC
VCC5/SPI
1
ESDP@ R1562
C1375 2 1 1000P_0402_50V7K CHG@ 10K_0402_5%
GATEA20 1 21 VGATE VGATE <42>
<8> GATEA20 2 GPIO85/GA20 GPIO15/A_PWM 23
KBRST# BEEP#
<8> KBRST# BEEP# <28>
2
SERIRQ 3 GPIO86/KBRST# GPIO21/B_PWM 26
<32,9> SERIRQ SERIRQ/GPIOF0 PWM Output GPIO32/D_PWM EC_FAN_PWM1 <32>
LPC_FRAME# 4 27
<32,8,9> LPC_FRAME# 5 LFRAME#/GPIOF6 GPIO45/E_PWM
LPC_AD3 CHG_ID
<32,9> LPC_AD3 LAD3/GPIOF4 +3VS
EMIU@ R1560 LPC_AD2 7
2 1 22P_0402_50V8J2 EMIU@ 1 <32,9> LPC_AD2 8 LAD2/GPIOF3 63
C1263 LPC_AD1 VCIN1_BATT_TEMP
<32,9> LPC_AD1 LAD1/GPIOF2 GPIO90/AD0 VCIN1_BATT_TEMP <36,37>
10_0402_5% LPC_AD0 10 64
<32,9> LPC_AD0 LAD0/GPIOF1 LPC & MISC GPIO91/AD1
1
65 ADP_I
12 GPIO92/AD2 66 ADP_I <36,37>
LPC_CLK0_EC AD Input R1564
<32,8,9> LPC_CLK0_EC LCLK/GPIOF5 GPIO93/AD3 PMON <37>
13 75 ADP_ID NOCHG@ 10K_0402_5%
2 1 <32,8> LPC_RST# 37 LRESET#/GPIOF7 GPIO05/AD4 76 ADP_ID <35> 1 2 4.7K_0402_5%
+3VALW_EC EC_RST# VRAM_TEMP TP_CLK R260
20 ECRST# GPIO04/AD5 VRAM_TEMP <19>
R192 47K_0402_5% EC_SCI#
<8> EC_SCI#
2
ADP_ID_CLOSE 38 GPIO54/ECSCI#
<35> ADP_ID_CLOSE GPIO11/CLKRUN# 68
C187 EC_CLEAR_CMOS
GPIO94/DA0 EC_CLEAR_CMOS <10>
1
70 TS_DISABLE# TP_DATA R261 1 2 4.7K_0402_5%

GPIO95/DA1 TS_DISABLE# <21>
DA Output 71
55 GPIO96/DA2 72 DGPU_PWR_EN <16,45,8>
0.1U_0201_10V7K KSI0 EC_WL_OFF#
EC_WL_OFF# <27>
2
KSI1 56 KBSIN0/GPIOA0 GPIO97/DA3

KSI2 57 KBSIN1/GPIOA1
KSI3 58 KBSIN2/GPIOA2 83 EC_MUTE#
59 KBSIN3/GPIOA3 GPIO31/SCL3/PSCLK1 84 EC_MUTE# <28>
C KSI4 USB_EN# C
60 KBSIN4/GPIOA4/N2TCK GPIO23/SDA3/PSDAT1 85 USB_EN# <30>
KSI5
KSO[0..17] KSI6 61 KBSIN5/GPIOA5/N2TMS GPIO47/SCL4/PSCLK2 86
KSO[0..17] <33> KBSIN6/GPIOA6 PS2 Interface GPIO53/SDA4/PSDAT2 CMOS_ON# <21>
KSI7 62 87 TP_CLK
KSI[0..7] KBSIN7/GPIOA7 GPIO50/PSCLK3 TP_CLK <33>
KSO0 39 88 TP_DATA
KSI[0..7] <33> 40 KBSOUT0/GPIOB0/SOUT_CR/JENK# GPIO52/PSDAT3 TP_DATA <33>
KSO1
KSO2 41 KBSOUT1/GPIOB1/TEST#
KSO3 42 KBSOUT2/GP(I)OB2/TRIST# 97 ENBKL
43 KBSOUT3/GP(I)OB3/XORTR# GPIO02 98 ENBKL <21,7> +3VS
+3VALW_EC KSO4
KSO5 44 KBSOUT4/GPIOB4/SDP_VIS# GPIO75 99 095VS_PWR_EN EC_ENVDD <21>
KBSOUT5/GPIOB5/TDO GPIO GPIO76 095VS_PWR_EN <34>
KSO6 45 109 VCIN0_PH1 VCIN0_PH1 <36>
KSO7 46 KBSOUT6/GPIOB6/RDY# VCIN1/GPIO16
KBSOUT7/GPIOB7 Int. K/B
R201 1 2 2.2K_0402_5% EC_SMB_CK1 KSO8 47
KSO9 48 KBSOUT8/GPIOC0 Matrix 119 EC_SPI_AISO FAN_SPEED1 R214 1 2 10K_0402_5%
R202 1 2 2.2K_0402_5% EC_SMB_DA1 KSO10 49 KBSOUT9/GPIOC1 F_SDI&F_SDIO1/GPO80 120 EC_SPI_AOSI EC_SPI_AISO <9>
KSO11 50 KBSOUT10&P80_CLK/GPIOC2 F_SDIO&F_SDIO0/GPIOC6 126 EC_SPI_CLK EC_SPI_AOSI <9> +3VALW
KSO12 51 KBSOUT11&P80_DAT/GPIOC3 F_CLK/GPIOC4 128 EC_SPI_CS1# EC_SPI_CLK <9>
KBSOUT12/GPIO64/TCK SPI Flash ROM F_CS0#/GPIOC5 EC_SPI_CS1# <9>
KSO14 53 KBSOUT13/GPIO63/TMS PBTN_OUT# R215 1 2 10K_0402_5%
KBSOUT14/GPIO62/TDI
KSO16 81 KBSOUT15/GPIO61/XOR_OUT GPIO03/AD6/CIRRXM 74 EC_MUTE# R198 1 @ 2 10K_0402_5%
KSO17 82 GPIO60/KBSOUT16 GPIO07/AD7/CIRTX1 89
GPIO57/KBSOUT17 GPIO67/N2TMS 90 BATT_CHG_LED# EC_PCIE_WAKE# R212 1 2 10K_0402_5%
GPIO51/N2TCK 91 BATT_CHG_LED# <33>
CAPS_LED#
GPIO36 CAPS_LED# <33>
<36,37> EC_SMB_CK1 GPIO17/SCL1/N2TCK GPIO GPIO40/F_PWM PWR_LED# <33>
EC_SMB_DA1 78 93 BATT_LOW_LED#
<36,37> EC_SMB_DA1 GPIO22/SDA1/N2TMS GPIO35 BATT_LOW_LED# <33> +3VLP
EC_SMB_CK2 79 95 SYSON LID_SW# R344 1 2 47K_0402_5%
<15,23,32,7> EC_SMB_CK2 GPIO73/SCL2 GPIO06/IOX_DOUT SYSON <34,39>
<15,23,32,7> EC_SMB_DA2 GPIO74/SDA2 SM Bus GPIO81/F_WP# SOC_ENVDD
1
127 ESDU@
B GPIO84/IOX_SCLK R343 C1366 2 1 0.1U_0201_10V7K B
47K_0402_5%
6 100 EC_RSMRST#
<30> USB_CHG_STATUS# 14 GPIO24 GPIO26/RSMRST# 101 EC_RSMRST# <8> 2 1
USB_CHG_CTL1 ADP_SET1 VCIN1_BATT_TEMP
<30> USB_CHG_CTL1
2
15 GPIO10/LPCPD# GPIO20/TA2/IOX_DIO 102 VCIN1_ADP_PROCHOT ADP_SET1 <36> C189 100P_0402_50V8J
GPIO65/SMI# VC_IN2/GPIO72 VCIN1_ADP_PROCHOT <36>
USB_CHG_CTL3 16 103 VCIN1_AC_IN 2 1
<30> USB_CHG_CTL3 17 GPIO34/1_WIRE/CIRRXL VC_OUT2/GPIO37 104 VCOUT1_PROCHOT# <36>
USB_CHG_EN# C190 100P_0402_50V8J
<30> USB_CHG_EN# GPIO01/TB2 VC_OUT1/GPIO25 VCOUT0_MAIN_PWR_ON <38>
USB_CHG_CTL2 18 GPIO 105 BKOFF# 1 @ 2
<30> USB_CHG_CTL2 GPIO43 GPIO77 BKOFF# <21>
19 GPIO 106 PM_SLP_S3# R203 4.7K_0402_5%
<27> EC_PCIE_WAKE# 1 EC_PIN25_TEST GPIO42/CIRTX2 GPIO44 PM_SLP_S3# <8>
25 107 095_18ALW_PWR_EN 095VS_PWR_EN 1 2
TP2 GPIO13/C_PWM GPIO12 095_18ALW_PWR_EN <40,41,44>
FAN_SPEED1 28 108 VR_ON VR_ON <42,44> R207 100K_0402_5%
<32> FAN_SPEED1 CHG_ID 29 GPIO56/TA1 GPIO30/F_WP# 095_18ALW_PWR_EN R213 1 2 10K_0402_5%
EC_TX 30 GPIO14/TB1 ESDU@
<27> EC_TX GPIO83/SOUT_CR/P80_DATA
EC_RX 31 110 VCIN1_AC_IN C1369 1 2 100P_0402_50V8J
<27> EC_RX 32 GPIO87/SIN_CR/P80_CLK AC_IN/GPIO41/F_WP# 112 VCIN1_AC_IN <15,33,37>
SYS_PWRGD_EC EC_ON
<8> SYS_PWRGD_EC GPIO27/RSMRST# EC_ON/GPIO71 EC_ON <30,38>
<30> NOVO# NOVO# 34 GPIO 114 ON/OFF#
GPIO66/G_PWM ON_OFFBTN#/GPIO70 ON/OFF# <33>
NUM_LED# 36 115 LID_SW#
<33> NUM_LED# GPIO33/H_PWM GPO82/IOX_LDSH/LIDIN 116 LID_SW# <33>
SUSP#
GPIO46/CIRRXM/PLCIN 117 SUSP# <34,39,41>
NUVOTON_VTT 2
VTT
100P_0402_50V8J
PECI 118 ESDU@
PECI
C1370
PBTN_OUT# 122 VCOUT1_PROCHOT# R204 1 2 0_0402_5%
<8> PBTN_OUT# GPIO00/EXTCLK
C823 4.7U_0603_6.3V6K
PM_SLP_S5# 123 124 +V18R 1
<8> PM_SLP_S5# GPIO55/CLKOUT/IOX_DIO VCORF 1 R205 1 2 0_0402_5% H_PROCHOT# <7>
<37,42,44> PROCHOT#
1
AGND
GND1
GND2
GND3
GND4
GND5
R1567
2 @ 0_0402_5%
ESD U11 1
11
24
35
94
113
69
2
A
NPCE388NA0DX_LQFP128_14X14 C191 A
SYSON 47P_0402_50V8J
2
C193
0.1U_0201_10V7K
ESDU@ ECAGND
1
2 Issued Date 2015/03/06 Deciphered Date 2016/03/06 Title
EC-Nuvoton 388N
Custom 1.0
LA-C293P
5 4 3 2 1
5 4 3 2 1
TCM +3VS
1 1 1
CS1 CS2 CS3
TCM@ TCM@ TCM@
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
TCM@ US1 2 2 2
1 24
2 NC 3V 10
3 NC 3V 19
7 NC 3V
PP 22
LFRAME# LPC_FRAME# <31,8,9>
6 28
D
9 NC LPCPD# D
NC 21 LPC_CLK0_TCM RS1 1 TCM@ 2 33_0402_5%
LCLK LPC_CLK0_EC <31,8,9>
4 27 SERIRQ
11 GND SIRQ SERIRQ <31,9>
18 GND 26 LPC_AD0
GND LAD0 LPC_AD0 <31,9>
25 23 LPC_AD1
GND LAD1 20 LPC_AD1 <31,9>
LPC_AD2
LAD2 LPC_AD2 <31,9>
5 17 LPC_AD3
8 NC LAD3 LPC_AD3 <31,9>
12 NC 15
13 NC CLKRUN# 16
14 NC LRESET# LPC_RST# <31,8>
NC
Z32H320TC-LPC-T28-233_TSSOP28
+3VGS +3VS
2
2 Channel Thermal Sensor
2
EX_THM@ R176
R186 0_0402_5% @
0_0402_5%
1
1
+3V_Thermal
EX_THM@
C329
2 SMSC thermal sensor
0.1U_0201_10V7K
placed near VRAM
1 EX_THM@
U17
C 1 8 EC_SMB_CK2 C
<15> REMOTE1+ VDD SCLK EC_SMB_CK2 <15,23,31,7>
1
REMOTE1+ 2 7 EC_SMB_DA2
D+ SDATA EC_SMB_DA2 <15,23,31,7>
C251 EX_THM@
2200P_0402_50V7K REMOTE1- 3 6 THM_ALERT#
2 D- ALERT# THM_ALERT# <15>
<15> REMOTE1- 4 5
THERM#
THERM# GND
Placed near U17
EMC1402-2-ACZL-TR MSOP 8P
+3V_Thermal 1 2
R171 10K_0402_5% Address is 1001100xb
B
CPU VGA NGFF NPTH Battery BD B
+5VS
FAN Conn H1 H2 H3 H14 H15 H5 H13 H22 H23 H24 H8 H9
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
JFAN1
R168 2 @ 1 0_0603_5% +5VS_FAN 1
2 1
<31> FAN_SPEED1
1
3 2
<31> EC_FAN_PWM1 3
4 H_2P6N H_2P6X4P0N H_2P6X4P0N H_2P0N
5 4
2 G5
6 H_4P0 H_4P0 H_4P0 H_3P3 H_3P3 H_3P2 H_3P3 H_3P3
C162 G6
10U_0603_6.3V6M ACES_85205-04001
1 ME@
SP020008X00
H10 H6 H18 H7 H20 H11 H21 H16 H19
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1
LANGAN
H_2P8X4P6 H_2P8X5P1 H_2P8X4P8 H_2P5 H_2P5 H_2P8 H_2P8 H_3P3 H_6P0
FD1 FD2 FD3 FD4

1
1
A A

EMC1403-2/FAN/Screw Hole/TCM
C 1.0
LA-C293P
5 4 3 2 1
NFC
1
JNFC1
ME@ +3VALW
KB For B15 KB For B14/E14
2 1 JKB2 JKB1
3 2 KSI[0..7] KSI1 1 KSI1 1
3 +3VALW +3VLP KSI[0..7] <31> 1 1
4 KSI7 2 KSI7 2
5 4 KSO[0..17] KSI6 3 2 KSI6 3 2
5 KSO[0..17] <31> 3 3
C1377 1U_0402_6.3V6K
C1368 1U_0402_6.3V6K
R274
R170
6 KSO9 4 KSO9 4
7 6 KSI4 5 4 KSI4 5 4
7 1 1 5 5
2
8 KSI5 6 KSI5 6
8 6 6
100K_0402_5%
100K_0402_5%
9 ESDP@ ESDU@ KSO0 7 KSO0 7
10 9 @ KSI2 8 7 KSI2 8 7
11 10 2 2 KSI3 9 8 KSI3 9 8
12 11 JPWRB1 KSO5 10 9 KSO5 10 9
1
13 12 1 KSO1 11 10 KSO1 11 10
14 13 2 1 KSI0 12 11 KSI0 12 11
15 14 3 2 KSO2 13 12 KSO2 13 12
15 16 <31> PWR_LED# 4 3 KSO4 14 13 KSO4 14 13
GND <31> ON/OFF# 4 14 14
17 5 KSO7 15 KSO7 15
GND LID_SW# 6 5 KSO8 16 15 KSO8 16 15
<31> LID_SW# 6 16 16
KSO6 17 KSO6 17
7 KSO3 18 17 KSO3 18 17
8 GND KSO12 19 18 KSO12 19 18
GND 19 19
L30ESD24VC3-2 3P C/A SOT23 ESD

KSO13 20 KSO13 20
For Debug ESDP@
ESDP@ ACES_88058-060N
ME@
+3VS KSO14
KSO11
21
22
20
21
KSO14
KSO11
21
22
20
21
D24 D29 SP010010T00 KSO10 23 22 KSO10 23 22
L30ESD24VC3-2 3P C/A SOT23 ESD KSO15 24 23 KSO15 24 23
KSO16 25 24 CAPS_LED#_R 25 24
J11: TOP <31,33> KSO16
1
SCA00002M00 KSO17 26 25 CAPS_LED# 26 25
<31,33> KSO17 26 26
J12: BOT J1
SCA00002M00 R263 2 1 470_0402_5% CAPS_LED#_R 27
28 27 GND2
27
28
@
1 2 <31> CAPS_LED# 28 GND1
R264 2 15@ 1 470_0402_5% NUM_LED#_R 29 31
SHORT PADS ESD <31> NUM_LED#

30 29
30
GND
GND
32
ACES_88514-02601-071
C1378
C1379
ACES_88514-3001 ME@
J2
@ ME@ SP01000R500
1
1 2 ON/OFF# SP010011A00
ESDP@ ESDP@
0.1U_0201_10V7K
0.1U_0201_10V7K
SHORT PADS
2
+3VS R258 1 2 0_0402_5% For B15
+5VS R259 1 @ 2 0_0402_5%
@
C163
0.1U_0201_10V7K
LED2
R172
RP33 Battery (Amber) <31> BATT_LOW_LED#
TP_VCC 1 8 JTP1 620_0402_5%
TP_CLK 2 7 B15_VCC_B14_R 1 (B14/B15/E14)
TP_DATA 3 6 B15_CLK_B14_L 2 1 19-217/S2C-FM2P1VY/3T 0603 ORANGE
<31> TP_CLK 4 5 3 2
B15_DATA_B14_GND SC500005T00
<31> TP_DATA 3
B15_GND_B14_DATA 4
0_0804_8P4R_5% B15_L_B14_CLK 5 4
15@ B15_R_B14_VCC 6 5
6
7 R295 1 2 0_0402_5%
15@ GND <31> BATT_CHG_LED#
8 CHG (Green) LED3
0_0804_8P4R_5% GND R173
4 5 ACES_88058-060N (B14/B15/E14) 1 2 1 2 +3VLP
TP_L 3 6 ME@ 330_0402_5%
TP_R 2 7 SP010010T00
8 LTST-C190KGKT-INV 0603 GREEN
SC50000DN00
RP34
C166
C167
0.1U_0201_10V7K
0.1U_0201_10V7K
1 1
@ @
2 2 LED4
R174
SATALED# 1 2 1 2
HDD (Green) <9> SATALED#
330_0402_5%
+3VS
(B14/B15/E14)
For B15/E14 TP module(100*50) For B14 TP module(84*42) LTST-C190KGKT-INV 0603 GREEN
SC50000DN00
1 1 VCC 1 VCC 6 1 VCC 1 VCC
14@
0_0804_8P4R_5%
2 2 CLK 2 CLK 5 2 CLK 2 CLK TP_VCC 4 5 B15_R_B14_VCC
TP_CLK 3 6 B15_L_B14_CLK
TP_DATA 2 7 B15_GND_B14_DATA
3 3 DAT 3 DAT 4 3 DAT 3 DAT 1 8 +3VLP
RP35 JLED1
4 4 GND 4 L 3 4 GND 4 L 1
2 1
DC-In LED (Green) DC_LED 3 2 5
5 5 L 5 R 2 5 L 5 R (B14/B15/E14) 4 3 G1 6
4 G2
ACES_51512-0040N-P01
6 6 R 6 GND 1 6 R 6 GND
1
D Q20 ME@
RP36 2 SP01001J100
<15,31,37> VCIN1_AC_IN
1 8 B15_DATA_B14_GND G 2N7002H_SOT23-3
TP_L 2 7 B15_CLK_B14_L S
3
TP_R 3 6 B15_VCC_B14_R
4 5
0_0804_8P4R_5%
14@
For B14 15@

+3VALW R278 1 2 0_0402_5% +VCC_LID 1 R279 2
100K_0402_5%
2
C1367 1
VDD
0.1U_0201_10V7K 15@
2
ESDU@ C248
0.1U_0201_10V7K 3 LID_SW#
2 OUTPUT
GND
L L R R 2
15@
C249
1
15@ 10P_0402_50V8J
15@ 14@ @ U16 1
SW1 SW3 SW2 SW4
SMT1-05_4P SMT1-05_4P SMT1-05_4P SMT1-05_4P
5
6
5
6
5
6
5
6
TCS20DLR SOT-23F 3P
4 2 4 2 4 2 4 2
TP_L TP_L TP_R TP_R
3 1 3 1 3 1 3 1
KB/PWR BTN/LED/TP
C 1.0
LA-C293P
A B C D E
+5VALW TO +5VS
+3VALW TO +3VS +3VALW
+3VS
Load switch U13 J4 @
1U_0402_6.3V6K
1 14 +3VS_LS 1 2
2 VIN1 VOUT1 13
VIN1 VOUT1
1 C12 C9 330P_0402_50V7K PAD-OPEN 4x4m
2
@ SUSP# 3 12 1 2
ON1 CT1 C13
VL 4 11 0.1U_0201_10V7K
1
2 VBIAS GND C10 180P_0402_50V8J
SUSP# 5 10 1 2
ON2 CT2 +5VS
6 9 J5 @
+5VALW 7 VIN2 VOUT2 8 +5VS_LS 1 2
1 VIN2 VOUT2 1
15 PAD-OPEN 4x4m
GPAD
2
APE8990GN3B DFN 14P C14
1 0.1U_0201_10V7K
1
@ C11 SA00007PM00
1U_0402_6.3V6K
2
+1.8VALW
+1.8VS
+1.8VALW TO +1.8VS J18V @
1U_0402_6.3V6K
U1895P
1 14 +1.8VS_LS 1 2
VIN1 VOUT1
+0.95VALW TO +0.95VS @
1 C24
SUSP#
2
VIN1 VOUT1
13
C21 180P_0402_50V8J PAD-OPEN 4x4m
2
3 12 1 2
ON1 CT1
Load switch 2
VL 4 11
@ C26
0.1U_0201_10V7K
1
VBIAS GND C15 330P_0402_50V7K
R1643 1 @ 2 0_0402_5% 5 10 1 2
<31> 095VS_PWR_EN ON2 CT2 +0.95VS
@
6 9 J95V @
SUSP# R1644 1 @ 2 0_0402_5% +0.95VALW 7 VIN2 VOUT2 8 +0.95VS_LS 1 2
VIN2 VOUT2
15 PAD-OPEN 4x4m
GPAD
2
APE8990GN3B DFN 14P C25
1 0.1U_0201_10V7K
1
@ C22 SA00007PM00
1U_0402_6.3V6K
2 2
2
+1.35V +0.675VS
1
R1627 R1629
470_0603_5% 470_0603_5%
@ @
1 2
1 2
2 SYSON# 2 SUSP
G Q25 G Q21
S 2N7002H_SOT23-3 S 2N7002H_SOT23-3
3
@ @
+3VLP
2
+1.5VS R1636
@ 100K_0402_5%
+5VALW
1
SUSP
1
1
Q101 DTC124EKAT146_SC59-3 @
1
R1638
R1461 @ 100K_0402_5%
OUT
@ 220_0603_5%
2
3 3
SYSON#
2
SUSP# 2
<31,39,41> SUSP# IN
1
GND
1
OUT
2 SUSP
G Q23 @ R1639 Q24
3
S 2N7002H_SOT23-3 100K_0402_5% SYSON 2 DTC124EKAT146_SC59-3

<31,39> SYSON
3
@ IN @
GND
2
1
@ R239
3
100K_0402_5%
2
4 4

DC Interface
C 1.0
LA-C293P
A B C D E
5 4 3 2 1
EMI@ PL101
HCB2012KF-121T50_0805 ADP_ID
JDCIN1 PF101 1 2
VIN AC Adapter 90W 65W
1 APDIN 7A_24VDC_429007.WRML
1 2 1 2 APDIN1 R(K ohm) open 10
2 3
3 4 EMI@
PL102 ADP_ID(V) 3.3 1.65
4
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
5 1 2
5 Detection voltage >2.64 1.32~1.98
ACES_88299-0510 HCB2012KF-121T50_0805
1
EMI@ PC101
EMI@ PC102
EMI@ PC103
EMI@ PC104
CONN@
2
D D
@ PR101
1 2
0_0402_5%
@ PR107
1 2
0_0402_5%
PQ101A
2N7002KDW-2N_SOT363-6
680P_0603_50V7K
1 2 6 1
+3VALW ADP_ID <31>
0.1U_0402_16V7K
PR102
750_0402_1% A/D
1
PC105
PC106
2
PR103
2
2N7002KDW-2N_SOT363-6
100K_0402_5%
1 2
VIN
3
1
PQ101B
PR104
5 ADP_ID_CLOSE <31>
100K_0402_5%
1
2
4
PR108
100K_0402_5%
2
C C
+CHGRTC
PR105
1K_0603_5%
1 2
PD101
+3VLP
S SCH DIO BAS40CW SOT-323
2 +CHGRTC_R
+RTCBATT_3V 1 JBATT1
3 PR106
1K_0603_5%
1 2 1 2
LOTES_AAA-BAT-019-K01
CONN@
RTC Battery
B B
A A

2015/03/06 2016/03/06 Title
Issued Date Deciphered Date PWR- DCIN / Vin Detector
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
LA-C293P 1.0
5 4 3 2 1
5 4 3 2 1
EMI@ PL201
HCB2012KF-121T50_0805
VMB2 VMB 1 2
CONN@ PF201
JBAT1 12A_32VDC_0501012WR
1 1 2
1 2 BATT+
2 3 EC_SMCA EMI@ PL202
3 4 EC_SMDA
4 P/N:SP040006C00 HCB2012KF-121T50_0805
5
5 6 SP040006A00 1 2
6
1
7
7 SP040006B00
1
100_0402_1%
100_0402_1%
8
GND 9 PC201 EMI@ PC202 EMI@
D GND 1000P_0402_50V7K 0.01U_0402_25V7K D
2
PR201
PR211
ALLTO_C144PF-K07H9-L
2
EC_SMB_CK1 <31,37>
EC_SMB_DA1 <31,37>
CONN@
JBAT3
1 2
3 1 2 4 1 2
3 4 +3VLP
5 6 PR212 BQ24780 /BATPRES pin low voltage changed
7 5 6 8 200K_0402_1%
9 7 8 10 H=3.3V, L=0.157V
11 9 10 12 1 2 PH201 under CPU botten side :
11 12 +3VALW
13 14 PR213
15 13 14 16 @ 200K_0402_1%
A/D CPU thermal protection at 93 +-3 degree C
17 15 16 18
19 17 18 20 1 2 Recovery at 56 +-3 degree C 20120314
21 19 20 22 VCIN1_BATT_TEMP <31,37>
PR214
23 21 22 24 10K_0402_5%
Change to +EC_VCCA from +3VLP
25 23 24 26
27 25 26 28
29 27 28 30
29 30
31 32
+EC_VCCA
GND GND <31,37> ADP_I
16.5K_0402_1%
1
10K_0402_1%
<31> VCOUT1_PROCHOT#
PR215
C PTPL2 C
2
30K_0402_1%
PR216
PTPL1
PR217
2
@ <31> VCIN0_PH1
1
<31> VCIN1_ADP_PROCHOT
PH201
2
100K_0402_1%_TSM0B104F4251RZ
75K_0402_1%
PR221
2
1
100K_0402_1%
PR223
1
ADP_SET2
2
45W adapter 0 0 ECAGND
1
D
65W adapter 1 0 2 PQ203
G 2N7002KW_SOT323-3
S
3
90W adapter 0 1
B B
135W adapter 1 1
<31> ADP_SET1
ECAGND
135W: 150W active and 135W recovery

90W : 120W active and 90W recovery
A A

2015/03/06 2016/03/06 Title
Issued Date Deciphered Date PWR- BATTERY CONN/OTP
LA-C293P 1.0
5 4 3 2 1
5 4 3 2 1
1
D
Rds(on) = 35mohm max
@ PR314 2
1 2 G
Vgs = 20V
S @ PQ307 max Power loss 0.22W for 90W;0.12W for 65W system B+ Vds = 30V
BA+
3
1M_0402_1% @ PR315 2N7002KW _SOT323-3 PQ302
P3 CSR rating: 1W ID = 7.7A (Ta=70C) AO4466L_SO8
1 2 VACP-VACN spec < 80.64mV
8 1
PQ301 3M_0402_5% PQ303 7 2
MDU1512RH_POW ERDFN56-8-5 AON7506_DFN33-8-5 PR302 6 3
1 1 0.01_1206_1% EMI@ PL301 5
2 2 1UH_NRS4018T1R0NDGJ_3.2A_30%
5 3 3 5 1 4 1 2
VIN
4
PC302
2 3
1 2
0.047U_0603_25V7M
4
4
D D
Rds(on) typ=35mohm max
1000P_0603_50V7
2200P_0402_50V7K
PC301
0.022U_0603_25V7K
68P_0402_50V8J
Vgs=20V
4.02K_0402_1%
1
10U_0805_25V6K
10U_0805_25V6K
PC303
EMI@ PC306
PR301
PC307
PC308
PC309
1
1
Vds=30V
PR329
4.02K_0402_1%
4.7_0603_1%
2
Id=10.6A (Ta=70C)
PR303
PR304
2
10_0402_1%
PC310 PC311 PC312
2
1U_0603_25V6K 0.1U_0402_25V6
2
1 2 1 2 1 2
2
0.1U_0402_25V6
BATDRV
BATSRC
PR308
1 2 ACDRV
4.02K_0402_1%
CMSRC ACP ACN
VIN PR312
PD303
10_1206_5% @ PC329
VIN 3 1 2
392K_0402_1%
1
1 1 2 Rds(on) = 30mohm max
SIS412DN-T1-GE3_POWERPAK8-5
PR311
2 ACDRV 1000P_0402_50V7K
BA+ 1U_0603_25V6K PC313
Vgs = 20V
1 2 BQ24780VDD PC314 Vds = 30V
S SCH DIO BAS40CW SOT-323 ID = 7A (Ta=70C)
2
5
C PU301 2.2U_0805_25V6K C
1 2
ACDRV
ACP
ACN
28
VCC
PQ305
2200P_0402_50V7K
59K_0402_1%
PR316
1
1
PC315
CMSRC 3 24
CMSRC REGN PR317 PC316 1 2 4 Support max charge 2A
PR313
6 0_0603_5% 0.047U_0603_25V7M 7X7X3 Power loss: 0.04W

BATT+
2
@ PR348 0_0402_5% ACDET 25 BST_CHG 1 2 1 2 0_0603_5%

BTST Isat: 6.5A CSR rating: 1W
<31,36> EC_SMB_DA1 1 2 EC_SMB_DA1_1 11 DCR: 33mohm VSRP-VSRN spec < 81.28mV
2
@ PR349 0_0402_5% SDA

Power loss:0.132W
3
2
1
<31,36> EC_SMB_CK1 1 2 EC_SMB_CK1_1 12 26 DH_CHG PR318
SCL HIDRV PL302 0.01_1206_1%
support Turbo boost : 2200P VCIN1_AC_IN 5 4.7UH_5.5A_20%_7X7X3_M
<31,36> ADP_I ACOK 27 LX_CHG 1 2CHG 1 4
no support Tirbo boost : 0.1u
SIS412DN-T1-GE3_POWERPAK8-5
5
100P_0603_50V8 PC317 8 23 DL_CHG
4.7_1206_5%
1 2 1 2 PMON_1 9
PQ306
@EMI@
PR320
100P_0603_50V8 PC318 1 2 10 22 1 2 SRP SRN
10U_0805_25V6K
10U_0805_25V6K
2
1
<31> PMON 1 2 1 2
PC322
PC320
13 21
680P_0603_50V7K
CMPIN ILIM
1
PMON:
3
2
1
2
<31,42,44> PROCHOT#
@EMI@
14
PC321
BQ24780 need contact capacitor to GND PR326 10_0402_1%
CMPOUT 20 1 2
BQ24780S need contact the pull down resistance
2
SRP PR328 10_0402_1%
<31,36> VCIN1_BATT_TEMP 15 19 1 2
/BATPRES SRN
B /BATPRES B
logic high: above 2.1V 16 18 PC323

/TB_STAT BATDRV
logic low: under 0.8V 29 17 1 2
BQ24780VDD PWPD BATSRC
0.1U_0402_25V6
BATDRV
BATSRC
BQ24780RUYR_W QFN28_4X4
1
PR319 **Design Notes**
0.1U_0402_25V6
0.1U_0402_25V6
1
1
PC324
PC325
10K_0402_1% For 65 /90W system, 3S1P/3S2P battery
Maximum Charging current 2A
2
2
<15,31,33> VCIN1_AC_IN VCIN1_AC_IN Maximum Battery discharge power 25.2W(12.6V*2A)
#Register Setting
1
1. 0X12 bit2 set 1 (default 0) to enable turbo boost function

PR325 2. Disable turbo when AC only
#Circuit Design
12K_0402_1% 1. ILIM pull high voltage need base on 3/5V enable control
2
2. Use 7X7 choke and 3X3 H/L side MOSFET

Charge current 2A
Power loss : 1.15W (H/S=0.0961W,L/S=0.9231W,Choke=0.132W)
Power density : 0.81 (23X16)
#Protect function
1. ACOVP : VCC voltage > 24V
2. Charger timeout : No communication within 175s(default)
3. ACOC : 3.33 X Input current DAC setting (default:Disable)
4. CHGOCP : based on charge current setting
A A
5. BATOVP : 103-106%
6. BATLOWV : 2.6V
7. TSHUT : 155C
8. IFAULT HI : 750mV (default:Disable)
9. IFAULT LOW : 230mV (default)
Title
Issued Date 2015/03/06 Deciphered Date 2016/03/06
PWR- CHARGER_BQ24780
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
5 4 3 2 1
A B C D E
Module model information

SY8208B_V2.mdd
1 EN1 and EN2 dont't floating 1
PR401
Change 3V5V_EN to 3VALW_EN 499K_0402_1%
ENLDO_3V5V 1 2
B+
PU401
1
150K_0402_1%
PC403 PR403
B+
PR404
EMI@ PL401 7 1 3V5V_EN 0.01U_0402_25V7K 1K_0402_5%
HCB2012KF-121T50_0805 EN2 EN1 1 2 1 2
2200P_0402_50V7K
1 2 3V_VIN 8 3 3V_FB
IN FB PR405 PC404
2
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
6 1
BST_3V 2 1 2
BS
1
1
PC407
C407
2.2_0603_5%
EMI@ PC401
PC405
PC406
0.1U_0603_25V7K
@
@P PL402
2
2
EMI@
10 LX_3V 1 2
LX +3VALWP
9 4 1.5UH_PCMB053T-1R5MS_6A_20%
GND OUT
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PR406
1
1
680P_0603_50V7K 4.7_1206_5%
2 5
PG LDO +3VLP
<40,41,44> 3V/5VALW_PG
@EMI@
PC408
PC409
PC410
PC411
1
PR402
2
100K_0402_1% SYX198BQNC_QFN10_3X3 PC412
1 3V_SN
1 2 4.7U_0603_6.3V6M
+3VLP
2
Check pull up resistor of SPOK at HW side
@EMI@ PC413
3.3V LDO 150mA~300mA
2
2 PR407 2
2.2K_0402_5%
Vout is 3.234V~3.366V
<30,31> EC_ON 1 2
@ PR408
TDC=6A
1 2
<31> VCOUT0_MAIN_PWR_ON 0_0402_5% 1
@ PJ401
2
+3VALWP 1 2 +3VALW
1M_0402_1%
4.7U_0402_6.3V6M
1
1
PR410
PC414
2
2
B+ EMI@ PL403 EN1 and EN2 dont't floating

HCB2012KF-121T50_0805
1 2 5V_VIN
Vout is 4.998V~5.202V
PU402
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
PC415 PR412 TDC=6A

8 1 3V5V_EN 6800P_0402_25V7K 1K_0402_5%
IN EN 1 2 1 2
1
1
PC416
PC418
C418
EMI@ PC419
EMI@ PC420
3 5V_FB PR413 PC417

3 FB 2.2_0603_5% 0.1U_0603_25V7K 3
@
@P 6 BST_5V 1 2 1 2
2
BS
PL404
9 10 LX_5V 1 2 +5VALWP
GND LX
5V_VCC 5 4 1.5UH_PCMB053T-1R5MS_6A_20%
VCC OUT
1
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
@EMI@ PR414
680P_0603_50V7K 4.7_1206_5%
1
2 7
PG LDO VL
1
PC421
PC422
PC423
PC424
PC425
4.7U_0603_6.3V6M
2
SYX198CQNC_QFN10_3X3
1 5V_SN
@ PJ402
2
2
1
PC426
4.7U_0603_6.3V6M
+5VALWP 1 2 +5VALW
1 2
JUMP_43X118
2
@EMI@ PC427
2
Module model information 5V LDO 150mA~300mA
SY8208C_V2.mdd
4 4

2015/03/06 2016/03/06 Title
Issued Date Deciphered Date PWR- 3VALW/5VALW-SY8208B/C
LA-C293P 1.0
A B C D E
5 4 3 2 1

RT8207M_V1.mdd For Single layer
RT8207M_V2.mdd For Dual layer
D D
Pin19 need pull separate from +1.35VP.

If you have +1.35V and +0.675V sequence question, 0.675Volt +/- 5%
EMI@ PL501 you can change from +1.35VP to +1.35VS. TDC 0.7A
HCB2012KF-121T50_0805
B+ 1 2 1.35V_B+ PR501 Peak Current 1A
2.2_0603_5%
BST_1.35V 1 2 BOOT_1.35V
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
+1.35VP
1
1
PC501
PC502
PC503
PC504
DH_1.35V +0.675VSP
2
2
EMI@
EMI@
SW _1.35V
10U_0805_6.3V6K
10U_0805_6.3V6K
1
1
PC505
PC506
PC507
5
0.1U_0603_25V7K
16
17
18
19
20
2
C C
2
VLDOIN
PHASE
UGATE
BOOT
VTT
21
PQ501 PAD
4 DL_1.35V 15 1
MDV1528URH 1N PDFN33-8 LGATE VTTGND
Change CS R to your estimation value
14 2
PL502 PR502 PGND PU501 VTTSNS
1
2
3
1UH_11A_20%_7X7X3_M 15K_0402_1%
1 2 1 2 CS_1.35V 13 RT8207PGQW _W QFN20_3X3 3
+1.35VP PC508 CS GND
1
1U_0603_10V6K
5
1 2 12
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
@EMI@ PR504
4.7_1206_5% 5.1_0603_5%
PC516
PC517
PC518
PC519
PC520
PC521
1 2 VDD_1.35V 11 5
+5VALW +1.35VP
2
1 2
1
PGOOD
PQ502
MDV1524_DFN8-5 4 PC509
TON
1
@EMI@ PC513 0.033U_0402_16V7K
FB
S5
S3
2
680P_0402_50V7K PC512
+5VALW
2
1U_0603_10V6K
10
6
1
2
3
FB_1.35V
EN_0.675VSP
TON_1.35V
EN_1.35V
PR506
8.2K_0402_1%
PR507 1 2 +1.35VP
470K_0402_1%
B 1 2 B
MOSFET: 3x3 DFN 1.35V_B+ Change FB Rtop to 8.2K for 1.35V
H/S Rds(on): 23.2mohm(Typ), 27.8mohm(Max)
1
Idsm: 10.1A@Ta=25C, 8.1A@Ta=70C
PR508
@ PR509 10K_0402_1%
L/S Rds(on): 9.7mohm(Typ), 11.6mohm(Max) <31,34> SYSON
1 2
2
Mode Level +0.75VSP VTTREF_1.5V Idsm: 15.4A@Ta=25C, 12.4A@Ta=70C 0_0402_5%
S5 L off off
1
@ PC514
S3 L off on Choke: 7x7x3 0.1U_0402_10V7K
S0 H on on Rdc=8.3mohm(Typ), 10mohm(Max)
2
Note: S3 - sleep ; S5 - power off Switching Frequency: 530kHz @ PR510
Ipeak=10.9A 1 2 @ PJ501
Iocp~14A <31,34,41> SUSP# +1.35VP 1 2 +1.35V
0_0402_5% 1 2
OVP: 110%~120% JUMP_43X118
MOSFET footprint: SIS412DN @ PJ502
1 2
1 2
1
@ PC515 JUMP_43X118
0.1U_0402_10V7K
2
PJ503 @
1 2
+0.675VSP 1 2 +0.675VS
A
JUMP_43X39 A
Security Classification Compal Secret Data

Title
Issued Date 2015/03/06 Deciphered Date 2016/03/06 PWR-+1.35VP/ +0.675VS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C293P 1.0
5 4 3 2 1
A B C D

SY8208D_V2.mdd
1 1
EN pin don't floating

If have pull down resistor at HW side, pls delete PR2
@ PR601
1 2
095_18ALW_PWR_EN <31,41,44>
0_0402_5%
@ PR610
0_0402_5%
1 2
3V/5VALW_PG <38,41,44>
1
+0.95VALW P PJ601
@ PC601 1 2
1M_0402_1% 1 2 +0.95VALW
0.22U_0402_10V6K
2
PR602 JUMP_43X118 @
2
@EMI@ PR603 @EMI@ PC602
2
4.7_1206_5% 680P_0603_50V7K 2
EMI@ PL601 1 2SNB_0.95V1 2

PU601
HCB2012KF-121T50_0805
B+ 1 2 B+_0.95V 8
IN EN
1 PR604
0_0603_5%
PC606
0.1U_0603_25V7K TDC 8A
10U_0805_25V6K
10U_0805_25V6K
6 1
BST_0.95V 2 1 2 PL602
2200P_0402_50V7K
0.1U_0402_25V6
BS
1
1
PC604
PC607
PC605
1UH_PCMB062D-1R0MS_9A_20%
0.95LDO_3V
+0.95VALWP
PC603
9 10 LX_0.95V 1 2
GND LX
EMI@
2
2
EMI@
11.8K_0402_1%
47U_0805_6.3V6M
47U_0805_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
330P_0402_50V7K
1
1
4
PR606
PC611
PC612
PR605 @
FB
PC608
PC609
PC610
0_0402_5%
ILMT_0.95V3 7
Rup
2
ILMT BYP +3VALW
4.7U_0603_6.3V6K
2
2
ILMT_0.95V 0.95LDO_3V
4.7U_0603_6.3V6K
PC614
1
PC613
SYX198DQNC_QFN10_3X3
FB = 0.6V
1
PR608 @
0_0402_5% 2 PR609
Rdown
2
20K_0402_1%
2
Pin 7 BYP is for CS.
The current limit is set to 8A, 12A or 16A when this pin Common NB can delete +3VALW and PC15
is pull low, floating or pull high
VFB=0.6V
3
Vout=0.6V* (1+Rup/Rdown) 3
Vout=0.95V
4 4

2015/03/06 2016/03/06 Title
Issued Date Deciphered Date PWR- +0.95VALW
A B C D
A B C D

SY8003_V2.mdd
1 1
@ PR701
1 2
095_18ALW_PWR_EN <31,40,44>
0_0402_5%
@ PR712
0_0402_5%
+1.8VSP_ON 1 2
3V/5VALW_PG <38,40,44>
0.1U_0402_16V7K
1
PC701
1
PR703
@ 1M_0402_5%
Note:Iload(max)=2.5A
2
PU701
9
1 PGND 8
FB SGND
2 7
@
PJ702 PG EN PL701 @
PJ701
+3VALW 1 2 3 6 LX_1.8V 1 2 1 2
1 2 IN LX 1UH_2.8A_30%_4X4X2_F +1.8VALWP +1.8VALWP 1 2 +1.8VALW
1 4 5
68P_0402_50V8J
JUMP_43X79 PGND NC JUMP_43X79
1
PC702
4.7_0603_5%
1
PR704
PC703
22U_0603_6.3V6M
1
SY8003DFC_DFN8_2X2 PR705
Rup
22U_0603_6.3V6M
22U_0603_6.3V6M
@EMI@
PC704
PC705
20K_0402_1%
2
2 2
2
FB_1.8V
1
1
FB=0.6V
680P_0402_50V7K
PC706
Note:Iload(max)=3A PR706
Rdown
10K_0402_1%
@EMI@
2
Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)
+3VS +5VALW
3 3
Ultra Low Dropout 0.23V(typical) at 3A Output Current

1
PC707
1
1U_0402_6.3V6K
JUMP_43X79
2
@ PJ703
2
2
PU702
APL5930KAI-TRG_SO8
1
PC708 6
4.7U_0603_6.3V6K 5 VCNTL 3
9 VIN VOUT 4 PJ704
PR707 @
2
100K_0402_5% VIN VOUT

+1.5VSP +1.5VSP 1
1 2
2 +1.5VS
1
1 2 8
1.54K_0402_1%
0.01U_0402_25V7K
<31,34,39> SUSP# EN
1
1 2 7 2 JUMP_43X79
+3VS
GND
POK FB
PR709
PC710
22U_0603_6.3V6M
1
@ PR708
Rup
0.1U_0402_16V7K
1
PC709
PR710 100K_0402_5%
1
PC711
47K_0402_5%
2
2
2
1.74K_0402_1%
PR711
Module model information Rdown

2
APL5930_V2.mdd
4 4
Vout=0.8V* (1+Rup/Rdown)

2015/03/06 2016/03/06 Title
Issued Date Deciphered Date PWR- +1.8VALW/ +1.5VS
A B C D
5 4 3 2 1
CPU_B+ EMI@ PL801

HCB2012KF-121T50_0805
1 2 B+
10U_0805_25V6K
10U_0805_25V6K
MDU1516URH_POWERDFN56-8-5
33U_25V_M
33U_25V_M
1 1
1
+ +
PC804
PC802
PC803
PC801
PR813=3.65K, PR804=1.5K and
PC805
PR802
330P_0402_50V7K 2K_0402_1% PR815=432 to set loadline -4mV/A
2
1 2 1 2 0_0603_5% PR803 2 2
PQ801
PR801 UGATE_NB1 1 2 4
<7> APU_VDDNB_SEN
PR804 PR805 PC806 PR806
10_0402_5% 1.5K_0402_1% 137K_0402_1% 390P_0402_50V7K 41.2K_0402_1%
1 2 1 2 1 2 1 2 1 2
+APU_CORE_NB SH00000NX00PL802
(DCR:1.4± 5%)
3
2
1
@ PR807 .36UH 20% PDME064T-R36MS1R405 24A
PC807 PC808
0_0402_5% 1000P_0402_50V7K 180P_0402_50V8J PHASE_NB1 1 4
VSUMP_NB
1 2 1 2 1
PR808
2 1 2
PR809 PC809 2 3
+APU_CORE_NB
1
PC810 301_0402_1% 2.2_0603_1% 0.22U_0603_25V7K @EMI@
2.61K_0402_1%
D D
1
0.01U_0402_50V7K BOOT_NB1 1 2 1 2 PR811

10K_0402_5%_ERTJ0ER103J
PR810
PR813=3.65K, PR804=1.5K and 4.7_1206_5%

0.022U_0402_25V7K
MDU1511RH 1N POWERDFN56-8
1 2
0.15U_0603_16V7K
PR815=432 to set loadline -4mV/A
PQ802
680P_0603_50V7K
11K_0402_1%
@ PC811
1 2
1
while PR815=432 to set OCP 21.49A PR813

1 2
PC812 3.65K_0603_1%
for EDC 17A application. APU_CORE_NB
PR812
@EMI@ VSUMP_NB 1 2
LGATE_NB1 4 PC813 TDC 12A
2
2
PR814
2
Peak Current 17 A
PH802
PR815 1_0402_1%
432_0402_1%
PR815 set 432 ohm to OCP 21.49A VSUMN_NB 1 2
OCP current > 21.49A
2
VSUMN_NB 1 2
3
2
1
Load line -4mV/A
1
@ PR816 @PC815
@ PC815
PH1000 near APU_CORE_NB choke 100_0402_1% 220P_0402_50V7K LGATE_NB1
FSW=450kHz
PC814 1 2 1 2
2
0.1U_0603_50V7K
PHASE_NB1 DCR 1.4mohm +/-5%
VRHOT Assert Threshold : 0.64V
UGATE_NB1 TYP MAX
TSENSE Bias Current : 30uA PR817 BOOT_NB1 H/S Rds(on) :11.7mohm , 14mohm
27.4K_0402_1%
PH1001=27.4K, 110C active 1 2
PR818 Module model information L/S Rds(on) :2.7mohm , 3.3mohm
Reset Threshold: 0.66V, 98C active 20K_0402_1%
41
40
39
38
37
36
35
34
33
32
31
1 2 1 2 PU801
110C Assert Threshold: PR1016=27.4K ISL62771_V1A.mdd for IC portion
TP
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
100C Assert Threshold: PR1016=16.9K PH801 470K_0402_5%_TSM0B474J4702RE
ISL62771_V1B.mdd for SW portion
1 30
PH1001 near APU_CORE_NB H/S mos NTC_NB BOOT2
1 2 IMON_NB 2 29
PC816 1000P_0402_50V7K IMON_NB UGATE2
3 28
PR819 133K_0402_1% <7> APU_SVC SVC PHASE2
1 2
4 27 +5VALW
<31,37,44> PROCHOT# VR_HOT_L LGATE2
@ PR820 100K_0402_1%
1 2 5 26
+3VS <7> APU_SVD SVD VDDP
@ ISL62771HRTZ-T_TQFN40_5X5 PR822
+1.8VS 1 PR821 20_0402_5% VDDIO 6 25 1 2
PR848 0_0402_5% VDDIO VDD 1_0603_5%
1U_0603_10V6K
1
0_0402_5% 1 2 7 24 LGATE1
<7> APU_SVT SVT LGATE1
1
C 1PR823 2 C
@ @ PR824 0_0402_5%
1U_0603_10V6K
+1.5VS
PC817 1 2ENABLE 8 23
PC819
PHASE1
<31,44> VR_ON
2
ENABLE PHASE1
PC818
0.1U_0402_25V6K
2
VDDIO pin: 1.8VS for DDRII voltage level<44,7> 9 22 UGATE1 CPU_B+
APU_PWRGD PWROK UGATE1
1.5VS for DDRIII voltage level
1 2 IMON 10 21 BOOT1
IMON BOOT1 +3VS
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
PR825
PGOOD
0.1U_0402_25V6K
133K_0402_1%
ISUMN
ISUMP
COMP
ISEN2
ISEN1
SVC, SVD, SVT, ENABLE and

VSEN
APU_IMON
NTC
RTN
2 PC820
PWROK no need pull high for 1 FB
1
1
EMI@ PC823
1000P_0402_50V7K
PC821
PC822
EMI@ PC824
AMD KABINI
PR828 PR827
11
12
13
14
15
16
17
18
19
27.4K_0402_1% 20K_0402_1% 20 PR826
2
2
2
1 2 1 2 100K_0402_1%
0_0603_5% PR829
2
UGATE1 1 2 4
PQ803
PH1002 near APU_CORE H/S mos 1 2 VGATE <31>
PH803 SH00000NX00 (DCR:1.4± 5%)
470K_0402_5%_TSM0B474J4702RE PL803
3
2
1
VRHOT Assert Threshold : 0.64V .36UH 20% PDME064T-R36MS1R405 24A
TSENSE Bias Current : 30uA +5VS
PHASE1 1 4
PH1002=27.4K, 110C active
PR831 PC825 2 3
+APU_CORE
Reset Threshold: 0.66V, 98C active 1 2 ISEN1 2.2_0603_1% 0.22U_0603_25V7K @EMI@
1
110C Assert Threshold: PR1031=27.4K PR830 BOOT11 2 1 2 PR832
100C Assert Threshold: PR1031=16.9K 10K_0402_1% PC827 4.7_1206_5% PR835
PC826 PR833 180P_0402_50V8J @ PR834 3.65K_0603_1%
5
1000P_0402_50V7K 301_0402_1% 32.4K_0402_1% VSUM+ 1 2
MDU1511RH_POWERDFN56-8-5
VSUM+ 1 2 1 2 1 2 1 2 @EMI@
1 2
PC829
330P_0402_50V7K
@ PC828
680P_0603_50V7K PR839
2.61K_0402_1%
1
PQ804
PQ805
PR837 PR838 PC832 1_0402_1%
10K_0402_5%_ERTJ0ER103J
4 4 1 2
PR836
0.01U_0402_50V7K
0.15U_0603_16V7K
1.62K_0402_1% 137K_0402_1% 390P_0402_50V7K LGATE1 VSUM-

APU_core
11K_0402_1%
2
1
1 2 1 2 1 2
PC830
2
1
1
PR840
PC831
TDC 22A
1 2
PR841 PC833 Peak Current 35A

2
3
2
1
3
2
1
@ 2K_0402_1% 330P_0402_50V7K
OCP current > 44.13A
2
PR835=3.65K, PR837=1.62K and 1 2 1 2

PH1003 near APU_CORE_NB choke
PH804
PR842=887 to set loadline -2.1mV/A Load line -2.1mV/A

B B
PR842 PR843
FSW=450kHz
2
887_0402_1% 10_0402_5%
VSUM- 1 2 1 2
+APU_CORE DCR 1.4mohm +/-5%
@ PC835 @ PR845
TYP MAX
1
@ PR844 820P_0402_50V7K 0_0402_5%

PC834 100_0402_1% 1 2 H/S Rds(on) :11.7mohm , 14mohm
0.1U_0603_50V7K 1 2 1 2 APU_VDD_SEN <7>
L/S Rds(on) :2.7mohm , 3.3mohm
2
PR842 set 887 ohm to OCP 44.13A 1 2

APU_VDD_RUN_FB_L <7>
0.01U_0402_50V7K
0_0402_5%
1
PC836
@ PR846
PR847
10_0402_5%
2
PR835=3.65K, PR837=1.62K and 1 2

PR842=887 to set loadline -2.1mV/A
while PR842=887 to set OCP 44.13A
for EDC 35A application.
A A

2016/03/06 Title
Issued Date 2015/03/06 Deciphered Date PWR- APU_CORE/APU_CORE_NB
5 4 3 2 1
A
B
C
D
PC1031 PC1001
2
1
+
22U_0603_6.3V6M 22U_0603_6.3V6M
PC1084 2 1 2 1
330U_D2_2VM_R9M
PC1032 PC1002
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
1
+
5
5
+APU_CORE
+APU_CORE
PC1085 @ PC1033 PC1003

330U_D2_2VM_R9M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
1
+
PC1034 PC1004
PC1086 22U_0603_6.3V6M 22U_0603_6.3V6M
330U_D2_2VM_R9M 2 1 2 1
PC1035 @ PC1005
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
@ PC1036 PC1029
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
22uF*20
330uF*3
@ PC1037 @ PC1006
22U_0603_6.3V6M 22U_0603_6.3V6M
APU_CORE
2 1 2 1
@ PC1038 @ PC1007
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
+APU_CORE
@ PC1039 PC1008
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
@ PC1040 PC1009
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
4
4
PC1041 PC1010
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
1
+
@ PC1042 PC1011
PC1087 22U_0603_6.3V6M 22U_0603_6.3V6M
330U_D2_2VM_R9M 2 1 2 1
@ PC1043 PC1012
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
+APU_CORE_NB
@ PC1044 @ PC1013
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
Issued Date
@ PC1045 PC1014
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
Security Classification
PC1015
22U_0603_6.3V6M
2 1
3
3
PC1016
22U_0603_6.3V6M
2 1
+APU_CORE_NB
PC1017
22U_0603_6.3V6M
22uF*15
330uF*1
2015/03/06
2 1
PC1018
22U_0603_6.3V6M
2 1
APU_CORENB
PC1019
22U_0603_6.3V6M
2 1
Compal Secret Data

Deciphered Date
2
2
2016/03/06
CZ@ PC1046 CZ@ PC1020

2
1
+
22U_0603_6.3V6M 22U_0603_6.3V6M
CZ@ PC1088 2 1 2 1
330U_D2_2VM_R9M
CZ@ PC1047 CZ@ PC1021
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
+APU_GFX
+APU_GFX
2
1
+
CZ@ PC1089 CZ@ PC1048 CZ@ PC1022

Size
Title
Date:
330U_D2_2VM_R9M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1
Custom
2
1
+
CZ@ PC1049 CZ@ PC1023

CZ@ PC1090 22U_0603_6.3V6M 22U_0603_6.3V6M
330U_D2_2VM_R9M 2 1 2 1
+APU_GFX
CZ@ PC1050 CZ@ PC1024

Document Number
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
LA-C293P
CZ@ PC1051 CZ@ PC1025

Monday, March 09, 2015
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
22uF*20
330uF*3
CZ@ PC1052 CZ@ PC1026

22U_0603_6.3V6M 22U_0603_6.3V6M
APU_CORE
2 1 2 1
1
1
CZ@ PC1053 CZ@ PC1027

Sheet
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
43
CZ@ PC1054 CZ@ PC1028

+APU_CORE Cap
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
of
CZ@ PC1055 CZ@ PC1030

22U_0603_6.3V6M 22U_0603_6.3V6M
48
2 1 2 1
Rev
1.0
A
B
C
D
5 4 3 2 1
+3VALW
@
PJ1102
+0.775VALWP 1 2 +0.775VALW
1
1 2
PJ1101 @
1
JUMP_43X39
JUMP_43X79
2
PU1102
2
VIN_0.775VALW 1
VIN NC
8 +3VALW
PC1102 2 7
GND NC
1
4.7U_0603_6.3V6M
3.24K_0402_1%
D D
1
3 6 PC1103
VREF VCNTL 1U_0402_6.3V6K
+3VALW
PR1102
1
2
4 5
VOUT NC
9
2
2
TP
PR1148 VREF_0.775VALW APL5336KAI-TRL_SOP8P8
100K_0402_1%
1
@ PR1144
0.1U_0402_16V7K
SSM3K7002FU_SC70-3
+0.775VALWP
1
D
PQ1102
1K_0402_1%
PR1104
0_0402_5%
1
<38,40,41> 3V/5VALW_PG 1 2 2
PC1104
1
G
Fsw=400K Hz
2
PR1103 PC1105
SSM3K7002FU_SC70-3
S
2
1
1
D 10U_0805_6.3V6M
PQ1106
PR1106 10K_0402_1% 0_0402_5%
2
LGATE_GNB1 1 2 <31,40,41> 095_18ALW_PWR_EN 1 2 2
PR1105 G
1
41.2K_0402_1% PHASE_GNB1 S
3
PR1108 10K_0402_1% PC1106
2
UGATE_GNB11 2 0.1U_0402_16V7K
2
VRHOT Assert Threshold : 0.64V PR1109
TSENSE Bias Current : 30uA 2
BOOT_GNB1 1
+5VALW
41
40
39
38
37
36
35
34
33
32
31
Reset Threshold: 0.66V, 98C active PU1101 1_0402_5%
110C Assert Threshold: PR1016=27.4K
TP
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
100C Assert Threshold: PR1016=16.9K
PR1110 100K_0402_1%
1 2 1 30
NTC_NB BOOT2
PR1111 100K_0402_1%
1 2 IMON_GNB 2 29
IMON_NB UGATE2
3 28
<7> GFX_SVC SVC PHASE2 GFX_B+
4 27 +5VALW
<31,37,42> PROCHOT# VR_HOT_L LGATE2 EMI@ PL1101
@ PR1112 100K_0402_1%
1 2 5 26 HCB2012KF-121T50_0805
B+
+3VS <7> GFX_SVD SVD VDDP
PR1113 ISL62771HRTZ-T_TQFN40_5X5 PR1114 1 2
+1.8VS 10_0402_5% 2 VDDIO_GFX 6 25 1 2
PR1145 0_0402_5% VDDIO VDD 1_0603_5%
1U_0603_10V6K
1
@PR1115 0_0402_5% 1 2 7 24 LG1_GFX
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
<7> GFX_SVT SVT LGATE1
1
C 1 2 C
1U_0603_10V6K
+1.5VS
PC1101 8 23
PC1108
EN_GFX LX1_GFX
2
ENABLE PHASE1
1
PC1107
EMI@PC1109
EMI@PC1110
PC1111
PC1112
0.1U_0402_25V6K
2
1 @ PR11172 9 22 UG1_GFX
<42,7> APU_PWRGD PWROK UGATE1
2
1 2 0_0402_5% IMON_GFX 10 21 BST1_GFX
IMON BOOT1 +3VALW
PR1118
PGOOD
133K_0402_1%
ISUMN
ISUMP
COMP
ISEN2
ISEN1
VSEN
NTC
RTN
PWROK no need pull high for 1 2 PC1113 FB
1
AMD KABINI 1000P_0402_50V7K
5
PR1120 PR1121
11
ISEN2_GFX 12
ISEN1_GFX 13
14
15
16
17
18
19
20
PQ1101
27.4K_0402_1% 20K_0402_1% PR1119
1 2 1 2 100K_0402_1%
2
PR1122 0_0603_5%
UG1_GFX 1 2 4
APU_VRM_GFX_PWRGD <8>
1 2
PH1101 LX1_GFX SH00000OY00 (DCR:0.98±5%) +APU_GFX
2
PR1123 PL1102
0_0402_5%
10K_0402_1%
470K_0402_5%_TSM0B474J4702RE
PR1124
PR1125
VRHOT Assert Threshold : 0.64V 2.2_0603_1% 0.22UH_PCME064T-R22MS_28A_20%
3
2
1
BST1_GFX 1 2 1
BST1_GFX_R 2 1 4
TSENSE Bias Current : 30uA
PH1002=27.4K, 110C active GFX15W@ PC1114 2 3
1
5
GFX15W@ 0.22U_0603_25V7K
Reset Threshold: 0.66V, 98C active +5VS
1
PQ1103
PQ1104
110C Assert Threshold: PR1031=27.4K 15W
PR1126@EMI@
100C Assert Threshold: PR1031=16.9K PC1118 4.7_1206_5%
PC1117 PR1128 180P_0402_50V8J @ PR1127 @
1000P_0402_50V7K 301_0402_1% 32.4K_0402_1% LG1_GFX 4 4
2
VSUM+_GFX 1 2 1 2 1 2 1 2
GFX_core
330P_0402_50V7K
1
@ PC1119
PC1120@EMI@
2.61K_0402_1%
1
PR1130 PR1131 PC1123 680P_0603_50V7K TDC 22A

10K_0402_5%_ERTJ0ER103J
3
2
1
3
2
1
0.1U_0603_16V7K
PR1129
0.022U_0402_25V7K
1.78K_0402_1% 137K_0402_1% 390P_0402_50V7K

11K_0402_1%
2
1
1 2 1 2 1 2 Peak Current 35A

PC1121
2
1
1
PR1132
PC1122
OCP current > 48A

1 2
PR1133 PC1124
Load line -2.1mV/A
2
2K_0402_1% 330P_0402_50V7K
2
1 2 1 2
FSW=450kHz
PH1102
B
PR1134 PR1135
PR1136
3.65K_0603_1%
DCR 0.98mohm +/-5% B
2
681_0402_1% 10_0402_5% VSUM+_GFX 1 2 TYP MAX

VSUM-_GFX 1 2 1 2 +APU_GFX
H/S Rds(on) :11.7mohm , 14mohm
@ PC1126 @ PR1137
L/S Rds(on) :2.7mohm , 3.3mohm
1
@ PR1138 820P_0402_50V7K 0_0402_5%

PC1125 100_0402_1% 1 2
0.1U_0603_50V7K 1 2 1 2 APU_GFX_SEN_H <7>
2
@ PR1139 PR1140
0_0402_5% 1_0402_1%
1 2 VSUM-_GFX 1 2
APU_GFX_SEN_L <7>
0.01U_0402_50V7K
PR1141
10_0402_5%
1
PC1127
1 2
2
PR1147
2 1
<31,42> VR_ON
47K_0402_1% EN_GFX
PR1146
1
10K_0402_1% D
<8> VDDGFX_PD
1 2 2 PQ1105 GPU 15W setting
G 2N7002KW_SOT323-3
1000P_0402_50V7K
S
3
1
PC1129
PR931=536 ohm, PR924=1K ohm, PC925=0.1uF,

PR944 =0 ohm, PR920=10K ohm,
2
PC961 @, PC962 @, PR938 @ and PR939 @

while PR931=536 ohm to set OCP for GPU 15W application.
A A
Power Dissipation: H/S 0.720W

L/S 0.876W

PWR- +APU_GFX/+0.775VALW for CZ
5 4 3 2 1
5 4 3 2 1
GPU_B+
+VGA_CORE
Module model information AMD EXO PRO
EMI@ PL901
TDC 28A
ISL62771_V1A.mdd for IC portion HCB2012KF-121T50_0805
B+ OCP > 38.55A
GPU_LGATE1 1 2
ISL62771_V1B.mdd for SW portion
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
GPU_PHASE1
1
EMI@ PC902
EMI@ PC903
PC904
PC905
PR905 PC906
2.2_0603_1% 0.22U_0603_25V7K
1
GPU_BOOT1 2 1 2
PQ901
2
D D
6
7 G2
@ PR904 S1/D2 5
GPU_UGATE1 1 2 1 S2
G1 4
0_0402_5% 2 S2
D1 3
S2
AON6932A_DFN5X6-8-7
@ PR946
1 2 Fsw=400K Hz
1
0_0402_5% PR902 10K_0402_1%
GPU_LGATE_NB1 1 2
@ PR947 PR945
1 2 41.2K_0402_1% GPU_PHASE_NB1 SH00000OY00 (DCR:0.98±5%)
0_0402_5% PR903 10K_0402_1% PL902 +VGA_CORE
2
GPU_UGATE_NB1 1 2 0.22UH_PCME064T-R22MS_28A_20%
VRHOT Assert Threshold : 0.64V 1 4
PR906
TSENSE Bias Current : 30uA GPU_BOOT_NB1 2 1 2 3
+5VALW
390U_2.5V_M
390U_2.5V_M
330U_D2_2V_Y
330U_D2_2V_Y
1 1 1 1
1
1_0402_5%
41
40
39
38
37
36
35
34
33
32
31
Reset Threshold: 0.66V, 98C active + + + +
PC910
PC907
PC908
PC909
PU901 PR907 @EMI@ 25W@ PR938 25W@PR939
25W@ PR939
110C Assert Threshold: PR1016=27.4K 4.7_1206_5% 10K_0402_1% 10K_0402_1%
TP
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
100C Assert Threshold: PR1016=16.9K GPU_ISEN11 2 1 2 GPU_ISEN2
2 2 2 2
2
PR901 100K_0402_1%
1 2 1 30 GPU_BOOT2 PR908
1
NTC_NB BOOT2 PC911 @EMI@ 3.65K_0603_1%
PR909 100K_0402_1%
1 2 GPU_IMON_NB 2 29 GPU_UGATE2 680P_0603_50V7K GPU_VSUM+1 2
IMON_NB UGATE2
2
3 28 GPU_PHASE2
<15> GPU_PROCHOT# <15> GPU_SVC SVC PHASE2 PR910
@ PR911 100K_0402_1% 4 27 GPU_LGATE2 +5VALW 1_0402_1% 1/7 change to H=6 CAP_SF000002O00
1 2 VR_HOT_L LGATE2 1
GPU_VSUM- 2
+3VS
5 26
<15> GPU_SVD SVD VDDP
@PR912 0_0402_5% ISL62771HRTZ-T_TQFN40_5X5 PR913
+1.8VGS 1 2 6
GPU_VDDIO 25 1 2
VDDIO VDD 1_0603_5%
1U_0603_10V6K
1
PR914 0_0402_5% 7 24 GPU_LGATE1

<15> GPU_SVT SVT LGATE1
1
C 1 2 GPU_B+ C
@ PR915 GPU_LGATE2
1U_0603_10V6K
+3VGS
PC901 1 2 8 23
PC913
GPU_ENABLE GPU_PHASE1
<16,31,8> DGPU_PWR_EN
2
ENABLE PHASE1
PC912
0.1U_0402_25V6K 0_0402_5%
2
1 @ PR937 2 9 22 GPU_UGATE1
PR912 for MESO <45,8> DGPU_PWROK PWROK UGATE1 GPU_PHASE2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
0_0402_5%
PR914 for EXO pro 1 2 10
GPU_IMON
IMON BOOT1
21 GPU_BOOT1
+3VS
PC915
PR916 25W@ PR928 25W@PC922
25W@PC922
1
PGOOD
PC916
PC917
PC918
133K_0402_1% 2.2_0603_1% 0.22U_0603_25V7K
ISUMN
ISUMP
PQ902
COMP
ISEN2
ISEN1

VSEN
GPU_BOOT2 1 2 1 2
NTC
RTN
PWROK no need pull high for 1 2 PC914 FB 6
2
G2
1
1000P_0402_50V7K 7
FOR PE Bruce
AMD KABINI S1/D2
PR919 PR918 @ PR921 0_0402_5% 5
11
GPU_ISEN2 12
GPU_ISEN1 13
14
15
16
17
18
19
27.4K_0402_1% 20K_0402_1% 20 PR917 GPU_UGATE2 1 2 1 S2 EMI@

1 2 1 2 100K_0402_1% G1 4 EMI@
2 S2
2
D1 3
S2 25W@ 25W@
DGPU_PWROK <45,8>
1 2
PH901 AON6932A_DFN5X6-8-7
2
2
0_0402_5%
10K_0402_1%
470K_0402_5%_TSM0B474J4702RE
PR944
PR920
VRHOT Assert Threshold : 0.64V 25W 25W@

TSENSE Bias Current : 30uA
0.22U_0402_10V6K
0.22U_0402_10V6K
PH1002=27.4K, 110C active 15W@

1
PC962
PC961
15W@
Reset Threshold: 0.66V, 98C active +5VS SH00000OY00 (DCR:0.98±5%)
110C Assert Threshold: PR1031=27.4K 15W PL903 +VGA_CORE
2
100C Assert Threshold: PR1031=16.9K 25W@ 25W@ PC920 0.22UH_PCME064T-R22MS_28A_20%

GPU_VSUM- PC919 PR922 100P_0402_50V8J @ PR923 1 4
1000P_0402_50V7K 301_0402_1% 32.4K_0402_1%
GPU_VSUM+ 1 2 1 2 1 2 1 2 2 3
330P_0402_50V7K
@ PC921
PR940 PR943
2.61K_0402_1%
25W@
1
1
25W@ 25W@PR924 PR925 PC923 PR929 @EMI@ 10K_0402_1% 25W@ 10K_0402_1% 25W@
10K_0402_5%_ERTJ0ER103J
GPU_ISEN21 2 1 2
PR926
0.047U_0402_25V7K
0.15U_0603_16V7K
1.54K_0402_1% 137K_0402_1% 390P_0402_50V7K 4.7_1206_5% GPU_ISEN1

11K_0402_1%
1
1 2 1 2 1 2
PC924
2
1
1
PR927
PC925
PR942
1 2
1 2
PR930 PC926 3.65K_0603_1% 25W@
2
2K_0402_1% 330P_0402_50V7K GPU_VSUM+1 2

2
1 2 1 2 PC927 @EMI@
PH902
680P_0603_50V7K
2
B PR941 B
25W@PR931 PR932 1_0402_1% 25W@
2
332_0402_1% 10_0402_5% 1
GPU_VSUM- 2
GPU_VSUM- 1 2 1 2 +VGA_CORE
@ PC929 @ PR933 +VGA_CORE
1
@ PR934 820P_0402_50V7K 0_0402_5%

PC928 100_0402_1% 1 2
0.1U_0603_50V7K 1 2 1 2 GPU_VDD_SEN <15> Power Dissipation: H/S 0.720W
2
@ PR935
0_0402_5% L/S 0.876W
1 2
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
GPU_VDD_RUN_FB_L <15>
0.01U_0402_50V7K
PR936
1
PC931
PC932
PC933
PC934
PC935
PC936
PC937
PC938
PC939
PC940
PC941
PC942
PC943
PC944
PC945
PC946
10_0402_5%
1
PC930
1 2
2
2
GPU 15W setting
15W@ PR931 15W@ PR924 15W@ PC925

PR931=536 ohm, PR924=1K ohm, PC925=0.1uF, 536_0402_1% 1K_0402_1% 0.1U_0603_25V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
PR944 =0 ohm, PR920=10K ohm,
1
PC961 @, PC962 @, PR938 @ and PR939 @
PC947
PC948
PC949
PC950
PC951
PC952
PC953
PC954
PC955
PC956
PC957
PC958
PC959
PC960
while PR931=536 ohm to set OCP for GPU 15W application.
2
A A

2015/03/06 2016/03/06 Title
Issued Date Deciphered Date PWR- +VGA_CORE
5 4 3 2 1
A B C D E
EC_ON
+3VLP
B+
+EC_VCCA
PU401
SYX198BQNC
+3VALW
+3V_LAN
1 1
SUSP#
U13 +3VS
APE8990GN3B
SUSP#
PU702 +1.5VS
APL5930KAI
DGPU_PWR_EN
QV16 +3VGS
LP2301ALT1G
095_18ALW_PWR_EN
PU701 +1.8VALW
SY8003DFC
SUSP#
U1895P +1.8VS
APE8990GN3B
2 2
DGPU_PWR_EN
U1895V +1.8VGS
APE8990GN3B
EC_ON
+VL
PU402
SYX198CQNC
U13 +5VS
APE8990GN3B
SUSP# / SYSON
+0.675VS
PU501
RT8207PGQW
+1.35V
DGPU_PWR_EN#
UV14 +1.35VGS
3
AP4800BGM-HF 3
095_18ALW_PWR_EN
PU601 +0.95VALW
SYX198DQNC
095VS_PWR_EN
U1895P +0.95VS
APE8990GN3B
DGPU_PWR_EN
U1895V +0.95VGS
APE8990GN3B
DGPU_PWR_EN
PU901 +VGA_CORE
ISL62771HRTZ-T
VR_ON
+APU_CORE
PU801
ISL62771HRTZ-T
+APU_CORE_NB
4 4

2015/03/06 2016/03/06 Title
Issued Date Deciphered Date Power Map
Custom LA-C293P 1.0
A B C D E
5 4 3 2 1
+3VALW B+
+3VALW / +1.8VALW / +0.95VALW
+3VS / +1.8VS / +1.5VS / +0.95VS
+3VLP +3VALW
+APU_CORE / +APU_CORE_NB
+3VGS / +1.35VGS
PU701 PU601 +RTCBATT
+1.8VGS / +0.95VGS
+1.8VALW +0.95VALW
V V +3VGS +VGA_CORE
D EC EC_RSMRST# 5 D
V V
3A 3B
PBTN_OUT# 6 APU 19
095_18ALW_PWR_EN PXS_RST# 20
V V
SLP_S3# / SLP_S5# 7 AND GPU_RST# GPU
V
GATE Jet LE S3
V V
4A 5
B+ B+
KBRST# 10 18 APU_PCIE_RST#
3B 5
V
16 APU_PWRGD +3VS +1.5VA
PU402 PU401 SYS_PWRGD_EC 15
12 DGPU_PWROK
V
+5VALW / VL +3VALW/+3VLP
V
V V
LPC_RST# 17
V
2A 2B EC_ON
WLAN / WiMAX
V
NGFF WLAN/BT Card
1A ACIN
V V
B+ +5VS +3VS
13 DGPU_PWR_EN 11
V
C C
ON/OFF#
4A 1B
+5VS / +3VS / +1.8VS
+5VALW B+ PU901
AC MODE
V
+VGA_CORE
VIN
16 +1.8VALW VL
+3V_LAN
APU_PWRGD 14
V
PU801 VGATE
V
BATT MODE +APU_CORE /
VR_ON U1895V
BATT+ +APU_CORE_NB
V
+3VALW +5VALW
V
LAN
V
+1.8VGS
SYSON
SUSP#
+5VALW VL
RTC Battery
QV16
V
+CHGRTC_R 8 9 095VS_PWR_EN 9 +3VGS
+3VALW +0.95VALW VL
V
B
+5VALW +3VALW VL U13 B
B+ +5VS
+CHGRTC_R +3VLP VIN BATT+ U1895V
V
+1.8VALW VL
U13 +1.35V B+
+0.95VGS
V
PU501 +3VS
V
UC3 PU301 +1.35V

+1.5V U1895P
V
+RTCBATT B+ UV14
V
+1.8VS
+1.35VGS
+3VALW
PU702 +5VALW
V
+0.95VALW VL
B+
+1.5VS
MODEL NAME: PU501 U1895P

V
V
A
PCB NAME: +0.675VS +0.95VS A
REVISION:
DATE: 2014/11/18 Security Classification Compal Secret Data Compal Electronics, Inc.
2015/03/06 2016/03/06 Title
Issued Date Deciphered Date Power Sequence Block
COMPAL CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
Date:
LA-C293P
Monday, March 09, 2015 Sheet 47 of 48
Rev
1.0
5 4 3 2 1

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Lenovo B41-35 Compal LA-C293P AAWBC - BD Rev 1.0 PDF

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A B C D E

B/N series AMD

Security Classification Compal Secret Data Compal Electronics, Inc.

eDP Conn. DP0

Right USB 2.0

TCM Int. MIC Int. Speaker Conn. Audio Combo Jacks

14" Sub-borad 15" Sub-borad

IO/B Int.KBD Touch Pad Thermal Sensor

3 EC_SMB_CK2 EC 388N V X X X V V 8111H_LDO@

EC_SMB_DA2 +3VS +3VS +3VS +3VS Touch Screen

Device Address HEX @ Unpop

EXO Pro VRAM STRAP Power-Up/Down Sequence

Global ASIC Reset

Security Classification Compal Secret Data Compal Electronics, Inc.

D U10 R1 PCIE_ATX_DRX_P0 CC15 1 2 0.1U_0201_10V7K D

L7 P_GFX_RXP[3] P_GFX_TXP[3] J1 PCIE_ATX_GRX_P3 CC13 PX_CZL@ 1 2 0.1U_0402_16V7K

J7 P_GFX_RXP[7] P_GFX_TXP[7] G4 UAPU1

PCIe GPP: Four x1 Gen2

Security Classification Compal Secret Data Compal Electronics, Inc.

MA_DATA[16] G22 MB_DATA[16] E30 DDRAB_SDQ16

A6@ +1.35V RPC1 +MEM_VREF

UAPU1C +1.8VS +3VS

APU_TDO H14 TDO VDDCR_CPU_SENSE G12

+1.8VS +3VS APU_DBRDY C13 DBRDY

CZ@ APU_PWRGD APU_DBREQ# A11 DBREQ_L

CZ@ CZL@ CC126 CC127 FP4 REV 0.93

ESDP@ ESDP@ FP4_BGA968

RC109 1 CZ@ 2 2.2K_0402_5% EC_SMB_CK2

Security Classification Compal Secret Data Compal Electronics, Inc.

15K_0804_8P4R_5% AY15 ESPI_RESET_L/KBRST_L/AGPIO129

RC60 1 2 10K_0402_5% APU_PCIE_W AKE# A6@ MEM_VOLT_SEL1/AGPIO3 RTC_CLK BLINK/AGPIO11 SYS_RST#

RC66 1 CZL@ 2 10K_0402_5% APU_SCLK1 +3VS +3VALW

2 1 32K_X2 2 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5%

+0.95VS RC88 2 1 1K_0402_1% SATA_ZVDD AW2 SATA_ZVDDP USB_HSD3P AN3 YC2

APU_SPI_AOSI_U 1 8 APU_SPI_AOSI 2 EMIP@ 1 LPC_CLK0_APU AW14 USB_SS_1TXP AA2

FP4 REV 0.93

1 Under APU UAPU1F 1

AG28 VDDIO_MEM_S3_26 VDDCR_CPU_26 AE12

AK25 VDDIO_MEM_S3_30 VDDCR_CPU_32 AG13

VDDCR_CPU_49 AN6 0.775VALW_GATE

+1.8VALW AP10 VDD_18_S5_1 VDDCR_CPU_41 AK6

AL13 VDDCR_NB_2 VDDCR_GFX_1 F12

AN13 VDDCR_NB_6 VDDCR_GFX_5 J8

VDDCR_GFX_30 T12 CZ@ QC7A

PX@ PX@ VDDCR_GFX_34 U13

VDDCR_GFX_36 U19 ME2N7002D1KW-G 2N_SOT363-6

FP4 REV 0.93 CZ@

+APU_GFX CC109 @ 0_0402_5%

S 2N7002H_SOT23-3 for Clear CMOS

FP4 REV 0.93 FP4 REV 0.93

Security Classification Compal Secret Data Compal Electronics, Inc.

+VREF_DQ_R R187 2 1 0_0402_5%

DDRAB_SMA9 85 A12/BC# A11 86 DDRAB_SMA7

+VREF_DQ +1.35V +1.35V

Security Classification Compal Secret Data Compal Electronics, Inc.

PCI EXPRESS INTERFACE

R29 T26 No Use GPU Display Port outpud

UV2 PX@ AH20

<25,26,27,8> APU_PCIE_RST# B PERSTB TXCBM_DPB3N

216-0841018 A0 SUN PRO S3 EXO@

Security Classification Compal Secret Data Compal Electronics, Inc.

2 2 @ Y8 AJ7 4.53k 4.99k 100

@ FOR MESO only NC#AL7 8.45K_0402_1%