Lenovo Z40-70 LA-C281P (AIWZ0 AIWZ1) Rev 1.0 SchematicDiagram

A B C D E
1 1
Compal Confidential
2 2
AIWZ0/AIWZ1
DIS M/B Schematics Document
Intel Boardwell U Processor with DDR3L
AMD Meso XT / Tropo XT2
2015-02-02
3 3
LA-C281P
：1.0
REV：
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

2014/09/01 2015/09/01 Title
Issued Date Deciphered Date Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C281
Date: Friday, February 06, 2015 Sheet 1 of 50
A B C D E
A B C D E
For DIS
1
AMD Meso XT S3( 25W~35W) 1
PCIe X4
VRAM(DDR3L) 2GB/4GB (Gen2)
Memory Bus
AMD Tropo XT2 M2 (Max. 40W) A-ch DDR3L-SO-DIMM X1
VRAM(DDR3L) 2GB/4GB DDR3L 1600MHz (1.35V)
Memory Bus
eDP X1
B-ch DDR3L-SO-DIMM X1
(2 Lanes) DDR3L 1600MHz (1.35V)
Page25 eDP Panel
Intel Broadwell U Left USB3.0 x2 Right USB2.0 x1

Page27 USB3.0 x3
DDI X1 15W
CRT Translator (2 Lanes)
CRT Conn. Realtek USB2.0 x5 Int. Camera Card Reader
2
RTD2168-CG 1168pin BGA Normal Camera (USB2.0) Realtek 2
3D Camera (USB3.0) RTS5170-GR
DDI X1 Option
(4 Lanes)
Page26 HDMI Conn.
SATA X1 HDD Conn.
Page34
PCIe X1 SATA Port 0
LAN (1 Lanes)
PCIe Port 0
RJ45 Conn. Realtek Page28
RTL8111H
SATA X1 ODD Conn.
GIGA
SATA Port 1
Audio Codec
AZALIA Realtek Page35
ALC3240
PCIe X1
Page29 NGFF Conn. (1 Lanes)
WLAN / BT
3 USB2.0 X1 Int. MIC Conn. Int. Speaker Conn. Audio Combo Jacks 3
(1 Lanes) HP & MIC
PCIe Port 1
LPC BUS
Sub-borad
Option
SPI ROM EC TCM
Nuvoton Nationz Page30
8MB NPCE288N Z32H320TC
15"
Page08 Page33
14"
Power/B Thermal Sensor Touch Pad Int. KBD
Option
ODD/B
IO/B Digital MIC

4
15" 3D camera only 4

Issued Date 2014/09/01 Deciphered Date 2015/09/01 Title
MB Block Diagram
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D E
1 2 3 4 5
Voltage Rails USB Port Table BOM Structure Table

3 External Item BOM Structure
USB 2.0 Port USB Port AIWZ0 (14") Z14@
+5VS 0 USB Port (Left Side) USB3.0 AIWZ1 (15") Z15@
UHCI0
+3VS 1 USB Port (Left Side) USB3.0 AIWZ0 (17") Z17@
power
plane +1.5VS 2 Sub Board LAN Switch mode SWITCH@
UHCI1
+1.05VS 3 CardReader LAN RTL8111GS-CG 8111GLDO@
EHCI1
+5VALW +1.35V +VCC_CORE 4 Touch Screen WLAN Support ISCT ISCT@
A UHCI2 A
B+ +VGA_CORE 5 Camera WLAN No Support ISCT NOISCT@
+3VALW +1.8VS 6 Bluetooth (NGFF) For Green CLK GCLK@
UHCI3
+0.675VS 7 For No Green CLK NOGCLK@
State +1.05VS 8 Green CLK IC For DIS GCLKDIS@
UHCI4
9 Green CLK IC For UMA GCLKUMA@
10 For system DIS PX@
EHCI1 UHCI5
11 For TROPO DIS pop DIS@
12 For TROPO DIS unpop @DIS@
UHCI6
13 For UMA UMA@
3D Camera 3DCMOS@
S0 O O O O Camera CMOS@
HDMI HDMI@
BDW_CPU NO keyboard backlight NOKBL@
S3 O O O X UC1
Keyboard backlight KBL@
SA000089A60 I7-5500U
S IC FH8065801620004 SR23W F0 2.4G C38!
HDMI Royalty 45@
I7_5500@
S5 S4/AC O O X X Connector ME@
UC1
SA000089970 I5-5200U
Un-pop component for EMI @EMI@
S IC FH8065801620204 SR23Y F0 2.2G C38!
S5 S4/ Battery only O X X X I5_5200@
Un-pop component for ESD @ESD@
B UC1
pop component for EMI EMI@ B
SA000089880 I3-5010U
S5 S4/AC & Battery
X X X X S IC FH8065801620406 SR23Z F0 2.1G C38!
pop component for ESD ESD@
don't exist I3_5010@
Un-pop for TPM TPM@
UC1
SA000083EH0 I3-5005U
pop for TPM NOTPM@
S IC FH8065801884006 SR244 F0 2G C38!
I3_5005@
VRAM indentify X76@
For TROPO function TROPO@
ADB function ADB@
EC SM Bus1 address EC SM Bus2 address PCB NO ADB function NOADB@
ZZZ
DAZ1BK00101
CPU_SA000083E30 QGZ3@
Device Address Device Address
PCB AIWZ0 LA-C281P LS-C281P/C282P 02
Smart Battery 0001 011x Thermal Sensor 0100 1100 Z14@
CPU_SA000083C10 QH17@
PCB AIWZ0 LA-C281P LS-C281P/C282P 02
CPU_SA00007AM00 QFSY@
ZZZ
DAZ1BJ00101
CPU_SA000083A10 QH15@
PCH SM Bus address AMD-GPU SM Bus address PCB AIWZ1 LA-C281P LS-C281P/C282P/C283P/C285P/C286P 02
Z15@
CPU_SA000083D30 QH18@
PCB AIWZ1 LA-C281P LS-C281P/C282P/C283P/C285P/C286P 02
CPU_SA00007UG00 QGHA@
Device Address Device Address
DDR_JDIMM1 1010 000x A0h Internal thermal sensor 0100 0001 41h
CPU_SA00007UH00 QGHB@
DDR_JDIMM2 1010 010x A4h
CPU_SA00007U900 QGH9@
SMBUS Control Table

C C
Thermal
SOURCE CRT BATT KB9012 SODIMM WLAN Sensor PCH
EC_SMB_CK1
NPCE288
EC_SMB_DA1 +3VALW X V
+3VALW
X X X X X
EC_SMB_CK2
NPCE288
EC_SMB_DA2 +3VS
V
+3VS
X X X X V
+3VS
V
+3VALW
PCH_SMBCLK
PCH
PCH_SMBDATA +3VALW
X X X V
+3VS
X X X
PCH_SML0CLK
PCH
PCH_SML0DATA +3VALW
X X X X X X X
SML1CLK
SML1DATA
PCH
+3VALW
V
+3VS
X V
+3VS
X X V
+3VGS
X
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH ON ON ON ON
S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW

D D
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF

Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2014/09/01 Deciphered Date 2015/09/01
Size
Notes List
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Date:
LA-C281
Friday, February 06, 2015 Sheet 3 of 50
1 2 3 4 5
5 4 3 2 1
D D
UC1A BDW_ULT_DDR3L(Interleaved)
C54 C45
<19> CPU_DP1_N0 C55 DDI1_TXN0 EDP_TXN0 B46 EDP_TXN0 <17>
<19> CPU_DP1_P0 DDI1_TXP0 EDP_TXP0 EDP_TXP0 <17>
CRT B58 A47
<19> CPU_DP1_N1 DDI1_TXN1 EDP_TXN1 EDP_TXN1 <17>
C58 B47
<19> CPU_DP1_P1 B55 DDI1_TXP1 EDP_TXP1 EDP_TXP1 <17>
A55 DDI1_TXN2 C47
A57 DDI1_TXP2 EDP_TXN2 C46
B57 DDI1_TXN3 EDP_TXP2 A49
DDI1_TXP3 DDI EDP EDP_TXN3 B49
eDP
HDMI_TX2-_CK C51 EDP_TXP3
<18> HDMI_TX2-_CK DDI2_TXN0
HDMI_TX2+_CK C50 A45 EDP_AUXN <17>
<18> HDMI_TX2+_CK C53 DDI2_TXP0 EDP_AUXN B45
HDMI_TX1-_CK EDP_AUXP <17>
<18> HDMI_TX1-_CK DDI2_TXN1 EDP_AUXP
HDMI_TX1+_CK B54
<18> HDMI_TX1+_CK DDI2_TXP1
HDMI_TX0-_CK C49 D20 EDP_COMP R1 1 2 24.9_0402_1%
HDMI <18> HDMI_TX0-_CK
HDMI_TX0+_CK B50 DDI2_TXN2 EDP_RCOMP A43 CPU_INV_PWM
+VCCIOA_OUT
<18> HDMI_TX0+_CK DDI2_TXP2 EDP_DISP_UTIL
HDMI_CLK-_CK A53 T1
<18> HDMI_CLK-_CK B53 DDI2_TXN3
HDMI_CLK+_CK
<18> HDMI_CLK+_CK DDI2_TXP3
EDP_COMP (R1):
Trace width=20 mils,Spacing=25mil,Max length=100mils
1 OF 19
BDW-ULT-DDR3L-IL_BGA1168
@
C C
UC1B BDW_ULT_DDR3L(Interleaved)
T2 D61
T3 K61 PROC_DETECT MISC
+1.05VS N62 CATERR J62 XDP_PRDY#
<25> H_PECI PECI PRDY K62 XDP_PREQ#
R2 1 2 62_0402_5% PREQ E60 XDP_TCK
PROC_TCK E61 XDP_TMS
R3 1 2 56_0402_5% H_PROCHOT#_R K63 JTAG PROC_TMS E59 XDP_TRST#
<25> H_PROCHOT# PROCHOT PROC_TRST
THERMAL F63 XDP_TDI
PROC_TDI F62 XDP_TDO
PROC_TDO
R4 1 2 10K_0402_5% H_CPUPWRGD C61
PROCPWRGD PWR
J60 XDP_BPM#0
BPM#0 H60 XDP_BPM#1
BPM#1 H61 XDP_BPM#2
+1.35V BPM#2 H62 XDP_BPM#3
R5 1 2 200_0402_1% SM_RCOMP0 AU60 BPM#3 K59 XDP_BPM#4
R6 1 2 470_0402_5% R7 1 2 120_0402_1% SM_RCOMP1 AV60 SM_RCOMP0 DDR3L BPM#4 H63 XDP_BPM#5
R8 1 2 100_0402_1% SM_RCOMP2 AU61 SM_RCOMP1 BPM#5 K60 XDP_BPM#6
DIMM_DRAMRST# AV15 SM_RCOMP2 BPM#6 J61 XDP_BPM#7
<15,16> DIMM_DRAMRST# SM_DRAMRST BPM#7
DDR_PG_CTRL AV61
<15> DDR_PG_CTRL SM_PG_CNTL1
1
C238 DDR3 Compensation Signals (R9, R10, R11): 2 OF 19

100P_0402_50V8J 20 mils to comp signals BDW-ULT-DDR3L-IL_BGA1168
2
ESD@ 25 mils to non-comp signals

500 mil for Max trace length
B
ESD B
ESD
H_CPUPWRGD
1
C237
100P_0402_50V8J
2
ESD@
A A

2014/09/01 2015/09/01 Title
Issued Date Deciphered Date BDW MCP(1/11) DDI,MSIC,XDP
5 4 3 2 1
5 4 3 2 1
Interleaved Memory
D D
UC1C BDW_ULT_DDR3L(Interleaved) UC1D BDW_ULT_DDR3L(Interleaved)
<15> DDR_A_D[0..15]
DDR_A_D0 AH63 AU37 M_CLK_DDR#0 M_CLK_DDR#0 <15>
SA_DQ0 SA_CLK#0 <16> DDR_B_D[0..15]
DDR_A_D1 AH62 AV37 M_CLK_DDR0 DDR_B_D0 AP58 AM38 M_CLK_DDR#2
SA_DQ1 SA_CLK0 M_CLK_DDR0 <15> SB_DQ0 SB_CK#0 M_CLK_DDR#2 <16>
DDR_A_D2 AK63 AW36 M_CLK_DDR#1 DDR_B_D1 AR58 AN38 M_CLK_DDR2
SA_DQ2 SA_CLK#1 M_CLK_DDR#1 <15> SB_DQ1 SB_CK0 M_CLK_DDR2 <16>
DDR_A_D3 AK62 AY36 M_CLK_DDR1 M_CLK_DDR1 <15> DDR_B_D2 AM57 AK38 M_CLK_DDR#3 M_CLK_DDR#3 <16>
DDR_A_D4 AH61 SA_DQ3 SA_CLK1 DDR_B_D3 AK57 SB_DQ2 SB_CK#1 AL38 M_CLK_DDR3
SA_DQ4 SB_DQ3 SB_CK1 M_CLK_DDR3 <16>
DDR_A_D5 AH60 AU43 DDR_CKE0_DIMMA DDR_CKE0_DIMMA <15> DDR_B_D4 AL58
DDR_A_D6 AK61 SA_DQ5 SA_CKE0 AW43 DDR_CKE1_DIMMA DDR_B_D5 AK58 SB_DQ4 AY49 DDR_CKE2_DIMMB
SA_DQ6 SA_CKE1 DDR_CKE1_DIMMA <15> SB_DQ5 SB_CKE0 DDR_CKE2_DIMMB <16>
DDR_A_D7 AK60 AY42 DDR_B_D6 AR57 AU50 DDR_CKE3_DIMMB
SA_DQ7 SA_CKE2 T13 SB_DQ6 SB_CKE1 DDR_CKE3_DIMMB <16>
DDR_A_D8 AM63 AY43 T9 DDR_B_D7 AN57 AW49 T10
DDR_A_D9 AM62 SA_DQ8 SA_CKE3 DDR_B_D8 AP55 SB_DQ7 SB_CKE2 AV50
SA_DQ9 SB_DQ8 SB_CKE3 T11
DDR_A_D10 AP63 AP33 DDR_CS0_DIMMA# DDR_CS0_DIMMA# <15> DDR_B_D9 AR55
DDR_A_D11 AP62 SA_DQ10 SA_CS#0 AR32 DDR_CS1_DIMMA# DDR_B_D10 AM54 SB_DQ9 AM32 DDR_CS2_DIMMB#
SA_DQ11 SA_CS#1 DDR_CS1_DIMMA# <15> SB_DQ10 SB_CS#0 DDR_CS2_DIMMB# <16>
DDR_A_D12 AM61 DDR_B_D11 AK54 AK32 DDR_CS3_DIMMB#
SA_DQ12 SB_DQ11 SB_CS#1 DDR_CS3_DIMMB# <16>
DDR_A_D13 AM60 AP32 T12 DDR_B_D12 AL55
DDR_A_D14 AP61 SA_DQ13 SA_ODT0 DDR_B_D13 AK55 SB_DQ12 AL32
SA_DQ14 SB_DQ13 SB_ODT0 T14
DDR_A_D15 AP60 AY34 DDR_A_RAS# DDR_A_RAS# <15> DDR_B_D14 AR54
<15> DDR_A_D[16..31] SA_DQ15 SA_RAS SB_DQ14
DDR_A_D16 AY58 AW34 DDR_A_WE# DDR_B_D15 AN54 AM35 DDR_B_RAS#
SA_DQ16 SA_WE DDR_A_WE# <15> <16> DDR_B_D[16..31] SB_DQ15 SB_RAS DDR_B_RAS# <16>
DDR_A_D17 AW58 AU34 DDR_A_CAS# DDR_B_D16 AK40 AK35 DDR_B_WE#
SA_DQ17 SA_CAS DDR_A_CAS# <15> SB_DQ16 SB_WE DDR_B_WE# <16>
C DDR_A_D18 AY56 DDR_B_D17 AK42 AM33 DDR_B_CAS# DDR_B_CAS# <16> C
DDR_A_D19 AW56 SA_DQ18 AU35 DDR_A_BS0 DDR_B_D18 AM43 SB_DQ17 SB_CAS
SA_DQ19 SA_BA0 DDR_A_BS0 <15> SB_DQ18
DDR_A_D20 AV58 AV35 DDR_A_BS1 DDR_A_BS1 <15> DDR_B_D19 AM45 AL35 DDR_B_BS0 DDR_B_BS0 <16>
DDR_A_D21 AU58 SA_DQ20 SA_BA1 AY41 DDR_A_BS2 DDR_B_D20 AK45 SB_DQ19 SB_BA0 AM36 DDR_B_BS1
SA_DQ21 SA_BA2 DDR_A_BS2 <15> SB_DQ20 SB_BA1 DDR_B_BS1 <16>
DDR_A_D22 AV56 DDR_B_D21 AK43 AU49 DDR_B_BS2
SA_DQ22 DDR_A_MA[0..15] <15> SB_DQ21 SB_BA2 DDR_B_BS2 <16>
DDR_A_D23 AU56 AU36 DDR_A_MA0 DDR_B_D22 AM40 DDR_B_MA[0..15] <16>
DDR_A_D24 AY54 SA_DQ23 SA_MA0 AY37 DDR_A_MA1 DDR_B_D23 AM42 SB_DQ22 AP40 DDR_B_MA0
DDR_A_D25 AW54 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D24 AM46 SB_DQ23 SB_MA0 AR40 DDR_B_MA1
DDR_A_D26 AY52 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D25 AK46 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
DDR_A_D27 AW52 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D26 AM49 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
DDR_A_D28 AV54 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D27 AK49 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
DDR_A_D29 AU54 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D28 AM48 SB_DQ27 SB_MA4 AP45 DDR_B_MA5
DDR_A_D30 AV52 SA_DQ29 SA_MA6 AW39 DDR_A_MA7 DDR_B_D29 AK48 SB_DQ28 SB_MA5 AW46 DDR_B_MA6
DDR_A_D31 AU52 SA_DQ30 DDR CHANNEL A SA_MA7 AY39 DDR_A_MA8 DDR_B_D30 AM51 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
<15> DDR_A_D[32..47] AY31 SA_DQ31 SA_MA8 AU40 AK51 SB_DQ30 SB_MA7 AY47
DDR_A_D32 DDR_A_MA9 DDR_B_D31 DDR_B_MA8
SA_DQ32 SA_MA9 <16> DDR_B_D[32..47] SB_DQ31 DDR CHANNEL B SB_MA8
DDR_A_D33 AW31 AP35 DDR_A_MA10 DDR_B_D32 AM29 AU46 DDR_B_MA9
DDR_A_D34 AY29 SA_DQ33 SA_MA10 AW41 DDR_A_MA11 DDR_B_D33 AK29 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D35 AW29 SA_DQ34 SA_MA11 AU41 DDR_A_MA12 DDR_B_D34 AL28 SB_DQ33 SB_MA10 AV47 DDR_B_MA11
DDR_A_D36 AV31 SA_DQ35 SA_MA12 AR35 DDR_A_MA13 DDR_B_D35 AK28 SB_DQ34 SB_MA11 AU47 DDR_B_MA12
DDR_A_D37 AU31 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_B_D36 AR29 SB_DQ35 SB_MA12 AK33 DDR_B_MA13
DDR_A_D38 AV29 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_B_D37 AN29 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D39 AU29 SA_DQ38 SA_MA15 DDR_B_D38 AR28 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
SA_DQ39 DDR_A_DQS#[0..1] <15> SB_DQ38 SB_MA15
DDR_A_D40 AY27 AJ61 DDR_A_DQS#0 DDR_B_D39 AP28 DDR_B_DQS#[0..1] <16>
DDR_A_D41 AW27 SA_DQ40 SA_DQSN0 AN62 DDR_A_DQS#1 DDR_B_D40 AN26 SB_DQ39 AM58 DDR_B_DQS#0
SA_DQ41 SA_DQSN1 DDR_A_DQS#[2..3] <15> SB_DQ40 SB_DQSN0
DDR_A_D42 AY25 AV57 DDR_A_DQS#2 DDR_B_D41 AR26 AM55 DDR_B_DQS#1
SA_DQ42 SA_DQSN2 SB_DQ41 SB_DQSN1 DDR_B_DQS#[2..3] <16>
DDR_A_D43 AW25 AV53 DDR_A_DQS#3 DDR_A_DQS#[4..5] <15> DDR_B_D42 AR25 AL43 DDR_B_DQS#2
DDR_A_D44 AV27 SA_DQ43 SA_DQSN3 AW30 DDR_A_DQS#4 DDR_B_D43 AP25 SB_DQ42 SB_DQSN2 AL48 DDR_B_DQS#3
DDR_A_D45 AU27 AV26 DDR_A_DQS#5 DDR_A_DQS#[6..7] <15> DDR_B_D44 AK26 AN28 DDR_B_DQS#4
DDR_A_D46 AV25 SA_DQ45 SA_DQSN5 AW22 DDR_A_DQS#6 DDR_B_D45 AM26 SB_DQ44 SB_DQSN4 AN25 DDR_B_DQS#5
DDR_A_D47 AU25 AV18 DDR_A_DQS#7 DDR_B_D46 AK25 AN21 DDR_B_DQS#6
<15> DDR_A_D[48..63] SA_DQ47 SA_DQSN7 SB_DQ46 SB_DQSN6
DDR_A_D48 AY23 DDR_A_DQS[0..1] <15> DDR_B_D47 AL25 AN18 DDR_B_DQS#7
AW23 SA_DQ48 AJ62 <16> DDR_B_D[48..63] AR21 SB_DQ47 SB_DQSN7
DDR_A_D49 DDR_A_DQS0 DDR_B_D48 DDR_B_DQS[0..1] <16>
DDR_A_D50 AY21 SA_DQ49 SA_DQSP0 AN61 DDR_A_DQS1 DDR_B_D49 AR22 SB_DQ48 AN58 DDR_B_DQS0
SA_DQ50 SA_DQSP1 DDR_A_DQS[2..3] <15> SB_DQ49 SB_DQSP0
DDR_A_D51 AW21 AW57 DDR_A_DQS2 DDR_B_D50 AL21 AN55 DDR_B_DQS1
SA_DQ51 SA_DQSP2 SB_DQ50 SB_DQSP1 DDR_B_DQS[2..3] <16>
DDR_A_D52 AV23 AW53 DDR_A_DQS3 DDR_B_D51 AM22 AL42 DDR_B_DQS2
DDR_A_D53 AU23 AV30 DDR_A_DQS4 DDR_B_D52 AN22 AL49 DDR_B_DQS3 DDR_B_DQS[4..5] <16>
DDR_A_D54 AV21 SA_DQ53 SA_DQSP4 AW26 DDR_A_DQS5 DDR_B_D53 AP21 SB_DQ52 SB_DQSP3 AM28 DDR_B_DQS4
DDR_A_D55 AU21 AV22 DDR_A_DQS6 DDR_B_D54 AK21 AM25 DDR_B_DQS5 DDR_B_DQS[6..7] <16>
B
DDR_A_D56 AY19 SA_DQ55 SA_DQSP6 AW18 DDR_A_DQS7 DDR_B_D55 AK22 SB_DQ54 SB_DQSP5 AM21 DDR_B_DQS6 B
DDR_A_D57 AW19 SA_DQ56 SA_DQSP7 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
DDR_A_D58 AY17 SA_DQ57 AP49 +SM_VREF_CA DDR_B_D57 AR20 SB_DQ56 SB_DQSP7
SA_DQ58 SM_VREF_CA +SM_VREF_CA <15> SB_DQ57
DDR_A_D59 AW17 AR51 +SM_VREF_DQ0 DDR_B_D58 AK18
SA_DQ59 SM_VREF_DQ0 +SM_VREF_DQ0 <15> SB_DQ58
DDR_A_D60 AV19 AP51 +SM_VREF_DQ1 +SM_VREF_DQ1 <16> DDR_B_D59 AL18
DDR_A_D61 AU19 SA_DQ60 SM_VREF_DQ1 DDR_B_D60 AK20 SB_DQ59
DDR_A_D62 AV17 SA_DQ61 DDR_B_D61 AM20 SB_DQ60
SA_DQ62 Trace width >= 10mils SB_DQ61
DDR_A_D63 AU17 DDR_B_D62 AR18
SA_DQ63 DDR_B_D63 AP18 SB_DQ62
SB_DQ63
3 OF 19 4 OF 19
BDW-ULT-DDR3L-IL_BGA1168 BDW-ULT-DDR3L-IL_BGA1168
A A

2014/09/01 2015/09/01 Title
Issued Date Deciphered Date BDW MCP(2/11) DDRIII
5 4 3 2 1
5 4 3 2 1
D D
GCLK
RG3 1 GCLK@ 2 0_0402_5% PCH_RTCX1
<28> CPU_RTCX1_GCLK
PCH_RTCX1
R9 1 2 10M_0402_5% PCH_RTCX2
NOGCLK@
2
R10 UC1E BDW_ULT_DDR3L(Interleaved)

0_0402_5% @
Y1 PCH_RTCX1 AW5
RTCX1
1
1 2 PCH_RTCX2 AY5
SM_INTRUDER# AU6 RTCX2 J5
INTRUDER SATA_RN0/PERN6_L3 SATA_PRX_DTX_N0 <20>
NOGCLK@ PCH_INTVRMEN AV7 H5
INTVRMEN SATA_RP0/PERP6_L3 SATA_PRX_DTX_P0 <20>
32.768KHZ_12.5PF_9H03200042 HDA for AUDIO PCH_SRTCRST# AV6 RTC B15
PCH_RTCRST# AU7 SRTCRST SATA_TN0/PETN6_L3 A15
SATA_PTX_DRX_N0 <20> HDD
1 1 RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0 <20>
C1 C2
12P_0402_50V8J 12P_0402_50V8J J8 SATA_PRX_DTX_N1 <20>
NOGCLK@ NOGCLK@ SATA_RN1/PERN6_L2 H8
2 2 SATA_RP1/PERP6_L2 SATA_PRX_DTX_P1 <20>
A17
RP1 SATA_TN1/PETN6_L2 B17
SATA_PTX_DRX_N1 <20> ODD
SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1 <20>
EMI@
<27> HDA_BITCLK_AUDIO 1 8 HDA_BIT_CLK AW8 J6
2 7 HDA_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
<27> HDA_SYNC_AUDIO HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1
3 6 HDA_RST# AU8 B14
4 5HDA_SDOUT HDA_SDIN0 AY10 HDA_RST/I2S_MCLK AUDIO SATA SATA_TN2/PETN6_L1 C15
C <27> HDA_SDOUT_AUDIO C
AU12 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1
33_0804_8P4R_5% HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0
1
@EMI@ AW10 E5
C227 AV10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 C17
22P_0402_50V8J
EMI AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17
2
I2S1_SCLK SATA_TP3/PETP6_L0
+RTCVCC
V1 PCH_GPIO34
1 2 0_0402_5% SATA0GP/GPIO34 U1 PCH_GPIO34 <9>
<25> ME_EN R11 @ SATA_ODD_PRSNT SATA_ODD_PRSNT <8>
R12 1 2 20K_0402_5% PCH_SRTCRST# HDA_SDIN0 SATA1GP/GPIO35 V6 PCH_GPIO36 +1.05VS_ASATA3PLL
<27> HDA_SDIN0 SATA2GP/GPIO36 PCH_GPIO36 <8>
AC1 PCH_GPIO37
SATA3GP/GPIO37 PCH_GPIO37 <9>
C3 1 2 1U_0402_6.3V6K PCH_JTAG_TRST# AU62
PCH_JTAG_TCK AE62 PCH_TRST A12
PCH_JTAG_TDI AD61 PCH_TCK SATA_IREF L11 +3VS
PCH_JTAG_TDO AE61 PCH_TDI RSVD K10
PCH_TDO RSVD within 500 mils
PCH_JTAG_TMS AD62 JTAG C12 SATA_RCOMP R13 1 2 3.01K_0402_1%
R14 1 2 20K_0402_5% PCH_RTCRST# AL11 PCH_TMS SATA_RCOMP U3 PCH_SATALED# R18 1 2 10K_0402_5%
AC4 RSVD SATALED
RSVD
2
C4 1 2 1U_0402_6.3V6K AE63
R509 @ AV2 JTAGX
CLRP2 1 2 SHORT PADS RSVD
Clear CMOS 0_0402_5%
1
D
1
R15 1 2 1M_0402_5% SM_INTRUDER# Q27 2

EC_CLEAR_CMOS <25>
2N7002K_SOT23-3 G 5 OF 19
S BDW-ULT-DDR3L-IL_BGA1168
1
R16 1 2 330K_0402_5% PCH_INTVRMEN

3
R80
R17 1 @ 2 330K_0402_5% 10K_0402_5%
：：
INTVRMEN:
2
(*) H Integrated VRM enable

( ) L Integrated VRM disable
B B
RTC Battery
+RTCVCC +RTCBATT
W=20mils
R19 1 @ 2 0_0402_5%
1
C5
1U_0402_6.3V6K
Safty suggestion remove EE side ,Keep PWR side
A A

2014/09/01 2015/09/01 Title
Issued Date Deciphered Date BDW MCP(3/11) RTC,SATA,XDP
5 4 3 2 1
5 4 3 2 1
GCLK
RG9 1 GCLK@ 2 0_0402_5% XTAL24_IN
<28> CPU_XTAL24_GCLK
RG11 1 @ 2 0_0402_5% XTAL24_OUT
UC1F BDW_ULT_DDR3L(Interleaved)
XTAL24_IN
C43 A25 XTAL24_IN R21 2NOGCLK@ 1 1M_0402_5% XTAL24_OUT

C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT
PCH_GPIO18 U2 CLKOUT_PCIE_P0 XTAL24_OUT Y2 NOGCLK@
<9> PCH_GPIO18 PCIECLKRQ0/GPIO18 K21 24MHZ_12PF_7V24000020
D
B41 RSVD M21 D
A41 CLKOUT_PCIE_N1 RSVD C26 XCLK_BIASREF R22 1 2 3.01K_0402_1% 1 3
CLKOUT_PCIE_P1 DIFFCLK_BIASREF +1.05VS_AXCK_LCPLL 1 3
PCH_GPIO19 Y5
<9> PCH_GPIO19 PCIECLKRQ1/GPIO19 C35 4 5 10K_0804_8P4R_5% GND GND
RP3 1 1
C41 CLOCK TESTLOW_C35 C34 3 6 C6
<26> CLK_PCIE_LAN# C7
B42 CLKOUT_PCIE_N2 TESTLOW_C34 AK8 2 7 15P_0402_50V8J 2 4 15P_0402_50V8J
LAN <26> CLK_PCIE_LAN AD1 CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8 AL8 1 8 NOGCLK@ NOGCLK@
<26> LANCLK_REQ# PCIECLKRQ2/GPIO20 TESTLOW_AL8 2 2
B38 AN15 CLKOUT_LPC0 R23 2 EMI@ 1 22_0402_5%
<21> CLK_PCIE_WLAN# CLKOUT_PCIE_N3 CLKOUT_LPC_0 CK_LPC_KBC <25>
WLAN C37 AP15 CLKOUT_LPC1 R58 2 1 22_0402_5%
<21> CLK_PCIE_WLAN CLKOUT_PCIE_P3 CLKOUT_LPC_1 CK_LPC_TPM <22>
N1 TPM@
<21> WLANCLK_REQ#
<30> CLK_PCIE_GPU#
A39
PCIECLKRQ3/GPIO21
CLKOUT_PCIE_N4
CLKOUT_ITPXDP
CLKOUT_ITPXDP_P
B35
A35 EMI
：DIMM1, DIMM2
B39
dGPU <30> CLK_PCIE_GPU
R25 1 @ 2 0_0402_5% GPUCLK_REQ#_R U5 CLKOUT_PCIE_P4
<31> GPUCLK_REQ# PCIECLKRQ4/GPIO22
B37
A37 CLKOUT_PCIE_N5 SMB
PCH_GPIO23 T2 CLKOUT_PCIE_P5
<9> PCH_GPIO23 PCIECLKRQ5/GPIO23 +3VS
+3VS
+3VS 6 OF 19
RP4 BDW-ULT-DDR3L-IL_BGA1168 @ R27 2.2K_0402_5%
1
2
UMA@ 1 8 Q1A 1 2
+3VS
R26 2 7 PCH_GPIO32
PCH_GPIO32 <8>
10K_0402_5% 3 6 EC_SCI# SMBDATA 6 1
EC_SCI# <9,25> PCH_SMB_DATA <15,16>
4 5
2N7002EDW_SOT363-6
2
10K_0804_8P4R_5%
GPUCLK_REQ#_R UC1G BDW_ULT_DDR3L(Interleaved)
2
LPC_AD0 AU14 AN2 PCH_GPIO11

<22,25> LPC_AD0 LAD0 SMBALERT/GPIO11 PCH_GPIO11 <9>
PX@ LPC_AD1 AW12 AP2 SMBCLK @ R29 2.2K_0402_5%
<22,25> LPC_AD1 LAD1 SMBCLK
5
R28 LPC_AD2 AY12 LPC AH1 SMBDATA Q1B 1 2
<22,25> LPC_AD2 LAD2 SMBUS SMBDATA +3VS
10K_0402_5% LPC_AD3 AW11 AL2 FW_UPDATE
<22,25> LPC_AD3 LAD3 SML0ALERT/GPIO60 FW_UPDATE <17>
LPC_FRAME# AV12 AN1 SML0CLK SMBCLK 3 4 PCH_SMB_CLK <15,16>
<22,25> LPC_FRAME#
1
LFRAME SML0CLK AK1 SML0DATA

SML0DATA AU4 PCH_GPIO73 2N7002EDW_SOT363-6
C C
SML1ALERT/PCHHOT/GPIO73 AU3 PCH_GPIO73 <9>
SML1CLK
+3VALW
EMI PCH_SPI_CLK
PCH_SPI_CS0#
AA3
Y7 SPI_CLK
SML1CLK/GPIO75
SML1DATA/GPIO74
AH3
AF2
SML1DATA
SPI_CS0 CL_CLK
1
@EMI@ Y4 AD2 SMBDATA R31 1 @ 2 0_0402_5% PCH_SMB_DATA
C225 AC2 SPI_CS1 SPI C-LINK
CL_DATA AF4
22P_0402_50V8J PCH_SPI_SI AA2 SPI_CS2 CL_RST SMBCLK R33 1 @ 2 0_0402_5% PCH_SMB_CLK
2
PCH_SPI_SO AA4 SPI_MOSI

PCH_SPI_WP# Y6 SPI_MISO
SPI_IO2
：Thermal IC, EC, dGPU

R34 1 2 1K_0402_1% PCH_SPI_HOLD# AF1
R35 1 2 1K_0402_1% SPI_IO3
SML1
7 OF 19
PCH_SPI_WP#_R R36 1 2 33_0402_5% PCH_SPI_WP# BDW-ULT-DDR3L-IL_BGA1168 +3VS
EMI RP5 EMI@ @ R37 2.2K_0402_5%
2
PCH_SPI_HOLD#_R 1 8 PCH_SPI_HOLD# Q2A 1 2 +3VS
To SPI 8MByte ROM PCH_SPI_CLK_R 2 7 PCH_SPI_CLK From PCH
PCH_SPI_SI_R 3 6 PCH_SPI_SI SML1DATA 6 1 EC_SMB_DA2 <19,22,25,31>
PCH_SPI_SO_R 4 5 PCH_SPI_SO
2N7002EDW_SOT363-6
33_0804_8P4R_5%
@ R39 2.2K_0402_5%
5
PCH_SPI_CS0#_R R38 1 @ 2 0_0402_5% PCH_SPI_CS0# Q2B 1 2 +3VS
SML1CLK 3 4 EC_SMB_CK2 <19,22,25,31>
2N7002EDW_SOT363-6
SML1DATA R41 1 @ 2 0_0402_5% EC_SMB_DA2
SML1CLK R42 1 @ 2 0_0402_5% EC_SMB_CK2
B B
+3VALW
@
RP7
SMBDATA 1 8
EMI RP8 EMI@

SMBCLK
SML1CLK
SML1DATA
2
3
4
7
6
5
1 8 PCH_SPI_CS0#_R
<25> EC_SPI_CS0#
2 7 PCH_SPI_CLK_R 2.2K_0804_8P4R_5%
<25> EC_SPI_CLK 3 6
From EC PCH_SPI_SI_R To SPI 8MByte ROM
<25> EC_SPI_MOSI
(For share ROM) 4 5 PCH_SPI_SO_R
<25> EC_SPI_MISO 1 2 499_0402_1%
SML0CLK R46
33_0804_8P4R_5% SML0DATA R47 1 2 499_0402_1%
EMI
1
@EMI@
C226
22P_0402_50V8J
2
+3VALW
SPI ROM ( 8MByte )

U1 @
PCH_SPI_CS0#_R 1 8 +3V_ROM C8 1 2 0.1U_0201_10V6K
CS# VCC
PCH_SPI_SO_R 2 7 PCH_SPI_HOLD#_R
SO IO3
PCH_SPI_WP#_R 3 6 PCH_SPI_CLK_R
IO2 SCLK
A 4 5 PCH_SPI_SI_R A
VSS SI
GD25B64BSIGR_SO8

2014/09/01 2015/09/01 Title
Issued Date Deciphered Date BDW MCP(4/11) CLK,SPI,SMBUS
5 4 3 2 1
5 4 3 2 1
ESD ESD ESD

SYS_PWROK EC_RSMRST# SYS_RESET#
1
1
ESD@ ESD@ ESD@
C239 C240 C246
100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J
2
2
D D
：
DSWODVREN - On Die DSW VR Enable
：
(*) H Enable(DEFAULT)
( ) L Disable
+RTCVCC
R49 1 2 330K_0402_5%
R50 1 @ 2 330K_0402_5%
UC1H BDW_ULT_DDR3L(Interleaved)
SYSTEM POWER MANAGEMENT
+3VALW AK2 AW7 DSWODVREN R53 1 @ 2 0_0402_5% EC_RSMRST#

SYS_RESET# AC3 SUSACK DSWVRMEN AV5 PCH_DPWROK R57 2 1 100K_0402_5%
<9> SYS_RESET# AG2 SYS_RESET DPWROK AJ5 1 2
<25> SYS_PWROK SYS_PWROK PCH_PCIE_WAKE# PCIE_WAKE# <21,25,26>
SYS_PWROK WAKE
1
<25> PCH_PWROK PCH_PWROK AY7 R216 @ 0_0402_5%

R54 R55 1 @ 2 0_0402_5% APWROK_R AB5 PCH_PWROK
10K_0402_5% CPU_PLT_RST# AG7 APWROK V5 PCH_GPIO32
PLTRST CLKRUN/GPIO32 PCH_GPIO32 <7>
AG4
SUS_STAT/GPIO61 AE6 SUSCLK
SUSCLK <21>
2
AC_PRESENT SUSCLK/GPIO62 AP5 PM_SLP_S5#

SLP_S5/GPIO63 PM_SLP_S5# <25>
EC_RSMRST# AW6
<25> EC_RSMRST# RSMRST
PCH_GPIO30 AV4
<9> PCH_GPIO30 SUSWARN/SUSPWRDNACK/GPIO30
<25> PBTN_OUT# PBTN_OUT# AL7 AJ6 PM_SLP_S4#
AJ8 PWRBTN SLP_S4 AT4 PM_SLP_S4# <25>
AC_PRESENT PM_SLP_S3#
ACPRESENT/GPIO31 SLP_S3 PM_SLP_S3# <25>
PCH_GPIO72 AN4 AL5
<9> PCH_GPIO72 BATLOW/GPIO72 SLP_A
T15 @ AF3 AP4
PCH_GPIO29 AM5 SLP_S0 SLP_SUS AJ7
<9> PCH_GPIO29 SLP_WLAN/GPIO29 SLP_LAN
+3VS
RP10
1 8 SERIRQ 8 OF 19
SERIRQ <9,22,25> BDW-ULT-DDR3L-IL_BGA1168
C 2 7 PCH_GPIO36 PCH_GPIO36 <6> C
3 6 TPMPD# TPMPD# <9>
4 5 SATA_ODD_PRSNT SATA_ODD_PRSNT <6>
10K_0804_8P4R_5% R59 2 @ 1 0_0402_5%
RP11
1 8 PCH_GPIO54 +3VS
2 7
3 6 PCH_GPIO52 @
ESD
5
4 5 U3
CPU_PLT_RST# 2
P
10K_0804_8P4R_5% B 4
Y PCIRST# <21,22,25,26,30>
1
A
1
G
RP12 1
1 8 PCH_GPIO68 PCH_GPIO68 <9> R60
3
2 7 DGPU_PWROK 100K_0402_5% C119
3 6 PCH_GPIO55 U74AHC1G08G-AL5-R_SOT353-5 10P_0402_50V8J
4 5 2
@
2
10K_0804_8P4R_5%
R61 1 2 2.2K_0402_5% DDI1_CTRL_CK

R62 1 2 2.2K_0402_5% DDI1_CTRL_DATA
UC1I BDW_ULT_DDR3L(Interleaved)
0_0402_5%
R63 1 @ 2 EDP_BKCTL B8 B9 DDI1_CTRL_CK
<17> INVPWM A9 EDP_BKLCTL DDPB_CTRLCLK C9 DDI1_CTRL_DATA
<17,25> ENBKL EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA
C6 D9
<17> PCH_ENVDD EDP_VDDEN DDPC_CTRLCLK HDMICLK_NB <18>
D11 HDMI DDC (Port C)
DDPC_CTRLDATA HDMIDAT_NB <18>
U6
<46> DGPU_PWROK PIRQA/GPIO77
P4 C5 DDI1_AUX_DN
B <25,32,43,46> DGPU_PWR_EN
N4 PIRQB/GPIO78 DDPB_AUXN B6
DDI1_AUX_DN <19> DP Aux (Port B for VGA) B
<30> DGPU_HOLD_RST# N2 PIRQC/GPIO79 DISPLAY DDPC_AUXN B5 DDI1_AUX_DP
<9,21> WLBT_OFF#
T16 @ AD4 PIRQD/GPIO80 DDPB_AUXP A6
DDI1_AUX_DP <19> DP Aux (Port B for VGA)
+3VALW PME PCIE DDPC_AUXP
PCH_GPIO55 U7
PCH_GPIO52 L1 GPIO55
PCH_GPIO54 L3 GPIO52 C8
GPIO54 DDPB_HPD DDI1_HPD <19> From VGA Trans.
PCH_GPIO51 R5 A8 TMDS_B_HPD <18> From HDMI
<9> PCH_GPIO51 L4 GPIO51 DDPC_HPD D6
R67 1 2 1K_0402_5% PCH_PCIE_WAKE# PCH_GPIO53 EDP_HPD <17> From eDP
<9> PCH_GPIO53 GPIO53 EDP_HPD
9 OF 19
+3VS BDW-ULT-DDR3L-IL_BGA1168
R223 1 2 10K_0402_5% DGPU_PWR_EN
+3VS
R225 1 2 10K_0402_5% DGPU_HOLD_RST#
A A

2014/09/01 2015/09/01 Title
Issued Date Deciphered Date BDW MCP(5/11) PM,GPIO,DDI
5 4 3 2 1
5 4 3 2 1
D D
+3VALW
1
RP13
8 EC_SCI#_2
ESD
2 7 PCH_GPIO47 H_THERMTRIP#
3 6 PCH_GPIO24
1
4 5 PCH_GPIO28 @
+1.05VS C241
10K_0804_8P4R_5% 100P_0402_50V8J
2
：
GPIO15 : TLS Confidentiality for iAMT
1
BDW_ULT_DDR3L(Interleaved)
：
RP14 @ ( ) H Intel ME TLS with conﬁden?ality UC1J
1 8 PCH_GPIO11 (*) L Intel ME TLS with no conﬁden?ality R68
PCH_GPIO11 <7>
2 7 1K_0402_1%
3 6
(Have internal PD)
PCH_GPIO26
4 5 PCH_GPIO58
2
PCH_GPIO76 P1 D60 H_THERMTRIP#
10K_0804_8P4R_5% +3VALW PCH_GPIO8 AU2 BMBUSY/GPIO76 THRMTRIP V4
AM7 GPIO8 RCIN/GPIO82 T4 KB_RST# <25>
SERIRQ SERIRQ <8,22,25>
<10> PCH_GPIO12 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ
RP15 R69 1 @ 2 PCH_GPIO15 AD6 AW15 PCH_OPIRCOMP 1 2
1 8 1K_0402_1% PCH_GPIO16 Y1 GPIO15 MISC PCH_OPI_RCOMP AF20 R70
USB_OC1# <10,24> GPIO16 RSVD
2 7 PCH_GPIO30 <8> PCH_GPIO17 T3 AB21 49.9_0402_1%
GPIO17 RSVD
：：
3 6 PCH_GPIO24 AD5
PCH_GPIO72 <8> GPIO24
4 5 PCH_GPIO44 PCH_GPIO27 AN5 PCH_GPIO86 Boot BIOS Loca?on
GPIO27
：
PCH_GPIO28 AD7 ( ) H LPC BUS
10K_0804_8P4R_5% PCH_GPIO26 AN3 GPIO28
GPIO26 (*) L SPI BUS
R6 PCH_GPIO83
1
2
RP16 @
8
7
PCH_GPIO59
PCH_GPIO8
Speaker_JBL PCH_GPIO56
PCH_GPIO57
PCH_GPIO58
AG6
AP1
AL4
GPIO56
GPIO57
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
L6
N6
L8
PCH_GPIO84
PCH_GPIO85
PCH_GPIO86 R71 1 @ 2 1K_0402_1%
+3VS
C
3 6 PCH_GPIO43
Function GPIO71 PCH_GPIO59 AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 PCH_GPIO87 R72 1 2 1K_0402_1%
C
PCH_GPIO43 <10> GPIO59 GPIO GSPI1_CS/GPIO87
4 5 PCH_GPIO57 Normal Speaker 1 PCH_GPIO44 AK4 L5 3DCMOS_ON#
GPIO44 GSPI1_CLK/GPIO88 3DCMOS_ON# <17>
PCH_GPIO47 AB6 N7 PCH_GPIO89
10K_0804_8P4R_5% TPMPD# U4 GPIO47 GSPI1_MISO/GPIO89 K2 PCH_GPIO90
JBL Speaker 0 <8> TPMPD#
DGPU_PRSNT# Y3 GPIO48 GSPI_MOSI/GPIO90 J1
P3 GPIO49 UART0_RXD/GPIO91 K3 UART0_TX <21>
RP9 @ PCH_GPIO50
GPIO50 UART0_TXD/GPIO92 UART0_RX <21>
8 1 PCH_GPIO56 Speaker_JBL Y2 J2
HSIOPC/GPIO71 UART0_RTS/GPIO93 UART0_CTS <21>
7 2 PCH_GPIO14 PCH_GPIO13 AT3 SERIAL IO G1
6 3 AH4 GPIO13 UART0_CTS/GPIO94 K4 UART0_RTS <21>
PCH_GPIO46 PCH_GPIO14 PCH_GPIO0
5 4 PCH_GPIO25 AM4 GPIO14 UART1_RXD/GPIO0 G2 PCH_GPIO1
R90 1 2 0_0402_5% EC_SCI#_2 AG5 GPIO25 UART1_TXD/GPIO1 J3 PCH_GPIO2
10K_0804_8P4R_5% @ PCH_GPIO46 AG3 GPIO45 UART1_RST/GPIO2 J4 PCH_GPIO3
GPIO46 UART1_CTS/GPIO3 F2 PCH_GPIO4
I2C0_SDA/GPIO4
：
AM3 F3 PCH_GPIO5 SDIO_D0 / GPIO66 : Top-Block Swap Override
GPIO9 I2C0_SCL/GPIO5
：
AM2 G4 PCH_GPIO6 (*) H ENABLED
<10> PCH_GPIO10 P2 GPIO10 I2C1_SDA/GPIO6 F1
RP23 PCH_GPIO33 PCH_GPIO7 ( ) L DISABLED(Have internal PD)(Default)
1 8 PCH_GPIO27 C4 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 E3 PCH_GPIO64 +3VS
2 7 PCH_GPIO25 PCH_GPIO38 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 PCH_GPIO65
3 6 PCH_GPIO29 R66 1 @ 2 0_0402_5% EC_SCI#_1 N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 PCH_GPIO66 R75 1 @ 2 1K_0402_1%
PCH_GPIO29 <8> <7,25> EC_SCI# DEVSLP2/GPIO39 SDIO_D0/GPIO66
4 5 V2 E4 PCH_GPIO67
<27> HDA_SPKR SPKR/GPIO81 SDIO_D1/GPIO67 C3 PCH_GPIO68
SDIO_D2/GPIO68 PCH_GPIO68 <8>
10K_0804_8P4R_5% E2 PCH_GPIO69
SDIO_D3/GPIO69
10 OF 19
+3VS
RP17
+3VS
RP18
BIOS Strap Pin
1 8 PCH_GPIO17 1 8 WLBT_OFF#
WLBT_OFF# <8,21>
2 7 PCH_GPIO23 2 7 PCH_GPIO50
B PCH_GPIO23 <7> B
3 6 KB_RST# 3 6 PCH_GPIO33 DGPU_PRSNT#(GPIO49)
4 5 SYS_RESET# 4 5 PCH_GPIO76
Function GPIO13 Function
SYS_RESET# <8>
10K_0804_8P4R_5% 10K_0804_8P4R_5%
No ISCT 1 UMA Only 1
RP19 @ RP20
ISCT 0 SG 0
2 7 PCH_GPIO34 <6> +3VS +3VS
2 7 PCH_GPIO5 PCH_GPIO16
3 6 PCH_GPIO67 3 6 PCH_GPIO37 NOISCT@
4 5 PCH_GPIO37 <6>
4 5 PCH_GPIO64 Speaker_JBL R282 1 2 10K_0402_5% PCH_GPIO13 R73 1 UMA@ 2 10K_0402_5% DGPU_PRSNT#
Speaker_JBL <27>
R283 1 2 10K_0402_5% R74 1 PX@ 2 10K_0402_5%
10K_0804_8P4R_5% 10K_0804_8P4R_5% ISCT@
RP21 @ RP22 @
1 8 UART0_RTS 1 8
2 7 UART0_CTS 2 7 PCH_GPIO19
3 6 3 6 PCH_GPIO19 <7>
UART0_TX 3DCMOS_ON#
4 5 UART0_RX 4 5 PCH_GPIO18
PCH_GPIO18 <7> Function GPIO73 Function GPIO1
10K_0804_8P4R_5% 10K_0804_8P4R_5% 3DCMOS@ 1 14 inch 1
RP24 @ RP2 CMOS@ 0 15 inch 0
PCH_GPIO53 <8> +3VS +3VS
4 5 PCH_GPIO3 5 4 PCH_GPIO51 3DCMOS@ Z14@
PCH_GPIO51 <8>
R286 1 2 10K_0402_5% PCH_GPIO73 PCH_GPIO73 <7> R288 1 2 10K_0402_5% PCH_GPIO1
10K_0804_8P4R_5% 10K_0804_8P4R_5% R287 1 2 10K_0402_5% R289 1 2 10K_0402_5%
CMOS@
RP26 @ RP25 Z15@
1 8 1 8 PCH_GPIO69
4 5 PCH_GPIO89 4 5 PCH_GPIO6 Function GPIO38
10K_0804_8P4R_5% 2.2K_0804_8P4R_5% TPM@ 1
A NOTPM@ 0 A
R76 1 @ 2 1K_0402_5% HDA_SPKR

+3VS
TPM@
R291 1 2 10K_0402_5% PCH_GPIO38
R292 1 2 10K_0402_5%
NOTPM@

2014/09/01 2015/09/01 Title
Issued Date Deciphered Date BDW MCP(6/11) GPIO,LPIO
5 4 3 2 1
5 4 3 2 1
D D
UC1K BDW_ULT_DDR3L(Interleaved)
<30> PCIE_CRX_GTX_N0 F10 AN8

PERN5_L0 USB2N0 USB20_N0 <24>
<30> PCIE_CRX_GTX_P0 E10
PERP5_L0 USB2P0
AM8
USB20_P0 <24>
Left USB2/3__I/O Port (Near End User)
C10 PX@ 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_N5_L0 C23 AR7
<30> PCIE_CTX_GRX_N0 PETN5_L0 USB2N1 USB20_N1 <24>
<30> PCIE_CTX_GRX_P0 C11 PX@ 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_P5_L0 C22
PETP5_L0 USB2P1
AT7
USB20_P1 <24>
Left USB2/3__I/O Port (Near HDMI CONN)(Debug Port)
F8 AR8
<30> PCIE_CRX_GTX_N1 PERN5_L1 USB2N2 USB20_N2 <24> Right USB2__I/O Port (Sub Board)
E8 AP8
<30> PCIE_CRX_GTX_P1 PERP5_L1 USB2P2 USB20_P2 <24>
C12 PX@ 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_N5_L1 B23 AR10
<30> PCIE_CTX_GRX_N1 PETN5_L1 USB2N3 USB20_N3 <24> Right USB2 CardReader
dGPU C13 PX@ 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_P5_L1 A23 AT10
<30> PCIE_CTX_GRX_P1 PETP5_L1 USB2P3 USB20_P3 <24>
H10 AM15
<30> PCIE_CRX_GTX_N2 G10 PERN5_L2 USB2N4 AL15 USB20_N4 <17> Touch Screen
C14 PX@ 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_N5_L2 B21 AM13
<30> PCIE_CTX_GRX_N2 PETN5_L2 USB2N5 USB20_N5 <17>
C15 PX@ 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_P5_L2 C21 AN13
Camera
<30> PCIE_CTX_GRX_P2 PETP5_L2 USB2P5 USB20_P5 <17>
C C
E6 AP11
<30> PCIE_CRX_GTX_N3 PERN5_L3 USB2N6 USB20_N6 <21>
F6 AN11 Bluetooth (NGFF)
C16 PX@ 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_N5_L3 B22 AR13
<30> PCIE_CTX_GRX_N3 PETN5_L3 USB2N7
C17 PX@ 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_P5_L3 A21 AP13
<30> PCIE_CTX_GRX_P3 PETP5_L3 USB2P7
<26> PCIE_PRX_DTX_N3 G11

F11 PERN3 G20
<26> PCIE_PRX_DTX_P3 PERP3 USB3RN1 USB3_RX1_N <24>
H20
LAN C22 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_N3 C29 USB3RP1 USB3_RX1_P <24>
<26> PCIE_PTX_C_DRX_N3
C23 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_P3 B30 PETN3 PCIE USB C33
Left USB2/3__I/O Port
<26> PCIE_PTX_C_DRX_P3 PETP3 USB3TN1 USB3_TX1_N <24>
B34
USB3TP1 USB3_TX1_P <24>
F13
<21> PCIE_PRX_DTX_N4 PERN4
G13 E18
<21> PCIE_PRX_DTX_P4 PERP4 USB3RN2 USB3_RX2_N <24>
WLAN F18 USB3_RX2_P <24>
C18 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_N4 B29 USB3RP2
<21> PCIE_PTX_C_DRX_N4
C19 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_P4 A29 PETN4 B33
Left USB2/3__I/O Port
<21> PCIE_PTX_C_DRX_P4 PETP4 USB3TN2 USB3_TX2_N <24>
A33
G17 USB3TP2 USB3_TX2_P <24>
<17> USB3_RX3_N PERN1/USB3RN3
<17> USB3_RX3_P F17
PERP1/USB3RP3
3D Camera CAD note:
C30 Route single-end 50-ohms and max 450-mils length.
<17> USB3_TX3_N PETN1/USB3TN3
C31 AJ10 USBRBIAS R77 1 2 22.6_0402_1% Avoid routing next to clock pins or under stitching capacitors.
<17> USB3_TX3_P PETP1/USB3TP3 USBRBIAS AJ11
F15 USBRBIAS AN10
Recommended minimum spacing to other signal traces is 15 mils
G15 PERN2/USB3RN4 RSVD AM10
PERP2/USB3RP4 RSVD
B31
A31 PETN2/USB3TN4
PETP2/USB3TP4 AL3 USB_OC0#
OC0/GPIO40 USB_OC0# <24>
AT1 USB_OC1#
+1.05VS_AUSB3PLL OC1/GPIO41 USB_OC1# <9,24>
AH2 PCH_GPIO42
E15 OC2/GPIO42 AV3 PCH_GPIO43
E13 RSVD OC3/GPIO43 PCH_GPIO43 <9>
R78 1 2 3.01K_0402_1% PCIE_RCOMP A27 RSVD
B27 PCIE_RCOMP
PCIE_IREF
B B
11 OF 19
+3VALW
RP27
USB_OC0# 1 8
<9> PCH_GPIO10 2 7
PCH_GPIO42 3 6
4 5
<9> PCH_GPIO12
10K_0804_8P4R_5%
A A

2014/09/01 2015/09/01 Title
Issued Date Deciphered Date BDW MCP(7/11) PCIE,USB
5 4 3 2 1
5 4 3 2 1
+CPU_CORE
UC1L BDW_ULT_DDR3L(Interleaved)
D D
L59 C36
+1.35V J58 RSVD VCC C40
RSVD VCC C44
AH26 VCC C48
AJ31 VDDQ VCC C52
AJ33 VDDQ VCC C56
AJ37 VDDQ VCC E23
AN33 VDDQ VCC E25
AP43 VDDQ VCC E27
+1.05VS AR48 VDDQ VCC E29
AY35 VDDQ VCC E31
AY40 VDDQ VCC E33
VDDQ VCC
1
AY44 E35
+CPU_CORE AY50 VDDQ VCC E37
R79 VDDQ VCC E39
F59 VCC E41
10K_0402_5% VCC VCC
2 N58 E43
VCCST_PWRGD AC58 RSVD VCC E45
<25> VCCST_PWRGD RSVD VCC E47
VCCSENSE E63 VCC E49
AB23 VCC_SENSE VCC E51
T17 A59 RSVD VCC E53
E20 VCCIO_OUT VCC E55
+VCCIOA_OUT VCCIOA_OUT VCC
AD23 E57
AA23 RSVD VCC F24
AE59 RSVD VCC F28
RSVD VCC F32
H_CPU_SVIDALRT# L62 VCC F36
N63 VIDALERT HSW ULT POWER VCC F40
<47> VR_SVID_CLK VIDSCLK VCC
H_CPU_SVIDDATA L63 F44
VCCST_PWRGD B59 VIDSOUT VCC F48
F60 VCCST_PWRGD VCC F52
<47> VR_ON C59 VR_EN VCC F56
<47> VGATE VR_READY VCC G23
D63 VCC G25
CPU_PWR_DEBUG H59 VSS VCC G27
P62 PWR_DEBUG VCC G29
C C
P60 VSS VCC G31
P61 RSVD_TP VCC G33
N59 RSVD_TP VCC G35
N61 RSVD_TP VCC G37
T59 RSVD_TP VCC G39
AD60 RSVD VCC G41
AD59 RSVD VCC G43
+1.05VS AA59 RSVD VCC G45
SVID ALERT Place the PU AE60 RSVD
RSVD
VCC
VCC
G47
AC59 G49
resistors close to CPU
1
AG58 RSVD VCC G51

R81 +1.05VS U59 RSVD VCC G53
75_0402_5% V59 RSVD VCC G55
RSVD VCC G57
R82 AC22 VCC H23
2
43_0402_1% +CPU_CORE AE22 VCCST VCC J23

2 1 H_CPU_SVIDALRT# AE23 VCCST VCC K23
<47> VR_SVID_ALRT# VCCST VCC K57
AB57 VCC L22
AD57 VCC VCC M23
AG57 VCC VCC M57
C24 VCC VCC P57
C28 VCC VCC U57
C32 VCC VCC W57
+1.05VS VCC VCC
SVID DATA Place the PU BDW-ULT-DDR3L-IL_BGA1168
12 OF 19
resistors close to CPU
2
R83
130_0402_1%
1
R84
1 @ 2 H_CPU_SVIDDATA
<47> VR_SVID_DAT
0_0402_5% +1.35V
B B
VDDQ DECOUPLING
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
@
10U_0603_6.3V6M
C24
C25
C26
C27
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1 @
+1.05VS
C33
C28
C29
C30
C31
C32
+CPU_CORE
2 2 2 2 2 2 2 2 2 2
2
R253: CPU_PWR_DEBUG
1
R86 CRB mount

R85 PU resistor should be close to CPU @ 150_0402_1% Check list ,XDP use only
100_0402_1% CRB:
+1.35V : 470UF/2V/7343 *2 (Un-mount)
1
2
CPU_PWR_DEBUG 10UF/6.3V/0603 * 6
VCCSENSE 2.2UF/6.3V/0402 * 4
<47> VCCSENSE
2
R87 @
10K_0402_5%
<13,47> VSSSENSE
1
1
R88 PD resistor should be close to CPU

100_0402_1%
2
A A

2014/09/01 2015/09/01 Title
Issued Date Deciphered Date BDW MCP(8/11) Power
5 4 3 2 1
5 4 3 2 1
+RTCVCC <1mA
+1.05VS +1.05VS_AUSB3PLL
41mA
@
D D
L1
2.2UH_LQM2MPN2R2NG0L_30%
1 2 1 1
47U_0805_6.3V6M
22U_0603_6.3V6M
C37 C38 @
1U_0402_6.3V6K
0.1U_0201_10V6K
1 1 1
1
2 2
C34
@ C35 @ C36
R271 1U_0402_6.3V6K
2 2 2
0_0402_5% @
2
+1.05VS_ASATA3PLL
42mA +3VALW
63/62mA
1838mA
L2
1
1 2 +1.05VS
22U_0603_6.3V6M
47U_0805_6.3V6M
R89
1 1 1 @ 0_0603_5%
C39
C40
@ C41 Close to M9 Close to K9, L10
2
1U_0402_6.3V6K
2 2 2
1 C42 1 C43 1 C44 1
@ C45
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
+1.05VS_APLLOPI
57mA 1U_0402_6.3V6K
L3 2 2 2 2 +3VALW
1 2 UC1M BDW_ULT_DDR3L(Interleaved)
47U_0805_6.3V6M
22U_0603_6.3V6M
1
K9 +RTCVCC
1 1 1 VCCHSIO
@ @ C46 L10 C49
VCCHSIO
C47
C48
1U_0402_6.3V6K M9 0.1U_0201_10V6K
+1.05VS_ASATA3PLL +1.05VS_AUSB3PLL N8 VCCHSIO HSIO RTC AH11 2
2 2 2 P9 VCC1_05 VCCSUS3_3 AG10
VCC1_05 VCCRTC 18mA 658mA
B18 AE7 +VCCRTCEXT
B11 VCCUSB3PLL DCPRTC
VCCSATA3PLL
C
+1.05VS_AXCK_DCB
200mA +1.05VS_APLLOPI
1
+1.05VS
C
@
Y20 SPI Y8
L4 VCCHDA=11mA RSVD VCCSPI
C50 @ 1741/1632mA
2.2UH_LQM2MPN2R2NG0L_30% AA21 OPI 0.1U_0201_10V6K
1 2
VCCDSW3_3= 114mA W21 VCCAPLL 2
+3VALW +3VALW VCCAPLL +1.05VS
22U_0603_6.3V6M
47U_0805_6.3V6M
AG14
VCCASW AG13
1 1 1 Close to AH10 Close to AH14 VCCASW
C53
1
C51
C52
@ @ 1U_0402_6.3V6K 2 @ T18 J13 USB3

1 1 1
R272 C54 DCPSUS3 J11 C56 C57 C58
2 2 2 2 VCC1_05
0_0402_5% @ C55 1U_0402_6.3V6K H11 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
1U_0402_6.3V6K AH14 HDA VCC1_05 H15
@ 1 VCCHDA VCC1_05 AE8 2 2 2
VCC1_05
2
1 AF22
+1.05VS_AXCK_LCPLL
31mA VCC1_05
@ T19 AH13 VRM AG19 +PCH_VCCDSW C59 1 2 1U_0402_6.3V6K
L5 DCPSUS2 CORE DCPSUSBYP AG20
2.2UH_LQM2MPN2R2NG0L_30% DCPSUSBYP AE9 +1.05VS
1 2 +3VALW VCCASW AF9
VCCASW
47U_0805_6.3V6M
22U_0603_6.3V6M
AC9 AG8
+3VS AA9 VCCSUS3_3 GPIO/LPC
VCCASW AD10 T20 @
1 1 1 VCCSUS3_3 DCPSUS1
C62 Close to V8 AH10 AD8 T21 @ 1 C64 1 C65
VCCDSW3_3 DCPSUS1 +1.5VS
C61
1U_0402_6.3V6K
C60
@ V8 3mA @
22U_0603_6.3V6M
1U_0402_6.3V6K 1 VCC3_3
41mA C63 W9
2 2 2 22U_0603_6.3V6M VCC3_3 J15
THERMAL SENSOR VCCTS1_5 K14 2 2
2 VCC3_3 K16
+1.05VS_AXCK_DCB VCC3_3
+1.05VS_AXCK_LCPLL J18
K19 VCCCLK SERIAL IO U8
A20 VCCCLK VCCSDIO T9 +3VS +3VS
+1.05VS VCCACLKPLL VCCSDIO 17mA
J17
R21 VCCCLK
T21 VCCCLK LPT LP POWER
VCCCLK 1 C68 1
1U_0402_6.3V6K
K18 SUS OSCILLATOR AB8 @ T22
+3VALW M20 RSVD DCPSUS4 C69
1 1 RSVD
C66 C67 V21 +1.05VS 0.1U_0201_10V6K
AE20 RSVD AC20 2 2
1U_0402_6.3V6K
1U_0402_6.3V6K
B
AE21 VCCSUS3_3 RSVD AG16 B
2 2 VCCSUS3_3 USB2 VCC1_05 AG17
VCC1_05 1 C71
1U_0402_6.3V6K
1
C70
22U_0603_6.3V6M
13 OF 19 2
2 BDW-ULT-DDR3L-IL_BGA1168
Close to R21 Close to J17
Close to AC9,AA9,
AE20,AE21
A A

2014/09/01 2015/09/01 Title
Issued Date Deciphered Date BDW MCP(9/11) Power
5 4 3 2 1
5 4 3 2 1
D D
UC1N BDW_ULT_DDR3L(Interleaved) UC1O BDW_ULT_DDR3L(Interleaved) UC1P BDW_ULT_DDR3L(Interleaved)

H17
A11 AJ35 AP22 AV59 D33 VSS H57
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS J10
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J22
A32 VSS VSS AJ47 AP31 VSS VSS AW35 D39 VSS VSS K1
A36 VSS VSS AJ50 AP38 VSS VSS AW37 D41 VSS VSS K12
A40 VSS VSS AJ52 AP39 VSS VSS AW4 D42 VSS VSS L13
AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D49 VSS VSS L58
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L61
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L7
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS M22
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS N10
C C
AB7 VSS VSS AL13 AR33 VSS VSS AY16 D54 VSS VSS N3
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS P59
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P63
AD3 VSS VSS AL22 AR49 VSS VSS AY24 D59 VSS VSS R10
AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R22
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R8
AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS T1
AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T58
AF11 VSS VSS AL33 AT37 VSS VSS AY51 F20 VSS VSS U20
AF17 VSS VSS AL45 AT46 VSS VSS AY6 F38 VSS VSS V10
AF18 VSS VSS AL46 AT49 VSS VSS B20 F42 VSS VSS V3
AG1 VSS VSS AL51 AT61 VSS VSS B24 F46 VSS VSS V7
AG11 VSS VSS AL52 AT62 VSS VSS B26 F50 VSS VSS W20
AG21 VSS VSS AL54 AT63 VSS VSS B28 F54 VSS VSS W22
AG23 VSS VSS AL57 AU1 VSS VSS B32 F58 VSS VSS Y10
AG60 VSS VSS AL60 AU16 VSS VSS B36 F61 VSS VSS Y59
AG61 VSS VSS AL61 AU18 VSS VSS B4 G18 VSS VSS Y63
AG62 VSS VSS AM1 AU20 VSS VSS B40 G22 VSS VSS
AG63 VSS VSS AM17 AU22 VSS VSS B44 G3 VSS
AH17 VSS VSS AM23 AU24 VSS VSS B48 G5 VSS V58
AH19 VSS VSS AM31 AU26 VSS VSS B52 G6 VSS VSS AH46
AH20 VSS VSS AM52 AU28 VSS VSS B56 G8 VSS VSS V23
AH22 VSS VSS AN17 AU30 VSS VSS B60 H13 VSS VSS E62 VSSSENSE
VSS VSS VSS VSS VSS VSS_SENSE VSSSENSE <11,47>
AH24 AN23 AU33 C11 AH16
AH28 VSS VSS AN31 AU51 VSS VSS C14 16 OF 19 VSS
AH30 VSS VSS AN32 AU53 VSS VSS C18 BDW-ULT-DDR3L-IL_BGA1168
AH32 VSS VSS AN35 AU55 VSS VSS C20
AH38 VSS VSS AN40 AV14 VSS VSS C38
AH44 VSS VSS AN45 AV24 VSS VSS D12
B
AH51 VSS VSS AN48 AV33 VSS VSS D18 B
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ25 VSS VSS AP10 AV49 VSS VSS D29
VSS VSS VSS 15 OF 19 VSS
14 OF 19
A A

2014/09/01 2015/09/01 Title
Issued Date Deciphered Date BDW MCP(10/11) GND
5 4 3 2 1
1
UC1R BDW_ULT_DDR3L(Interleaved)
N23
UC1Q BDW_ULT_DDR3L(Interleaved) RSVD R23
RSVD T23
AT2 RSVD
RSVD U10
AU44 RSVD
DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3 RSVD
DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 AV44
DC_TEST_AY3_AW3 AY3 A4 @ T24 RSVD
DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 D15
T23 @ AY60 RSVD AL1
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60 @ T25 RSVD AM11
DC_TEST_AY62_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61 RSVD AP7
DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 F22 RSVD
T26 @ B2 A62 @ T27 RSVD AU10
DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 H22 RSVD
DC_TEST_A3_B3 B3 AV1 @ T28 RSVD AU15
DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 J21 RSVD
DC_TEST_A61_B61 B61 AW1 @ T29 RSVD AW14
DC_TEST_B62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2 RSVD AY14
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3 RSVD
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW62 18 OF 19
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63 @ T30 BDW-ULT-DDR3L-IL_BGA1168
17 OF 19 DAISY_CHAIN_NCTF_AW63
UC1S BDW_ULT_DDR3L(Interleaved)
AC60 AV63
AC62 CFG0 RSVD_TP AU63
CFG3
AC63
AA63
CFG1
CFG2
RSVD_TP
CFG Straps for Processor
CFG4 AA60 CFG3 C63
Y62 CFG4 RSVD_TP C62
Y61 CFG5 RSVD_TP B43
Y60 CFG6 RSVD CFG3
V62 CFG7 A51
CFG8 RSVD_TP
1
V61 B51
V60 CFG9 RSVD_TP R92
U60 CFG10 L60 1K_0402_1%
T63 CFG11 RSVD_TP @
T62 CFG12 RESERVED N60
2
T61 CFG13 RSVD
T60 CFG14 W23
A AA62
CFG15 RSVD
RSVD
Y22
AY15 OPI_COMP
A
U63 CFG16 PROC_OPI_RCOMP
AA61 CFG18 AV62
U62 CFG17 RSVD D58
CFG19 RSVD Physical Debug Enable (DFX Privacy)
CFG_RCOMP V63 P22
CFG_RCOMP VSS N21
A5 VSS 1: DISABLED
RSVD P20
CFG3 0: ENABLED; SET DFX ENABLED BIT
E1 RSVD R20 IN DEBUG INTERFACE MSR
D1 RSVD RSVD
J20 RSVD
H18 RSVD
TD_IREF B12 RSVD CFG4
TD_IREF
1
19 OF 19
BDW-ULT-DDR3L-IL_BGA1168 R93
1K_0402_1%
2
2 1 CFG_RCOMP
R94 49.9_0402_1%
2 1 OPI_COMP
R95 49.9_0402_1%
2 1 TD_IREF
R96 8.2K_0402_5%
Display Port Presence Strap
1 : Disabled; No Physical Display Port attached

CFG4 to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

2014/09/01 2015/09/01 Title
Issued Date Deciphered Date BDW MCP(11/11) RSVD
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A B C D E
+SM_VREF_DQ0 <5> DIMM1

<5> DDR_A_D[0..63] +1.35V Reverse Type
<5> DDR_A_DQS#[0..7] D/DQ Signals link to CPU
Near CPU
1
<5> DDR_A_DQS[0..7]
R97
1.8K_0402_1%
R98 +SM_VREF_DQ0_DIMM1
<5> DDR_A_MA[0..15]
0_0402_5% 10mils JDIMM1
2
DDR_A_BS0 1 @ 2 1 2
<5> DDR_A_BS0 VREF_DQ VSS
DDR_A_BS1 3 4 DDR_A_D4
<5> DDR_A_BS1 VSS DQ4
2.2U_0402_6.3V6M
0.1U_0402_25V6
DDR_A_BS2 CMD Signals from CPU C72 DDR_A_D0 5 6 DDR_A_D5
<5> DDR_A_BS2 DQ0 DQ5
DDR_A_RAS# @ 0.022U_0402_16V7K 1 1 DDR_A_D1 7 8
<5> DDR_A_RAS#
1
DQ1 VSS
C74
DDR_A_WE# 9 10 DDR_A_DQS#0
<5> DDR_A_WE#
1 2
VSS DQS0#
C73
DDR_A_CAS# R99 11 12 DDR_A_DQS0
1 <5> DDR_A_CAS# DM0 DQS0 1
1.8K_0402_1% 13 14
R100 @2 2 DDR_A_D2 15 VSS VSS 16 DDR_A_D6
M_CLK_DDR#0 @ DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7
<5> M_CLK_DDR#0 24.9_0402_1%
2
M_CLK_DDR0 19 DQ3 DQ7 20
<5> M_CLK_DDR0 VSS VSS
M_CLK_DDR#1 Clock Signals from CPU DDR_A_D8 21 22 DDR_A_D12
<5> M_CLK_DDR#1
2
M_CLK_DDR1 DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
<5> M_CLK_DDR1 25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS VSS 28
DDR_CKE0_DIMMA DDR_A_DQS1 29 DQS1# DM1 30 DDR3_DRAMRST#
<5> DDR_CKE0_DIMMA DQS1 RESET# DIMM_DRAMRST# <4,16>
DDR_CKE1_DIMMA 31 32
<5> DDR_CKE1_DIMMA VSS VSS
DDR_CS0_DIMMA# CTL Signals from CPU DDR_A_D10 33 34 DDR_A_D14 1
<5> DDR_CS0_DIMMA# 35 DQ10 DQ14 36
DDR_CS1_DIMMA# DDR_A_D11 DDR_A_D15
<5> DDR_CS1_DIMMA# DQ11 DQ15
37 38 C75 ESD@
DDR_A_D16 39 VSS VSS 40 DDR_A_D20
DQ16 DQ20 100P_0402_50V8J
PCH_SMB_DATA DDR_A_D17 41 42 DDR_A_D21 2
<7,16> PCH_SMB_DATA DQ17 DQ21
<7,16> PCH_SMB_CLK
PCH_SMB_CLK SMBUS Signals link to CPU
DDR_A_DQS#2
43
45 VSS VSS
44
46
+EC_VCCA
DDR_A_DQS2 47 DQS2# DM2 48
49 DQS2 VSS 50 DDR_A_D22
DDR_A_D18 51 VSS DQ22 52 DDR_A_D23
ESD
16.5K_0402_1%
DQ18 DQ23
1
DDR_A_D19 53 54
55 DQ19 VSS 56 DDR_A_D28
R1648
DDR_A_D24 57 VSS DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS 62 DDR_A_DQS#3
Layout Note:
2
63 VSS DQS3# 64 DDR_A_DQS3
Place near JDIMM1 65 DM3 DQS3 66
ESD request DVT DDR_A_D26
DDR_A_D27
67
69
VSS
DQ26
DQ27
VSS
DQ30
DQ31
68
70
DDR_A_D30
DDR_A_D31
<25> DDR_TEMP
1
+1.35V 71 72
+1.35V VSS VSS +1.35V RH202
100K_0402_1%_TSM0B104F4251RZ
+1.35V DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
75 CKE0 CKE1 76
2
77 VDD VDD 78 DDR_A_MA15
1 1 1 1 1 NC A15
DDR_A_BS2 79 80 DDR_A_MA14
BA2 A14
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0201_10V6K
C320 C321 C322 C323 C324 81 82
ESD@ ESD@ ESD@ ESD@ ESD@ DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11 ECAGND
2 1 1 1 1 2
@ @ 2 2 2 2 2 DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
A9 A7
C77
C78
C76
C79
87 88
DDR_A_MA8 89 VDD VDD 90 DDR_A_MA6
2 2 2 2 DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD VDD 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
M_CLK_DDR0 101 VDD VDD 102 M_CLK_DDR1
M_CLK_DDR#0 103 CK0 CK1 104 M_CLK_DDR#1
105 CK0# CK1# 106
+1.35V DDR_A_MA10 107 VDD VDD 108 DDR_A_BS1 +1.35V
DDR_A_BS0 109 A10/AP BA1 110 DDR_A_RAS#
111 BA0 RAS# 112
VDD VDD
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_A_WE# 113 114 DDR_CS0_DIMMA#

DDR_A_CAS# 115 WE# S0# 116 SA_ODT0 R101
@ @ 117 CAS# ODT0 118 1.8K_0402_1%
1 VDD VDD
@ DDR_A_MA13 119 120 SA_ODT1 +VREF_CA
1 1 1 1 1 1 1 1 A13 ODT1
C83
C87
C88
C82
C84
C85
C86
C89
+ C250 DDR_CS1_DIMMA# 121 122 R102
2
330U_D3_2.5VY_R6M 123 S1# NC 124 0_0402_5%
VDD VDD 10mils
125 126 1 @ 2
2 2 2 2 2 2 2 2 2 TEST VREF_CA +SM_VREF_CA <5>
2.2U_0402_6.3V6M
0.1U_0402_25V6
127 128
DDR_A_D32 129 VSS VSS 130 DDR_A_D36 @
DQ32 DQ36
1
DDR_A_D33 131 132 DDR_A_D37 1 1 C93
DQ33 DQ37
C91
C92
133 134 0.022U_0402_16V7K
DDR_A_DQS#4 135 VSS VSS 136
1 2
DDR_A_DQS4 137 DQS4# DM4 138
DQS4 VSS
1
139 140 DDR_A_D38 2 2 @
DDR_A_D34 141 VSS DQ38 142 DDR_A_D39 @ R103 R104
DDR_A_D35 143 DQ34 DQ39 144 1.8K_0402_1%
DQ35 VSS 24.9_0402_1%
145 146 DDR_A_D44
Layout Note: Layout Note: DDR_A_D40 147 VSS DQ44 148 DDR_A_D45
Place near JDIMM1.203,204 Place near JDIMM1.199
2
2
DDR_A_D41 149 DQ40 DQ45 150
155 DM5 DQS5 156
3
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47 3
+0.675VS +3VS 161 DQ43 DQ47 162

DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
167 DQ49 DQ53 168
VSS VSS
0.1U_0402_25V6
1U_0402_6.3V6K
0.1U_0402_25V6
1U_0402_6.3V6K
DDR_A_DQS#6 169 170

@ 1 @ 1 DDR_A_DQS6 171 DQS6# DM6 172
1 1 1 1 DQS6 VSS
C95
0.1U_0402_25V6
2.2U_0402_6.3V6M
C94
@ 173 174 DDR_A_D54

Address : 00 VSS DQ54
C96
C97
DDR_A_D50 175 176 DDR_A_D55

DQ50 DQ55
C99
C98
R105 1 @ 2 0_0402_5% DDR_A_SA0 DDR_A_D51 177 178

2 2 2 2 2 2 179 DQ51 VSS 180 DDR_A_D60
R106 1 @ 2 0_0402_5% DDR_A_SA1 DDR_A_D56 181 VSS DQ60 182 DDR_A_D61
DDR_A_D57 183 DQ56 DQ61 184
189 DM7 DQS7 190
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
+0.675VS +3VS 195 DQ59 DQ63 196 +0.675VS
DDR_A_SA0 197 VSS VSS 198
199 SA0 EVENT# 200 PCH_SMB_DATA
DDR_A_SA1 201 VDDSPD SDA 202 PCH_SMB_CLK
203 SA1 SCL 204
VTT VTT
205 206
207 GND1 GND2 208
BOSS1 BOSS2
DDR3L SODIMM ODT GENERATION FOX_AS0A621-J4RB-7H

ME@
SP07000J520
+1.35V
R107
1 66.5_0402_1%
C100 1 2
+5VALW +1.35V SB_ODT0 <16>
0.1U_0201_10V6K
4 R109 4
2 66.5_0402_1%
1
1 2
SB_ODT1 <16>
U4 R108
1 5 220K_0402_5% Q3 R110
NC VCC MESS138-G 1N SOT23-3 66.5_0402_1%
1
Interleaved Memory
2 D 1 2 SA_ODT0
<4> DDR_PG_CTRL
2
A 4 2
From CPU 3 Y G R111
GND 66.5_0402_1%
S
3
74AUP1G07GW_TSSOP5 M_A_B_DIMM_ODT 1 2 SA_ODT1

For ODT & VTT Issued Date 2014/09/01 Deciphered Date 2015/09/01 Title
power control DDR_VTT_PG_CTRL <42>
DDR3L_DIMMA
A B C D E
A B C D E
+SM_VREF_DQ1 <5> DIMM2

<5> DDR_B_D[0..63] +1.35V Standard Type
<5> DDR_B_DQS#[0..7] D/DQ Signals link to CPU
Near User
1
<5> DDR_B_DQS[0..7]
R112
1.8K_0402_1%
R113 +SM_VREF_DQ1_DIMM2
<5> DDR_B_MA[0..15]
0_0402_5% 10mils JDIMM2
2
DDR_B_BS0 1 @ 2 1 2
<5> DDR_B_BS0 VREF_DQ VSS
DDR_B_BS1 3 4 DDR_B_D22
<5> DDR_B_BS1 VSS DQ4
2.2U_0402_6.3V6M
0.1U_0402_25V6
DDR_B_BS2 CMD Signals from CPU C101 DDR_B_D23 5 6 DDR_B_D16
<5> DDR_B_BS2 DQ0 DQ5
DDR_B_RAS# @ 0.022U_0402_16V7K 1 1 DDR_B_D17 7 8
<5> DDR_B_RAS# DQ1 VSS
1
DDR_B_WE# 9 10 DDR_B_DQS#2
<5> DDR_B_WE#
1 2
VSS DQS0#
C103
C102
DDR_B_CAS# R114 11 12 DDR_B_DQS2
1 <5> DDR_B_CAS# DM0 DQS0 1
1.8K_0402_1% 13 14
R115 @2 2 DDR_B_D21 15 VSS VSS 16 DDR_B_D19
M_CLK_DDR#2 @ DDR_B_D18 17 DQ2 DQ6 18 DDR_B_D20
<5> M_CLK_DDR#2 24.9_0402_1%
2
M_CLK_DDR2 19 DQ3 DQ7 20
<5> M_CLK_DDR2 VSS VSS
M_CLK_DDR#3 Clock Signals from CPU DDR_B_D3 21 22 DDR_B_D4
<5> M_CLK_DDR#3
2
M_CLK_DDR3 DDR_B_D2 23 DQ8 DQ12 24 DDR_B_D5
<5> M_CLK_DDR3 25 DQ9 DQ13 26
DDR_B_DQS#0 27 VSS VSS 28
DDR_CKE2_DIMMB DDR_B_DQS0 29 DQS1# DM1 30 DDR3_DRAMRST#
<5> DDR_CKE2_DIMMB DQS1 RESET# DIMM_DRAMRST# <4,15>
DDR_CKE3_DIMMB 31 32
<5> DDR_CKE3_DIMMB VSS VSS
DDR_CS2_DIMMB# CTL Signals from CPU DDR_B_D0 33 34 DDR_B_D6 1
<5> DDR_CS2_DIMMB# 35 DQ10 DQ14 36
DDR_CS3_DIMMB# DDR_B_D1 DDR_B_D7
<5> DDR_CS3_DIMMB# DQ11 DQ15
37 38 C104 ESD@
DDR_B_D12 39 VSS VSS 40 DDR_B_D13
DQ16 DQ20 100P_0402_50V8J
PCH_SMB_DATA DDR_B_D8 41 42 DDR_B_D9 2
<7,15> PCH_SMB_DATA DQ17 DQ21
PCH_SMB_CLK SMBUS Signals link to CPU 43 44
<7,15> PCH_SMB_CLK 45 VSS VSS 46
DDR_B_DQS#1
DDR_B_DQS1 47 DQS2# DM2 48
49 DQS2 VSS 50 DDR_B_D11
DDR_B_D14
DDR_B_D15
51
53
55
VSS
DQ18
DQ19
DQ22
DQ23
VSS
52
54
56
DDR_B_D10
DDR_B_D30
ESD
DDR_B_D31 57 VSS DQ28 58 DDR_B_D26
Layout Note: DDR_B_D25 59 DQ24 DQ29 60
Place near JDIMM2 61 DQ25 VSS 62 DDR_B_DQS#3
63 VSS DQS3# 64 DDR_B_DQS3
65 DM3 DQS3 66
DDR_B_D24 69 DQ26 DQ30 70 DDR_B_D28
71 DQ27 DQ31 72
+1.35V +1.35V VSS VSS +1.35V
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
CKE0 CKE1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
75 76
@ 1 @ 1 77 VDD VDD 78 DDR_B_MA15
1 1 NC A15
DDR_B_BS2 79 80 DDR_B_MA14
BA2 A14
C108
C105
C106
C107
81 82
DDR_B_MA12 83 VDD VDD 84 DDR_B_MA11
2 2
2 2 2 2 DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
+1.35V M_CLK_DDR2 101 VDD VDD 102 M_CLK_DDR3
M_CLK_DDR#2 103 CK0 CK1 104 M_CLK_DDR#3
105 CK0# CK1# 106
VDD VDD
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_B_MA10 107 108 DDR_B_BS1

DDR_B_BS0 109 A10/AP BA1 110 DDR_B_RAS#
111 BA0 RAS# 112
@ 1 @ 1 DDR_B_WE# 113 VDD VDD 114 DDR_CS2_DIMMB#
1 1 1 1 1 1 WE# S0#
C112
C113
C111
C114
C115
C116
C117
C118
DDR_B_CAS# 115 116 SB_ODT0

CAS# ODT0 SB_ODT0 <15>
117 118
DDR_B_MA13 119 VDD VDD 120 SB_ODT1
2 2 2 2 2 2 2 2 121 A13 ODT1 122 SB_ODT1 <15> +VREF_CA
DDR_CS3_DIMMB#
123 S1# NC 124
VDD VDD 10mils
125 126
127 TEST VREF_CA 128
VSS VSS
2.2U_0402_6.3V6M
0.1U_0402_25V6
DDR_B_D32 129 130 DDR_B_D33
DDR_B_D35 131 DQ32 DQ36 132 DDR_B_D34
133 DQ33 DQ37 134
VSS VSS 1 1
C121
DDR_B_DQS#4 135 136
DQS4# DM4
C120
DDR_B_DQS4 137 138
DDR_B_D36 141 VSS DQ38 142 DDR_B_D37 @2 2
Layout Note: Layout Note: DDR_B_D38 143 DQ34 DQ39 144
Place near JDIMM2.203,204 Place near JDIMM2.199 145 DQ35 VSS 146 DDR_B_D44
DDR_B_D45 149 DQ40 DQ45 150
151 DQ41 VSS 152 DDR_B_DQS#5
155 DM5 DQS5 156
+0.675VS +3VS DDR_B_D43 157 VSS VSS 158 DDR_B_D47
3
DDR_B_D42 159 DQ42 DQ46 160 DDR_B_D46 3
161 DQ43 DQ47 162
DQ48 DQ52
0.1U_0402_25V6
1U_0402_6.3V6K
0.1U_0402_25V6
1U_0402_6.3V6K
0.1U_0402_25V6
2.2U_0402_6.3V6M
DDR_B_D49 165 166 DDR_B_D55

@ 1 @ 1 167 DQ49 DQ53 168
1 1 1 1 Address : 01 VSS VSS
C122
C126
C123
@ DDR_B_DQS#6 169 170

DQS6# DM6
C125
+3VS
C124
C127
DDR_B_DQS6 171 172

2 2 2 2 2 2 R116 1 @ 2 0_0402_5% DDR_B_SA1 DDR_B_D50 175 VSS DQ54 176 DDR_B_D54
DDR_B_D53 177 DQ50 DQ55 178
R117 1 @ 2 0_0402_5% DDR_B_SA0 179 DQ51 VSS 180 DDR_B_D56
DDR_B_D62 183 DQ56 DQ61 184
185 DQ57 VSS 186 DDR_B_DQS#7
189 DM7 DQS7 190
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D61
+0.675VS +3VS 195 DQ59 DQ63 196 +0.675VS
DDR_B_SA0 197 VSS VSS 198
199 SA0 EVENT# 200 PCH_SMB_DATA
DDR_B_SA1 201 VDDSPD SDA 202 PCH_SMB_CLK
203 SA1 SCL 204
VTT VTT
205 206
207 GND1 GND2 208
BOSS1 BOSS2
FOX_AS0A621-J4SB-7H
ME@
SP07000P110
4 4
Interleaved Memory
DDR3L_DIMMB
A B C D E
5 4 3 2 1
3D/Normal Camera Power Switch

+3VS +5VS +CMOSVDD
W=60mils
+3VS
LCD Power Circuit +LCDVDD_CONN
+CMOSVDD
1
3DCMOS@
W=60mils U5 CMOS@ R273
1
5 1 +LCDVDD_CONN R276 0_0603_5% 0_0603_5%
4.7U_0603_6.3V6K
IN OUT R252
2 @
C128
1
2
GND +5VALW R275 2 @ 1 0_0603_5% 470_0402_5%
4 3
<8> PCH_ENVDD
1 2
EN OC Q4
G524B1T11U SOT-23-5 2 ME2301DC-G_SOT23-3
1
D D
D
S
3 1 3DCMOS_GATE 2 Q28 @
D
10K_0402_5%
1
R120 G 2N7002K_SOT23-3
100K_0402_5% W=50mils W=50mils S
R316 3DCMOS@
G
2
3
1
1
2
C129 C130 @
R336 3DCMOS@ 0.1U_0201_10V6K 10U_0603_6.3V6M
1 2 3DCMOS_GATE 2
2
2
100K_0402_5%
1
OUT
1
2 C435 C435
<9> 3DCMOS_ON# IN 3DCMOS@ CMOS@
GND
0.01U_0402_16V7K 0.1U_0402_25V6
2 S CER CAP 0.1U 25V K X5R 0402
Q30 3DCMOS@ SE00000G880 +3VS
3
DRC2124E0L NPN MINI3-G3-B @
5
U15
R126 1 @ 2 0_0402_5% EDP_HPD_R From PCH 2
P
<8> EDP_HPD <8,25> ENBKL B 4 DISPOFF#
1
CMOS@ 1 Y
From EC <25> BKOFF# A
G
R40 1 2 150K_0402_5%
<25> CMOS_ON#
2
R128
3
2
100K_0402_5% R124
R211 U74AHC1G08G-AL5-R_SOT353-5 100K_0402_5%
2
100K_0402_5%
1
1
R123 1 @ 2 0_0402_5%
C C
eDP CONN.
EMI B+ +LEDVDD
R125 2 @ 1 0_0402_5%
R121 +LCDVDD_CONN
0_0603_5%
L6 @EMI@ 2 @ 1
4 3 USB20_N5_R 1
<10> USB20_N5 4 3 @
Camera C133
1 2 USB20_P5_R 4.7U_0805_25V6-K
<10> USB20_P5 1 2 2
DLW21HN900HQ2L_4P
JeDP1 W=60mils
R127 2 @ 1 0_0402_5% 1 2
3 1 2 4
5 3 4 6
7 5 6 8 EDP_AUXN_C 0.1U_0201_10V6K 2 1 C134
eDP <8> INVPWM
DISPOFF# 9 7 8 10 EDP_AUXP_C 0.1U_0201_10V6K 2 1 C135 EDP_AUXN <4>
9 10 EDP_AUXP <4>
EDP_HPD_R 11 12 eDP
13 11 12 14 EDP_TXP0_C 0.1U_0201_10V6K 2 1 C136
13 14 EDP_TXP0 <4>
15 16 EDP_TXN0_C 0.1U_0201_10V6K 2 1 C137
<25> TS_DISABLE# 15 16 EDP_TXN0 <4>
R43 1 @ 2 0_0402_5% R270 2 @ 1 0_0603_5% +3VS_TS 17 18
Intel_PCH_USB3.0 Touch Screen +3VS
USB20_P4_R 19 17 18 20 EDP_TXP1_C 0.1U_0201_10V6K 2 1 C138
<10> USB3_RX3_N
EMI 1
L23
1
@EMI@
2
2 U3RXDN3
USB20_N4_R
USB20_P5_R
21
23
25
19
21
23
20
22
24
22
24
26
EDP_TXN1_C 0.1U_0201_10V6K 2 1 C139
EDP_TXP1 <4>
EDP_TXN1 <4>
25 26 DMIC_CLK <27>
USB20_N5_R 27 28
4 3 U3RXDP3
Camera 29 27 28 30 DMIC_DAT <27> DMIC
<10> USB3_RX3_P 4 3 +CMOSVDD 29 30 +3VS
DLW21HN900HQ2L_4P 31 32
GND GND
0.1U_0201_10V6K
R44 1 @ 2 0_0402_5%
B B
2 ACES_87242-3001-09
SP02000NB00
@ ME@
3D Camera 3DCMOS@ R45 1 @ 2 0_0402_5% C242
C194 1
0.1U_0201_10V6K L22 @EMI@
1 2 U3TXDN3_L 1 2 U3TXDN3
<10> USB3_TX3_N 1 2
1 2 U3TXDP3_L 4 3 U3TXDP3 Close JeDP1

<10> USB3_TX3_P 4 3
3DCMOS@ DLW21HN900HQ2L_4P
C204 R48 1 @ 2 0_0402_5%
0.1U_0201_10V6K
+3VALW +3VS 3D Camera CONN.

EMI
1
+CMOSVDD
R132 2 @ 1 0_0402_5% R135 @
10K_0402_5% JCMOS1
Q8 @
2
L7 @EMI@ 2N7002H_SOT23-3 1
G
4 3 USB20_N4_R 2 2 1
<10> USB20_N4 4 3 1 3 3 2
FW_UPDATE_R
<7> FW_UPDATE 3
4
Touch Screen
D
S
1 2 USB20_P4_R U3RXDP3 5 4
<10> USB20_P4 1 2 6 5
U3RXDN3
DLW21HN900HQ2L_4P 7 6
U3TXDP3 8 7
R134 2 @ 1 0_0402_5% R64 1 @ 2 U3TXDN3 9 8
10 9
0_0402_5% 11 10
12 GND
A A
GND
ACES_50463-0104A-001
1 2 SP01001G000
<25> EC_FW_UPDATE
R65 @ 0_0402_5% ME@

LVDS/CAMERA
C 1.0
5 4 3 2 1
5 4 3 2 1
EMI Only change P/N and value

Near JHDMI1
+5V_Display
U6
+5VS 3
W=40mils
D Near JHDMI1 OUT D
1
HCM1012GH900BP_4P 1
IN
1
<4> HDMI_CLK+_CK C229 1 2 0.1U_0201_10V6K HDMI_CLK+_CK_C 4 3 HDMI_CLK+_CONN 1 C140
R1658 @EMI@ @ 2 0.1U_0201_10V6K
HDMI@ 150_0402_5% C141 GND 2
<4> HDMI_CLK-_CK C230 1 2 0.1U_0201_10V6K HDMI_CLK-_CK_C 1 2 HDMI_CLK-_CONN 0.1U_0201_10V6K
2 G5250Q1T73U SOT-23
2
HDMI@ L8 EMI@
For CRT and HDMI

HCM1012GH900BP_4P
1
<4> HDMI_TX0+_CK C231 1 2 0.1U_0201_10V6K HDMI_TX0+_CK_C 4 3 HDMI_TX0+_CONN
R1659 @EMI@
HDMI@ 150_0402_5%
<4> HDMI_TX0-_CK C232 1 2 0.1U_0201_10V6K HDMI_TX0-_CK_C 1 2 HDMI_TX0-_CONN
2
HDMI@ L9 EMI@
+3VS
2
HCM1012GH900BP_4P R133
1
<4> HDMI_TX1+_CK C233 1 2 0.1U_0201_10V6K HDMI_TX1+_CK_C 4 3 HDMI_TX1+_CONN 1M_0402_5%
2
R1660 @EMI@ HDMI@ Q5 HDMI@
G
HDMI@ 150_0402_5% 2N7002K_SOT23-3
1
<4> HDMI_TX1-_CK C234 1 2 0.1U_0201_10V6K HDMI_TX1-_CK_C 1 2 HDMI_TX1-_CONN JHDMI1 ZZZ 45@
3 1 HDMI_DET 19
<8> TMDS_B_HPD
2
HDMI@ L10 EMI@ 18 HP_DET
D
+5V_Display +5V
2
17
R137 HDMIDAT_R 16 DDC/CEC_GND
HDMICLK_R 15 SDA
20K_0402_5% SCL
HDMI@ 14 HDMI Logo
13 Reserved
1
HCM1012GH900BP_4P HDMI_CLK-_CONN 12 CEC 20 RO0000003HM
C C
1
C235 1 2 0.1U_0201_10V6K HDMI_TX2+_CK_C 4 3 HDMI_TX2+_CONN 11 CK- GND 21
<4> HDMI_TX2+_CK CK_shield GND
R1661 @EMI@ HDMI_CLK+_CONN 10 22
HDMI@ 150_0402_5% HDMI_TX0-_CONN 9 CK+ GND 23
C236 1 2 0.1U_0201_10V6K HDMI_TX2-_CK_C 1 2 HDMI_TX2-_CONN 8 D0- GND
<4> HDMI_TX2-_CK D0_shield
HDMI_TX0+_CONN 7
2
HDMI@ L11 EMI@ HDMI_TX1-_CONN 6 D0+
5 D1-
HDMI_TX1+_CONN 4 D1_shield
HDMI_TX2-_CONN 3 D1+
2 D2-
HDMI_TX2+_CONN 1 D2_shield
D2+
LCN_AUF05-1922S10-0013
+3VS ME@
+3VS DC232002J00
R143 1 HDMI@ 2 2.2K_0402_5% HDMIDAT_NB

Q6A
R144 1 HDMI@ 2 2.2K_0402_5% HDMICLK_NB HDMI@
2
2N7002EDW_SOT363-6
<8> HDMICLK_NB 1 6 HDMICLK_R

RP29
5
HDMI_TX1+_CK_C 5 4
HDMI_TX1-_CK_C 6 3
4 3 HDMIDAT_R HDMI_CLK+_CK_C 7 2
<8> HDMIDAT_NB
HDMI_CLK-_CK_C 8 1
Q6B
HDMI@ 470 +-5% 8P4R
2N7002EDW_SOT363-6 HDMI@
RP30
HDMI_TX0+_CK_C 5 4
HDMI_TX0-_CK_C 6 3
+5V_Display HDMI_TX2+_CK_C 7 2
HDMI_TX2-_CK_C 8 1
R145 1 HDMI@ 2 2.2K_0402_5% HDMIDAT_R
B B
470 +-5% 8P4R
R146 1 HDMI@ 2 2.2K_0402_5% HDMICLK_R HDMI@
+3VS
1
D
2
G
ESD S Q7 HDMI@
2N7002K_SOT23-3
3
@ESD@ D1 @ESD@ D2 @ESD@ D3
HDMIDAT_R 9 10 1 1 HDMIDAT_R HDMI_CLK-_CONN 9 10 1 1 HDMI_CLK-_CONN HDMI_TX0+_CONN 9 10 1 1 HDMI_TX0+_CONN
HDMICLK_R 8 9 2 2 HDMICLK_R HDMI_CLK+_CONN 8 9 2 2 HDMI_CLK+_CONN HDMI_TX0-_CONN 8 9 2 2 HDMI_TX0-_CONN
HDMI_DET 7 7 4 4 HDMI_DET HDMI_TX1-_CONN 7 7 4 4 HDMI_TX1-_CONN HDMI_TX2+_CONN 7 7 4 4 HDMI_TX2+_CONN
6 6 5 5 HDMI_TX1+_CONN 6 6 5 5 HDMI_TX1+_CONN HDMI_TX2-_CONN 6 6 5 5 HDMI_TX2-_CONN
3 3 3 3 3 3
8 8 8
L05ESDL5V0NA-4_SLP2510P8-10-9 L05ESDL5V0NA-4_SLP2510P8-10-9
L05ESDL5V0NA-4_SLP2510P8-10-9
A A

HDMI CONN
C 1.0
5 4 3 2 1
5 4 3 2 1
+3VS +3VS_CRT
JP2
1 2
1 2
JUMP_43X39
@
D D
+3VS_CRT
0.1U_0201_10V6K
0.1U_0201_10V6K
2 2
0.1U_0201_10V6K
CT33
CT34
2 2
+5V_Display +5V_Display
CT35
CT36
1 1 10U_0603_6.3V6M
1 1
1
RT31 RT32
2.2K_0402_5% 2.2K_0402_5%
20
UT1
2
DVCC_33
DVCC_33
VDD_DAC_33
<8> DDI1_HPD VGA_HPD_R 1
HPD
1
<8> DDI1_AUX_DN CT37 2 1 0.1U_0201_10V6K DDI1_AUX_C_DN 27 6 CRT_DATA

CT38 2 1 0.1U_0201_10V6K DDI1_AUX_C_DP 26 AUX_N VGA_SDA 4 CRT_CLK
<8> DDI1_AUX_DP AUX_P VGA_SCL
RT24 8 HSYNC
100K_0402_5% CT39 2 1 0.1U_0201_10V6K CPU_DP1_C_P0 29 HSYNC 7 VSYNC
<4> CPU_DP1_P0 LANE0P VSYNC
CT40 2 1 0.1U_0201_10V6K CPU_DP1_C_N0 30
<4> CPU_DP1_N0
2
LANE0N 15 CRT_R +5VS

CT41 2 1 0.1U_0201_10V6K CPU_DP1_C_P1 31 RED_P
<4> CPU_DP1_P1 LANE1P
CT42 2 1 0.1U_0201_10V6K CPU_DP1_C_N1 32 12 CRT_G
<4> CPU_DP1_N1 LANE1N GREEN_P
1
+3VS_CRT 10 CRT_B @
BLUE_P CT19
8
7
6
5
C 22 POL1_SDA 0.1U_0201_10V6K C
CT43 2 1 2.2U_0402_6.3V6M POL1_SDA 23 POL2_SCL RPT1 2
POL2_SCL
1
75_0804_8P4R_1%
CT44 2 1 0.1U_0201_10V6K VCCK_12 19 2 EC_SMB_CK2
OE#
P
VCCK_12 SMB_SCL 3 EC_SMB_CK2 <7,22,25,31> 2 4 1 2 36_0402_1%
EC_SMB_DA2 VSYNC CRT_VSYNC_1 RT8 @ CRT_VSYNC_2
EC_SMB_DA2 <7,22,25,31>
1
2
3
4
CT45 2 1 0.1U_0201_10V6K 24 SMB_SDA A Y
AVCC_33
G
UT2 @ 1
CT46 2 1 0.1U_0201_10V6K VCCK_12 25 SN74AHCT1G125DCKR_SC70-5
3
AVCC_12 21 LDO_EN @ CT20
RT15 1 2 12K_0402_1% 28 LDO_EN 10P_0402_50V8J
RRX 2
18 RT9 1 2 36_0402_1%
11 XO
13 BLUE_N 17
14 GREEN_N XI/CKIN
16 GND_DAC
33 RED_N
EPAD_GND +5VS
RTD2168-CG_QFN32_5X5
SA000077U00 1
2 @
CT25
CT47 0.1U_0201_10V6K
10U_0603_6.3V6M 2
1
1
OE#
P
HSYNC 2 4 CRT_HSYNC_1 RT10 1 @ 2 36_0402_1% CRT_HSYNC_2
+3VS_CRT +3VS_CRT +3VS_CRT A Y
G
UT3 @
SN74AHCT1G125DCKR_SC70-5 1
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
3
1
1
RT18
@
RT16
@RT17
CT26
10P_0402_50V8J
RT11 1 2 36_0402_1% 2
2
POL2_SCL POL1_SDA LDO_EN
B B
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
1
1
@RT21
@RT19
RT20
2
2
+5V_Display
CRT
ESD EMI LT1 EMI@ 6
JCRT1
BLM15BA220SN1D 0402 11
CRT_R 1 2 CRT_R_2 1
+5V_Display LT2 EMI@ 7
BLM15BA220SN1D 0402 CRT_DATA 12
CRT_G 1 2 CRT_G_2 2
DT1 @ LT3 EMI@ 8 G 16
CRT_CLK 6 3 CRT_HSYNC_2 BLM15BA220SN1D 0402 CRT_HSYNC_2 13 17
I/O4 I/O2 1 2 3 G
CRT_B CRT_B_2
9
CRT_VSYNC_2 14
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
5 2 1 1 1 1 1 1 4
VDD GND EMI@ EMI@ EMI@ EMI@ EMI@ EMI@ 10
CT27 CT28 CT29 CT30 CT31 CT32 CRT_CLK 15
5
CRT_VSYNC_2 4 1 CRT_DATA 2 2 2 2 2 2
I/O3 I/O1 J-L_TNBNRACZZ013015
A AZC099-04S.R7G_SOT23-6 ME@ A
DC060008D00
+5V_Display DT2 @
CRT_R_2 6 3 CRT_B_2
I/O4 I/O2
5 2
VDD GND
CRT_G_2 4 1 Security Classification Compal Secret Data Compal Electronics, Inc.

I/O3 I/O1
AZC099-04S.R7G_SOT23-6
CRT
C 1.0
5 4 3 2 1
A B C D E F G H
HDD
SATA HDD Conn.
Near Connector
JHDD1
1 23
0.01U_0402_16V7K 2 1 C142 SATA_PTX_C_DRX_P0 2 GND GND 24
<6> SATA_PTX_DRX_P0 A+ GND
<6> SATA_PTX_DRX_N0 0.01U_0402_16V7K 2 1 C143 SATA_PTX_C_DRX_N0 3
4 A-
C144 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 5 GND
<6> SATA_PRX_DTX_N0 C145 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 6 B-
<6> SATA_PRX_DTX_P0 7 B+
GND
1 1
8
R141 1 @ 2 0_0805_5% +3V_HDD 9 VCC3.3
+3VS 10 VCC3.3
C149 1 2 0.1U_0402_25V6 11 VCC3.3
@ 12 GND
ESD R142 1 @ 2 0_0805_5% +5V_HDD

13
14
15
GND
GND
VCC5
+5VS VCC5
16
17 VCC5
18 GND
Near HDD 19 RESERVED
20 GND
+5V_HDD
ESD 21
22
VCC12
VCC12
VCC12
1 1 1 SANTA_193202-1
@ DC010008700
C146 C147 @ C148 ME@
1000P_0402_50V7K 0.1U_0402_25V6 10U_0603_6.3V6M
2 2 2
KB Backlight ODD
2 2
+5VS
FOR Z14"
KB Backlight Conn. FOR Z15"/17"
Q18 KBL@
ME2301DC-G_SOT23-3 30mil
JKBL1
+5VS +5V_ODD SATA ODD Conn.
S
+5VALW +5VS 3 1 +5VS_KBL 1 R147 1 @ 2 0_0805_5%

D
2 1
3 2 5 JODD1
KBL@ 4 3 G1 6 +5VS_KBL 1
G
4 G2 2 1
10K_0402_5%
10K_0402_5%
1 2
1
ACES_51512-0040N-P01 3
ME@ C150 4 3
R337
R315
<6> SATA_PTX_DRX_P1 4
1 SP01001J100 10U_0603_6.3V6M <6> SATA_PTX_DRX_N1 5
2 6 5
2
C449
@ V0.2 KBL@ 7 6
2
1U_0402_6.3V6K <6> SATA_PRX_DTX_N1 8 7

V0.3A R335 KBL@ 2 <6> SATA_PRX_DTX_P1 9 8
1 2 10 9
+5V_ODD 11 10
100K_0402_5% 12 11
13 12 15
1
1
C434 14 13 GND 16
V0.3 14 GND
OUT
0.01U_0402_16V7K
@ JXT_FP202DH-014M10M
2 ME@
2 SP010021G00
<25> KB_BL_PWM IN
GND
Q26 KBL@ V0.3A

3
DRC2124E0L NPN MINI3-G3-B

3 3
FOR Z14"
SATA ODD Conn.
Near Connector JODD2
1
SATA_PTX_DRX_P1 Z14@ C151 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P1_14 2 GND
SATA_PTX_DRX_N1 Z14@ C152 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N1_14 3 A+
4 A-
SATA_PRX_DTX_N1 Z14@ C153 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N1_14 5 GND
SATA_PRX_DTX_P1 Z14@ C154 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P1_14 6 B-
7 B+
GND
8
+5V_ODD 9 DP
10 +5V 14
11 +5V GND 15
12 MD GND
13 GND
GND
SANTA_201304-1
ME@
DC01000AV00
4 4

HDD/ODD/KB_BL Connector
C 1.0
A B C D E F G H
A B C D E
1 1
+3VS +3VS_WLAN
R153 1 @ 2 0_0805_5%
NGFF for WLAN / BT(Key E) +3VALW

Support ISCT(Intel Smart Connect Technology) Q10 ISCT@
ME2301DC-G_SOT23-3
S
3 1
D
1 1
C155
+3VS_WLAN C156 @
G
4.7U_0603_6.3V6K 0.1U_0201_10V6K
JWLAN1 2 2
1 2
3 GND 3.3VAUX 4
<10> USB20_P6 USB_D+ 3.3VAUX
5 6
2
BT <10> USB20_N6 7 USB_D- LED1# 8
GND PCM_CLK <25> WLAN_PWR_ON#
9 10 1
11 SIDO_CLK PCM_SYNC 12 ISCT@
13 SDIO_CMD PCM_IN 14 R154 C157 ISCT@
15 SDO_DAT0 PCM_OUT 16 150K_0402_5%
2 0.1U_0201_10V6K 2
17 SDO_DAT1 LED2# 18 2
19 SDO_DAT2 GND 20
21 SDO_DAT3 UART_WAKE# 22 UART0_RX_R RP6 @
23 SDIO_WAKE# UART_RX 1 8
SDIO_RESET# UART0_RX <9>
2 7
3 6 UART0_TX <9>
UART0_CTS <9>
4 5
UART0_RTS <9>
24 UART0_TX_R
25 UART_TX 26 UART0_CTS_R 0_0804_8P4R_5%
27 GND UART_CTS 28 UART0_RTS_R
<10> PCIE_PTX_C_DRX_P4 29 PETP0 UART_RTS 30 R155 1 @ 2 0_0402_5%
<10> PCIE_PTX_C_DRX_N4 PETN0 RESERVED EC_TX <25>
31 32 R156 1 @ 2 0_0402_5%
GND RESERVED EC_RX <25>
33 34
<10> PCIE_PRX_DTX_P4 35 PERP0 RESERVED 36
WLAN <10> PCIE_PRX_DTX_N4
37 PERN0 COEX3 38
39 GND COEX2 40
<7> CLK_PCIE_WLAN REFCLKP0 COEX1
41 42 SUSCLK_R R157 1 @ 2 0_0402_5%
<7> CLK_PCIE_WLAN# REFCLKN0 SUSCLK SUSCLK <8>
43 44 WL_RST#
R158 1 @ 2 0_0402_5% WLANCLK_REQ#_R 45 GND PERST0# 46 BT_DISABLE_R R159 1 @ 2 0_0402_5%
<7> WLANCLK_REQ# CLKEQ0# W_DISABLE2# WLBT_OFF# <8,9>
<8,25,26> PCIE_WAKE# 47 48 R161 1 @ 2 0_0402_5%
49 PEWAKE0# W_DISABLE1# 50 EC_WL_OFF# <25>
51 GND I2C_DATA 52
53 RSRVD/PETP1 I2C_CLK 54
55 RSRVD/PETN1 ALERT 56
Note: The real behavior of BT_DISABLE are
57 GND RESERVED 58 BT_DISABLE=LOW, BT=OFF
59 RSRVD/PERP1 RESERVED 60 BT_DISABLE=HIGH, BT=ON
61 RSRVD/PERN1 RESERVED 62
63 GND RESERVED 64
65 RESERVED 3.3VAUX 66
67 RESERVED 3.3VAUX
GND
+3VS_WLAN
69 68 +3VS
MTG77 MTG76
1
ISCT@
LCN_DAN05-67306-0102 R163
ME@ 100K_0402_5%
2
3 3
SP070013F00 Q11 ISCT@
2N7002K_SOT23-3
G
2
2
R507 WL_RST# 1 3 PCIRST# PCIRST# <8,22,25,26,30>
100K_0402_5%
S
1
R164 1 @ 2 0_0402_5%
4 4
Security Classification
2014/09/01
Compal Secret Data
2015/09/01 Title
Issued Date Deciphered Date
Mini-Card/NEW Card/SIM
1.0
A B C D E
5 4 3 2 1
2 Channel
D D
+3VGS +3VS
2
@ TROPO@
R193 R195
0_0402_5% 0_0402_5%
1
TROPO@ +3V_Thermal
<31> REMOTE1+ U17
2
1 REMOTE1+ 2 1 TROPO@
C251 TROPO@ D+ VCC C175
2200P_0402_50V7K REMOTE1- 3 6 THM_ALERT# THM_ALERT# <31> 0.1U_0201_10V6K
D- ALERT# 1
2 EC_SMB_CK2 8 4 THERM# 2 1
<31> REMOTE1- <7,19,25,31> EC_SMB_CK2 SCL THERM# 10K_0402_5% R30
EC_SMB_DA2 7 5 TROPO@
<7,19,25,31> EC_SMB_DA2 SDA GND
F75397M_MSOP8
Address is 1001100xb
C C
+3VS
+5VS
FAN Conn
1
R191 ADB@
10K_0402_5%
R168
JFAN1 CPU VGA NPTH NGFF Battery BD
2
2 @ 1 +FAN 1
2 1
<25> FAN_SPEED1 3 2
0_0603_5% <25> EC_FAN_PWM1 H15
4 3 H1 H2 H3 H4 H5 H8 H18 H22 HOLEA H23 H24
B 2 4 B
5 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
<25> EC_FAN_REVERSE 5
C162 6
7 GND
10U_0603_6.3V6M
1
1 GND
1
1
1
1
1
ACES_50278-00501-001
ME@ H_2P6X3P6N H_2P6N H_2P6X3P6N H_1P5N H_1P5N
SP021308280 H_3P2
H_4P0 H_4P0 H_4P0 H_3P3 H_3P3
H6 H7 H9 H10 H11 H12 H17 H19 H20 H21

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
TPM
1
1
1
+3VS
H_6P0 H_2P8 H_6P0 H_2P8 H_3P3 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8
1 1 1
C297 C298 C299
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
TPM@ TPM@ TPM@
U24 TPM@ 2 2 2 H13 H14 H16 H30 H31

HOLEA HOLEA HOLEA HOLEA HOLEA
1 24 FD1 FD2 FD3 FD4
2 NC 3V 10
3 NC 3V 19
1
1
1
7 NC 3V
1
1
PP 22 LPC_FRAME#
6 LFRAME# 28 LPC_FRAME# <7,25>
LANGAN1 LANGAN1 LANGAN
9 NC LPCPD# H_2P8 H_3P3 H_3P3 H_2P8 H_2P6N
NC 21 R290 1 TPM@ 2 33_0402_5% CK_LPC_TPM
4 LCLK 27 CK_LPC_TPM <7>
GND SIRQ SERIRQ <8,9,25>
A 11 A
18 GND 26 LPC_AD0
25 GND
GND
LAD0
LAD1
23
20
LPC_AD1
LPC_AD2
LPC_AD0
LPC_AD1
<7,25>
<7,25> For LAN Add at DVT
5 LAD2 17 LPC_AD2 <7,25>
LPC_AD3
NC LAD3 LPC_AD3 <7,25>
8
12 NC 15
13 NC CLKRUN# 16 PCIRST#
NC LRESET# PCIRST# <8,21,25,26,30>
14
NC
Z32H320TC-LPC-T28-233_TSSOP28
SA00007YP00
Fintek-Thermal IC/FAN/screw
C 1.0
5 4 3 2 1
KB For Z15 KB For Z17 KB For Z14
JKB2 JKB3
KSI[0..7] KSI1 1 KSI1 1 JKB1
KSI[0..7] <25> 2 1 2 1 1
KSI7 KSI7 KSI1
KSO[0..17] KSI6 3 2 KSI6 3 2 KSI7 2 1
KSO[0..17] <25> 3 3 2
KSO9 4 KSO9 4 KSI6 3
KSI4 5 4 KSI4 5 4 KSO9 4 3
+3VALW +3VALW +3VLP KSI5 6 5 KSI5 6 5 KSI4 5 4
KSO0 7 6 KSO0 7 6 KSI5 6 5
KSI2 8 7 KSI2 8 7 KSO0 7 6
8 8 7
2
KSI3 9 KSI3 9 KSI2 8
@ KSO5 10 9 KSO5 10 9 KSI3 9 8
R274 R170 JPWRB1 KSO1 11 10 KSO1 11 10 KSO5 10 9
100K_0402_5% 100K_0402_5% 1 KSI0 12 11 KSI0 12 11 KSO1 11 10
2 1 KSO2 13 12 KSO2 13 12 KSI0 12 11
1
PWR_LED# 3 2 KSO4 14 13 KSO4 14 13 KSO2 13 12
ON/OFF# 4 3 KSO7 15 14 KSO7 15 14 KSO4 14 13
<25> ON/OFF# 4 15 15 14
5 KSO8 16 KSO8 16 KSO7 15
LID_SW# 6 5 KSO6 17 16 KSO6 17 16 KSO8 16 15
<25> LID_SW# 6 17 17 16
KSO3 18 KSO3 18 KSO6 17
J1: TOP 7 KSO12 19 18 KSO12 19 18 KSO3 18 17
J2: BOT 8 GND KSO13 20 19 KSO13 20 19 KSO12 19 18
J1 GND +3VS 20 20 19
R264 KSO14 21 KSO14 21 KSO13 20
21 21 20
2
1 2 ACES_88058-060N 470_0402_5% KSO11 22 KSO11 22 KSO14 21
ESD@ @ ME@ KSO10 23 22 KSO10 23 22 KSO11 22 21
Z17@ 23 23 22
SHORT PADS D24 D26 SP010010T00 KSO15 24 KSO15 24 KSO10 23
KSO16 25 24 KSO16 25 24 KSO15 24 23
J2 25 25 24
KSO17 26 KSO17 26 CAPS_LED#_R 25
1 2 ON/OFF# R263 2 1 470_0402_5% CAPS_LED#_R 27 26 CAPS_LED#_R 27 26 CAPS_LED# 26 25
1
28 27 CAPS_LED# 28 27 26 27
<25> CAPS_LED# 28 28 GND2
SHORT PADS R264 2 Z15@ 1 470_0402_5% NUM_LED#_R 29 31 NUM_LED#_R 29 31 28
MESC5V02BD03_SOT23-3 MESC5V02BD03_SOT23-3 30 29 GND 32 NUM_LED# 30 29 GND 32 GND1
<25> NUM_LED# 30 GND 30 GND
ACES_88514-3001 ACES_88514-3001 ACES_88514-02601-071
ESD ESD
ME@
SP010011A00
ME@
SP010011A00
ME@
SP01000R500
1 1
0.1U_0402_25V6
0.1U_0402_25V6
C131 C132
ESD@ ESD@
2 2
For Z15/Z17
+3VS R258 1 @ 2 0_0402_5% RP33
0_0804_8P4R_5%
1 Z17@
@
C163 RP34
0.1U_0201_10V6K 0_0804_8P4R_5%
2
Z17@ LED1
Z15@
R171 Z15@
RP33 JTP1 PWR_LED# 1 2 1 2
TP_VCC 1 8 Z15_VCC_Z14_R 1
Power (White) <25> PWR_LED#
300_0402_1%
+3VALW
TP_CLK 2 7 Z15_CLK_Z14_L 2 1
<25> TP_CLK 3 6 3 2
TP_DATA Z15_DATA_Z14_GND
<25> TP_DATA 3 LTW-C193TS5-C_WHITE
1 1 4 5 4
@ @ 5 4
C164 C165 0_0804_8P4R_5% 6 5
6 LED2
100P_0402_50V8J 100P_0402_50V8J Z15@ Z15@
2 2 7 R173 Z15@
GND
3
RP34 8 Battery (white) <25> BATT_CHG_LED# BATT_CHG_LED# 1 2 1 2 +3VLP

1 8 Z15_GND_Z14_DATA GND 300_0402_1%
@ESD@ TP_L 2 7 Z15_L_Z14_CLK ACES_88058-060N
D5 TP_R 3
4
6
5
Z15_R_Z14_VCC ME@
SP010010T00 LTW-C193TS5-C_WHITE
For Z15
1
1 1 0_0804_8P4R_5%
PACDN042Y3R_SOT23-3 @ @ Z15@ LED3 Z15@
C166 C167 R172 Z15@
0.1U_0201_10V6K 0.1U_0201_10V6K BATT_LOW_LED# 1 2 1 2
2 2 Battery (Amber) <25> BATT_LOW_LED#
A 620_0402_5%
+3VLP
ESD For Z14 LTST-C191KFKT-2CA_ORANGE
LED4
RP35 Z14@
TP_VCC 1 8 Z15_R_Z14_VCC R176 Z14@
TP_CLK 2 7 Z15_L_Z14_CLK 1 2 1 2 +3VALW
TP_DATA 3 6 Z15_GND_Z14_DATA
4 5 680_0402_1%
0_0804_8P4R_5% LTW-C193TS5-C_WHITE
Z14@
LED5
RP36 Z14@
1 8 Z15_DATA_Z14_GND R174 Z14@
For Z14,Z15,Z17 TP module(100*50) For Z14 TP module(100*50)
1 1 VCC 6 1 VCC
TP_L
TP_R
2
3
4
7
6
5
Z15_CLK_Z14_L
Z15_VCC_Z14_R
1 2 1
300_0402_1%
2
+3VLP
For Z14
2 2 CLK 5 2 CLK
0_0804_8P4R_5%
Z14@ NOVO LTW-C193TS5-C_WHITE
+3VLP LED6 Z14@

R175 Z14@
3 3 DAT 4 3 DAT 1 2 1 2 +3VLP
2
A 620_0402_5%
100K_0402_5%
4 4 GND 3 4 GND R169 LTST-C191KFKT-2CA_ORANGE
5 5 L 2 5 L
1
SW8 JLED1
6 6 R 1 6 R 1
+3VALW
1
NOVO# 2 PWR_LED# 2 1
<25> NOVO#
MB TP module MB TP module 3
+3VLP
BATT_LOW_LED#
BATT_CHG_LED#
3
4
5
2
3
4 7
7
6
5
4
6 5 G1 8
6 G2
NTC325-EA1J-A160C_3P E-T_6915K-Q06N-00L
SN100008N00 SP01001NO00
ME@
GND
GND
L L L R R R
Z17@ Z15@ Z14@ Z17@ Z15@ Z14@
SW5 SW1 SW3 SW6 SW2 SW4
EVQPLHA15_4P EVQPLHA15_4P EVQPLHA15_4P EVQPLHA15_4P EVQPLHA15_4P EVQPLHA15_4P
5
6
5
6
5
6
5
6
5
6
5
6
4 2 4 2 4 2 4 2 4 2 4 2
TP_L TP_L TP_L TP_R TP_R TP_R
3 1 3 1 3 1 3 1 3 1 3 1
2014/09/01 2015/09/01 Title
Issued Date Deciphered Date ROM/KBD/PWR/CR/LED/TP Conn.
C 1.0
5 4 3 2 1
ESD
@ D6 @ D7 @ D8 @ D9
U3RXDN1 9 10 1 1 U3RXDN1 U3RXDN2 9 10 1 1U3RXDN2 U2DP1 3 6 U2DP2 3 6
I/O2 I/O4 I/O2 I/O4
U3RXDP1 8 9 2 2 U3RXDP1 U3RXDP2 8 9 2 2U3RXDP2
U3TXDN1 7 7 4 4 U3TXDN1 U3TXDN2 7 7 4 4U3TXDN2 2 5 +USB3_VCCA

2 5
GND VDD GND VDD
+USB3_VCCA
U3TXDP1 6 6 5 5 U3TXDP1 U3TXDP2 6 6 5 5U3TXDP2
without charger 3 3 3 3 1 4 U2DN1 1 4 U2DN2
I/O1 I/O3 I/O1 I/O3
8 8
AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6
D D
+5VALW
2A/Active Low +USB_VCCB L05ESDL5V0NA-4_SLP2510P8-10-9 L05ESDL5V0NA-4_SLP2510P8-10-9
U8
100mil 1 100mil
5 OUT
IN 2
4 GND R179
<25> USB_EN# EN 3 USB_OC1#_U8 1 @ 2 USB_OC1#
OCB USB_OC1# <9,10>
1
C195
0.1U_0201_10V6K
2
SY6288D20AAC_SOT23-5
C170
1
+
1
@
0_0402_5%
USB3.0_Port Intel_PCH_USB2.0
EMI
R1664 1
@EMI@
2 0_0402_5%
220U_6.3V_M C171
S_A-P_CAP 220U 6.3V M 6.3X4.5 ESR18M
2 2
470P_0402_50V7K
2
PANASONIC EXC24CQ900U
3 U2DN2
Left USB CONN
<10> USB20_N1 2 3
1 4 U2DP2
<10> USB20_P1 1 4
L12 EMI@
@EMI@
R1665 1 2 0_0402_5%
EMI Intel_PCH_USB3.0 R1666 1 @ 2 0_0402_5%

+USB3_VCCA
@EMI@ INPAQ HCM1012GD670A05P
R1676 1 2 0_0402_5%
2 3 U3RXDN2
W=80mils
Right USB2__I/O Port L14 EMI@
<10> USB3_RX2_N 2 3 JUSB1
USB20_N2 1 4 USB20_N2_R 1
<10> USB20_N2 1 4 VBUS
1 4 U2DN2 2
<10> USB3_RX2_P 1 4 D-
U3RXDP2 U2DP2 3
USB20_P2 2 3 USB20_P2_R L13 @EMI@ 4 D+
<10> USB20_P2 2 3 GND
U3RXDN2 5
PANASONIC EXC24CQ900U R1667 1 @ 2 0_0402_5% U3RXDP2 6 STDA_SSRX-
C STDA_SSRX+ C
@EMI@
7
R1677 1 2 0_0402_5% U3TXDN2 8 GND
R1668 1 @ 2 0_0402_5% U3TXDP2 9 STDA_SSTX-
C168 STDA_SSTX+
0.1U_0201_10V6K INPAQ HCM1012GD670A05P 10
@EMI@ GND
R1678 1 2 0_0402_5% 1 2 U3TXDN2_L 2 3 U3TXDN2 11
<10> USB3_TX2_N 2 3 GND
12
PANASONIC EXC24CQ900U 13 GND
USB20_P3 2 3 USB20_P3_R 1 2 U3TXDP2_L 1 4 GND
<10> USB20_P3 2 3 <10> USB3_TX2_P 1 4 SINGA_2UB4039-200011F
C169 L15 @EMI@ ME@
USB20_N3 1 4 USB20_N3_R 0.1U_0201_10V6K U3TXDP2 DC23300AQ00
<10> USB20_N3 1 4 R1669 1 @ 2 0_0402_5%
L19 EMI@
Right Card Reader
R1679 1
@EMI@
2 0_0402_5%
Near HDMI CONN.
(Debug Port)
@EMI@
R1670 1 2 0_0402_5%
Intel_PCH_USB2.0
PANASONIC EXC24CQ900U
2 3 U2DN1
<10> USB20_N0 2 3
+USB_VCCB
1 4 U2DP1
<10> USB20_P0 1 4
L16 EMI@
JIO1
100mil 1 R1671 1
@EMI@
2 0_0402_5%
USB20_P3_R
2
3
1
2
Left USB CONN
USB20_N3_R 43 R1672 1 @ 2 0_0402_5%
Right Card Reader 54 Intel_PCH_USB3.0
USB20_P2_R 65 INPAQ HCM1012GD670A05P
USB20_N2_R 76 2 3 U3RXDN1 +USB3_VCCA
Right USB2__I/O Port 87 <10> USB3_RX1_N 2 3
B +3VS
98 W=80mils B
<27> PLUG_IN 9
10 1 4 U3RXDP1 JUSB2
<27> HPOUT_R 10 <10> USB3_RX1_P 1 4
11 1
1211 L17 @EMI@ U2DN1 2 VBUS
<27> HPOUT_L 12 D-
13 15 U2DP1 3
<27> HGNDA 13 GND 16 D+
14 R1673 1 @ 2 0_0402_5% 4
<27> HGNDB 14 GND GND
U3RXDN1 5
JXT_FP202DH-014M10M U3RXDP1 6 STDA_SSRX-
ME@ R1674 1 @ 2 0_0402_5% 7 STDA_SSRX+
SP010021G00 C172 U3TXDN1 8 GND
0.1U_0201_10V6K INPAQ HCM1012GD670A05P U3TXDP1 9 STDA_SSTX-
1 2 U3TXDN1_L 2 3 U3TXDN1 STDA_SSTX+
<10> USB3_TX1_N 2 3 10
11 GND
1 2 U3TXDP1_L 1 4 U3TXDP1 12 GND
<10> USB3_TX1_P 1 4 GND
13
C173 L18 @EMI@ GND
0.1U_0201_10V6K SINGA_2UB4039-200011F
R1675 1 @ 2 0_0402_5% ME@
DC23300AQ00
+5VALW
2A/Active Low+USB3_VCCA
U10
Near End User
W=80mils W=80mils
1
5 OUT
IN 2
USB_EN# 4 GND R185
EN 3 USB_OC0#_R 1 @ 2
OCB USB_OC0# <10>
1
SY6288D20AAC_SOT23-5 0_0402_5%
C196 1
A 0.1U_0201_10V6K 1 A
2 + @
C178 C177
220U_6.3V_M 470P_0402_50V7K
S_A-P_CAP 220U 6.3V M 6.3X4.5 ESR18M 2 2

2014/09/01 2015/09/01 Title
USB3.0/Left USB Ports
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
5 4 3 2 1
+3VLP
+3VALW
+3VLP
R188 1 @ 2 0_0603_5% 1@
C179
100P_0402_50V8J
+3VALW_EC +EC_VCCA R189 1 @ 2 0_0603_5%
2
L20 +3VALW_EC
FBMA-L11-160808-601LMT_2P 1 1 1 1 +5VALW
+EC_VCCA
0.1U_0201_10V6K
0.1U_0201_10V6K
1000P_0402_50V7K
C182
1000P_0402_50V7K
C183
1 2 C180 C181
1 1 R194
C184 C185 @ USB_EN# 1 2
0.1U_0201_10V6K 2 2 @ 2 @ 2
111
125
1000P_0402_50V7K 10K_0402_5%
22
33
96
67
U11
9
1 2 2 ECAGND 2
L21
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
FBMA-L11-160808-601LMT_2P
+3VS +3VS
ECAGND 1 21
GA20/GPIO85 GPIO15/A_PWM VCCST_PWRGD <11>
2 23 BEEP#
<9> KB_RST# KBRST#/GPIO86 GPIO21/B_PWM BEEP# <27>
3 26
<8,9,22> SERIRQ 4 SERIRQ/GPIOF0 GPIO32/D_PWM 27 EC_FAN_PWM1 <22>
<7,22> LPC_FRAME# LFRAME#/GPIOF6 GPIO45/E_PWM EC_FAN_REVERSE <22>
LPC_AD3 5
EMI
EMI@ EMI@
<7,22> LPC_AD3
<7,22> LPC_AD2
<7,22> LPC_AD1
LPC_AD2
LPC_AD1
LPC_AD0
7
8
10
LAD3/GPIOF4
LAD2/GPIOF3
LAD1/GPIOF2
PWM Output
GPIO90/AD0
63
64
VCIN1_BATT_TEMP <39,40>
TP_CLK R260 1 2 4.7K_0402_5%
<7,22> LPC_AD0 LPC & MISC

LAD0/GPIOF1 GPIO91/AD1
2 1 R190 2 1 10_0402_1% 65
GPIO92/AD2 ADP_I <39,40>
C186 22P_0402_50V8J 12 AD Input 66 TP_DATA R261 1 2 4.7K_0402_5%
<7> CK_LPC_KBC 13 LCLK/GPIOF5 GPIO93/AD3 75 PMON_SKYLAKE <40>
ADP_ID
<8,21,22,26,30> PCIRST# LRESET#/GPIOF7 GPIO05/AD4 ADP_ID <38>
1 2 EC_RST# 37 76
+3VALW_EC R192 47K_0402_5% EC_SCI# 20 EC_RST# GPIO04/AD5 VRAM_TEMP <35>
<7,9> EC_SCI# ECSCI#/GPIO45
2 38 VCIN1_BATT_TEMP 1 2
<38> ADP_ID_CLOSE GPIO11/CLKRUN 68 C189 100P_0402_50V8J
C187 GPIO94/DA0 70 EC_CLEAR_CMOS <6> 1 2
VCIN1_AC_IN
GPIO95/DA1 TS_DISABLE# <17>
0.1U_0402_25V6 DA Output 71 +3VALW C190 100P_0402_50V8J
1 GPIO96/DA2 DGPU_PWR_EN <8,32,43,46>
KSI0 55 72 1 2
56 KSI0/GPIOA0 GPIO97/DA3 EC_WL_OFF# <21>
KSI1 R203 @ 4.7K_0402_5%
KSI2 57 KSI1/GPIOA1 EC_MUTE# R198 1 @ 2 10K_0402_5%
KSI3 58 KSI2/GPIOA2 83
KSO[0..17] KSI3/GPIOA3 GPIO31/SCL3/PSCKL1 EC_MUTE# <27>
KSI4 59 84
<23> KSO[0..17] KSI4/GPIOA4/N2TCK GPIO23/SDA3/PSDAT1 USB_EN# <24>
KSI5 60 85
KSI[0..7] 61 KSI5/GPIOA5/N2TMS GPIO47/SCL4/PSCKL2 86 ADP_SET2
KSI6 PS2 Interface
<23> KSI[0..7] KSI6/GPIOA6 GPIO53/SDA4/PSDAT2 CMOS_ON# <17>
KSI7 62 87 TP_CLK
39 KSI7/GPIOA7 GPIO50/PSCLK3 88 TP_CLK <23>
KSO0 TP_DATA
KSO0/GPOB0/SOUT_CR/JENK# GPIO52/PSDAT3 TP_DATA <23>
+3VALW_EC KSO1 40
KSO2 41 KSO1/GPIB1/TEST#
R201 KSO3 42 KSO2/GPIOB2/TRIST# 97
KSO3/GPIOB3/XORTR# GPIO02 ENBKL <8,17>
1 2 EC_SMB_CK1 KSO4 43 98
44 KSO4/GPOB4/SDP_VIS# GPIO75 99 SYS_PWROK <8>
2.2K_0402_5% KSO5
KSO5/GPIOB5/TDO GPIO76 ME_EN <6>
R202 KSO6 45 109
KSO6/GPIOB6/RDY# GPIO16/VC_IN1 VCIN0_PH1 <39>
1 2 EC_SMB_DA1 KSO7 46
2.2K_0402_5% KSO8 47 KSO7/GPIOB7 Int. K/B SPI Device Interface
KSO9 48 KSO8/GPIOC0 Matrix 119
49 KSO9/GPIOC1 (F_SDI&F_SDIO1)GPIO80 120 EC_SPI_MISO <7>
KSO10
KSO10&P80_CLK/GPIOC2 (F_SDIO&F_SDIO0)GPIO8C6 EC_SPI_MOSI <7>
KSO11 50 126 +3VALW
KSO11&P80_DAT/GPIOC3 (F_SCK)/GPIOC4 EC_SPI_CLK <7>
KSO12 51
KSO12/GPIO64/TCK
SPI Flash ROM (F_CS1#)/GPIOC5 128
EC_SPI_CS0# <7>
KSO13 52
KSO14 53 KSO13/GPIO63/TMS ADB@
KSO15 54 KSO14/GPIO62/TDI 73 FAN_ID R516 1 2 10K_0402_5%
KSO15/GPIO61/XOR_OUT GPIO03/AD6/CIRRXM DDR_TEMP <15>
KSO16 81 74 FAN_ID R517 1 2 10K_0402_5%
KSO17 82 KSO16/GPIO60 GPIO07/AD7/CIRTX1 89
KSO17/GPIO57 GPIO67/N2TMS 90 WLAN_PWR_ON# <21>
GPIO51/N2TCK BATT_CHG_LED# <23> NOADB@
91
77 GPIO36 92 CAPS_LED# <23>
EC_SMB_CK1 GPIO
<39,40> EC_SMB_CK1 GPIO17/SCL1/N2TCK GPIO40/F_PWM PWR_LED# <23>
EC_SMB_DA1 78 93
<39,40> EC_SMB_DA1 GPIO22/SDA1/N2TMS GPIO35 BATT_LOW_LED# <23>
<7,19,22,31> EC_SMB_CK2
EC_SMB_CK2 79
GPIO73/SCL2
SM Bus GPIO06/IOX_DOUT
95 SYSON
SYSON <29,42>
EC_SMB_DA2 80 121 AC_BATT_R R165 1 @ 2 0_0402_5% T34 @
<7,19,22,31> EC_SMB_DA2 GPIO74/SDA2 GPIO81/F_WP# 127
GPIO84/IOX_SCLK EC_FW_UPDATE <17>
6
14 GPIO024 GPIO26/RSMRST#
100
101 EC_RSMRST# <8>
keyboard back light
15 LPCPD#/GPIO10 GPIO20/TA2/IOX_DIN_DIO 102
ADP_SET1 <39> Function GPIO71
<41> 3V/5VALW_PG 16 SMI#/GPIO65 GPIO72/VC_IN2 103 VCIN1_ADP_PROCHOT <39>
T31 @ +3VALW KBL 1
GPIO34/1_WIRE/CIRRXL GPIO37/VC_OUT2 VCOUT1_PROCHOT# <39,40>
T32 @ 17 104
GPIO01/TB2 GPIO25/VC_OUT1 VCOUT0_MAIN_PWR_ON <41>
18 GPO 105 BKOFF#
R215 1 @ 2 0_0402_5% EC_PCIE_WAKE# 19 GPIO43 GPIO77 106 BKOFF# <17>
KBL@
NOKBL 0
<8,21,26> PCIE_WAKE# GPIO42/CIRTX2 GPIO GPIO44 PM_SLP_S3# <8>
25 107 R2000 1 2 10K_0402_5%
<20> KB_BL_PWM 28 GPIO13/C_PWM GPIO12 108 1.05V_VS_PG_PWR <45> R2001 1 2 10K_0402_5%
ESD T33 @
<22> FAN_SPEED1
<21> EC_TX
EC_TX
EC_RX
29
30
31
GPIO56/TA1
GPIO14/TB1
PORT80_DATA/GPIO83/SOUT_CR
GPIO30/F_WP#
110
NOKBL@
<21> EC_RX PORT80_CLK/GPIO87/SIN_CR AC_IN/GPIO41/F_WP# VCIN1_AC_IN <31,40>
PCH_PWROK PCH_PWROK 32 112 EC_ON
<8> PCH_PWROK 34 GPIO27/RSMRST# EC_ON/GPIO71 114 EC_ON <41>
NOVO# ON/OFF# <23> VCOUT1_PROCHOT# R204 1 @ 2 0_0402_5%
<23> NOVO# GPIO66/G_PWM ON_OFFBTN#/GPIO70
1
ESD@ 36 GPIGPIO82/IOX_LDSH_LIDIN 115 LID_SW#

1 <23> NUM_LED# GPIO33/H_PWM LID_SW# <23>
C247 R207 2 116 SUSP#
100P_0402_50V8J GPIO46/CIRRXM/PLCIN SUSP# <29,42,44,45>
117 NUVOTON_VTT R205 1 @ 2 0_0402_5% H_PROCHOT# <4>
<47> VR_HOT#
2
100K_0402_5% 122 VTT 118 PECI 1 2

<8> PBTN_OUT# EXTCLKI/GPIO00 PECI H_PECI <4>
AGND/AGND
PM_SLP_S4#_R 123 R208 43_0402_1%

GPIO55/CLKOUT/IOX_DIN_DIO 124 +V18R R209 1 @ 2 0_0402_5%
GND/GND
GND/GND
GND/GND
GND/GND
Share ROM VCORF

C192 +3VALW_EC
1 1
4.7U_0603_6.3V6K
GND0
@
C191
47P_0402_50V8J
2 2
94
113
69
11
24
35
NPCE288NA0DX_LQFP128_14X14
+3VALW ESD +3VALW
ECAGND
SYSON
1 2 EC_PCIE_WAKE#
R212 1K_0402_5% LID_SW# 1 R206 2
100K_0402_5%
1
1 @ 2 PBTN_OUT#
R196 10K_0402_5% C193
ESD R269 2 @ 1 0_0402_5% 0.1U_0201_10V6K

2 +1.05VS
1
@EMI@
C197 +3VS
0.1U_0201_10V6K NUVOTON_VTT R210 1 @ 2 0_0402_5%
2 @
5
U14
2
P
<8> PM_SLP_S4# B 4 PM_SLP_S4#_R

1 Y
<8> PM_SLP_S5# A
G
3
U74AHC1G08G-AL5-R_SOT353-5
+3VS
1 2 FAN_SPEED1
R214 10K_0402_5%
BIOS & EC I/O Port
C 1.0
5 4 3 2 1
+3VS +3V_LAN
J6 RL11 1 @ 2 0_0603_5%
1 2
1 2
60mil JUMP_43X79
W=60mil +LAN_VDD
LL1
W=60mils
+3VALW +LAN_SROUT1.05 1 2
2.2UH_NLC252018T-2R2J-N_5%
J7 1 SWITCH@
4.7U_0603_6.3V6K
1 2 CL15 1 1
0.1U_0201_10V6K
1 2 8111GLDO@ CL16 CL17
2
JUMP_43X79 0.1U_0201_10V6K
SWITCH@
CL1 @ 2 SWITCH@
D 2 2 D
1U_0402_6.3V6K
1
LL1, CL16, and CL17 close to Pin24

( Should be place within 200 mils )
RJ-45 CONN.
要>1mS and <100mS
+LAN_VDD
Rising ?me (10%~90%) W=40mils JLAN1
+3V_LAN RL1
1 @ 2 +LAN_VDDREG 12
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
+3V_LAN RJ45_TX3- 8 GND
W=60mils 1 1 1 1 1
1U_0402_6.3V6K
4.7U_0603_6.3V6K
0_0603_5% PR4- 11
1 1
0.1U_0201_10V6K
RJ45_TX3+ 7 GND
CL8
CL9 CL10 CL4 CL5 CL6 CL7
PR4+
SWITCH@
SWITCH@
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2 2 2 2 2 RJ45_RX1- 6
1 1 1 1
0.1U_0201_10V6K
0.1U_0201_10V6K
@ @ 2 2 PR2-
CL2 CL3 CL20 CL21 RJ45_TX2- 5
PR3-
2 2 2 2 RJ45_TX2+ 4
PR3+
Pin3 Pin8 Pin22 Pin30 Pin22 RJ45_RX1+ 3
PR2+
C Close to Pin23 RJ45_TX0- 2
C
PR1- 10
RJ45_TX0+ 1 GND
PR1+ 9
GND
CL2 close to Pin 11, only 8106E LDO mode unpop SANTA_130460-3
CL3 close to Pin 32 DC234007K00
ME@
LANGAN1 LANGAN
+LAN_VDD +LAN_VDD
UL2 +3VS
CL11 1 2 0.1U_0201_10V6K
PCIE_PRX_DTX_P3 <10>
LAN_MDIP0 1 17 PCIE_PRX_DTX_P3_C
MDIP0 HSOP
1
LAN_MDIN0 2 18 PCIE_PRX_DTX_N3_C CL12 1 2 0.1U_0201_10V6K PCIE_PRX_DTX_N3 <10>
3 MDIN0 HSON 19 PCIRST# RL8
LAN_MDIP1 4 AVDD10 PERSTB 20 ISOLATE# PCIRST# <8,21,22,25,30> 1K_0402_5%
LAN_MDIN1 5 MDIP1 ISOLATEB 21
6 MDIN1 LANWAKEB 22 PCIE_WAKE# <8,21,25>
LAN_MDIP2
EMI
2
LAN_MDIN2 7 MDIP2 DVDD10 23 +LAN_VDDREG ISOLATE#
8 MDIN2 VDDREG 24 +LAN_SROUT1.05 +3V_LAN
LAN_MDIP3 9 AVDD10 REGOUT 25 LED2 TPL1
EMI@ RL4 1 2 0.1U_0402_25V6 LAN_MDIN3 10 MDIP3 LED2 26 LED1_GPIO 1 @ 2
11 MDIN3 LED1/GPO 27 LED0 RL17 10K_0402_5% RL10
+3V_LAN AVDD33 LED0
EMI@ RL5 1 2 0.1U_0402_25V6 12 28 XTLO TPL2 15K_0402_5%
<7> LANCLK_REQ# 13 CLKREQB CKXTAL1 29 XTLI
<10> PCIE_PTX_C_DRX_P3 14 HSIP CKXTAL2 30 reserved GPIO pin
<10> PCIE_PTX_C_DRX_N3 15 HSIN AVDD10 31 2.49K_0402_1% 2 1 RL9
LANGAN <7> CLK_PCIE_LAN 16 REFCLK_P RSET 32
<7> CLK_PCIE_LAN# REFCLK_N AVDD33 +3V_LAN
33
GND
EMI@ RL6 1 2 0.1U_0402_25V6
B B
SA000080P00 RTL8111H-CG_QFN32_4X4
EMI@ RL7 1 2 0.1U_0402_25V6
LANGAN1
TL1
+V_DAC 1 24 MCT
CL13 TCT1 MCT1
1 2
10P_0402_50V8J
XTLO
ESD EMI LAN_MDIP3
LAN_MDIN3
2
3
TD1+ MX1+
23
22
RJ45_TX3+
RJ45_TX3-
EMI
NOGCLK@ CL18 TD1- MX1- RL19 EMI@ CL19 EMI@
1
@ESD@ 1 2 +V_DAC 4 21 1 2 1 2
YL1 DL1 TCT2 MCT2
OSC
NC
25MHZ_10PF_7V25000014 LAN_MDIN3 1 4 LAN_MDIP2 0.01U_0402_16V7K LAN_MDIP2 5 20 RJ45_TX2+ 75_0805_5% 10P_0603_50V8-J

NOGCLK@ I/O1 I/O3 TD2 MX2+
LAN_MDIN2 6 19 RJ45_TX2-
OSC
EMI@ TD2- MX2-

NC
2 5 +V_DAC 7 18 2 1
GND VDD TCT3 MCT3
2
LAN_MDIP1 8 17 RJ45_RX1+ DL3 EMI@

CL14 TD3+ MX3+ BS4200N-C-LV_SMB-F2
1 2 XTLI LAN_MDIP3 3 6 LAN_MDIN2 LAN_MDIN1 9 16 RJ45_RX1-
I/O2 I/O4 TD3- MX3-
10P_0402_50V8J AZC099-04S.R7G_SOT23-6 +V_DAC 10 15 LANGAN1
DL1 Only For GIGA
GCLK
NOGCLK@ SC300001G00
LAN_MDIP0 11
TCT4
TD4+
MCT4
MX4+
14 RJ45_TX0+ EMI
@ESD@ LAN_MDIN0 12 13 RJ45_TX0-
RG6 1 GCLK@ 2 0_0402_5% XTLI DL2 TD4- MX4-
<28> LAN_XTLI_GCLK 1 4
LAN_MDIN1 LAN_MDIP0
I/O1 I/O3 NS892407
A A
2 5
GND VDD
LAN_MDIP1 3 6 LAN_MDIN0
I/O2 I/O4
AZC099-04S.R7G_SOT23-6
SC300001G00
LAN RTL8111/8106
C 1.0
5 4 3 2 1
A B C D E
+5VS_PVDD
ALC3240 Input
0.1U_0201_10V6K
4.7U_0603_6.3V6K
+5VS
2 1
+3VDD_CODEC
RA1 1 2
CA1
CA3
@
+1.8VS 0_0402_5%
4.7U_0603_6.3V6K
1 2
2 1 140813→Vendor recommended DVDD-IO voltage equal Pin12 pull high voltage
CA2
CA32
2 place close audio codec
0.1U_0201_10V6K
CA17 1 2
4.7U_0603_6.3V6K +IOVDD_CODEC
1 +5VS_PVDD
Combo Jack
2
29
34
39
1
UA1
RA38 (Normal Open)
PVDD1
PVDD2
CPVDD
DVDD
<6> HDA_SDIN0 33_0402_5% 2 1 RA12 HDA_SDIN0_AUDIO 7 100K_0402_5%
1
4 SDATA-IN 25 HP_OUTL 1
<6> HDA_SDOUT_AUDIO Headphone
1
SDATA-OUT HPOUT-L(PORT-I-L) 26 HP_OUTR PLUG_IN_R RA13 1 2 200K_0402_1%
HPOUT-R(PORT-I-R) PLUG_IN <24>
PC_BEEP 11 CA27 1 2 1U_0402_6.3V6K
EMI 5
PCBEEP
VREF
22
27 CPVEE 2 1
22P_0402_50V8J @EMI@
<6> HDA_BITCLK_AUDIO
CA12 33_0402_5% 2 @EMI@ 1 RA10
BCLK CPVEE
CA20 1U_0402_6.3V6K EXT_MIC_SLEEVE
EMI LA2 2 EMI@ 1 FBMA-L11-160808-121LMT_0603 HGNDB
W=40mils EXT_MIC_RING2 LA3 2 EMI@ 1 FBMA-L11-160808-121LMT_0603 HGNDA
HGNDB <24>
RA6 1 2 2.2K_0402_5% EXT_MIC_RING2 13 17 LINE1-R
W=40mils HP_OUTL RA22 1 EMI@ 2 47_0402_5% HPOUT_L
HGNDA <24>
wide 40MIL RA7

1 2 2.2K_0402_5%
CA19 2
EXT_MIC_SLEEVE
1 2.2U_0402_6.3V6M
14
15
23
MIC2-L(PORT-F-L)/RING
MIC2-R(PORT-F-R)/SLEEVE
MIC2-CAP
LINE1-R(PORT-C-R)
LINE1-L(PORT-C-L)
LINE1-VREFO-L
18
24
12
LINE1-L
PLUG_IN_R
+LINE1-VREFO-R
EMI HP_OUTR RA23 1 EMI@ 2 47_0402_5% HPOUT_R
HPOUT_L <24>
HPOUT_R <24>
+MIC2-VREFO MIC2-VREFO HP/ LINE1-JD(JD1)

SPK_L2+ 35 2
External DMIC
SPK-OUT-LP GPIO0/DMIC-DATA12 For Universal Audio Jack
2
2
SPK_L1- 36 3 DMIC_CLK_R BLM15PX221SN1D_2P 2 EMI@ 1 LA1 DMIC_DAT <17>
SPK-OUT-LN GPIO1/DMIC-CLK 1 1
SPK_R1- 37 DMIC_CLK <17> LINE1-L CA21 2 1 1U_0402_6.3V6K CA33 CA34
RA27
RA26
10K_0402_5%
10K_0402_5%
SPK_R2+ 38 SPK-OUT-RN 8 @ @
SPK-OUT-RP DVDD-IO +IOVDD_CODEC
LINE1-R CA22 2 1 1U_0402_6.3V6K
470P_0402_50V7K
470P_0402_50V7K
2.2U_0402_6.3V6M 1 2 CA26 2 2
1
1
1
LDO1 21 28
2.2U_0402_6.3V6M 1 2 CA16 LDO2 32 LDO1-CAP CBN 30 CA15
LDO3 6 LDO2-CAP CBP RA29 1 2 4.7K_0402_5%
LDO3-CAP 1U_0402_6.3V6K
2.2U_0402_6.3V6M 1 2 CA13 2
40 1 @ 2 EC_MUTE# <25> +LINE1-VREFO-R RA32 1 2 4.7K_0402_5%
10 PDB 0_0402_5% RA11 2 1
VD33STB
9 DC DET 41
AVDD1
AVDD2
AVSS1
AVSS2
<6> HDA_SYNC_AUDIO SYNC THERMAL PAD RA8 10K_0402_5%
@
ALC3240-CG_MQFN40_5X5
20
33
19
31
16
RA9 1 @ 2 0_0402_5% +3VALW
2
Output 2
EMI
：
+5VDDA_CODEC +1.8VS
RA5 1 @ 2 0_0402_5%
SPEAK 4 ohm
SPEAK 8 ohm ：40MIL
20MIL
JSPK2
CA8 1 2 1U_0402_6.3V6K SPK_R1- LA5 1 @ 2 0_0603_5% SPK_R1-_CONN 1 7
SPK_R2+ LA6 1 @ 2 0_0603_5% SPK_R2+_CONN 2 1 G1
SPK_L1- LA7 1 @ 2 0_0603_5% SPK_L1-_CONN 3 2
Place near Pin33 SPK_L2+ LA8 1 @ 2 0_0603_5% SPK_L2+_CONN 4 3
5 4
<9> Speaker_JBL 5
6 8
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
6 G2
1 1 1 1 ACES_50278-00601-001
→ +5VDDA_CODEC
ME@
EMI@ CA29
EMI@ CA28
EMI@ CA31
EMI@ CA30
：
SP011310040
+5VS Each PlaTorm Power Net Support List

2 2 2 2
+5VS +5VDDA_CODEC
+1.5VS +1.8VS +3VS +5VS +3VALW
RA4
0_0603_5% 1.5V(S0) 1.8V(S0) 3.3V(S0) 5V(S0) 3.3V(S0~S5) ESD protection needs to be placed near connector side
1 @ 2
AMD Carrizo V V V V V
ESD
0.1U_0201_10V6K
1 1 AMD Carrizo-L V V V V V
1U_0402_6.3V6K
CA7
CA11
Place RA4 on AGND/DGND moat Intel Broadwell V V V V SPK_R1-_CONN SPK_L2+_CONN

2 2
Intel Braswell V V V V V
SPK_R2+_CONN SPK_L1-_CONN
Intel Skylake V V V V V
3 3
Intel Bay trail-M V V V V V
2
Place near Pin20 D4 @ESD@ D10 @ESD@
2
Each PlaTorm HDA Link Voltage Support (Pin 8)
3.3V 1.5V
1
AMD Carrizo V
1
AMD Carrizo-L V L03ESDL5V0CG3-2_SOT-523-3 L03ESDL5V0CG3-2_SOT-523-3
Intel Broadwell V V
Intel Braswell V
Intel Skylake V V
Intel Bay trail-M V
→
+3VDD_CODEC
+IOVDD_CODEC
+3VS → +3VDD_CODEC PC Beep EMI
+3VS +3VDD_CODEC
RA2 1 2 CA91 RA21 1 @ 2 0_0402_5%

0_0603_5% EC Beep <25> BEEP#
RA35 47K_0402_5% 1U_0402_6.3V6K
1 @ 2 1 2 1 2 PC_BEEP
HDA_SPKR <9> HDA_SPKR
RA37 47K_0402_5% RA24 1 @ 2 0_0402_5%
1U_0402_6.3V6K
0.1U_0201_10V6K
4 1 1 RA25 1 @ 2 0_0402_5% 4
1
+3VDD_CODEC +IOVDD_CODEC
CA5
CA4
CA90 RA39
100P_0402_50V8J 27K_0402_5%
RA3 @ESD@ RA28 1 @ 2 0_0402_5%
2
0_0603_5% 2 2
2
1 @ 2
0.1U_0201_10V6K
1 GND GNDA
CA6
Place near Pin1
Place near Pin8

2 Security Classification Compal Secret Data Compal Electronics, Inc.
HD Audio Codec_ALC3240
C 1.0
A B C D E
5 4 3 2 1
D D
+CHGRTC_R
1
UG1
RG1
330_0402_5%
GCLK@
2
SLG3NB3375VTR_TQFN16_2X3
GCLKUMA@
C 1 SA00006RE00 1 C
CG5 CG11
22U_0603_6.3V6M 2.2U_0402_6.3V6M
GCLK@ GCLK@
2 UG1 2
GCLK_VRTC 10 14 RTC_VOUT
VRTC VOUT
+3VLP
15
2
V3.3A EMI
+3VALW VDD 9 CPU_RTCX1_GCLK_R RG4 1 GCLK@ 2 0_0402_5%
1 32.768kHz CPU_RTCX1_GCLK <6> CPU_32.768KHz
CG4 1
0.1U_0201_10V6K CG10 11 12 GPU_XTALIN_GCLK_R RG5 1GCLKDIS@ 2 10_0402_5%
2 +1.8VGS VIOE_27M 27M GPU_XTALIN_GCLK <31> GPU_27MHz only for DIS
GCLK@ 0.1U_0201_10V6K
GCLK@ 8 6 LAN_XTLI_GCLK_R RG7 1 GCLK@ 2 33_0402_5%
2 +3V_LAN VIO_25M 25M LAN_XTLI_GCLK <26> LAN_25MHz
1
CG1 3 5 CPU_XTAL24_IN_GCLK_R RG8 1 GCLK@ 2 0_0402_5%
+1.05VS VIOE_24M 24M CPU_XTAL24_GCLK <7> CPU_24MHz
0.1U_0201_10V6K 1
GCLKDIS@ CG3 CLK_X2 16 1
2 0.1U_0201_10V6K CLK_X1 1 X2 CG9
1 X1
GND1
GND2
GND3
GND4
GCLK@ CG2 5P_0402_50V8C CG9 no stuff any of component
2 0.1U_0201_10V6K @EMI@
GCLK@ 2
2 SLG3NB3377VTR_TQFN16_2X3
4
7
13
17
GCLKDIS@ 1
SA00007VH00 CG8
5P_0402_50V8C CG8 just can use 4.7pF~33pF
@EMI@
2
CLK_X1 1
CG7
YG1 CLK_X2 5P_0402_50V8C
4 3 @EMI@ CG7 no stuff any of component
NC OSC 2
1 2
B OSC NC B
1 25MHZ_10PF_7V25000014 1
CL28 GCLK@ CL29
12P_0402_50V8J 15P_0402_50V8J
GCLK@ GCLK@
2 2
A A
Security Classification
2014/09/01
Compal Secret Data
2015/09/01 Title
GCLK
1.0
5 4 3 2 1
A B C D E
+5VALW
+5VALW
10U_0603_6.3V6M
+5VALW +0.675VS +1.05VS
0.1U_0201_10V6K
1 1
+5VALW to +5VS
C214
C215
@
1
2 2 U13 +5VS R230 R228 R229
J5 @ @ @
1 10 +5VALW_5VS 2 1 100K_0402_5% 470_0402_5% 470_0402_5%
IN1 OUT1 2 1
1 2
1 2
10U_0603_6.3V6M
2 9 C213 1 2 220P_0402_50V7K JUMP_43X79 SUSP
1 EN1 CT1 1
0.1U_0201_10V6K
3 8 1 1
<25,42,44,45> SUSP# VBIAS GND
1
C217
C218
4 7 1 2 D D
+3VALW EN2 CT2 C207 470P_0402_50V7K @ D SUSP 2 Q21 @ SUSP 2 Q22 @
5 6 +3VALW_3VS SUSP# 2 Q23 @ G 2N7002K_SOT23-3 G 2N7002K_SOT23-3
IN2 OUT2 2 2 G 2N7002K_SOT23-3 S S
11 S
3
GND PAD
10U_0603_6.3V6M
3
0.1U_0201_10V6K
1 1
C205
C206
G5016KD1U_TDFN14-11_2X3 +3VS
@ J4
2 1 R235 1 @ 2 470_0603_5%
2 2 2 1
10U_0603_6.3V6M
JUMP_43X79
+3VALW to +3VS
1
0.1U_0201_10V6K
1 1
C211
C212
D
@ 2 SUSP
G
2 2 S
Q14 @
3
2N7002K_SOT23-3
+5VALW
2
@
R233
+3VALW to +1.8VS 220K_0402_5% +1.35V
+3VALW
1
+5VALW SYSON#
@ Q24 R234
1
DRC2124E0L NPN MINI3-G3-B 470_0603_5%
@
OUT
1 2
1
1
@ C450 C80 @
1U_0402_6.3V6K 4.7U_0603_6.3V6K 2 D
<25,42> SYSON IN 2
@ Q25 SYSON#
GND
2
2 2N7002K_SOT23-3
2
Ultra Low Dropout 0.23V(typical) at 3A Output Current S
G 2
3
R239
100K_0402_5%
2
6
5
VCNTL
7 VIN
POK 4 +3VALW_1.8VS R32 1 @ 2 0_0402_5%
VOUT +1.8VS
3
VOUT
1
SUSP# R20 1 @ 2 60.4K_0402_1% 8 2

Rup 1
EN FB R512 @ C452 @
GND
1 9 24K_0402_1% 0.01U_0402_16V7K 1 1
0.1U_0402_25V6
1U_0402_6.3V6K
0.1U_0402_25V6
1
VIN 2
2
C9
C21
C20
R24 @
1
47K_0402_5%
2@ 2@ 2@
Vout=0.8V* (1+Rup/Rdown)
2
U25 @
Rdown
SA00007IZ00 R513 @
AP7175SP-13_SO-8EP-8 19.1K_0402_1%
2
+3VALW
3 3
U26
1 5 +3VALW_1.8VS_1 R51 1 @ 2 0_0402_5% +1.8VS
IN OUT
1
1 2
1U_0402_6.3V6K
GND R514
SUSP# R131 1 2 3 4
Rup 1
C81
44.2K_0402_1% C109 @
SHDN SET 4.7U_0603_6.3V6K
2 100K_0402_5% G916T1UF_SOT23-5
2
2
1
1
C110
0.1U_0402_25V6 R515
100K_0402_1%
2
Rdown
2
4 4

DC Interface
C 1.0
A B C D E
1 2 3 4 5
UV1A
A
AC Coupling Capacitor A
PCIe Gen3: Recommended value is 220 nF
PCIe Gen1 and Gen2 only: Recommended value is 100 nF
AF30 AH30 PCIE_CRX_GTX_P0_C 0.1U_0201_10V6K 2 1 PX@ CV1

<10> PCIE_CTX_GRX_P0 PCIE_RX0P PCIE_TX0P PCIE_CRX_GTX_P0 <10>
AE31 AG31 PCIE_CRX_GTX_N0_C 0.1U_0201_10V6K 2 1 PX@ CV2
<10> PCIE_CTX_GRX_N0 PCIE_RX0N PCIE_TX0N PCIE_CRX_GTX_N0 <10>
AE29 AG29 PCIE_CRX_GTX_P1_C 0.1U_0201_10V6K 2 1 PX@ CV3

AD28 AF28 PCIE_CRX_GTX_N1_C 0.1U_0201_10V6K 2 1 PX@ CV4
AD30 AF27 PCIE_CRX_GTX_P2_C 0.1U_0201_10V6K 2 1 PX@ CV5

AC31 AF26 PCIE_CRX_GTX_N2_C 0.1U_0201_10V6K 2 1 PX@ CV6
AC29 AD27 PCIE_CRX_GTX_P3_C 0.1U_0201_10V6K 2 1 PX@ CV7

AB28 AD26 PCIE_CRX_GTX_N3_C 0.1U_0201_10V6K 2 1 PX@ CV8
AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_RX4N PCIE_TX4N
AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N
Y30 AB27
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N
W29 Y27
B
V28 PCIE_RX7P PCIE_TX7P Y26 B
PCIE_RX7N PCIE_TX7N
V30 W24
U31 NC#V30 NC#W24 W23
NC#U31 NC#W23
U29 V27
T28 NC#U29 NC#V27 U26
NC#T28 NC#U26
PCI EXPRESS INTERFACE

T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23
No Use GPU Display Port outpud
R29 T26
P28 NC#R29 NC#T26 T27
NC#P28 NC#T27 UV1F
+VGA_CORE
P30 T24
N31 NC#P30 NC#T24 T23
NC#N31 NC#T23 AB11
VARY_BL AB12 FOR TOPAS CORE POWER USE
N29 P27 DIGON
M28 NC#N29 NC#P27 P26
NC#M28 NC#P26
M30 P24 AL15

L31 NC#M30 NC#P24 P23 TXCAP_DPA3P AK14
NC#L31 NC#P23 TXCAM_DPA3N
AH16
L29 M27 TX0P_DPA2P AJ15
K30 NC#L29 NC#M27 N26 TX0M_DPA2N
NC#K30 NC#N26 AL17
TX1P_DPA1P AK16
C C
TX1M_DPA1N
CLOCK AH18
CLK_PCIE_GPU AK30 TX2P_DPA0P AJ17
<7> CLK_PCIE_GPU PCIE_REFCLKP TX2M_DPA0N
CLK_PCIE_GPU# AK32
<7> CLK_PCIE_GPU# PCIE_REFCLKN +0.95VGS AL19
+3VGS NC_TXOUT_L3P AK18
CALIBRATION NC_TXOUT_L3N
Y22 RV1 1 PX@ 2 1.69K_0402_1%
PCIE_CALR_TX TMDP
RV2 1 PX@ 2 1K_0402_5% N10 AA22 RV3 1 PX@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX
5
UV2 PX@ AH20

PCIRST# 2 TXCBP_DPB3P AJ19
P
<8,21,22,25,26> PCIRST# B TXCBM_DPB3N

4 GPU_RST# AL27
DGPU_HOLD_RST# 1 Y PERSTB AL21
<8> DGPU_HOLD_RST# A TX3P_DPB2P
G
AK20
TX3M_DPB2N
1
216-0864018 A0 MESO XT S3
3
PX@ PX@ AH22

MC74VHC1G08DFT2G_SC70-5 RV4 TX4P_DPB1P AJ21
100K_0402_5% TX4M_DPB1N
AL23
2
TX5P_DPB0P AK22
TX5M_DPB0N
AK24
NC_TXOUT_U3P AJ23
NC_TXOUT_U3N
<31> GPU_RST#
216-0864018 A0 MESO XT S3
PX@
D D

Title
Issued Date 2014/09/01 Deciphered Date 2015/09/01 Meso XT_PCIE/DP
Date:
LA-C281Sheet
Friday, February 06, 2015 30 of 50
1 2 3 4 5
1 2 3 4 5
for GPU tempture issue

+1.8VGS
+3VGS +3VGS UV1B
PS_0[3:1]=001 Strap Name :
U?
<30> GPU_RST# PS_0[5:4]=11
1
PX@
PS_0[1] ROM_CONFIG[0]
1
AF2 RV12 PS_0[2] ROM_CONFIG[1]
@ R56 R52 NC#AF2 AF4 8.45K_0402_1%
@ 0_0402_5% NC#AF4
0_0402_5% PS_0[3] ROM_CONFIG[2]
2
N9 AG3 PS_0
L9 DBG_DATA16 NC#AG3 AG5 Resistor Divider Lookup Lable PS_0[4] N/A
2
DBG_DATA15 NC#AG5
1
AE9 1
0.68U_0402_10V
DPA
Y11 DBG_DATA14 AH3 PX@
AE8 DBG_DATA13 NC#AH3 AH1 CV30 RV7
PS_0[5] AUD_PORT_CONN_PINSTRAP[0]
AD9 DBG_DATA12 NC#AH1 R_pu (ohm) R_pd (ohm) Bitd [3:1] 2K_0402_1%
DBG_DATA11
1
A AC10 AK3 @ 2 A
2
RV202 RV203 AD7 DBG_DATA10 NC#AK3 AK1
45.3K_0402_1% 45.3K_0402_1% AC8 DBG_DATA9 NC#AK1 NC 4.75k 000
DVO
DBG_DATA8
2
AC7 AK5
AB9 DBG_DATA7 NC#AK5 AM3
8.45k 2k 001
2
6 1 VGA_SMB_DA3 AB8 DBG_DATA6 NC#AM3
<7,19,22,25> EC_SMB_DA2
AB7 DBG_DATA5 AK6
4.53k 2k 010
QV9A AB4 DBG_DATA4 NC#AK6 AM5
DBG_DATA3 NC#AM5 6.98k 4.99k 011
5
2N7002EDW 2N SOT-363-6 AB2
Y8 DBG_DATA2 DPB
AJ7
PS_1[3:1]=000 Strap Name :
3 4 VGA_SMB_CK3 Y7 DBG_DATA1 NC#AJ7 AH6
4.53k 4.99k 100
<7,19,22,25> EC_SMB_CK2 DBG_DATA0 NC#AH6 PS_1[5:4]=11
1
QV9B AK8
3.24k 5.62k 101 @
PS_1[1] STRAP_BIF_GEN3_EN_A
2N7002EDW 2N SOT-363-6 NC#AK8 AL7 RV9
NC#AL7 3.4k 10k 110 8.45K_0402_1%
PS_1[2] TRAP_BIF_CLK_PM_EN
4.75k NC 111 PS_1[3] N/A
2
+1.8VGS W6 PS_1
V6 NC#W6
NC#V6 0402 1% resistors are equired PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING
1
V4 1
0.68U_0402_10V
AC6 NC#V4 U5 PX@
AC5 NC#AC5 NC#U5 CV31 RV14
PS_1[5] STRAP_TX_DEEMPH_EN
NC#AC6 W3 4.75K_0402_1%
NC#W3
2
AA5 V2 @ 2
Capacitor Divider Lookup Lable
2
RV16 RV11 AA6 NC#AA5 NC#V2
DPC
4.7K_0402_5% 4.7K_0402_5% NC#AA6 Y4
PX@ PX@ NC#Y4 W5
NC#W5 Cap (nF) Bitd [5:4]
1
U1 AA3 PLL_ANALOG_OUT 1 PX@ 2
1 FB_VDDCI W1 NC#U1 NC#AA3 Y2 RV17
TV23
U3 NC#W1 NC#Y2 16.2K_0402_1%
680nF 00
Y6 NC#U3 J8 +1.8VGS
1 PLL_ANALOG_IN AA1 NC#Y6 NC#J8 82nF 01 PS_2[3:1]=000 Strap Name :
TV18 NC#AA1
10nF 10 PS_2[5:4]=00
1
@
PS_2[1] N/A
NC 11 RV57
8.45K_0402_1%
PS_2[2] N/A
I2C
PS_2[3] STRAP_BIOS_ROM_EN
2
B R1 PS_2 B
R3 SCL
SDA PS_2[4] STRAP_BIF_VGA_DIS
1
1
0.68U_0402_10V
+3VGS AM26 PX@ PX@
REAK CURRENT CONTROL ( Topaz only ) +VGA_CORE R AK26 CV32 RV19
PS_2[5] N/A
GENERAL PURPOSE I/O AVSSN#AK26
U6 +3VGS 4.75K_0402_1%
GPIO_0
2
U10 AL25 2
2
RV10 PX@ T10 GPIO_1 G AJ25
GPIO_2 AVSSN#AJ25
2
10K_0402_5% VGA_SMB_DA3 U8
PX@ VGA_SMB_CK3 U7 SMBDATA AH24 RV371
PX@RV15 DV1 1 2 GPU_GPIO5 T9 SMBCLK B AG25
<25,40> VCIN1_AC_IN 4.7K_0402_5%
1
1K_0402_5% GPU_GPIO6 T8 GPIO_5_AC_BATT AVSSN#AG25 @

GPU_GPIO6 1 2 GPU_PROCHOT# DB2J31400L SOD323-2 T7 GPIO_6 DAC1 AH26
GPU_PROCHOT# <46>
1
P10 GPIO_7_BLON HSYNC AJ27
P4 GPIO_8_ROMSO VSYNC +1.8VGS
1 GPIO_9_ROMSI PS_3[3:1]=000 Strap Name :
2
CV17 PX@ P2
+VGA_CORE N6 GPIO_10_ROMSCK AD22 RV372
0.1U_0201_10V6K GPIO_11 RSET PS_3[5:4]=11
1
N5 4.7K_0402_5% PS_3[1] BOARD_CONFIG[0] (Memory ID)
2 N3 GPIO_12 AG24 PX@ X76@
Y9 GPIO_13 AVDD AE22 RV21 PS_3[2] BOARD_CONFIG[1] (Memory ID)
1
N1 GPIO_14_HPD2 AVSSQ Pull down for none OBFF design 8.45K_0402_1%
M4 GPIO_15_PWRCNTL_0 AE23
PS_3[3] BOARD_CONFIG[2] (Memory ID)
2
THM_ALERT# RV251 1 @ 2 0_0402_5% THM_ALERT#_R R6 GPIO_16 VDD1DI AD23 PS_3
<22> THM_ALERT# GPIO_17_THERMAL_INT VSS1DI
W10 PS_3[4] AUD_PORT_CONN_PINSTRAP[1]
GPIO_18
1
GPIO19_CTF M2 1
0.68U_0402_10V
GPIO_19_CTF FutureASIC/SEYMOUR/PARK
P8 AM12
CV33
X76@ PS_3[5] AUD_PORT_CONN_PINSTRAP[2]
+1.8VGS P7 GPIO_20_PWRCNTL_1 CEC_1 @ RV24
N8 GPIO_21 2K_0402_1%
1 RV13 2 GPIO19_CTF AK10 GPIO_22_ROMCSB AK12 GPU_SVD 2
GPU_SVD <46>
2
10K_0402_5% AM10 GPIO_29 RSVD#AK12 AL11 GPU_SVT
GPIO_30 RSVD#AL11 GPU_SVT <46>
@ 1 @ 2 GPUCLK_REQ#_GPU N7 AJ11 GPU_SVC GPU_SVC <46>
<7> GPUCLK_REQ# CLKREQB RSVD#AJ11
2
RV25 0_0402_5%
RV22 JTAG_TRSTB L6
JTAG_TDI L5 JTAG_TRSTB
10K_0402_5% JTAG_TDI
JTAG_TCK L3
1 @ 2 JTAG_TMS L1 JTAG_TCK AL13
+3VGS
1
RV26 5.11K_0402_5% 1 JTAG_TDO K4 JTAG_TMS GENLK_CLK AJ13

TV24 JTAG_TDO GENLK_VSYNC
+3VGS 1 PX@ 2 TESTEN K7
C RV27 1K_0402_5% AF24 TESTEN C
RV18 2 PX@ 1 4.7K_0402_5% THM_ALERT# +VGA_CORE NC#AF24 AG13
SWAPLOCKA AH12
AB13 SWAPLOCKB
W8 GENERICA
W9 GENERICB
W7 GENERICC AC19 PS_0
AD10 GENERICD PS_0
AJ9 GENERICE AD19 PS_1
+3VGS AL9 NC#AJ9 PS_1
NC#AL9 AE17 PS_2
AC14 PS_2
1 PX_EN AB16 HPD1 AE20 PS_3
TV25 PX_EN PS_3
RV58 1 PX@ 2 10K_0402_5% GPU_GPIO5
RV20 1 @ 2 10K_0402_5% JTAG_TDO AE19

AC16 TS_A
DBG_VREFG
VGA_AC_BATT
pull up DDC/AUX
+3VGS AE6
PLL/CLOCK DDC1CLK AE5
DDC1DATA OPTIAN FOR 3.3V tolerance VR,
RPV1 @ AD2 Check with VR vendor
1 8 JTAG_TRSTB AUX1P AD4 +VGA_CORE +1.8VGS +3VGS
2 7 JTAG_TDI AUX1N RV206 RV207
3 6 JTAG_TMS AC11 1 @ 2 1 @ 2
4 5 JTAG_TCK DDC2CLK AC13 0_0402_5%
DDC2DATA
2
0_0402_5%
10K_0804_8P4R_5% XTALIN AM28 AD13 RV209 RV208
XTALOUT AK28 XTALIN AUX2P AD11 10K_0402_5% 10K_0402_5%
XTALOUT AUX2N PX@ @
RV28 RV29 1 PX@ 2 10K_0402_5% AC22 AD20 GPU_VDD_RUN_FB_L
1
XTALIN 1M_0402_5% XTALOUT RV31 1 PX@ 2 10K_0402_5% AB22 XO_IN NC#AD20 AC20 GPU_VDD_SEN GPU_VDD_RUN_FB_L <46> GPU_SVD
NOGCLKDIS@ XO_IN2 NC#AC20 GPU_VDD_SEN <46> GPU_SVC
TO EXTERNAL THERMAL SENSOR AE16
NC#AE16
2
AD16
D YV1 NOGCLKDIS@ NC#AD16 D
4 3 SEYMOUR/FutureASIC AC1 @ PX@
NC OSC RV248 1 @ 2 0_0402_5% THERM_D+ T4 DDCVGACLK AC3 RV204 RV205
<22> REMOTE1+ DPLUS THERMAL DDCVGADATA
1 2 RV249 1 @ 2 0_0402_5% THERM_D- T2 10K_0402_5% 10K_0402_5%
<22> REMOTE1-
1
OSC NC DMINUS GPU_VDD_RUN_FB_L RV30 1 PX@ 2 10_0402_5%
27MHZ 10PF X3G027000DA1H +1.8VGS Enable MLPS GPU_VDD_SEN RV32 1 PX@ 2 10_0402_5%
2 2 +VGA_CORE
CV19 SJ10000FH00 CV20 R5
8.2P_0402_50V_NPO 8.2P_0402_50V_NPO 13mA AD17 GPIO28_FDO
NOGCLKDIS@ NOGCLKDIS@ LV4 1 @ 2 0_0402_5% +TSVDD AC17 TSVDD
1 1 TSVSS
1
CV21
1U_0402_6.3V6K
PX@ 216-0864018 A0 MESO XT S3
Title
2 PX@
Issued Date 2014/09/01 Deciphered Date 2015/09/01 Meso XT_MSIC
GPU_XTALIN_GCLK RV253 1GCLKDIS@2 0_0402_5% XTALIN
<28> GPU_XTALIN_GCLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Date:
LA-C281Sheet
Friday, February 06, 2015 31 of 50
1 2 3 4 5
1 2 3 4 5
+1.35VS to +1.35VGS (6.234A) UV1E PX@ U?
+1.35V +1.35VGS
UV14 PX@ AA27 A3
AO4478L_SO8 No Use GPU Display Port outpud AB24 GND GND A30
B+ 8 1 +1.8VGS AB32 GND GND AA13
7 2 AC24 GND GND AA16
GND GND
2
6 3 UV1G PX@ U? AC26 AB10
GND GND
10U_0603_6.3V6M
1U_0402_6.3V6K
1 5 1 1 AC27 AB15
GND GND
CV26
CV22
CV25 RV34 AD25 AB6
CV23
CV24
DP POWER NC/DP POWER
RV35 10_0603_5% AD32 GND GND AC9
0.1U_0201_10V6K 1 1
4
@ AG15 AE11 AE27 GND GND AD6
A 1M_0402_5% A
2 PX@
3 1
2 PX@ 2 PX@ AG16 DP_VDDR#AG15 NC#AE11 AF11 AF32 GND GND AD8
PX@ DP_VDDR#AG16 NC#AF11 GND GND
AF16 AE13 AG27 AE7
1U_0402_6.3V6K
10U_0603_6.3V6M
2
2 2 AG17 DP_VDDR#AF16 NC#AE13 AF13 AH32 GND GND AG12
DP_VDDR#AG17 NC#AF13 GND GND
PX@
PX@
AG18 AG8 K28 AH10
RV60 5 DGPU_PWR_EN# AG19 DP_VDDR#AG18 NC#AG8 AG10 K32 GND GND AH28
1.35VSG_GATE_R PX@ 1.35VSG_GATE AF14 DP_VDDR#AG19 NC#AG10 L27 GND GND B10
QV10B DP_VDDR#AF14 M32 GND GND B12
4
220K_0402_5% 2N7002EDW 2N SOT-363-6 N25 GND GND B14
PX@ N27 GND GND B16
1 GND GND
6
CV27 P25 B18

0.022U_0402_25V7K AG20 AF6 P32 GND GND B20
PX@ AG21 DP_VDDC#AG20 NC#AF6 AF7 R27 GND GND B22
DGPU_PWR_EN# 2 2 +0.95VGS AF22 DP_VDDC#AG21 NC#AF7 AF8 T25 GND GND B24
AG22 DP_VDDC#AF22 NC#AF8 AF9 T32 GND GND B26
AD14 DP_VDDC#AG22 NC#AF9 U25 GND GND B6
1
QV10A DP_VDDC#AD14 U27 GND GND B8

2N7002EDW 2N SOT-363-6 V32 GND GND C1
CV28
CV29
PX@ W25 GND GND C32
1 1 GND GND
AG14 AE1 W26 E28
AH14 DP_VSSR NC#AE1 AE3 W27 GND GND F10
AM14 DP_VSSR NC#AE3 AG1 Y25 GND GND F12
1U_0402_6.3V6K
2 2 AM16 DP_VSSR NC#AG1 AG6 Y32 GND GND F14
0.1U_0201_10V6K
DP_VSSR NC#AG6 GND GND
PX@
PX@
AM18 AH5 F16
AF23 DP_VSSR NC#AH5 AF10 GND F18
AG23 DP_VSSR NC#AF10 AG9 GND F2
AM20 DP_VSSR NC#AG9 AH8 GND F20
AM22 DP_VSSR NC#AH8 AM6 M6 GND F22
AM24 DP_VSSR NC#AM6 AM8 N13 GND GND F24
AF19 DP_VSSR NC#AM8 AG7 N16 GND GND F26
AF20 DP_VSSR NC#AG7 AG11 N18 GND GND F6
+1.05VS to +0.95VGS AE14 DP_VSSR
DP_VSSR
NC#AG11 N21
P6
GND
GND
GND
GND
GND
F8
G10
P9 GND GND G27
R12 GND GND G31
B
AF17 AE10 R15 GND GND G8 B
DPAB_CALR NC#AE10 R17 GND GND H14
+1.05VS +0.95VGS R20 GND GND H17
UV15 PX@ T13 GND GND H2
AO4354_SO8 T16 GND GND H20
8 1 216-0864018 A0 MESO XT? S3 T18 GND GND H6
7 2 T21 GND GND J27
GND GND
2
B+
0.1U_0201_10V6K
6 3 T6 J31
GND GND
1U_0402_6.3V6K
1 5 1 U15 K11
GND GND
CV34
CV44
RV239 U17 K2
GND GND
1
10_0603_5% U20 K22

4
RV59 @ U9 GND GND K6

3 1
2 PX@ 2 PX@ V13 GND GND
200K_0402_5% GND
PX@ V16
V18 GND
2
Y10 GND
RV61 5 DGPU_PWR_EN# Y15 GND
PX@ DGPU_PWR_EN#_GATE Y17 GND
QV22B Y20 GND
4
10K_0402_5% 2N7002EDW 2N SOT-363-6 R11 GND A32

1 GND VSS_MECH
6
CV35 PX@ T11 AM1

0.1U_0402_25V6 AA11 GND VSS_MECH AM32
PX@ M12 GND VSS_MECH
DGPU_PWR_EN# 2 2 N11 GND
V11 GND
GND
1
QV22A
2N7002EDW 2N SOT-363-6
PX@ 216-0864018 A0 MESO ?XT S3
C C
+3VS to +3VS_VGA (25mA)

+3VS QV16 PX@ +3VGS
ME2301DC-G_SOT23-3
3
S
1 4.7U_0603_6.3V6K 1U_0402_6.3V6K
D
1 1
CV36 CV37 @
G
RV40
PX@ @ 470_0603_5%
2 2
2
+5VALW
2
D
@ QV17 2
RV42 PX@ DGPU_PWR_EN# RV43 PX@ 2N7002K_SOT23-3 G
S
20K_0402_5% 10K_0402_5%
3
1
PX@
1
D D
CV38
RV264 D 0.1U_0402_25V6 DGPU_PWR_EN#
1 @ 2 DGPU_PWR_EN_3V3_MOS 2 QV18 PX@ 2
<8,25,43,46> DGPU_PWR_EN
G 2N7002K_SOT23-3
0_0402_5% S
3

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Meso XT_Power/GND
Size Document Number Rev
Date:
LA-C281Sheet 32 of 50
Friday, February 06, 2015
1 2 3 4 5
1 2 3 4 5
A
+VGA_CORE 10uF 2.2uF 1uF 0.1uF A
+PCIE_PVDD:
VDDC TBD +1.35VGS 50mA (PCIE2.0) +1.8VGS
UV1D PX@
7 16 4 3 U?
100mA (PCIE3.0)
AM30
VDDCI 3.5A MEM I/O PCIE_PVDD
PCIE
CV47
CV48
1A H13 AB23 1 1
H16 VDDR1 NC#AB23 AC23
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
H19 VDDR1 NC#AC23 AD24
CV75
CV74
CV82
CV85
CV88
CV80
CV83
CV84
CV87
CV77
CV78
CV76
CV79
CV81
CV89
CV86
1
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
220U_B2_2.5VM_R35
J10 VDDR1 NC#AD24 AE24
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10U_0603_6.3V6M
1U_0402_6.3V6K
+ J23 VDDR1 NC#AE24 AE25 2 2
+0.95VGS 10uF 1uF 0.1uF VDDR1 NC#AE25
PX@
PX@
@ J24 AE26
J9 VDDR1 NC#AE26 AF25
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VDDR1 NC#AF25
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
@
@
K10 AG26
K23 VDDR1 NC#AG26
PCIE_VDDC 1A 1 5(1@) 0 K24 VDDR1
K9 VDDR1 L23
L11 VDDR1 PCIE_VDDC L24
L12 VDDR1 PCIE_VDDC L25
BIF_VDDC 0.8A 0 1(1@) 0 L13 VDDR1 PCIE_VDDC L26
L20 VDDR1 PCIE_VDDC M22 +0.95VGS
L21 VDDR1 PCIE_VDDC N22 +PCIE_VDDC: 1A
L22 VDDR1 PCIE_VDDC N23
SPLL_VDDC 100mA 0 1 1 VDDR1 PCIE_VDDC N24
PCIE_VDDC R22
PCIE_VDDC T22
CV49
CV50
CV51
CV52
CV54
+1.8VGS 13mA LEVEL PCIE_VDDC U22 1 1 1 1 1
TRANSLATION PCIE_VDDC V22
AA20 PCIE_VDDC
+1.35VGS 10uF 1uF 0.1uF 0.01uF AA21 VDD_CT
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
AB20 VDD_CT AA15 2 2 2 2 2
CV55
B VDD_CT VDDC B
PX@
CORE
PX@
PX@
PX@
PX@
1 AB21 N15
VDD_CT VDDC N17
VDDR1 1.5A 5(3@) 5 5 0 +3VGS VDDC R13
25mA I/O VDDC R16
1U_0402_6.3V6K
2 AA17 VDDC R18
VDDR3 VDDC
PX@
AA18 Y21
AB17 VDDR3 VDDC T12
CV56
AB18 VDDR3 VDDC T15 +VGA_CORE
+1.8VGS 10uF 1uF 0.1uF 1 VDDR3 VDDC T17
V12 VDDC T20
Y12 VDDR4 VDDC U13
1U_0402_6.3V6K
2 U12 VDDR4 VDDC U16
PCIE_PVDD 100mA 1 1 0 VDDR4 VDDC
PX@
U18
VDDC V21 VGA_CORE Cap in power side sheet
VDDC V15
VDDC V17
MPLL_PVDD 130mA 2 1 0 VDDC V20
VDDC
POWER
Y13
VDDC Y16
VDDC Y18
SPLL_PVDD 75mA 0 1 0 VDDC AA12
VDDC M11
VDDC N12 21A (VDDC + VDDCI (Merged) - PRO S3 (DDR3))
VDDC U11
VDDR4 (300mA) 0 0 0 VDDC
+1.8VGS
90mA PLL
+0.95VGS
VDD_CT 13mA 0 1 0
R21 0.8A
CV39
CV40
CV41
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
BIF_VDDC U21
+TSVDD 13mA 0 1 0 1 1 1 BIF_VDDC
L8
CV62
+1.8VGS MPLL_PVDD
C
2 2 2 75mA +VGA_CORE
1 C
PX@
PX@
PX@
+DP_VDDR 1 1 0 ISOLATED
CORE I/O
M13
1U_0402_6.3V6K
H7 VDDCI M15 2
CV42
CV43
10U_0603_6.3V6M
1U_0402_6.3V6K
SPLL_PVDD VDDCI
@
M16
+DP_VDDC 0 1 1 1 1 VDDCI M17
+0.95VGS VDDCI M18
100mA VDDCI M20
2 2 VDDCI
PX@
PX@ H8 M21
SPLL_VDDC VDDCI N20
J7 VDDCI
+3VGS 10uF 1uF 0.1uF
0.1U_0201_10V6K
SPLL_PVSS
CV90
CV46
1U_0402_6.3V6K
1 1
VDDR3 25mA 0 1 0 216-0864018 A0 MESO XT S3? VGA_CORE Cap in power side sheet
2 2
PX@
PX@
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Meso XT_Power
Date:
LA-C281Sheet 33 of 50
Friday, February 06, 2015
1 2 3 4 5
1 2 3 4 5
PX@
UV1C U?
M_DA[63..0]
A <35,36> M_DA[63..0] GDDR5/DDR3 GDDR5/DDR3 A
M_MA[15..0] M_DA0 K27 K17 M_MA0
<35,36> M_MA[15..0] DQA0_0 MAA0_0/MAA_0
M_DA1 J29 J20 M_MA1
M_DQM[7..0] M_DA2 H30 DQA0_1 MAA0_1/MAA_1 H23 M_MA2
<35,36> M_DQM[7..0] DQA0_2 MAA0_2/MAA_2
M_DA3 H32 G23 M_MA3
M_DQS[7..0] M_DA4 G29 DQA0_3 MAA0_3/MAA_3 G24 M_MA4
<35,36> M_DQS[7..0] F28 DQA0_4 MAA0_4/MAA_4 H24
M_DA5 M_MA5
M_DQS#[7..0] M_DA6 F32 DQA0_5 MAA0_5/MAA_5 J19 M_MA6
<35,36> M_DQS#[7..0] F30 DQA0_6 MAA0_6/MAA_6 K19
M_DA7 M_MA7
M_DA8 C30 DQA0_7 MAA0_7/MAA_7 G20 M_MA13
M_DA9 F27 DQA0_8 MAA0_8/MAA_13 L17 M_MA15
M_DA10 A28 DQA0_9 MAA0_9/MAA_15
M_DA11 C28 DQA0_10 J14 M_MA8
M_DA12 E27 DQA0_11 MAA1_0/MAA_8 K14 M_MA9
M_DA13 G26 DQA0_12 MAA1_1/MAA_9 J11 M_MA10
M_DA14 D26 DQA0_13 MAA1_2/MAA_10 J13 M_MA11
M_DA15 F25 DQA0_14 MAA1_3/MAA_11 H11 M_MA12
M_DA16 A25 DQA0_15 MAA1_4/MAA_12 G11 M_BA2
C25 DQA0_16 MAA1_5/MAA_BA2 J16 M_BA2 <35,36>
M_DA17 M_BA0
DQA0_17 MAA1_6/MAA_BA0 M_BA0 <35,36>
M_DA18 E25 L15 M_BA1 +1.35VGS
DQA0_18 MAA1_7/MAA_BA1 M_BA1 <35,36>
M_DA19 D24 G14 M_MA14
M_DA20 E23 DQA0_19 MAA1_8/MAA_14 L16
MEMORY INTERFACE
M_DA21 F23 DQA0_20 MAA1_9/RSVD RV136 1 PX@ 2 100_0402_1% M_MA0 100_0402_1% 1 PX@ 2 RV137
M_DA22 D22 DQA0_21 E32 M_DQM0 RV138 1 PX@ 2 100_0402_1% M_MA1 100_0402_1% 1 PX@ 2 RV139
+1.35VGS M_DA23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 M_DQM1 RV140 1 PX@ 2 100_0402_1% M_MA2 100_0402_1% 1 PX@ 2 RV141
M_DA24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 M_DQM2 RV142 1 PX@ 2 100_0402_1% M_MA3 100_0402_1% 1 PX@ 2 RV143
M_DA25 D20 DQA0_24 WCKA0_1/DQMA0_2 C21 M_DQM3 RV144 1 PX@ 2 100_0402_1% M_MA4 100_0402_1% 1 PX@ 2 RV145
M_DA26 F19 DQA0_25 WCKA0B_1/DQMA0_3 E13 M_DQM4 RV146 1 PX@ 2 100_0402_1% M_MA5 100_0402_1% 1 PX@ 2 RV147
1
M_DA27 A19 DQA0_26 WCKA1_0/DQMA1_0 D12 M_DQM5 RV148 1 PX@ 2 100_0402_1% M_MA6 100_0402_1% 1 PX@ 2 RV149
PX@ M_DA28 D18 DQA0_27 WCKA1B_0/DQMA1_1 E3 M_DQM6 RV150 1 PX@ 2 100_0402_1% M_MA7 100_0402_1% 1 PX@ 2 RV151
RV44 M_DA29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 M_DQM7 RV152 1 PX@ 2 100_0402_1% M_MA8 100_0402_1% 1 PX@ 2 RV153
40.2_0402_1% M_DA30 A17 DQA0_29 WCKA1B_1/DQMA1_3 RV154 1 PX@ 2 100_0402_1% M_MA9 100_0402_1% 1 PX@ 2 RV155
M_DA31 C17 DQA0_30 H28 M_DQS0 RV156 1 PX@ 2 100_0402_1% M_MA10 100_0402_1% 1 PX@ 2 RV157
2
M_DA32 E17 DQA0_31 EDCA0_0/QSA0_0 C27 M_DQS1 RV158 1 PX@ 2 100_0402_1% M_MA11 100_0402_1% 1 PX@ 2 RV159
M_DA33 D16 DQA1_0 EDCA0_1/QSA0_1 A23 M_DQS2 RV160 1 PX@ 2 100_0402_1% M_MA12 100_0402_1% 1 PX@ 2 RV161
M_DA34 F15 DQA1_1 EDCA0_2/QSA0_2 E19 M_DQS3 RV162 1 PX@ 2 100_0402_1% M_MA13 100_0402_1% 1 PX@ 2 RV163
M_DA35 A15 DQA1_2 EDCA0_3/QSA0_3 E15 M_DQS4 RV164 1 PX@ 2 100_0402_1% M_MA14 100_0402_1% 1 PX@ 2 RV165
DQA1_3 EDCA1_0/QSA1_0
1
B 1 M_DA36 D14 D10 M_DQS5 RV166 1 PX@ 2 100_0402_1% M_MA15 100_0402_1% 1 PX@ 2 RV167 B
PX@ PX@ M_DA37 F13 DQA1_4 EDCA1_1/QSA1_1 D6 M_DQS6
RV46 CV65 M_DA38 A13 DQA1_5 EDCA1_2/QSA1_2 G5 M_DQS7
100_0402_1% 1U_0402_6.3V6K M_DA39 C13 DQA1_6 EDCA1_3/QSA1_3 RV168 1 PX@ 2 100_0402_1% M_BA0 100_0402_1% 1 PX@ 2 RV169
2 M_DA40 E11 DQA1_7 H27 M_DQS#0 RV170 1 PX@ 2 100_0402_1% M_BA1 100_0402_1% 1 PX@ 2 RV171
2
M_DA41 A11 DQA1_8 DDBIA0_0/QSA0_0B A27 M_DQS#1 RV172 1 PX@ 2 100_0402_1% M_BA2 100_0402_1% 1 PX@ 2 RV173
M_DA42 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 M_DQS#2
M_DA43 F11 DQA1_10 DDBIA0_2/QSA0_2B C19 M_DQS#3
M_DA44 A9 DQA1_11 DDBIA0_3/QSA0_3B C15 M_DQS#4 RV174 1 PX@ 2 100_0201_1% VRAM_ODT0100_0201_1% 1 PX@ 2 RV175
M_DA45 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 M_DQS#5 RV176 1 PX@ 2 100_0201_1% VRAM_ODT1100_0201_1% 1 PX@ 2 RV177
M_DA46 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 M_DQS#6
M_DA47 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 M_DQS#7
+1.35VGS M_DA48 E7 DQA1_15 DDBIA1_3/QSA1_3B RV178 1 PX@ 2 100_0201_1% M_RAS#0 100_0201_1% 1 PX@ 2 RV179
M_DA49 A7 DQA1_16 L18 VRAM_ODT0 RV180 1 PX@ 2 100_0201_1% M_RAS#1 100_0201_1% 1 PX@ 2 RV181
C7 DQA1_17 ADBIA0/ODTA0 K16 VRAM_ODT0 <35,36>
M_DA50 VRAM_ODT1
DQA1_18 ADBIA1/ODTA1 VRAM_ODT1 <35,36>
M_DA51 F7
1
M_DA52 A5 DQA1_19 H26 M_CLK0 RV182 1 PX@ 2 100_0201_1% M_CAS#0 100_0201_1% 1 PX@ 2 RV183
DQA1_20 CLKA0 M_CLK0 <35,36>
PX@ M_DA53 E5 H25 M_CLK#0 RV184 1 PX@ 2 100_0201_1% M_CAS#1 100_0201_1% 1 PX@ 2 RV185
DQA1_21 CLKA0B M_CLK#0 <35,36>
RV45 M_DA54 C3
40.2_0402_1% M_DA55 E1 DQA1_22 G9 M_CLK1
DQA1_23 CLKA1 M_CLK1 <35,36>
M_DA56 G7 H9 M_CLK#1 RV186 1 PX@ 2 100_0201_1% M_CS0B#0 100_0201_1% 1 PX@ 2 RV187
2
DQA1_24 CLKA1B M_CLK#1 <35,36> 1

M_DA57 G6 RV190 1 PX@ 2 100_0201_1% M_CS1B#0 100_0201_1% PX@ 2 RV191
M_DA58 G1 DQA1_25 G22 M_RAS#0
DQA1_26 RASA0B M_RAS#0 <35,36>
M_DA59 G3 G17 M_RAS#1
DQA1_27 RASA1B M_RAS#1 <35,36> 1
M_DA60 J6 RV188 1 PX@ 2 100_0201_1% M_CS0B#1 100_0201_1% PX@ 2 RV189
DQA1_28
1
1 M_DA61 J1 G19 M_CAS#0 RV192 1 PX@ 2 100_0201_1% M_CS1B#1 100_0201_1% 1 PX@ 2 RV193
J3 DQA1_29 CASA0B G16 M_CAS#0 <35,36>
PX@ PX@ M_DA62 M_CAS#1
DQA1_30 CASA1B M_CAS#1 <35,36>
RV47 CV66 M_DA63 J5
100_0402_1% 1U_0402_6.3V6K DQA1_31 H22 M_CS0B#0 RV194 1 PX@ 2 100_0201_1% M_CKE0 100_0201_1% 1 PX@ 2 RV195
2 CSA0B_0 M_CS0B#0 <35> 1
+MVREFDA K26 J22 M_CS0B#1 RV196 PX@ 2 100_0201_1% M_CKE1 100_0201_1% 1 PX@ 2 RV197
M_CS0B#1 <36>
2
+MVREFSA J26 MVREFDA CSA0B_1

MVREFSA G13 M_CS1B#0
CSA1B_0 M_CS1B#0 <35>
J25 K13 M_CS1B#1 RV198 1 PX@ 2 100_0201_1% M_WE#0 100_0201_1% 1 PX@ 2 RV199
NC#J25 CSA1B_1 M_CS1B#1 <36>
RV52 1 PX@ 2 120_0402_1% K25 RV200 1 PX@ 2 100_0201_1% M_WE#1 100_0201_1% 1 PX@ 2 RV201
MEM_CALRP0 K20 M_CKE0
CKEA0 M_CKE0 <35,36>
PX@ PX@ J17 M_CKE1
CKEA1 M_CKE1 <35,36>
RV48 RV49
49.9_0402_1% 10_0402_1% G25 M_WE#0
C
1 2 2 1 WEA0B M_WE#0 <35,36> C
DRST L10 H10 M_WE#1
<35,36> DRAM_RST DRAM_RST WEA1B M_WE#1 <35,36>
1 RV54 @ 1 2 51.1_0402_1% CV69 @ 1 2 0.1U_0201_10V6K K8
1
@ RV55 @ 1 2 51.1_0402_1% CV70 @ 1 2 0.1U_0201_10V6K L7 CLKTESTA

1 CLKTESTB
PX@ PX@ CV67
CV68 RV50 68P_0402_50V8J
120P_0402_50V8J 5.1K_0402_1% 2 Route 50ohms single-ended/100ohm diff and keep short
216-0864018 A0 MESO XT S3
2 debug only, for clock observation,if not need, DNI. ?
2
Place close to GPU (within 25mm)

and place componment close to each other
D D

Title
Size
Meso
Document Number
XT_MEM Rev
Date:
LA-C281
1 2 3 4 5
1 2 3 4 5
M_DA[63..0] UV3 UV4 UV5 UV6

<34,36> M_DA[63..0]
M_MA[15..0] VREFCA_UV3 M8 E3 M_DA19 VREFCA_UV4 M8 E3 M_DA14 VREFCA_UV5 M8 E3 M_DA41 VREFCA_UV6 M8 E3 M_DA58
<34,36> M_MA[15..0] VREFDQ_UV3 H1 VREFCA DQL0 F7 M_DA21 VREFDQ_UV4 H1 VREFCA DQL0 F7 M_DA9 VREFDQ_UV5 H1 VREFCA DQL0 F7 M_DA46 VREFDQ_UV6 H1 VREFCA DQL0 F7 M_DA63
M_DQM[7..0] VREFDQ DQL1 F2 M_DA18 VREFDQ DQL1 F2 M_DA15 VREFDQ DQL1 F2 M_DA43 VREFDQ DQL1 F2 M_DA59
<34,36> M_DQM[7..0] M_MA0 N3 DQL2 F8 M_DA22 M_MA0 N3 DQL2 F8 M_DA10 M_MA0 N3 DQL2 F8 M_DA44 M_MA0 N3 DQL2 F8 M_DA61
M_DQS[7..0] M_MA1 P7 A0 DQL3 H3 M_DA17 M_MA1 P7 A0 DQL3 H3 M_DA12 M_MA1 P7 A0 DQL3 H3 M_DA40 M_MA1 P7 A0 DQL3 H3 M_DA57
<34,36> M_DQS[7..0] M_MA2 P3 A1 DQL4 H8 M_DA23 M_MA2 P3 A1 DQL4 H8 M_DA11 M_MA2 P3 A1 DQL4 H8 M_DA45 M_MA2 P3 A1 DQL4 H8 M_DA62
M_DQS#[7..0] M_MA3 N2 A2 DQL5 G2 M_DA16 M_MA3 N2 A2 DQL5 G2 M_DA13 M_MA3 N2 A2 DQL5 G2 M_DA42 M_MA3 N2 A2 DQL5 G2 M_DA56
<34,36> M_DQS#[7..0] M_MA4 P8 A3 DQL6 H7 M_DA20 M_MA4 P8 A3 DQL6 H7 M_DA8 M_MA4 P8 A3 DQL6 H7 M_DA47 M_MA4 P8 A3 DQL6 H7 M_DA60
M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7
M_MA6 R8 A5 M_MA6 R8 A5 M_MA6 R8 A5 M_MA6 R8 A5
M_MA7 R2 A6 D7 M_DA4 M_MA7 R2 A6 D7 M_DA26 M_MA7 R2 A6 D7 M_DA39 M_MA7 R2 A6 D7 M_DA55
M_MA8 T8 A7 DQU0 C3 M_DA2 M_MA8 T8 A7 DQU0 C3 M_DA28 M_MA8 T8 A7 DQU0 C3 M_DA35 M_MA8 T8 A7 DQU0 C3 M_DA52
A M_MA9 R3 A8 DQU1 C8 M_DA7 M_MA9 R3 A8 DQU1 C8 M_DA27 M_MA9 R3 A8 DQU1 C8 M_DA38 M_MA9 R3 A8 DQU1 C8 M_DA51 A
M_MA10 L7 A9 DQU2 C2 M_DA0 M_MA10 L7 A9 DQU2 C2 M_DA31 M_MA10 L7 A9 DQU2 C2 M_DA32 M_MA10 L7 A9 DQU2 C2 M_DA50
M_MA11 R7 A10/AP DQU3 A7 M_DA5 M_MA11 R7 A10/AP DQU3 A7 M_DA25 M_MA11 R7 A10/AP DQU3 A7 M_DA37 M_MA11 R7 A10/AP DQU3 A7 M_DA53
M_MA12 N7 A11 DQU4 A2 M_DA1 M_MA12 N7 A11 DQU4 A2 M_DA29 M_MA12 N7 A11 DQU4 A2 M_DA33 M_MA12 N7 A11 DQU4 A2 M_DA49
M_MA13 T3 A12 DQU5 B8 M_DA6 M_MA13 T3 A12 DQU5 B8 M_DA24 M_MA13 T3 A12 DQU5 B8 M_DA36 M_MA13 T3 A12 DQU5 B8 M_DA54
M_MA14 T7 A13 DQU6 A3 M_DA3 M_MA14 T7 A13 DQU6 A3 M_DA30 M_MA14 T7 A13 DQU6 A3 M_DA34 M_MA14 T7 A13 DQU6 A3 M_DA48
M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7
A15/BA3 +1.35VGS A15/BA3 +1.35VGS A15/BA3 +1.35VGS A15/BA3 +1.35VGS
M_BA0 M2 B2 M_BA0 M2 B2 M_BA0 M2 B2 M_BA0 M2 B2

<34,36> M_BA0 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9
<34,36> M_BA1 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7
<34,36> M_BA2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
M_CLK0 J7 VDD N9 M_CLK0 J7 VDD N9 M_CLK1 J7 VDD N9 M_CLK1 J7 VDD N9
<34,36> M_CLK0 M_CLK#0 K7 CK VDD R1 M_CLK#0 K7 CK VDD R1 <34,36> M_CLK1 M_CLK#1 K7 CK VDD R1 M_CLK#1 K7 CK VDD R1
<34,36> M_CLK#0 M_CKE0 K9 CK VDD R9 M_CKE0 K9 CK VDD R9 <34,36> M_CLK#1 M_CKE1 K9 CK VDD R9 M_CKE1 K9 CK VDD R9
<34,36> M_CKE0 CKE/CKE0 VDD +1.35VGS CKE/CKE0 VDD +1.35VGS <34,36> M_CKE1 CKE/CKE0 VDD +1.35VGS CKE/CKE0 VDD +1.35VGS
VRAM_ODT0 K1 A1 VRAM_ODT0 K1 A1 VRAM_ODT1 K1 A1 VRAM_ODT1 K1 A1

<34,36> VRAM_ODT0 M_CS0B#0 L2 ODT/ODT0 VDDQ A8 M_CS0B#0 L2 ODT/ODT0 VDDQ A8 <34,36> VRAM_ODT1 M_CS1B#0 L2 ODT/ODT0 VDDQ A8 M_CS1B#0 L2 ODT/ODT0 VDDQ A8
<34> M_CS0B#0 M_RAS#0 J3 CS/CS0 VDDQ C1 M_RAS#0 J3 CS/CS0 VDDQ C1 <34> M_CS1B#0 M_RAS#1 J3 CS/CS0 VDDQ C1 M_RAS#1 J3 CS/CS0 VDDQ C1
<34,36> M_RAS#0 M_CAS#0 K3 RAS VDDQ C9 M_CAS#0 K3 RAS VDDQ C9 <34,36> M_RAS#1 M_CAS#1 K3 RAS VDDQ C9 M_CAS#1 K3 RAS VDDQ C9
<34,36> M_CAS#0 M_WE#0 L3 CAS VDDQ D2 M_WE#0 L3 CAS VDDQ D2 <34,36> M_CAS#1 M_WE#1 L3 CAS VDDQ D2 M_WE#1 L3 CAS VDDQ D2
<34,36> M_WE#0 WE VDDQ E9 WE VDDQ E9 <34,36> M_WE#1 WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
M_DQS2 F3 VDDQ H2 M_DQS1 F3 VDDQ H2 M_DQS5 F3 VDDQ H2 M_DQS7 F3 VDDQ H2
M_DQS0 C7 DQSL VDDQ H9 M_DQS3 C7 DQSL VDDQ H9 M_DQS4 C7 DQSL VDDQ H9 M_DQS6 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
M_DQM2 E7 A9 M_DQM1 E7 A9 M_DQM5 E7 A9 M_DQM7 E7 A9

M_DQM0 D3 DML VSS B3 M_DQM3 D3 DML VSS B3 M_DQM4 D3 DML VSS B3 M_DQM6 D3 DML VSS B3
DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
B
M_DQS#2 G3 VSS J2 M_DQS#1 G3 VSS J2 M_DQS#5 G3 VSS J2 M_DQS#7 G3 VSS J2 B
M_DQS#0 B7 DQSL VSS J8 M_DQS#3 B7 DQSL VSS J8 M_DQS#4 B7 DQSL VSS J8 M_DQS#6 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 VSS P9 DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9
<34,36> DRAM_RST RESET VSS T1 RESET VSS T1 RESET VSS T1 RESET VSS T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
1
1
J1 B1 J1 B1 J1 B1 J1 B1
L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9 PX@ L1 NC/ODT1 VSSQ B9 PX@ L1 NC/ODT1 VSSQ B9
PX@ PX@
J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1 RV69 J9 NC/CS1 VSSQ D1 RV70 J9 NC/CS1 VSSQ D1
RV67 RV68
L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8
243_0402_1% 243_0402_1%
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2
2
2
2
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
M_CLK0 RV71 1 2 PX@ VSSQ VSSQ VSSQ VSSQ
80.6_0402_1% 96-BALL 96-BALL M_CLK1 RV75 1 2 PX@ 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 80.6_0402_1% SDRAM DDR3 SDRAM DDR3
M_CLK#0RV72 1 2 PX@ H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96
80.6_0402_1% X76@ X76@ M_CLK#1RV76 1 2 PX@ X76@ X76@
1 80.6_0402_1%
CV143 1
.01U_0402_16V7-K CV166
PX@ .01U_0402_16V7-K
2 PX@
2
C +1.35VGS C
+1.35VGS +1.35VGS +1.35VGS +1.35VGS +1.35VGS
CV133
CV137
CV129
CV130
CV126
CV128
CV134
CV135
CV136
CV127
CV131
CV132
CV138
1
1
1
1
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0603_6.3V6M
CV140
10U_0603_6.3V6M
CV141
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0603_6.3V6M
CV180
10U_0603_6.3V6M
CV142
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
RV73 RV74 RV210 RV212
+EC_VCCA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
PX@ PX@ PX@ PX@
2
2
2
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
@
@
PX@
PX@
@
PX@
PX@
@
@
16.5K_0402_1%
1
VREFCA_UV3 VREFCA_UV4 VREFCA_UV5 VREFCA_UV6
R1649
1
1 1 1 1
RV77 CV144 RV78 CV145 RV211 CV224 RV213 CV225
4.99K_0402_1% 0.1U_0201_10V6K 4.99K_0402_1% 0.1U_0201_10V6K 4.99K_0402_1% 0.1U_0201_10V6K 4.99K_0402_1% 0.1U_0201_10V6K
2
PX@ PX@ PX@ PX@
2 PX@ 2 PX@ 2 PX@ 2 PX@ <25> VRAM_TEMP +1.35VGS
2
1U_0402_6.3V6K
CV157
1U_0402_6.3V6K
CV164
1U_0402_6.3V6K
CV146
1U_0402_6.3V6K
CV147
1U_0402_6.3V6K
CV161
1U_0402_6.3V6K
CV151
1U_0402_6.3V6K
CV155
1U_0402_6.3V6K
CV162
1U_0402_6.3V6K
CV148
1U_0402_6.3V6K
CV152
1U_0402_6.3V6K
CV154
1U_0402_6.3V6K
CV149
1U_0402_6.3V6K
CV150
10U_0603_6.3V6M
CV156
1U_0402_6.3V6K
CV160
1U_0402_6.3V6K
CV165
1U_0402_6.3V6K
CV153
1U_0402_6.3V6K
CV158
1U_0402_6.3V6K
CV159
1U_0402_6.3V6K
CV163
RH203
100K_0402_1%_TSM0B104F4251RZ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
+1.35VGS +1.35VGS +1.35VGS +1.35VGS
1
1
1
1
RV214 RV217 RV219 RV221

4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
PX@ PX@ PX@ PX@ ECAGND
D D
2
2
2
2
VREFDQ_UV3 VREFDQ_UV4 VREFDQ_UV5 VREFDQ_UV6

1
1
1
1 1 1 1
PX@ PX@ PX@ PX@
2 PX@ 2 PX@ 2 PX@ 2 PX@
2
2
2
Title
Size Document Number
Meso XT_VRAM A Lower Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
Date:
LA-C281
1 2 3 4 5
1 2 3 4 5
M_DA[63..0]
<34,35> M_DA[63..0]
M_MA[15..0]
<34,35> M_MA[15..0]
M_DQM[7..0] UV7 UV8 UV9 UV10
<34,35> M_DQM[7..0]
M_DQS[7..0] VREFCA_UV7 M8 E3 M_DA21 VREFCA_UV8 M8 E3 M_DA9 VREFCA_UV9 M8 E3 M_DA44 VREFCA_UV10 M8 E3 M_DA63
<34,35> M_DQS[7..0] VREFDQ_UV7 H1 VREFCA DQL0 F7 M_DA19 VREFDQ_UV8 H1 VREFCA DQL0 F7 M_DA14 VREFDQ_UV9 H1 VREFCA DQL0 F7 M_DA41 VREFDQ_UV10 H1 VREFCA DQL0 F7 M_DA58
M_DQS#[7..0] VREFDQ DQL1 F2 M_DA22 VREFDQ DQL1 F2 M_DA10 VREFDQ DQL1 F2 M_DA45 VREFDQ DQL1 F2 M_DA61
<34,35> M_DQS#[7..0] M_MA0 N3 DQL2 F8 M_DA18 M_MA0 N3 DQL2 F8 M_DA15 M_MA0 N3 DQL2 F8 M_DA43 M_MA0 N3 DQL2 F8 M_DA59
M_MA1 P7 A0 DQL3 H3 M_DA20 M_MA1 P7 A0 DQL3 H3 M_DA11 M_MA1 P7 A0 DQL3 H3 M_DA47 M_MA1 P7 A0 DQL3 H3 M_DA60
M_MA3 N2 A2 DQL5 G2 M_DA23 M_MA3 N2 A2 DQL5 G2 M_DA8 M_MA3 N2 A2 DQL5 G2 M_DA46 M_MA3 N2 A2 DQL5 G2 M_DA62
A M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7 A
M_MA6 R8 A5 M_MA6 R8 A5 M_MA6 R8 A5 M_MA6 R8 A5
M_MA7 R2 A6 D7 M_DA2 M_MA7 R2 A6 D7 M_DA28 M_MA7 R2 A6 D7 M_DA35 M_MA7 R2 A6 D7 M_DA52
M_MA8 T8 A7 DQU0 C3 M_DA4 M_MA8 T8 A7 DQU0 C3 M_DA26 M_MA8 T8 A7 DQU0 C3 M_DA37 M_MA8 T8 A7 DQU0 C3 M_DA55
M_MA9 R3 A8 DQU1 C8 M_DA0 M_MA9 R3 A8 DQU1 C8 M_DA31 M_MA9 R3 A8 DQU1 C8 M_DA32 M_MA9 R3 A8 DQU1 C8 M_DA50
M_MA10 L7 A9 DQU2 C2 M_DA7 M_MA10 L7 A9 DQU2 C2 M_DA27 M_MA10 L7 A9 DQU2 C2 M_DA39 M_MA10 L7 A9 DQU2 C2 M_DA51
M_MA11 R7 A10/AP DQU3 A7 M_DA3 M_MA11 R7 A10/AP DQU3 A7 M_DA30 M_MA11 R7 A10/AP DQU3 A7 M_DA34 M_MA11 R7 A10/AP DQU3 A7 M_DA48
M_MA12 N7 A11 DQU4 A2 M_DA6 M_MA12 N7 A11 DQU4 A2 M_DA24 M_MA12 N7 A11 DQU4 A2 M_DA38 M_MA12 N7 A11 DQU4 A2 M_DA54
M_MA13 T3 A12 DQU5 B8 M_DA1 M_MA13 T3 A12 DQU5 B8 M_DA29 M_MA13 T3 A12 DQU5 B8 M_DA33 M_MA13 T3 A12 DQU5 B8 M_DA49
M_MA14 T7 A13 DQU6 A3 M_DA5 M_MA14 T7 A13 DQU6 A3 M_DA25 M_MA14 T7 A13 DQU6 A3 M_DA36 M_MA14 T7 A13 DQU6 A3 M_DA53
M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7
A15/BA3 +1.35VGS A15/BA3 +1.35VGS A15/BA3 +1.35VGS A15/BA3 +1.35VGS
M_BA0 M2 B2 M_BA0 M2 B2 M_BA0 M2 B2 M_BA0 M2 B2

<34,35> M_BA0 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9
<34,35> M_BA1 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7
<34,35> M_BA2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
M_CLK0 J7 VDD N9 M_CLK0 J7 VDD N9 M_CLK1 J7 VDD N9 M_CLK1 J7 VDD N9
<34,35> M_CLK0 M_CLK#0 K7 CK VDD R1 M_CLK#0 K7 CK VDD R1 <34,35> M_CLK1 M_CLK#1 K7 CK VDD R1 M_CLK#1 K7 CK VDD R1
<34,35> M_CLK#0 M_CKE0 K9 CK VDD R9 M_CKE0 K9 CK VDD R9 <34,35> M_CLK#1 M_CKE1 K9 CK VDD R9 M_CKE1 K9 CK VDD R9
<34,35> M_CKE0 CKE/CKE0 VDD +1.35VGS CKE/CKE0 VDD +1.35VGS <34,35> M_CKE1 CKE/CKE0 VDD +1.35VGS CKE/CKE0 VDD +1.35VGS
VRAM_ODT0 K1 A1 VRAM_ODT0 K1 A1 VRAM_ODT1 K1 A1 VRAM_ODT1 K1 A1

<34,35> VRAM_ODT0 M_CS0B#1 L2 ODT/ODT0 VDDQ A8 M_CS0B#1 L2 ODT/ODT0 VDDQ A8 <34,35> VRAM_ODT1 M_CS1B#1 L2 ODT/ODT0 VDDQ A8 M_CS1B#1 L2 ODT/ODT0 VDDQ A8
<34> M_CS0B#1 M_RAS#0 J3 CS/CS0 VDDQ C1 M_RAS#0 J3 CS/CS0 VDDQ C1 <34> M_CS1B#1 M_RAS#1 J3 CS/CS0 VDDQ C1 M_RAS#1 J3 CS/CS0 VDDQ C1
<34,35> M_RAS#0 M_CAS#0 K3 RAS VDDQ C9 M_CAS#0 K3 RAS VDDQ C9 <34,35> M_RAS#1 M_CAS#1 K3 RAS VDDQ C9 M_CAS#1 K3 RAS VDDQ C9
<34,35> M_CAS#0 M_WE#0 L3 CAS VDDQ D2 M_WE#0 L3 CAS VDDQ D2 <34,35> M_CAS#1 M_WE#1 L3 CAS VDDQ D2 M_WE#1 L3 CAS VDDQ D2
<34,35> M_WE#0 WE VDDQ E9 WE VDDQ E9 <34,35> M_WE#1 WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
M_DQS2 F3 VDDQ H2 M_DQS1 F3 VDDQ H2 M_DQS5 F3 VDDQ H2 M_DQS7 F3 VDDQ H2
M_DQS0 C7 DQSL VDDQ H9 M_DQS3 C7 DQSL VDDQ H9 M_DQS4 C7 DQSL VDDQ H9 M_DQS6 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
B B
M_DQM2 E7 A9 M_DQM1 E7 A9 M_DQM5 E7 A9 M_DQM7 E7 A9
M_DQM0 D3 DML VSS B3 M_DQM3 D3 DML VSS B3 M_DQM4 D3 DML VSS B3 M_DQM6 D3 DML VSS B3
DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
M_DQS#2 G3 VSS J2 M_DQS#1 G3 VSS J2 M_DQS#5 G3 VSS J2 M_DQS#7 G3 VSS J2
M_DQS#0 B7 DQSL VSS J8 M_DQS#3 B7 DQSL VSS J8 M_DQS#4 B7 DQSL VSS J8 M_DQS#6 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 VSS P9 DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9
<34,35> DRAM_RST RESET VSS T1 RESET VSS T1 RESET VSS T1 RESET VSS T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
1
J1 B1 J1 B1 J1 B1 J1 B1
4GVRAM@ L1 NC/ODT1 VSSQ B9 4GVRAM@ L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9 4GVRAM@ L1 NC/ODT1 VSSQ B9
4GVRAM@
RV79 J9 NC/CS1 VSSQ D1 RV80 J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1 RV82 J9 NC/CS1 VSSQ D1
RV81
243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8
243_0402_1%
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2
2
2
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
M_CLK0 RV83 1 2 PX@ VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 M_CLK1 RV87 1 2 PX@ VSSQ G1 VSSQ G1
80.6_0402_1%
VSSQ G9 VSSQ G9 80.6_0402_1% VSSQ G9 VSSQ G9
M_CLK#0RV84 1 2 PX@ VSSQ VSSQ VSSQ VSSQ
80.6_0402_1% 96-BALL 96-BALL M_CLK#1RV90 1 2 PX@ 96-BALL 96-BALL
1 SDRAM DDR3 SDRAM DDR3 80.6_0402_1% SDRAM DDR3 SDRAM DDR3
CV183 H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96 1 H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96
.01U_0402_16V7-K @ @ CV187 @ @
PX@ .01U_0402_16V7-K
2 PX@
2
C C
+1.35VGS +1.35VGS +1.35VGS +1.35VGS

1
1
RV85 RV86 RV223 RV225

4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% +1.35VGS
4GVRAM@ 4GVRAM@ 4GVRAM@ 4GVRAM@
+1.35VGS
2
2
CV172
CV174
CV168
CV171
CV173
CV175
CV176
CV177
CV179
CV167
CV169
CV170
CV178
VREFCA_UV7 VREFCA_UV8 VREFCA_UV9 VREFCA_UV10
1
1
1
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0603_6.3V6M
CV139
10U_0603_6.3V6M
CV181
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0603_6.3V6M
CV182
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0603_6.3V6M
CV184
1 1 1 1
RV88 CV185 RV89 CV186 RV222 CV230 RV224 CV231 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 4GVRAM@ 2 4GVRAM@ 2 4GVRAM@ 2 4GVRAM@
2
2
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
4GVRAM@
4GVRAM@
@
4GVRAM@
@
@
@
@
4GVRAM@
+1.35VGS +1.35VGS +1.35VGS +1.35VGS +1.35VGS
1
1
1U_0402_6.3V6K
CV189
1U_0402_6.3V6K
CV203
1U_0402_6.3V6K
CV207
1U_0402_6.3V6K
CV188
1U_0402_6.3V6K
CV192
1U_0402_6.3V6K
CV193
1U_0402_6.3V6K
CV194
1U_0402_6.3V6K
CV196
1U_0402_6.3V6K
CV197
1U_0402_6.3V6K
CV200
1U_0402_6.3V6K
CV205
1U_0402_6.3V6K
CV191
10U_0603_6.3V6M
CV198
1U_0402_6.3V6K
CV201
1U_0402_6.3V6K
CV202
1U_0402_6.3V6K
CV190
1U_0402_6.3V6K
CV195
1U_0402_6.3V6K
CV199
1U_0402_6.3V6K
CV204
1U_0402_6.3V6K
CV206
RV233 RV227 RV229 RV231 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
2
2
D 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 D
4GVRAM@
4GVRAM@
4GVRAM@
4GVRAM@
4GVRAM@
4GVRAM@
4GVRAM@
4GVRAM@
4GVRAM@
4GVRAM@
4GVRAM@
4GVRAM@
4GVRAM@
4GVRAM@
4GVRAM@
4GVRAM@
4GVRAM@
4GVRAM@
4GVRAM@
4GVRAM@
VREFDQ_UV7 VREFDQ_UV8 VREFDQ_UV9 VREFDQ_UV10
1
1
1
1 1 1 1
2 4GVRAM@ 2 4GVRAM@ 2 4GVRAM@ 2 4GVRAM@
2
2
2

Title
Size Document Number
Meso XT_VRAM A Upper Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
Date:
LA-C281
1 2 3 4 5
5 4 3 2 1
Meso XT_VRAM_STRAP
X76@
X76@
Vendor R_pu R_pd
UV3, UV4, UV5, UV6, UV7, UV8, UV9, UV10
ID PS_3[ 3 ] PS_3[ 2 ] PS_3[ 1 ]
RV21 RV24
Hynix 2G
2GBytes 4GBytes
HYN2@ SA00006E830
2GBytes 256Mx16 H5TC4G63AFR-11C 0 0 0 0 NC 4.75K
Micron 2G ZZZ2 ZZZ3
MIC2@ SA000077K10
D 2GBytes 256Mx16 MT41J256M16HA-093G:E 1 0 0 1 8.45K 2K D
Samsung 2G
SAM2@ SA000076P10 V2G@ V4G@
2GBytes 256Mx16 K4W4G1646D-BC1A 2 0 1 0 4.53K 2K 2G VRAM 4G VRAM
X7660638L07 X7660638L10
3 0 1 1 6.98K 4.99K
Hynix 4G
HYN4@
4GBytes
SA00006E830
256Mx16 H5TC4G63AFR-11C 4 1 0 0 4.53K 4.99K HYNIX 2G RV24
HYNIX 4G RV21 RV24
Micron 4G
MIC4@ SA000077K10
4GBytes 256Mx16 MT41J256M16HA-093G:E 5 1 0 1 3.24K 5.62K HYN2@ HYN4@ HYN4@
4.75K_0402_1% 4.53K_0402_1% 4.99K_0402_1%
Samsung 4G SD034475180 SD034453180 SD034499180
SAM4@ SA000076P10 UV3 UV4 UV5 UV6 UV3 UV4 UV5 UV6
4GBytes 256Mx16 K4W4G1646D-BC1A 6 1 1 0 3.4K 10K
7 1 1 1 4.75K NC HYN2@ HYN2@ HYN2@ HYN2@ HYN4@ HYN4@ HYN4@ HYN4@

H5TC4G63AFR-11C H5TC4G63AFR-11C H5TC4G63AFR-11C H5TC4G63AFR-11C H5TC4G63AFR-11C H5TC4G63AFR-11C H5TC4G63AFR-11C H5TC4G63AFR-11C
SA00006E830 SA00006E830 SA00006E830 SA00006E830 SA00006E830 SA00006E830 SA00006E830 SA00006E830
UV7 UV8 UV9 UV10
C C
HYN4@ HYN4@ HYN4@ HYN4@

H5TC4G63AFR-11C H5TC4G63AFR-11C H5TC4G63AFR-11C H5TC4G63AFR-11C
SA00006E830 SA00006E830 SA00006E830 SA00006E830
Micron 2G RV21 RV24

Micron 4G RV21 RV24
MIC2@ MIC2@ MIC4@ MIC4@

8.45K_0402_1% 2K_0402_1% 3.24K_0402_1% 5.62K_0402_1%
SD000000680 SD034200180 SD034324180 SD034562180
UV3 UV4 UV5 UV6 UV3 UV4 UV5 UV6
MIC2@ MIC2@ MIC2@ MIC2@ MIC4@ MIC4@ MIC4@ MIC4@

MT41J256M16HA-093G:EMT41J256M16HA-093G:EMT41J256M16HA-093G:EMT41J256M16HA-093G:EMT41J256M16HA-093G:EMT41J256M16HA-093G:EMT41J256M16HA-093G:EMT41J256M16HA-093G:E
SA000077K10 SA000077K10 SA000077K10 SA000077K10 SA000077K10 SA000077K10 SA000077K10 SA000077K10
UV7 UV8 UV9 UV10
MIC4@ MIC4@ MIC4@ MIC4@

B
MT41J256M16HA-093G:EMT41J256M16HA-093G:EMT41J256M16HA-093G:EMT41J256M16HA-093G:E B
SA000077K10 SA000077K10 SA000077K10 SA000077K10
Samsung 2G RV21 RV24

Samsung 4G RV21 RV24
SAM2@ SAM2@ SAM4@ SAM4@

4.53K_0402_1% 2K_0402_1% 3.4K_0402_1% 10K_0402_1%
SD034453180 SD034200180 SD034340180 SD034100280
UV3 UV4 UV5 UV6

UV3 UV4 UV5 UV6

SAM2@ SAM2@ SAM2@ SAM2@ K4W4G1646D-BC1A K4W4G1646D-BC1A K4W4G1646D-BC1A K4W4G1646D-BC1A
K4W4G1646D-BC1A K4W4G1646D-BC1A K4W4G1646D-BC1A K4W4G1646D-BC1A SA000076P10 SA000076P10 SA000076P10 SA000076P10
SA000076P10 SA000076P10 SA000076P10 SA000076P10
UV7 UV8 UV9 UV10
A A
K4W4G1646D-BC1A K4W4G1646D-BC1A K4W4G1646D-BC1A K4W4G1646D-BC1A
SA000076P10 SA000076P10 SA000076P10 SA000076P10

VGA Notes List
C 1.0
5 4 3 2 1
5 4 3 2 1
EMI@ PL101 ADP_ID

JDCIN1 PF101
HCB2012KF-121T50_0805
1 2
VIN AC Adapter 90W 65W
1 APDIN 7A_32VDC_0437007.WRML
1 2 1 2 APDIN1 R(K ohm) open 10
2 3 EMI@ PL102
3 4 HCB2012KF-121T50_0805 ADP_ID(V) 3.3 1.65
4
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
5 1 2
5 Detection voltage >2.64 1.32~1.98
ACES_88299-0510
1
EMI@ PC101
EMI@ PC102
EMI@ PC103
EMI@ PC104
CONN@
2
D D
@ PR101
0_0402_5%
1 2
PR1125
1@ 2
0_0402_5%
PQ101A
2N7002KDW-2N_SOT363-6
680P_0603_50V7K
1 2 6 1
+3VALW ADP_ID <25>
0.1U_0402_16V7K
PR102
750_0402_1%
A/D
1
PC105
PC106
2
PR103
2
2N7002KDW-2N_SOT363-6
100K_0402_5%
1 2
VIN
3
1
PQ101B
PR104
5 ADP_ID_CLOSE <25>
100K_0402_5%
1
2
4
PR1124
C C
100K_0402_5%
2
+CHGRTC
PR105
1K_0603_5%
1 2
PD101 +3VLP
S SCH DIO BAS40CW SOT-323
2 +CHGRTC_R
+RTCBATT 1 JBATT1
3 PR106
1K_0603_5%
1 2 1 2
+ -
LOTES_AAA-BAT-054-K01
CONN@
RTC Battery
B B
A A

PWR DCIN / RTC Battery
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Z_BDW
5 4 3 2 1
5 4 3 2 1
EMI@ PL201
VMB2 VMB HCB2012KF-121T50_0805
PF201 1 2
JBAT1 F1206HB12V024TM 12A 24V UL FAST
1 1 2
1 2 BATT+
EMI@ PL202
2 3 EC_SMCA HCB2012KF-121T50_0805
3 4 EC_SMDA 1 2
4 5
5 6
6
1
7
7
1
100_0402_1%
100_0402_1%
8
8 9 PC201 EMI@ PC202 EMI@
D GND 10 1000P_0402_50V7K 0.01U_0402_25V7K D
2
GND
PR201
PR211
11
2
GND 12
GND
SUYIN_125022HB008M200ZL
CONN@
EC_SMB_CK1 <25,40>
EC_SMB_DA1 <25,40>
1 2
+3VLP
PR212
2
1200K_0402_1%
+3VALW
PR213
@ 200K_0402_1%
1 2
PR214
VCIN1_BATT_TEMP <25,40> PH201 under CPU botten side :
10K_0402_5%
A/D CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C 20120314
Change to +EC_VCCA from +3VLP
+EC_VCCA
<25,40> ADP_I
14K_0402_1%
1
10K_0402_1%
<25,40> VCOUT1_PROCHOT#
PR215
C C
2
30K_0402_1%
PR216
PR217
2
@ <25> VCIN0_PH1
1
<25> VCIN1_ADP_PROCHOT
PH201
2
100K +-1% 0402 B25/50 4250K
75K_0402_1%
PR221
2
1
100K_0402_1%
PR223
1
2
ADP_SET1 ADP_SET2 ECAGND
1
D
45W adapter 0 0
2 PQ203
G 2N7002KW_SOT323-3
65W adapter 1 0 S
3
90W adapter 0 1
B B
135W adapter 1 1
<25> ADP_SET1
ECAGND
135W: 150W active, 135W recovery

90W : 120W active, 90W recovery
A A

PWR-BATTERY CONN/OTP
5 4 3 2 1
5 4 3 2 1
1
D
Rds(on) = 35mohm max
@ PR314 2
1 2 G
Vgs = 20V
Vds = 30V
S @ PQ307 max Power loss 0.22W for 90W;0.12W for 65W system B+ BA+
3
1M_0402_1% @ PR315 2N7002KW _SOT323-3 P3 CSR rating: 1W ID = 7.7A (Ta=70C) PQ302
1 2 VACP-VACN spec < 80.64mV AO4406AL_SO8
PQ301 8 1
3M_0402_5% PQ303 7 2
MDU1512URH_PDFN56-8-5 AON7506_PDFN33-8-5 PR302 6 3
1 1 0.01_1206_1% EMI@ PL301 5
2 2 1UH_NRS4018T1R0NDGJ_3.2A_30%
5 3 3 5 1 4 1 2
VIN
4
PC302
2 3 SH00000YG00
1 2
0.047U_0603_25V7M
4
4
D D
Rds(on) typ=35mohm max
1000P_0603_50V7
2200P_0402_50V7K
PC301
0.022U_0603_25V7K
68P_0402_50V8J
Vgs=20V
4.02K_0402_1%
1
10U_0805_25V6K
10U_0805_25V6K
PC303
@EMI@ PC306
PR301
EMI@ PC307
PC308
PC309
Vds=30V
1
PR329
4.7_0603_1%
1
Id=10.6A (Ta=70C)
4.02K_0402_1%
2
PC310 PC311 PC312
PR303
PR304
2
10_0402_1%
0.1U_0603_25V7K 0.01U_0402_25V7K
2
1 2 1 2 1 2
2
0.1U_0402_25V6
BATDRV
BATSRC
PR308
1 2 ACDRV
4.02K_0402_1%
CMSRC
VIN PR312
ACP ACN
PD303
10_1206_5% @ PC329
VIN 3 1 2
422K_0402_1%
1
1 1 2 Rds(on) = 30mohm max
AON7408L_DFN8-5
PR311
2 ACDRV 1000P_0402_50V7K
BA+ 1U_0603_25V6K PC313
Vgs = 20V
1 2 BQ24780VDD PC314 Vds = 30V
S SCH DIO BAS40CW SOT-323 ID = 7A (Ta=70C)
2
5
4
1
C C
PU301 2.2U_0805_25V6K Support max discharge 6A(55W)
1 2 Power loss: 0.36W
ACDRV
ACP
ACN
28 CSR rating: 1W
VCC
PQ305
2200P_0402_25V7K
66.5K_0402_1%
PR316 VSRP-VSRN spec < 81.28mV

1
3 24
PC315
CMSRC
CMSRC REGN PR317 PC316 1 2 4
PR313
@ PR348 6 0_0603_5% 0.047U_0603_25V7M 7X7X3

BATT+
2
0_0402_5% ACDET 25 BST_CHG 1 2 1 2 0_0603_5%

BTST
Isat: 6.5A
<25,39> EC_SMB_DA1 1 2 EC_SMB_DA1_1 11 DCR: 33mohm
2
SDA
Power loss:0.297W
3
2
1
<25,39> EC_SMB_CK1 1 2 EC_SMB_CK1_1 12 26 DH_CHG PR318
@ PR349 SCL HIDRV PL302 0.01_1206_1%
0_0402_5% VCIN1_AC_IN 5 4.7UH_PCMB063T-4R7MS_5.5A_20%
<25,39> ADP_I ACOK 27 LX_CHG 1 2CHG 1 4
1 2 7 PHASE
IADP 2 3
AON7408L_DFN8-5
5
DCHG_I
100P_0603_50V8 PC317 8 23 DL_CHG
IDCHG LODRV
1
PC330 0.1U_0402_25V6
4.7_1206_5%
1 2 1 2 PMON_1 9
PMON
PQ306
PR320
@ PR322 PR321 316K_0402_1%
100P_0603_50V8 PC318 1 2 10 22 1 2 SRP SRN
10U_0805_25V6K
10U_0805_25V6K
@ 0_0402_5% /PROCHOT GND +3VLP 4
2
PR1126@ 0_0402_5% PR324 100K_0402_1% @EMI@
1
1
1 2 1 2
PC320
PC322
<25> PMON_SKYLAKE 13 21
680P_0603_50V7K
CMPIN ILIM
1
3
2
1
2
2
<25,39> VCOUT1_PROCHOT# 14
PC321
PR326 10_0402_1%
CMPOUT 20 1 2
2
SRP PR328 10_0402_1%
<25,39> VCIN1_BATT_TEMP 15 19 1 2 @EMI@
/BATPRES SRN
B B
16 18 PC323
/TB_STAT BATDRV
BQ24780VDD 29 17 1 2
PWPD BATSRC
0.1U_0402_25V6
BATDRV
BATSRC
BQ24780RUYR_W QFN28_4X4
1
PR319
100K_0402_1%
0.1U_0402_25V6
0.1U_0402_25V6
1
1
PC325
PC324
**Design Notes**
For 65 /90W system, 3S1P/3S2P battery
2
<25,31> VCIN1_AC_IN
Maximum Charging current 3A
2
2
Maximum Battery discharge power 55W
1
#Register Setting
PR325
1. 0X12 bit2 set 1 (default 0) to enable turbo boost function
2. Disable turbo when AC only
120K_0402_1% #Circuit Design
2
1. ILIM pull high voltage need base on 3/5V enable control

2. Use 7X7 choke and 3X3 H/L side MOSFET
Charge current 3A
Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W)
Power density : 0.61 (23X16)
#Protect function
Vin Dectector 1. ACOVP : VCC voltage > 24V
Min. Typ Max. 2. Charger timeout : No communication within 175s(default)
L-->H 17.16V 17.63V 18.12V 3. ACOC : 3.33 X Input current DAC setting (default:Disable)
4. CHGOCP : based on charge current setting
H-->L 16.76V 17.22V 17.70V 5. BATOVP : 103-106%
6. BATLOWV : 2.6V
A A
VILIM = 20*ILIM*Rsr 7. TSHUT : 155C
ILIM = 3.3*100/(316+100)/20/0.01 8. IFAULT HI : 750mV (default:Disable)
= 3.966 A 9. IFAULT LOW : 230mV (default)

Title
BQ24780
Custom 1.0
5 4 3 2 1
A B C D E
Module model information

SY8208B_V2.mdd
1 EN1 and EN2 dont't floating 1
PR401
Change 3V5V_EN to 3VALW_EN 499K_0402_1%
2014.10.30 reserve for ESD ENLDO_3V5V 1 2
B+
1
150K_0402_1%
PU401 PC403 PR403
B+
PR404
EMI@ PL401 7 1 3V5V_EN 0.01U_0402_25V7K 1K_0402_5%
HCB2012KF-121T50_0805 IN EN1 1 2 1 2
2200P_0402_50V7K
1 2 3V_VIN 8 3 3V_FB
IN EN2 PR405 PC404
2
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0402_25V6
6 1
BST_3V 2 1 2
BS
1
1
PC407
2.2_0603_5%
1
@EMI@ PC401
PC405
PC406
0.1U_0603_25V7K
PC1238
@ PL402
2
2
EMI@
10 LX_3V 1 2
+3VALWP
2
LX
@EMI@
9 4 1.5UH_PCMB053T-1R5MS_6A_20%
GND OUT
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PR406
1
1
680P_0603_50V7K 4.7_1206_5%
2 5
PG LDO +3VLP
<25> 3V/5VALW_PG
@EMI@
PC408
PC409
PC410
PC411
1
PR402 SYX196BQNC_QFN10_3X3
2
100K_0402_1% PC412
13V_SN
1 2 4.7U_0603_6.3V6M
+3VLP
2
2
Check pull up resistor of SPOK at HW side
@EMI@ PC413
3.3V LDO 150mA~300mA
2
2 PR407 2
2.2K_0402_5%
Vout is 3.234V~3.366V
<25> EC_ON 1 2
@ PR408
TDC=6A
1 2
<25> VCOUT0_MAIN_PWR_ON 0_0402_5% EC VDD0 is +3VL, PC13 UNPOP
1
@ PJ401
2
EC VDD0 is +3VALW, PC13 POP +3VALWP 1 2 +3VALW
JUMP_43X118
3V5V_EN EN1 and EN2 dont't floating
1M_0402_1%
4.7U_0402_6.3V6M
@ PR415
1
1 2 3V5V_EN
1
PR410
PC414
0_0402_5%
2
2
B+ EMI@ PL403
HCB2012KF-121T50_0805
1 2 5V_VIN
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
PU402 PC415 PR412

8 1 5V_EN 6800P_0402_25V7K 1K_0402_5%
IN EN1 1 2 1 2 Vout is 4.998V~5.202V
1
1
PC416
PC418
EMI@ PC419
@EMI@ PC420
3 5V_FB PR413 PC417

3 EN2 2.2_0603_5% 0.1U_0603_25V7K 3
@ 6 BST_5V 1 2 1 2
TDC=6A
2
BS
PL404
9 10 LX_5V 1 2 +5VALWP
GND LX
5V_VCC 5 4 1.5UH_PCMB053T-1R5MS_6A_20%
VCC OUT
1
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
@EMI@ PR414
680P_0603_50V7K 4.7_1206_5%
1
1
1
2 7
PG LDO VL
1
PC421
PC422
PC423
PC425
PC424
PC428
4.7U_0603_6.3V6M
SYX198CQNC_QFN10_3X3
2
2
2
15V_SN
@ PJ402
2
2
1
PC426
4.7U_0603_6.3V6M
+5VALWP 1 2 +5VALW
1 2
JUMP_43X118
2
@EMI@ PC427
2
Module model information 5V LDO 150mA~300mA
SY8208C_V2.mdd
4 4

+3VALW/+5VALW
A B C D E
5 4 3 2 1

RT8207M_V1.mdd For Single layer
RT8207M_V2.mdd For Dual layer
D D
Pin19 need pull separate from +1.5VP.

If you have +1.5V and +0.75V sequence question, 0.75Volt +/- 5%
EMI@ PL501 you can change from +1.5VP to +1.5VS. TDC 0.7A
HCB2012KF-121T50_0805
B+ 1 2 1.35V_B+ PR501 Peak Current 1A
2.2_0603_5%
BST_1.35V 1 2 BOOT_1.35V
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
+1.35VP
1
1
PC501
PC502
PC503
PC504
DH_1.35V +0.675VSP
2
2
EMI@
@EMI@
SW _1.35V
10U_0805_10V6K
10U_0805_10V6K
1
1
PC505
PC506
PC507
5
0.1U_0603_25V7K
16
17
18
19
20
2
C C
2
VLDOIN
PHASE
UGATE
BOOT
VTT
21
PQ501 PAD
AON7408L_DFN8-5 4 DL_1.35V 15 1
LGATE VTTGND
Change CS R to your estimation value
14 2
PL502 PR502 PGND VTTSNS
1
2
3
1UH +-20% 11A 7X7X3 MOLDING 22K_0402_1%
1 2 1 2 CS_1.35V 13 3
+1.35VP PC508 CS PU501 GND
1
1U_0603_10V6K RT8207PGQW _W QFN20_3X3

PC516 22U_0603_6.3V6M
PC521 22U_0603_6.3V6M
PC520 22U_0603_6.3V6M
PC519 22U_0603_6.3V6M
PC518 22U_0603_6.3V6M
PC517 22U_0603_6.3V6M
5
1 2 12 4 +VTTREFP
EMI@ PR503 PR504 VDDP VTTREF
1 1 1 1 1 1
4.7_1206_5% 5.1_0603_5%
1 2 VDD_1.35V 11 5
+5VALW +1.35VP
1 2
VDD VDDQ
1
PGOOD
PQ502
2 2 2 2 2 2 AON7752L_DFN8-5 4 PC509
TON
1
EMI@ PC513 PR1127 0.033U_0402_16V7K
FB
S5
S3
2
680P_0402_50V7K PC512 5.1_0603_5%
2
1U_0603_10V6K 1 2
10
6
1
2
3
FB_1.35V
EN_0.675VSP
TON_1.35V
EN_1.35V
PR506
8.2K_0402_1%
+5VALW 1 2 +1.35VP
PR507
B
2014/10/15 add PR1127 for module design 470K_0402_1% B
1.35V_B+ 1 2 Change FB Rtop to 8.2K for 1.35V
MOSFET: 3x3 DFN
1
H/S Rds(on): 27mohm(Typ), 34mohm(Max)
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C PR508
@ PR509 10K_0402_1%
L/S Rds(on): 9.9mohm(Typ), 13mohm(Max) 1 2
<25,29> SYSON
2
Idsm: 13.5A@Ta=25C, 11A@Ta=70C 0_0402_5%
1
@ PC514
Choke: 7x7x3 0.1U_0402_10V7K
Rdc=8.3mohm(Typ), 10mohm(Max)
2
Switching Frequency: 285kHz
Ipeak=10A @ PR510
1 2 @ PJ501
Iocp~13A <25,29,44,45> SUSP# 0_0402_5% +1.35VP 1 2 +1.35V
OVP: 110%~120% 1 2
MOSFET footprint: SIS412DN @ PR505 JUMP_43X118
1 2 @ PJ502
<15> DDR_VTT_PG_CTRL 1 2
0_0402_5% 1 2
1
Mode Level +0.75VSP VTTREF_1.5V @ PC515 JUMP_43X118
0.1U_0402_10V7K
S5 L off off
2
PJ503 @
S3 L off on 1 2
S0 H on on +0.675VSP 1 2 +0.675VS
A
JUMP_43X39 A
Note: S3 - sleep ; S5 - power off

Title
RT8207M
Custom 1.0
5 4 3 2 1
A B C D

APL5930_V1.mdd
1 1
+3VALW +5VALW
Ultra Low Dropout 0.23V(typical) at 3A Output Current
1
PC601
1
1U_0402_6.3V6K
JUMP_43X79
2
@ PJ601
2
2
PC602 PU601
1
4.7U_0805_6.3V6K AP7175SP-13_SO-8EP-8
6
5 VCNTL 3
PJ602
2
PR601 9 VIN VOUT 4 @
30K_0402_1% VIN VOUT
+1.8VGSP +1.8VGSP 1
1 2
2 +1.8VGS
1
1 2 8
24K_0402_1%
<8,25,32,46> DGPU_PWR_EN EN
1
1 2 7 2 JUMP_43X79
+3VS
GND
POK FB
PR603
PC603
1
@ PR602 0.01U_0402_25V7K
2
Rup
0.1U_0402_16V7K
2
1
PC605
PR604 100K_0402_5% PC604
2
47K_0402_5% 22U_0603_6.3V6M
2
2
2
1
PR605
19.1K_0402_1%
Rdown
2
3 3
4 4

+1.8VGS-+0.95VVGS
Custom 1.0
A B C D
A B C D
1 1
+3VALW +5VALW
Ultra Low Dropout 0.23V(typical) at 3A Output Current
1
PC707
1
1U_0402_6.3V6K
JUMP_43X79
2
@ PJ703
2
2
PU702
AP7175SP-13_SO-8EP-8
1
PC708 6
4.7U_0603_6.3V6K 5 VCNTL 3
PR707 9 VIN VOUT 4
2
100K_0402_5% VIN VOUT
+1.5VSP
1
1 2 8
1.54K_0402_1%
0.01U_0402_25V7K
<25,29,42,45> SUSP# EN
1
7 2
GND
POK FB
PR708
PC710
22U_0603_6.3V6M
1
1
Rup
0.1U_0402_16V7K
1
PC709
PR709
PC711
47K_0402_5%
2
2 2
2
1
@
1.74K_0402_1%
PJ704
PR710
1 2
+1.5VSP 1 2 +1.5VS
Rdown
2
JUMP_43X79
3 3
4 4

+1.5VS
Custom 1.0
A B C D
5 4 3 2 1
D D

SY8208D_V1.mdd
EN pin don't floating

If have pull down resistor at HW side, pls delete PR2
@ PR802
1 2
SUSP# <25,29,42,44>
C C
0_0402_5%
1
@ PC802
1M_0402_1%
0.22U_0402_10V6K
2
PR803
PJ801
2
+1.05VSP 1 2 +1.05VS
1 2
JUMP_43X118 @
@EMI@ PR804 @EMI@ PC803
4.7_1206_5% 680P_0603_50V7K
EMI@ PL801 1 2SNB_1.05V 1 2
HCB2012KF-121T50_0805 PU801
B+ 1 2 B+_1.05V 8
IN EN
1 PR805 PC804
2.2_0603_5% 0.1U_0603_25V7K
TDC 8A
10U_0805_25V6K
10U_0805_25V6K
6 1
BST_1.05V 2 1 2 PL802
0.1U_0402_25V6
2200P_0402_50V7K
BS
1
1UH +-20% 11A 7X7X3 MOLDING

PC805
PC806
PC807
3VLDO_1.05 9 10 LX_1.05V 1 2
+1.05VSP
PC801
GND LX
@EMI@
2
2
EMI@
15K_0402_1%
47U_0805_6.3V6M
47U_0805_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
330P_0402_50V7K
1
1
PR806 4
PR807
FB
PC808
PC809
PC810
PC811
PC812
0_0402_5%
ILMT_1.05V3 7
Rup
@ +3VALW
2
ILMT BYP
2
2
4.7U_0603_6.3V6K
ILMT_1.05V
+3VS 1 21.05V_VS_PG_PWR 2
PG LDO
5 3VLDO_1.05
1
PR801
PC814
4.7U_0603_6.3V6K
1
10K_0402_5% SYX196DQNC_QFN10_3X3
PC813
FB = 0.6V
2
1
PR808 @
2
0_0402_5% PR809
Rdown
2
20K_0402_1%
2
<25> 1.05V_VS_PG_PWR
Pin 7 BYP is for CS.
B
The current limit is set to 8A, 12A or 16A when this pin Common NB can delete +3VALW and PC15 B
is pull low, floating or pull high
VFB=0.6V
Vout=1.05V
A A

+1.05VS
C 1.0
5 4 3 2 1
5 4 3 2 1
+VGA_CORE
GPU_B+ AMD Meso XT
Module model information TDC 36A, EDC 54A
OCP min 67.8A
EMI@ PL901
ISL62771_V1A.mdd for IC portion HCB2012KF-121T50_0805
B+
1 2
ISL62771_V1B.mdd for SW portion LGATE1
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
PHASE1
1
@EMI@ PC902
EMI@ PC903
PC904
PC905
PR905 PC906
2.2_0603_1% 0.22U_0603_25V7K
BOOT11 2 1 2
PQ901
2
D D
6
7 G2
PR904 S1/D2 5
UGATE1 1 2 1 S2
G1 4
0_0402_5% 2 S2
D1 3
S2
AON6932A_DFN5X6-8-7
@ PR946
1 2 Fsw=400K Hz
1
0_0402_5% PR902
LGATE_NB1
10K_0402_1%
1 2 SH00000NX00 (DCR:1.4± 5%)
@ PR947 PR945
1 2 41.2K_0402_1% PHASE_NB1
0_0402_5% PR903 10K_0402_1% +VGA_CORE
2
UGATE_NB1 1 2
1 4
PL902
PR906
0.22UH_PCME064T-R22MS_28A_20%
BOOT_NB12 1
+5VALW
2 3
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
1 1 1 1
330U_2.5V_M
41
40
39
38
37
36
35
34
33
32
31
1_0402_5% + + + +
PC908
PC910
PC907
PC909
PU901 PR907 @EMI@ PR938 PR939
4.7_1206_5% 10K_0402_1% 10K_0402_1%
TP
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
ISEN1 1 2 1 2 ISEN2
2 2 2 2
2
PR901 100K_0402_1%
1 2 1 30 BOOT2 PR908
1
NTC_NB BOOT2 PC911 @EMI@ 3.65K_0603_1%
<31> GPU_PROCHOT# PR909 100K_0402_1%
1 2 IMON_NB 2 29 UGATE2 680P_0603_50V7K VSUM+ 1 2
IMON_NB UGATE2
2
3 28 PHASE2
<31> GPU_SVC SVC PHASE2 PR910
@ PR911 100K_0402_1%
1 2 4 27 LGATE2 +5VALW 1_0402_1%
+3VS VR_HOT_L LGATE2
0_0402_5% VSUM- 1 2
1@ PR1123 2 5 26
+3VGS <31> GPU_SVD SVD VDDP
@ PR912 ISL62771HRTZ-T_TQFN40_5X5 PR913
+1.8VGS 1 2 VDDIO 6 25 1 2
0_0402_5% VDDIO VDD 1_0603_5%
1U_0603_10V6K
1
@ PR914 0_0402_5% 7 24 LGATE1

<31> GPU_SVT SVT LGATE1
1
C 1 2 GPU_B+ C
LGATE2
1U_0603_10V6K
+1.5VS
PC901 8 23
PC913
ENABLE PHASE1
2
ENABLE PHASE1
PC912
0.1U_0402_25V6K
2
1 PR937 2 @ 9 22 UGATE1
<8> DGPU_PWROK PWROK UGATE1
0_0402_5% PHASE2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1 2 IMON 10 21 BOOT1
IMON BOOT1 +3VS
@EMI@ PC915
PR916 PR928 PC922
1
1
PGOOD
PC917
PC918
EMI@ PC916
133K_0402_1% 2.2_0603_1% 0.22U_0603_25V7K
ISUMN
ISUMP
COMP
PQ902
ISEN2
ISEN1
VSEN
BOOT21 2 1 2
NTC
RTN
1 2 PC914 FB 6
2
2
1
1000P_0402_50V7K 7 G2
PR919 PR918 0_0402_5% PR921 S1/D2 5
11
12
13
14
15
16
17
18
19
27.4K_0402_1% 20K_0402_1% 20 @ PR917 UGATE2 1 2 1 S2

1 2 1 2 100K_0402_1% G1 4
2 S2
2
D1 3
ISEN2
ISEN1
DGPU_PWROK S2
1 2
@ PR932 PH901 AON6932A_DFN5X6-8-7
2
1 2
0_0402_5%
ENABLE
10K_0402_1%
<8,25,32,43> DGPU_PWR_EN 470K +-5% 0402 B25/50 4700K

PR944
PR920
0_0402_5%
1
0.22U_0402_10V6K
0.22U_0402_10V6K
0.1U_0402_16V7K
PC1236
@ @
1
PC962
PC961
+5VS
2
@ 2014.09.22 modify from FAE +VGA_CORE

2
PC920 PL903
2014.10.15 reserve for RC delay VSUM- PC919 PR922 330P_0402_50V7 @ PR923 1 4
1000P_0402_50V7K 301_0402_1% 32.4K_0402_1% 0.22UH_PCME064T-R22MS_28A_20%
VSUM+ 1 2 1 2 1 2 1 2 2 3
330P_0402_50V7K
@ PC921
PR940 PR943
2.61K_0402_1%
1
1
PR924 PR925 PC923 PR929 @EMI@ 10K_0402_1% 10K_0402_1%
10K +-5% 0402 B25/50 4250K
1 2 1 2
PR926
0.047U_0402_25V7K
0.15U_0603_16V7K
1.21K_0402_1% 137K_0402_1% 390P_0402_50V7K 4.7_1206_5% ISEN2 ISEN1

11K_0402_1%
1
1 2 1 2 1 2
PC924
2
1
PC925
PR927
PR942
1 2
1 2
PR930 PC926 3.65K_0603_1%
2
2K_0402_1% 330P_0402_50V7K VSUM+ 1 2

2014.09.22 modify from FAE
2
1 2 1 2 PC927 @EMI@
PH902
680P_0603_50V7K
2
B PR941 B
PR931 2014.09.22 modify from FAE 1_0402_1%
2
590_0402_1% VSUM- 1 2
VSUM- 1 2
@ PC929 @ PR933 +VGA_CORE

1
@ PR934 820P_0402_50V7K 0_0402_5%

PC928 100_0402_1% 1 2
0.1U_0603_50V7K 1 2 1 2 GPU_VDD_SEN <31>
2
@ PR935
0_0402_5%
PR1046 set 536 ohm to OCP 26.32A 1 2
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
GPU_VDD_RUN_FB_L <31>
0.01U_0402_50V7K
1
1
1
1
1
1
1
PC933
PC941
PC932
PC938
PC944
PC931
PC935
PC937
PC940
PC934
PC936
PC939
PC942
PC943
PC945
PC946
1
PC930
2
2
2
2
2
2
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
1
1
1
1
1
1
1
PC950
PC954
PC955
PC957
PC958
PC952
PC947
PC951
PC959
PC948
PC960
PC949
PC953
PC956
2
2
2
2
2
2
2
2
2
A A

PWR-+VGA_CORE
Custom 1.0
5 4 3 2 1
5 4 3 2 1
Base on BDW PDDG Rev_0_73

Module model information:
ISL95813 (for 15W & 28W CPU) 15W H-side MOS: MDV1525URH
Rds(on):
TDC 14A <10.1mohm@Vgs=10V
<14.0mohm@Vgs=4.5V
MAX 32A Id :24A@Vgs=10V
D
Location Note D
OCP 39A
L-side MOS: MDU1511RH
Loadline=-2.0mv/A Rds(on):
Follow intel guideline <2.4mohm@Vgs=10V
+1.05VS PR1102130_0402_1% PR1120 499 Ohm OCP <3.3mohm@Vgs=4.5V
1 2
Id :100A@Vgs=10V
PR537 1.27kOhm Droop
PC528 0.022uF RC Match

PC1102 Choke: 0.12UH (Size:7*7*3)
1U_0402_6.3V6K PR110354.9_0402_1%
1 2 1 2 PR507 90.9kOhm PROG1 Rdc=0.62mohm +-5%
Heat Rating Current=41.5A
Saturation Current=41A
PR703 93.1kOhm IMON
<11> VR_SVID_DAT
PC518 0.1uF ( 0402 ) RC Filter
Note:
VR_SVID_ALRT# Pull high on HW side
<11> VR_SVID_ALRT#
2014.10.30 reserve for ESD
<11> VR_SVID_CLK PR1104 Note: CPU_B+ EMI@ PL1103

HCB2012KF-121T50_0805
1 2 PR1104=169K 1 2 B+
C =>Icc(max)=33A C
VR_SVID_ALRT#
fsw=700KHz CPU_B+
VR_SVID_DAT
VR_SVID_CLK
90.9K_0402_1%
2200P_0402_50V7K
10U_0805_25V6K
0.022U_0402_25V7K
0.01U_0402_50V7K
<11> VR_ON @EMI@ PL1104
10U_0805_25V6K
0.1U_0402_25V6
HCB2012KF-121T50_0805
MDV1525URH_PDFN33-8-5
33U_25V_M
33U_25V_M
@RF@ PC1107
EMI@PC1105
EMI@PC1106
1 1 1 2
PRGM1
1
1
1
PC1104
PC1103
PC1123
@ PR1101
+1.05VS + +
PC1237
1.91K_0402_1%
PQ1101
1.5K_0402_1%
PC1235
1 2
2
2
2
1
@EMI@
PR1105
2 2
PR1122
0_0603_5%
21
20
19
18
17
<11> VGATE PU1101 1 2 4
SCLK
SDA
PAD
ALERT#
PRGM1
2
PC1101 VR_ON 1 16 LAGTE
3
2
1
1000P_0402_50V7K VR_ON LGATE PL1102
1 2 .15UH 20% PCME064T-R15MS0R667 36A
2 15 PHASE 1 4
PR1106 PGOOD PHASE
+CPU_CORE
4.7_1206_5%
EMI@PR1107
Note: 97.6K_0402_1% 2 3
MDU1511RH_POWERDFN56-8-5
1
5
1 2 IMON_CPU 3 14 UAGTE
MDU1511RH_POWERDFN56-8-5
VR_HOT# Pull high on HW side IMON UGATE
5
PR1108 PC1108 SH000011P00
PQ1102
ISL95813HRZ-T_QFN20_3X4 2.2_0603_5% 0.22U_0603_16V7K
1
PQ1103
<25> VR_HOT# VR_HOT_1# 4 13 BOOT 1 2 1 2
PH1101 VR_HOT# BOOT PR1109
2
47P_0402_50V8J
470K +-5% 0402 B25/50 4700K PR1110 4 3.65K_0603_1%

1 2 1 2 NTC 5 12 4
NTC VCC +5VS
1
680P_0603_50V7K
PC1109
EMI@PC1110
2
1
3.83K_0402_1%
PR1111 COMP 6 11 PRGM2
2
3
2
1
COMP PRGM2
1
27.4K_0402_1%
ISUMN
ISUMP
3
2
1
2
1 2 PC1111
RTN
124K_0402_1% 0.1U_0402_25V6
FB
2
1
PR1112
B Over temperature protection: B

7
10
OTP Setting: 100C active @

1.96K_0402_1%
Pin5 (NTC) voltage <0.88V, Protect

1
6800P_0402_25V7K PR1113
Pin5 (NTC) voltage >0.92v, recovery FB

ISUMN
ISUMP
Note:
33P_0402_50V8J PR1112=124K
1
=>Slew rate=53mV/us
2K_0402_1%
10_0402_1%
PC1112
2
Vboot = 1.7V
@PR1115
2
PR1114
1
1.27K_0402_1%
PC1113
PR1116
@
2
1
390P_0402_50V7K
1
1
330P_0402_50V7K
PR1118
2
1
@PC1115
PR1117 4.42K_0402_1%
RC Match
2
PC1114
Droop
2
2
20M_0402_5%
2
1
1
1
@ PC1116 PC1117 PR1119
0.033U_0402_25V7K 0.1U_0402_16V4Z 11K_0402_1%
2
2
1
<11> VCCSENSE
PH1102
10K +-5% 0402 B25/50 4250K
@ PC1118
2
0.082U_0402_16V7K
1 2 OCP Setting
@PC1119
330P_0402_50V7K
PR1120
1
1 2
A A
2
PC1120
1 2 267_0402_1%
1
0.01U_0402_50V7K
@ PC1121 @ PR1121 PC1239
0.1U_0402_16V4Z
2
1 2 1 2
<11,13> VSSSENSE Compal Electronics, Inc.
4700P_0402_25V7K 1.5K_0402_1% Title
Local sense put on HW site

ISL95813 for BDW-Y&U(15W/28W) CPU
1.0
Z_BDW
5 4 3 2 1
5 4 3 2 1
+CPU_CORE
24 X 22u/0603
D D
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1
PC1201
PC1202
PC1203
PC1204
PC1205
PC1206
PC1207
PC1208
PC1209
PC1210
2
2 2 2 2 2 2 2 2 2
@ @ @ @ @ @
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1
PC1211
PC1212
PC1213
PC1214
PC1215
PC1216
PC1217
PC1218
PC1219
PC1220
2 2 2 2 2 2 2 2 2 2
@
C C
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1 1 1 1
+ @ PC1234
PC1221
PC1222
PC1223
PC1224
330U_D2_2VM_R9M
2 2 2 2 2
B B
A A

Title
PWR-PROCESSOR_DECOUPLING
Custom 1.0
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase
add PC1236
1 reserve VGA_CORE RC delay P46 2014.10.15 SIV
D D
2 reserve 0.1uF for ESD P41/P47 add PC1237,PC1238 2014.10.30 SIV
C C
9
10
11
12
13
14
B B
15
16
17
A A

PIR (PWR)
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. BE_BDW
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1

Item Reason for change PG# Modify List for HW Phase
1 Reserve clean CMOS circuit P06 reserve R80,Q27 2014.10.28 SIV
2 HDMI Design P18 add R1650,R1651,R1652,R1653,R1654,R1655,R1656,R1657,R1658,R1659,R1660,R1661 2014.10.28 SIV
3 USB2.0 design for EMI request 2014.10.28 SIV

P24 add R1676 and R1677
D D
4 Change commom chock symbol for EMI request P24 change L12~L18 2014.10.28 SIV
5 Add FAN_ID for EC request P25 add R516 and R517 2014.10.29 SIV
6 Audio design for EMI request P36 add CA28,CA29,CA30,CA31 2014.10.29 SIV
7 Audio design for EMI request P36 change from RA19,RA20 to LA2,LA3 2014.10.29 SIV
8 Audio design for EMI request P36 add LA1 2014.10.29 SIV
9 +1.35V design for EMI request P15 add C320~C324 2014.10.29 SIV
10 modify +MEM_GFX power sequence P32 change C901 from 0.01uF to 0.1uF 2014.10.30 SIV
11 LAN design change for wake on lan P26 delete RL18, add J6,J7 2014.11.13 SIT
12 Change pcb foot print by DFX request P20,P24 change JIO1,JODD1,JHDMI pcb footprint 2014.12.08 SIT
C C
13 Change for VGA power sequence P32 change CV35 value 2014.12.08 SIT
14 Change Audio PCBEEP SCH by verdor suggestion P27 add RA35,RA37,CA90,CA91,RA39 / DELETE CA23,CA24,RA36,RA34,CA25 2014.12.15 SIT
15 Modify LED BOM setting P27 modify LED1,LED2,LED3,LED4,LED5,LED6 BOM setting 2014.12.15 SIT
16
17
18
19
20
21
B
22 B
23
24
25
26
27
28
29
30
A A

HW-PIR1
C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C281P
5 4 3 2 1

Lenovo Z40-70 LA-C281P (AIWZ0 AIWZ1) Rev 1.0 SchematicDiagram

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Lenovo Z40-70 LA-C281P (AIWZ0 AIWZ1) Rev 1.0 SchematicDiagram

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A B C D E

Security Classification Compal Secret Data Compal Electronics, Inc.

Intel Broadwell U Left USB3.0 x2 Right USB2.0 x1

(1 Lanes) HP & MIC

IO/B Digital MIC

Security Classification Compal Secret Data Compal Electronics, Inc.

Voltage Rails USB Port Table BOM Structure Table

SMBUS Control Table

Full ON HIGH HIGH HIGH ON ON ON ON

S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW

S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF

S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF

S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF

C238 DDR3 Compensation Signals (R9, R10, R11): 2 OF 19

ESD@ 25 mils to non-comp signals

Security Classification Compal Secret Data Compal Electronics, Inc.

UC1C BDW_ULT_DDR3L(Interleaved) UC1D BDW_ULT_DDR3L(Interleaved)

Security Classification Compal Secret Data Compal Electronics, Inc.

R10 UC1E BDW_ULT_DDR3L(Interleaved)

R15 1 2 1M_0402_5% SM_INTRUDER# Q27 2

R16 1 2 330K_0402_5% PCH_INTVRMEN

(*) H Integrated VRM enable

Safty suggestion remove EE side ,Keep PWR side

Security Classification Compal Secret Data Compal Electronics, Inc.

C43 A25 XTAL24_IN R21 2NOGCLK@ 1 1M_0402_5% XTAL24_OUT

LPC_AD0 AU14 AN2 PCH_GPIO11

LFRAME SML0CLK AK1 SML0DATA

PCH_SPI_SO AA4 SPI_MOSI

：Thermal IC, EC, dGPU

EMI RP5 EMI@ @ R37 2.2K_0402_5%

SML1DATA R41 1 @ 2 0_0402_5% EC_SMB_DA2

SML1CLK R42 1 @ 2 0_0402_5% EC_SMB_CK2

EMI RP8 EMI@

SPI ROM ( 8MByte )

Security Classification Compal Secret Data Compal Electronics, Inc.

ESD ESD ESD

SYSTEM POWER MANAGEMENT

+3VALW AK2 AW7 DSWODVREN R53 1 @ 2 0_0402_5% EC_RSMRST#

<25> PCH_PWROK PCH_PWROK AY7 R216 @ 0_0402_5%

AC_PRESENT SUSCLK/GPIO62 AP5 PM_SLP_S5#

R61 1 2 2.2K_0402_5% DDI1_CTRL_CK

R223 1 2 10K_0402_5% DGPU_PWR_EN

R225 1 2 10K_0402_5% DGPU_HOLD_RST#

Security Classification Compal Secret Data Compal Electronics, Inc.

R76 1 @ 2 1K_0402_5% HDA_SPKR

Security Classification Compal Secret Data Compal Electronics, Inc.

<30> PCIE_CRX_GTX_N0 F10 AN8

<26> PCIE_PRX_DTX_N3 G11

Security Classification Compal Secret Data Compal Electronics, Inc.

AG58 RSVD VCC G51

43_0402_1% +CPU_CORE AE22 VCCST VCC J23

R86 CRB mount

R88 PD resistor should be close to CPU

Security Classification Compal Secret Data Compal Electronics, Inc.

@ C41 Close to M9 Close to K9, L10

@ @ 1U_0402_6.3V6K 2 @ T18 J13 USB3

Security Classification Compal Secret Data Compal Electronics, Inc.

UC1N BDW_ULT_DDR3L(Interleaved) UC1O BDW_ULT_DDR3L(Interleaved) UC1P BDW_ULT_DDR3L(Interleaved)

Security Classification Compal Secret Data Compal Electronics, Inc.

1 : Disabled; No Physical Display Port attached

Security Classification Compal Secret Data Compal Electronics, Inc.

+SM_VREF_DQ0 <5> DIMM1

DDR_A_WE# 113 114 DDR_CS0_DIMMA#