IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 70, NO.
3, MARCH 2023
Towards Reconfigurable CNN Accelerator
for FPGA Implementation
Rizwan Tariq Syed , Marko Andjelkovic , Markus Ulbricht , and Milos Krstic
Abstract—Convolutional Neural Networks (CNNs) have rev-
olutionized many applications in recent years, especially in
image classification, video processing, and pattern recognition.
This success of CNNs has been a motivating factor for solving
even more complex problems involving multiple data modali-
ties. Traditionally, a single CNN accelerator has been optimized
for just one task or has been used to perform correlated tasks.
We leverage the CNNs capability to learn patterns and use one
accelerator to perform multiple uncorrelated tasks from different
modalities and achieve an average accuracy above 90%, which
would otherwise require three accelerators. Two types of CNN
architectures (i.e., fused and branched) are evaluated for three
distinct tasks based on accuracy, quantization, pruning, hardware
resource utilization, power, and latency. Capitalizing on this, we
have further proposed a runtime reconfigurable CNN accelera-
tor supporting fault-tolerant (FT), high-performance (HP), and
de-stress (DS) modes.
Index Terms—Multi-task learning, multi-modal learn-
ing, FPGAs, convolutional neural network, reliability,
reconfigurability.
I. I NTRODUCTION
NNS have revolutionized many applications in recent
C years, ranging from smart video surveillance and intelli-
gent manufacturing to smart cities and medical imaging, etc.
However, running CNN models is a resource-intensive process,
and deploying these complex models, with millions of param-
eters, on low-power edge devices is a growing concern. Using
multiple sensors to collect data is becoming common in var-
ious applications, i.e., using radars and cameras in industrial
and medical applications, lidar, radar, and camera in self-
driving cars, etc. This indicates that the CNNs are also becom-
ing increasingly complex, from processing images from a
single image sensor for object detection to processing multiple
data streams from numerous sensors classifying diverse tasks.
To fulfill the high-performance constraints, CNNs models are
Manuscript received 22 December 2022; accepted 23 January 2023. Date of
publication 31 January 2023; date of current version 6 March 2023. This work
was supported by the Federal Ministry of Education and Research of Germany
through the Project “Open6GHub” under Grant 16KISK009. This brief was
recommended by Associate Editor A. L. Zimpeck. (Corresponding author:
Rizwan Tariq Syed.)
Rizwan Tariq Syed, Marko Andjelkovic, and Markus Ulbricht are with
the System Architectures, Leibniz-Institut für innovative Mikroelektronik,
15236 Frankfurt (Oder), Germany (e-mail: syed@ihp-microelectronics.com;
andjelkovic@ihp-microelectronics.com; ulbricht@ihp-microelectronics.com).
Milos Krstic is with the System Architectures, Leibniz-Institut für inno-
vative Mikroelektronik, 15236 Frankfurt (Oder), Germany, and also with
the Chair of Design and Test Methodology, University of Potsdam, 14469
Potsdam, Germany (e-mail: krstic@ihp-microelectronics.com).
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TCSII.2023.3241154.
Digital Object Identifier 10.1109/TCSII.2023.3241154
1549-7747 
c 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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1249
implemented on hardware (i.e., ASICs, FPGAs) accelerators.
However, due to the varying AI requirements and work-
load, hardware resource utilization reaches a boundary very
quickly. An increase in hardware resources impacts directly
on power consumption. Many solutions have been proposed
to optimize CNN models for edge device deployment, i.e.,
pruning, quantization, knowledge distillation, and low-rank
factorization, etc. We tend to provide a different perspective
on saving hardware resources and power consumption. We
leverage the fundamental capability of CNNs of learning to
recognize patterns and train multiple distinct tasks from dif-
ferent modalities, thereby forcing one CNN accelerator to learn
the common features between the tasks, which would other-
wise require three separate accelerators (Fig. 2(a)). Thus, the
proposed approach, assisted by pruning and quantization meth-
ods, reduces hardware resources and power substantially. We
extend this concept further to propose runtime reconfigurable
CNNs. To cope further with the challenge of changing AI
application requirements, reconfigurable or adaptive acceler-
ators have been proposed by many researchers. The primary
idea is that AI accelerators should adapt based on the changing
needs of accuracy, power, latency, reliability, etc. Thus, vari-
ous concepts of reconfigurable DNNs have been presented: [1]
dynamically changes the bitstream of the DNN model for
a tradeoff between accuracy and power, [2] performs re-
programming weights of the DNN, [3] decomposes large CNN
kernel computations to small kernel-sized computations, [4]
conducts adaptive loading and processing of data in CNNs
kernels, [5] supports hybrid quantization, [6] performs data
path reconfiguration to reduce total energy. To the best of
our knowledge, one aspect of reconfigurability that seems to
be missing in most studies is hardware resource and power
efficiency while providing high reliability for safety-critical
applications, aging-aware, and high-performance computation.
Major contributions of this brief are:
• A novel approach of shared layers to execute multiple
distinct tasks from different modalities on one accelerator.
• Workflow for generating fused and branched CNN archi-
tectures.
• An approach for runtime reconfigurable CNN accelerator
for fault tolerance, de-stress (or aging-aware), and high-
performance computational needs.
II. M ULTI M ODAL M ULTI TASKS CNN ACCELERATOR
CNNs, a special type of neural networks, have proven to be
very effective in solving image classification problems. CNNs
have the ability to develop an internal representation of an
1250 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 70, NO. 3, MARCH 2023
image or pattern. This allows the CNN model to learn the
position and scale-invariant structures in the image data, which
is very important when working with images.
Multi-Modal Learning: We perceive the world in a multi-
modal fashion using our sensory organs, i.e., eyes, ears, nose,
etc. Similarly, neural networks can also learn features from
multiple input sources (i.e., multi-modal data from different
sensors) to make better decisions. The use of multiple sensors
in various applications has been increasing. Consumer devices,
industrial, medical, and safety-critical applications are getting
equipped with more sensors, which results in more data being
collected. The data from multiple modalities (e.g., camera,
radar, lidar, microphone) can be fused (i.e., sensor fusion) to
understand the environment more accurately. To learn the shared
representation, a CNN model can be trained on these modalities
using various fusion methods (early fusion, late fusion, etc.).
The resulting model tends to make better classification because
it balances the strengths of the multiple modalities.
Multi-Task Learning: Depending upon the application and
the data modality, a CNN model can be used to perform one
task (e.g., type of clothing) or multiple tasks (e.g., type of
clothing and color of clothing). In machine learning, this is
called multi-task learning (MTL). In MTL, a model is trained
for multiple tasks jointly by optimizing multiple loss func-
tions [7]. The joint training generally reduces overfitting, and
with the shared representations between related tasks, we can
facilitate the model to generalize better for different tasks at
hand. MTL can be termed multi-modal multi-task learning
(MMMT) when the model can learn a shared representation
of inputs across multiple data modalities and tasks.
Shared Layers for Un-Correlated Tasks for CNNs (Proposed
Approach): CNN models consist of a few thousand parameters
up to several million parameters. Eventually, these models will
be deployed on edge devices comprising ASICs or FPGAs.
The existing challenge is that deploying CNN models on
edge is both resource-intensive and energy-intensive due to
the large number of weights, activations and computations
involved. This indicates that there is a need to explore effi-
cient methods to minimize the hardware resource utilization,
power consumption and latency while trying to fulfill the
application requirements. The majority of the studies based
on CNNs MTL, and MMMT have focused on tasks that are
highly correlated. We tend to provide a different perspective
to MTL and MMMT, which is related to un-correlated tasks.
This perspective leverages the fundamental principle of how
CNN learns during training. The lower-level features of most
of the images are the same. Lower layers learn the low-level
features (i.e., edges, curves, blobs, etc.). The deeper we go in
the network, the layers start to learn the high-level (or more
abstract) features [8]. We leverage this concept to force one
model to learn the lower-level features of multiple uncorre-
lated tasks. These uncorrelated tasks, having similar low-level
features, share the layers. When mapped on the hardware
accelerator, these shared layers would mean sharing computing
resources, thereby saving significant hardware resources and
power consumption. This approach is further capitalized to re-
configure the FPGA-based CNN accelerator during runtime to
execute multiple tasks in FT, HP, and DS modes.
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Fig. 1. (a) FMCW radar hand gesture samples (b) SVHN samples
(c) Transformed MNIST dataset.
Fused and Branched CNN Model: To authenticate our
approach of shared layers for distinct tasks, we have created
two CNN models, i.e., fused and branched. A fused model
(FM) is an un-branched model, where all the tasks share all
the layers of the neural network (Fig. 2(c)). In comparison,
the branched model (BM) consists of tasks-specific branches
and shares only particular layers (Fig. 2(f)). Even though FM
is comparatively easier to train, and consumes slightly fewer
hardware resources and power, it may happen that having the
FM might not lead to the desired accuracy for a specific task.
The BM involves a multi-stage training process, and consumes
slightly higher hardware resources and power as compared
to FM. Additionally, BM can be helpful in 1) Task isolation
in case of faults, 2) Task-specific bit-stream reconfiguration in
FPGAs, 3) Selective replication of only specific layers (e.g.,
more vulnerable layers or tasks-specific layers), 4) Addition
of sub-task 5) Adding extra layers to achieve more accuracy
for specific tasks.
Workflow:
1) Data Preprocessing and Model Creation: Different tasks
are emulated as different datasets. i.e., Execution of a single
task would mean performing a classification task on a sin-
gle dataset. Thus, for three tasks, we have considered three
datasets (i.e., radar samples for hand gesture detection, SVHN,
MNIST) from two different modalities (i.e., radar and camera
image), illustrated in Fig. 1(a)(b)(c). These three tasks are exe-
cuted on one CNN accelerator in a time-division multiplexing
(TDM) manner. Before training, the dataset needs to be trans-
formed. CNNs perform extremely well on images and patterns.
Therefore, in order for CNN to learn the common represen-
tations in different tasks, the dataset of all the tasks needs
to be transformed into images. Task 2 (T2) consists of the
SVHN dataset, which is RGB image samples, and therefore
they don’t need any additional transformation. While task 3
(T3) is a grayscale dataset, and task 1 (T1) is from a differ-
ent modality. And thus, T1 and T3 need to be preprocessed
and transformed before CNN training. Data preprocessing
of T1 consists of collecting the raw radar data, extracting
information by fast Fourier transform (FFT), removing the
clutter, and fusing the range, velocity, and angle feature maps.
Additional technical details of the radar dataset are available
in [9].
T3 is a modified version of the MNIST dataset. The
original MNIST dataset consists of 2-dimensional grayscale
SYED et al.: TOWARDS RECONFIGURABLE CNN ACCELERATOR FOR FPGA IMPLEMENTATION
Fig. 2. (a) Tasks execution on application specific accelerators (b) Runtime reconfigurable CNN accelerators (c) Tasks execution on FM (d) Control element
(e) Workflow (f) Tasks execution on BM (g) CNN architecture with trainable params: 14926.
images. The T3 dataset has been converted to a 3-dimensional
RGB image, and noise has been added additionally to make
the whole dataset more challenging. Two colors have been
introduced in the dataset, (i.e., red and green) for subtasks
classification. The last step is resizing all tasks to the exact
dimensions, i.e., 32 x 32 x 3, so that there is a match between
the input dimensions of the images and CNN layers.
Model Creation, Training and Testing FM and BM: The
CNN architecture, illustrated in Fig. 2(g), has been created
using Tensor flow/Keras and Qkeras [10]. Following data pre-
processing and model creation, training and testing of the
model can be accomplished (Fig. 2(e)). FM training can be
treated as a single task learning and follows a standard train-
ing process in which the dataset now consists of three different
tasks, and all the output layers have classes representing all
three tasks.
BM training can be performed using two methods. 1) MTL
method 2) Transfer learning method. MTL method consists
of training multiple tasks jointly by optimizing multiple loss
functions. In this way, the common layers learn the shared rep-
resentations between related tasks, and the task-specific branch
learns to perform well on a specific task. As all the tasks are
being optimized simultaneously, it may happen that the train-
ing of all the tasks does not converge to the desired accuracy.
Therefore, an alternative method of transfer learning (TL) can
be applied. TL training method consists of a multi-stage train-
ing process. 1) First, the entire model is trained as an FM. The
last layer of the model is removed, leaving behind the layers
which are trained on all three tasks. 2) Freeze the weights
of the shared layers 3) Add task-specific layers to the model
and train each task individually 4) If a task has additional
sub-tasks, they can also be trained similarly.
Additional model optimization methods (i.e., pruning and
quantization) are also added to the training loop. Many exper-
iments have concluded that there are many parameters in the
DNNs that are not of much significance. It is still feasi-
ble to achieve the expected performance in the absence of
these parameters. This situation may occur when the neural
network’s parameters are zero, close to zero, or are replicated.
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1251
Thus, pruning is a way to remove unnecessary parameters
that do not significantly contribute to the accuracy of results,
thereby making the deep neural networks sparsed. This spar-
sity in the neural network parameters due to the pruning
has two advantages; a) it causes a significant reduction in
hardware resources, which further helps reduce the compu-
tational complexity, and b) It improves the resiliency of the
DNN model [11]. The focus of our implementation is on the
magnitude-based weight pruning method.
DNN quantization refers to a method of approximating
a neural network’s parameters and activations to low bit-
width fixed point (FxP) numbers because, in many cases, the
dynamic range that the floating-point (FP) provides is not
needed. FxP numbers are generally hardware-friendly. FxP
computations are not only faster than FP but also cost less
area overhead as compared to FP computations. Quantization
also happens to increase the reliability of the DNN model [12].
Hence, we can expect significant benefits in terms of model
size and reliability after model quantization. Both model
optimization methods lead to reduced hardware resources and
power consumption and have become the de-facto step during
the DNN deployment on the hardware. Accuracy results on
the test set for FM and BM are demonstrated in the Table I
HLS4ML Framework: The hls4ml [13] is an open-source
framework designed to deploy machine learning (ML) models
on FPGAs, especially for low-latency and low-power process-
ing at the edge. After achieving the desired test accuracy, the
hls4ml framework can be used to convert the trained model
into an HLS-compatible C/C++. The hls4ml framework takes
into account some parameters for generating the synthesizable
C/C++. These parameters include FPGA part no., interface
type, reuse factor (R), and FxP precision. The parameter reuse
factor determines the parallelism in the hls4ml generated DNN
model (Fig. 3(b)). Multiplication is the most fundamental
operation in neural networks as it involves the multiplication of
the weight with the input. After multiplication, a bias is added,
and the result is passed to an activation function. The reuse
factor is equal to 1 would mean the design is highly parallel
and would generate the HLS model with the lowest possible
1252 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 70, NO. 3, MARCH 2023
TABLE I
E XPERIMENTAL R ESULTS
Fig. 3. (a) FMQP weights distribution (b) Impact of different reuse factors
values on DSP48E utilization for the computation between 2 neuron pairs [13].
latency. If the reuse factor is increased by a factor N, the HLS
compiler will try to reduce the DSP resource by ∼1/N, which
will result in an increase in the overall latency of the model
by ∼N. The parameter ‘precision’ is used by hls4ml to per-
form quantization. The default precision in hls4ml is <16, 6>,
which means the model will be quantized to FxP 16 bits in
which 6 bits are integer bits (including the sign bit) and the
remaining 10 bits are fractional bits. The ‘precision’ parameter
is adjusted until it achieves the desired accuracy. Hls4ml com-
piles the model and calculates the model’s accuracy (termed
as hls4ml accuracy) using bit-accurate fixed point emulation
of the FPGA inference code.
FM, being un-branched, can be easily converted to HLS-
compatible C/C++. The hls4ml, version 0.6.0, does not
support the HLS code generation of BM. We propose a
workaround to use this framework for BM as well. 1) Dissect
the BM in linear branches 2) Using hls4ml, generate HLS
for each branch separately 3) Generate HDL code of all
branches using Vivado HLS 4) Stitch all branches in HDL
using control element (CE) (Fig. 2(d)). CE, 1) synchronize
the data and control signals between the stitched branches,
and 2) enable/disable single or multiple branches based on
the tasks.
III. R ESULTS AND D ISCUSSION
Following the workflow elaborated in the previous section,
we have created five CNN models. i.e., fused model (FM),
fused model pruned (FMP), fused model quantized (FMQ),
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fused model quantized and pruned (FMQP), and branched
model quantized and pruned (BMQP). Experimental results
are illustrated in the Table I. The latency of all the models is
calculated from RTL simulation, and power is estimated during
post-synthesis functional simulation using a switching activity
file of the design (i.e., SAIF file). All the models are synthe-
sized in Vivado, targeting Virtex UltraScale+ VCU118 (FPGA
part no. xcvu9p-flga2104-2L-e) at 200 MHz clock frequency.
All the models have maintained an average of above 90% accu-
racy for all three tasks on one application-specific accelerator,
unlike other studies where only one accelerator is optimized
to perform just one task.
FM is the non-optimized baseline implementation, has good
accuracy for all three tasks, and utilizes the most hardware
resources and power. FMP is a 50% pruned version of FM.
The high accuracy of FM and FMP comes at the cost of
increased resource utilization and power consumption as these
two models are post-training homogeneously quantized to <
20, 10>bit-widths (BW). This provides FM and FMP with
a good dynamic range and helps avoid any saturation and
wrap-around issues. Decreasing the BW of FM and FMP will
decrease their accuracy due to the loss of dynamic range. Thus,
precision tuning is required, not just in the neural network
weights but also in the activation functions. FMQ is trained
directly with lower precision (i.e., quantization-aware training
(QAT)). Any loss in accuracy due to loss of precision can
be rectified during the training process, and the model learns
to perform better in low BW. FMQ performs equally well in
terms of accuracy while consuming fewer hardware resources
and power. DSPs are a scarce resource, and these DSP hard
macros consume more power than LUTs. During the synthesis
of FQM, trained on low BW using QAT, the simpler multi-
plication operations are mapped on LUTs instead of DSPs,
leading to savings in DSP usage and power consumption.
FMP removes the unnecessary weights, but the existing
weights have high BW due to homogeneous PTQ. FMQ has
low BW due to heterogeneous QAT, but this model is not
pruned. Heterogeneous QAT and pruning are combined in
FMQP (see fig. 3(a)) to achieve the best possible results in
terms of accuracy, hardware resources, and power consump-
tion. BMQP is obtained using the multi-stage transfer learning
training method, and its HLS code is generated using the
SYED et al.: TOWARDS RECONFIGURABLE CNN ACCELERATOR FOR FPGA IMPLEMENTATION
workaround described in the previous section. BMQP has
achieved slightly higher accuracy as compared to FMQP.
In BMQP, multiple branches can be active simultaneously,
thereby supporting the classification of multiple sub-tasks.
Thus, for task 3, two branches get active to classify digits (T3)
and the color of the digits (T3c).1 BMQP consumes slightly
more hardware resources and power consumption as compared
to FMQP but has additional benefits from the reliability point
of view. The impact of quantization and pruning is the same in
BM; therefore, only the results of BMQP are shown. As evi-
dent from the FMP, FMQP, and BMQP results, pruning not
only helps reduce hardware resources but also improves the
model’s accuracy.
The latency of all the fused models is approximately the
same. The latency of the hls4ml generated CNN architec-
ture is dependent on the depth of the network, reuse factor
(R = 1) of DSPs, and size of the input (32 x 32 x 3). All
three parameters are similar for FM, FMP, FMQ, and FMQP.
The execution of the layers is sequential. Subsequent layers
can only process the data when the previous layer finishes
its computation. Therefore, for hls4ml, it is recommended to
have a wider network (more kernels/parameters in a layer) as
opposed to more layers (depth of the DNN), as it is more effi-
cient to parallelize per-layer computations in FPGA. Latency
is not affected by the quantization bit widths, kernel size, and
the number of kernels. This is why fused models being differ-
ent in terms of quantization bits and pruning percentage, have
the same latency. Each task has varied latency in BMQP, as
each task goes through only specific layers. i.e., T3c branched
earliest and has the lowest latency, while T2 branched at the
last layer and therefore has the highest latency in BMQP.
T3c latency is not added to the total latency, as T3 and T3c
branches execute in parallel. Our hardware results match the
analysis presented in [13]. Finding the best match of hardware
resource utilization, accuracy, power, and latency depend on
the specific application and the available hardware resources
in the targeted hardware.
IV. R ECONFIGURABLE CNN ACCELERATORS
We have discussed numerous interpretations of ‘reconfig-
urability’ in Section I. We approach reconfigurability from
the standpoint of hardware reliability, aging, and computing
performance. Execution of multiple tasks in different modes,
often associated with microprocessors [14], [15], is possible
in an application-specific CNN accelerator during runtime. By
default, one accelerator is enough to perform three tasks, but
with triple modular redundancy, it is possible to execute tasks
in 1) Fault tolerant (FT) mode, 2) De-stress mode (DS), and
3) High performance (HP) mode (Fig. 2(b)). FT mode: In this
mode, all tasks execute on all three accelerators, thereby pro-
viding maximum reliability. DS mode: this is an aging-aware
mode, only one accelerator is active at a time, and all tasks are
executed in a TDM fashion. HP mode: This mode runs all the
tasks in parallel, i.e., each accelerator executes the individual
task, which leads to a reduction in total latency by 2x. Using
1 Values marked with superscript ‘1’ in Table I are additional resource
utilization when T3c is added.
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1253
traditional approaches to perform these modes (e.g., FT mode)
will require nine CNN accelerators.
V. C ONCLUSION AND F UTURE W ORK
The proposed methodology leverages fundamental working
principles of CNNs and assists in executing three different
tasks on one optimized application-specific CNN accelera-
tor, thereby significantly reducing hardware resources and
power. Workflow, experimental results, and an extension of the
proposed approach to make a reconfigurable CNN accelerator
are presented.
Future work will focus on assisting the existing runtime
reconfigurability with dynamic partial reconfigurability (DPR)
and on-chip reliability sensors, thereby aiming toward a fully
adaptive AI processing system that can adapt based on the
changing real-time and application-specific design require-
ments. Additionally, comprehensive fault analysis against
different fault models will also be performed.
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