Mpi Unit 3

GYANMANJARI INSTITUTE OF TECHNOLOGY
Bachelor of Engineering | Semester : 6 | Computer Engineering
Microprocessor and
Interfacing
Course Code : 3160712
Prof. Mayank K. Champaneri

Computer Engineering Department
SYLLABUS
UNIT TITLE % WEIGHTAGE

1 Introduction to Microprocessor 8%
2 Microprocessor Architecture and Operations 7%
3 8085 Microprocessor 12%
4 Assembly Language Basics 13%
5 8085 Assembly Language Programs 12%
6 Stack and Subroutines 13%
7 I/O Interfacing 20%
8 Advanced Microprocessor 15%

UNIT : 3
8085 Microprocessor
4
Topics
Looping to be covered
  Introduction to 8085
 8085 Programming Model
 Bus Organization of 8085
 8085 pin diagram
 8085 Architecture/Block Diagram
 T-States, Machine and Instruction Cycle
 Demultiplexing Address and Data Bus AD0-AD7
 Timing Diagram
 Memory Interfacing
 Generating Control Signals
5
Topic : 1
Introduction to 8085
6
 8085 is pronounced as "eighty-eighty-five" microprocessor.
 It is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology.
7
 8 bit General purpose microprocessor (i.e. 8 bit data bus).

 It is a single chip NMOS device with 40 pins.
 It has multiplexed address and data bus.(AD0 - AD7).
 It works on 5-Volt DC power supply.
 The maximum clock frequency is 3MHz while minimum frequency is 500kHz.
 It provides 16 address lines, therefore capable of addressing 216= 64K of memory.
 It supports external interrupt request.
 It has two 16 bit registers named program counters (PC) and stack pointer (SP).
8
 It generates 8 bit I/O address so it can access 28 = 256 input ports.

 It provides 5 hardware interrupts:
TRAP
RST 5.5
RST 6.5
RST 7.5
INTR
 It provides accumulator, 5 flag register, 6 general purpose registers and 2 special purpose
registers (SP,PC).
9
Topic : 2
8085 Programming Model

10
General Purpose Registers

Accumulator (A) (8) Flag Register
B (8) C (8)
D (8) E (8)
H (8) L (8)
Stack Pointer (SP) (16)
Program Counter (PC) (16)
Data Bus Address Bus
16
8
Bidirectional Unidirectional
11
 6 general purpose registers to store 8-bit data B, C, D, E, H & L.

 Can be combined as fixed register pairs – BC, DE, HL to perform 16
bit operations.
 Used to store or copy data using data copy instructions.
B (8) C (8)
D (8) E (8)
H (8) L (8)
12
Accumulator A (8) Flag Register
B (8) C (8)
D (8) E (8)
H (8) L (8)
16
8
13
 8 - bit register, identified as A

 Part of ALU
 Used to store 8-bit data to perform
arithmetic & logical operations.
 Result of operation is stored in
Accumulator.
14
S Z  AC  P  CY
:Undefined
P -Parity Flag
S -Sign Flag Set (1) if result has even no. of 1’s &
Set (1) if 7th bit of result is Reset(0) if result has odd no. of 1’s
1;
otherwise reset (0)
CY -Carry Flag
Set (1) if arithmetic
AC -Auxiliary Carry Flag operation results in
Set (1) when carry bit is carry;
Z -Zero Flag generated by 3rd bit & otherwise reset(0)
Set (1) when result is zero; passed to bit 4th bit.
otherwise reset(0)
0 1 0 1 0
+ 0 11 11 0 1 0 0 1
1 00 00 11 0 0 10 01 11 0
AC+= 10 1 1 0 1 0 0 1
1 0 0 1 0 0 1 1
15
Accumulator A (8) Flag Register
B (8) C (8)
D (8) E (8)
H (8) L (8)
16
8
16
Stack Pointer(SP)
 Used as memory pointer.
 Points to the memory location in R/W memory,
called Stack.
 Beginning of stack is defined by loading a 16-bit
address in the stack pointer.
Program Counter(PC)
 Microprocessor uses PC register to sequence the
execution of instructions.
 Its function is to point to memory address from
which next byte is to be fetched.
 When a byte is being fetched, PC is incremented
by 1 to point next memory location.
17
Topic : 3
Bus Organization of 8085

18
CPU Memory Input/Output
Control Bus
Address Bus
Data Bus
System Bus
19
A15
Address Bus
A0
Memory Input
8085 MPU Output
D7
Data Bus
D0
Control Bus
Address Bus
20
 Group of 16 unidirectional lines generally identified as A0 to A15.
i.e. bits flow from microprocessor to peripheral devices.
 16 address lines are capable of addressing 65536 memory locations. So, 8085 has
64K memory locations.
Data Bus
21
 Group of 8 lines identified as D0 to D7.

 They are bidirectional i.e. data flow in both directions between
microprocessor, memory & peripheral.
 8 data lines enable microprocessor to manipulate data ranging from
00 H to FF H (28=256 numbers).
 Largest number appear on data bus is 1111 1111 => (255)10.
 As Data bus is of 8-bit, 8085 is known as 8-bit Microprocessor.
Control Bus
22
 It comprises of various single lines that carry synchronization,

timing & control signals.
 These signals are used to identify a device type with which MPU
intends to communicate.
 Some control signals are Read, Write and Opcode fetch etc.
23
Topic : 4
8085 Pin Diagram

8085 Pin Diagram
8085 Pin Diagram 24
• 8-bit microprocessor.
• Capable of addressing
64K of memory.
• It has 40 pins.
• Requires +5V single
power supply.
8085 Pin Diagram
25
Signals are classified into 6 groups:

1. Address bus
2. Multiplexed address/data bus
3. Control & status signals
4. Power supply & frequency signals
5. Externally initiated signals
6. Serial I/O ports
8085 Pin Diagram
26
Address Bus
 16 signal lines are used as address bus.

 However these lines are split into two
segments: A15 - A8 and AD7 - AD0
 A15 - A8 are unidirectional and used to carry
high-order address of 16-bit address.
 AD7 - AD0 are used for dual purpose.
8085 Pin Diagram
27
Multiplexed address/data bus
 Signal lines AD7-AD0 are bidirectional and

serve dual purpose.
 They are used as low-order address bus as
well as data bus.
 The low-order address bus can be separate
from these signals by using a latch (ALE).
8085 Pin Diagram
28
Control & Status signals
To identify nature of operation

 Two Control Signals
1. RD(Read)
2. WR(Write)
 Three Status Signals
1. S1
2. S0
3. IO/M
 To indicate beginning of operation
1. ALE(Address Latch Enable)
ALE  1, then Address bus
ALE  0, then Data bus
8085 Pin Diagram
29
ALE
 This is positive going pulse generated every
time the 8085 begins an operation (machine
cycle).
 It indicates that the bits on AD7-AD0 are
address bits.
 This signal is used primarily to latch the low-
address from multiplexed bus & generate a
separate set of address lines A7-A0.
8085 Pin Diagram
30
RD(Read)
 This is a read control signal (active low)
 This signal indicates that the selected I/O or
Memory device is to be read & data is
available on data bus.
8085 Pin Diagram
31
WR (Write)
 This is a write control signal (active low)
 This signal indicates that the selected I/O
or Memory device is to be write & data is
available on data bus.
8085 Pin Diagram
32
IO/M
 This is a status signal used to differentiate
I/O and memory operation.
 When signal is
High  I/O operation
Low  Memory operation
 This signal is combined with RD and WR to
generate I/O & memory control signals.
8085 Pin Diagram
33
S1 & S0
 These status signals can identify various
operations.
8085 Pin Diagram
34
Power Supply & Frequency Signal
 Vcc  Pin 40, +5V Supply.

 Vss  Pin 20, Ground Reference
8085 Pin Diagram
35
X1, X2
 Pin 1 & 2, Crystal Oscillator is connected
at these two pins.
 The frequency is internally divided by
two;
therefore, to operate a system at 3 MHz,
the crystal should have a frequency of 6
MHz.
8085 Pin Diagram
36
 CLK (OUT)  Clock output

 This signal is used as system clock
for other I/O devices for
synchronization with Microprocessor.
8085 Pin Diagram
37
Externally Initiated Signals
 INTR(Input)  Interrupt Request

It is used for general purpose interrupt.
 INTA(Output)  Interrupt Acknowledge.

8085 Pin Diagram
38
 RST7.5, RST6.5, RST5.5 (Input) 

Restart Interrupts.
 These are vector interrupts that transfer
the program control to specific memory
locations.
 RST7.5, RST6.5, RST5.5 have higher
priorities than INTR interrupt.
 Among these 3 interrupts, the priority
order (higher to lower) is RST7.5, RST6.5,
RST5.5 respectively.
8085 Pin Diagram
39
 TRAP(Input)  This is a non maskable

interrupt & has the highest priority.
8085 Pin Diagram
40
 HOLD(Input)  This signal indicates that a

peripheral such as DMA Controller is
requesting the use of address & data buses.
 HLDA(Output)  Hold Acknowledge. This
signal acknowledges the HOLD request.
8085 Pin Diagram
41
READY(Input) → This signal is used to delay

the microprocessor read or write cycles until
low-responding peripheral is ready to send or
accept data.
When the signal goes low, the microprocessor

waits for an integral no. of clock cycles until
READY signal goes high.
8085 Pin Diagram
42
RESET IN (Input) → When the signal on this

pin goes low, the Program Counter is set to
zero, the buses are tri-stated & microprocessor
is reset.
RESET OUT (Output) → This signal indicates

that microprocessor is being reset. The signal
is also used to reset other devices.
8085 Pin Diagram
43
Serial I/O Ports
Two pins for serial transmission:
SID (Serial Input Data)
SOD (Serial Output Data)
In serial transmission, data bits are sent over a

single line, one bit at a time.
8085 Pin Diagram
44
45
Topic : 5
8085 Architecture Diagram

46
47
8085 consists of the following functional units :
 Registers  Incrementer/Decrementer address latch
 Arithmetic and logic unit  Interrupt control
 Instruction decoder and machine cycle encoder  Serial I/O control
 Address buffer  Timing and control circuitry
 Address/Data buffer
48
Registers
1. General purpose register
 There are 6 general purpose registers in 8085

processor, i.e. B, C, D, E, H & L. Each register can
hold 8-bit data.
 These registers can work in pair to hold 16-bit

data and their pairing combination is like B-C, D-
E & H-L.
49
Registers
2. Special purpose register
 There are 5 special purpose registers in 8085 processor,
(i) Accumulator (ii) Flag Register

(iii) Program Counter (iv) Stack Pointer
(v) Instruction Register
50
Registers
Accumulator :
 It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE
operations.
 It is connected to internal data bus & ALU.
51
Registers
Flag Register :
 It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending
upon the result stored in the accumulator.
 These are the set of 5 flip-flops,
(1) Sign Flag (S) (2) Zero Flag(Z)
(3) Auxiliary Carry (AC) (4) Parity Flag (P)
(5) Carry Flag (C)
52
Flag Registers
Sign flag (S):

 After the execution of arithmetic or logical operations, if bit D7 of the result is
1, the sign flag is set.
 In a given byte if D7 is 1, the number will be viewed as negative number.
 If D7 is 0, the number will be considered as positive number.
Zero flag (Z) :

 The zero flag sets if the result of operation in ALU is zero and flag resets if
result is non zero.
 The zero flag is also set if a certain register content becomes zero following
an increment or decrement operation of that register.
53
Flag Registers
Auxiliary Carry flag (AC):

 This flag is set if there is an overflow out of bit 3 i.e., carry from lower nibble to
higher nibble D3 bit to D4 bit.
 This flag is used for BCD operations and it is not available for the
programmer.
Parity flag (P):

 Parity is defined by the number of ones present in the accumulator.
 After an arithmetic or logical operation if the result has an even number of
ones, i.e. even parity, the flag is set.
 If the parity is odd, flag is reset.
54
Flag Registers
Carry flag (CY):
 This flag is set if there is an overflow out of bit 7.
 The carry flag also serves as a borrow flag for

subtraction. In both the examples shown below,
the carry flag is set.
55
Registers
Program Counter :
 It is a 16-bit register used to store the memory address location of the

next instruction to be executed.
 Microprocessor increments the program whenever an instruction is being

executed, so that the program counter points to the memory address of
the next instruction that is going to be executed.
56
Registers
Stack Pointer :
 It is also a 16-bit register works like stack, which is always
incremented/decremented by 2 during push & pop operations.
Instruction Register :
 It is an 8-bit register.
 When an instruction is fetched from memory then it is stored in the
Instruction register.
57
Arithmetic Logic Unit
 As the name suggests, it performs arithmetic and logical operations like Addition,
Subtraction, AND, OR, etc. on 8-bit data.
 The ALU also looks after the branching decisions.
Instruction decoder and machine cycle encoder

 Instruction decoder decodes the opcode and accordingly gives information to the
timing and control circuit.
 The 8085 executes seven different types of machine cycles. This task is done by
machine cycle encoder.
58
Address Buffer
 This is an 8-bit unidirectional tristate buffer.

 It is used to drive external high order address bus (A15-A8).
Address/Data Buffer
This is an 8-bit bi-directional buffer.

It is used to drive multiplexed address/data bus, i.e. low order address bus
(A7- A0) and data bus (D7 - Do).
59
Incrementer / Decrementer Address Latch
 This 16-bit register is used to increment or decrement the contents of

program counter or stack pointer.
Interrupt Control
 The interrupt control block has five interrupt inputs RST 5.5, RST 6.5, RST 7.5,
TRAP and INTR and one acknowledge signal INTA.
 It controls the interrupt activity of 8085 microprocessor
60
Serial I/O Control
 The 8085's serial I/O control provides two lines, SOD and SID for serial
communication.
 The Serial Output Data (SOD) line is used to send data serially and Serial
Input Data (SID) line is used to receive data serially.
61
Timing and Control Circuitry
 The control circuitry in the processor 8085 is responsible for all the
operations.
 The control circuitry and hence the operations in 8085 are synchronized with
the help of clock signal.
 Along with the control of fetching and decoding operations and generating
appropriate signals for instruction execution, control circuitry also generates
signals required to interface external devices to the processor, 8085.
62
Topic : 6
T-States, Machine Cycle and

Instruction Cycle
T-States, Machine Cycle and Instruction Cycle
63
T-States Operation performed in one clock period.
Time required by the microprocessor to

Machine Cycle complete an operation.
Time required to complete execution of an

Instruction Cycle instruction.
64
T-States
 “T-States are defined as operation performed in one clock period.”
 These sub-divisions are internal states synchronized with system clock & each T-
state is precisely equal to one clock period.
CLK
Clock Period
65
Machine Cycle
m/m Read
 “Machine Cycle is defined as time required by the microprocessor to complete an
operation.“ m/m Read
 This cycle may consist 3 to 6 T-states.

 The basic microprocessor operation such as reading a byte from I/O port or writing
a byte to memory.
Opcode Fetch Memory Read I/O Write
T1 T2 T3 T4 T1 T2 T3 T1 T2 T3
CLK
Machine Machine Machine

Cycle-1 Cycle-2 Cycle-3
66
Instruction Cycle
 “Instruction Cycle is defined as time required to complete execution of an
instruction.”
 In 8085 microprocessor instruction cycle consists of 1 to 6 Machine Cycles or 1 to
6 operations.
CLK
67
Topic : 7
Demultiplexing Address and

Data Bus
A15 0 A15
0 A14 68
1 A13
0 High-
8085 Microprocessor
A12
0 A11 Order
0 A10 Address
Demultiplexing AD0-AD7
0 A9
0 Bus
A8 A8
ALE Enable G ALE=1
AD7 0 A7
0 A6 Address Bus
0 A5
0 A4 Low-
1 A3
0 A2 Order
1 A1 Address
AD0 1 A0
Bus
0 ALE= 0
1 D7 Data Bus
0 D 6
0 D5
1 D4 Data
1 D3 Bus
1 D2
1 D1
D0
Demultiplexing AD0-AD7
 The dual-purpose of the AD0-AD7 pins is achieved through multiplexing.

 In simple words, multiplexing allows us to use the pins of a microprocessor for
more than one function.
 Advantage:Since each pin can serve multiple purposes, the total number of
pins can be reduced.
IC 74LS373
 IC 74LS373 is an IC with 20 pins. IC 74LS373
 it is a memory unit to hold one bit of data.

70
Topic : 8
Timing Diagram
Opcode Fetch
Timing Diagram : Opcode Fetch
CLK
A15
High order memory address Unspecified
A8
AD7 Low order
Opcode
M/m addr.
AD0
ALE
IO/M
RD
Memory read cycle
Timing Diagram : Memory Read Cycle
CLK
A15
High order memory address
A8
AD7 Low order Data from
AD0 M/m addr. memory S1 S0 Mode
0 0 HLT
0 1 WRITE
1 0 READ
ALE
IO/M
S0 IO/M=0, S1=1 , S0=0
S1
RD
Memory write cycle
Timing Diagram : Memory Write Cycle
CLK
A15
High order memory address
A8
AD7 Low order Data from
AD0 M/m addr. Microprocessor S1 S0 Mode
0 0 HLT
0 1 WRITE
1 0 READ
ALE
IO/M
S1 IO/M=0, S0=1 , S1=0
S0
WR
74
Topic : 9
Memory Interfacing
Memory Structure
Block diagram of Memory Device: RAM

N=Number of Register
Data Inputs M=Word Length
E.g.
WR If a memory is having
Input Buffer
CS address lines=13
Internal Decoder
A10
data lines=8
then
Address NXM 1. Number of memory locations
Input Memory = N=213 = 8192
2. Word length M= 8 bit
A0 Therefore, N X M= 8192 X 8
Output Buffer
RD
Data
Output
Memory Structure
Memory Interfacing
 8085 can access 64K of memory, thus address bus is of 16-bit.
 It is not always necessary to use full 64K address space. The total
memory size depends upon the application.
 Generally EPROM is used as a program memory and RAM is used as

data memory.
 When both are used then total 64K address will be shared by both.
 The capacity of program memory and data memory depends on the

application.
Memory Interfacing
 It is not always necessary to select 1 EPROM and 1 RAM. We can

have multiple EPROMs and multiple RAMs as per the requirement of
application.
 We can place EPROM / RAM anywhere in full 64 Kbytes address

space.
 Program memory (EPROM) should be located from address 0000H,

since reset address of 8085 microprocessor is 0000H.
 It is not always necessary to locate EPROM and RAM in consecutive

memory addresses.
Memory Interfacing : Example-1
Interface 4kB of EPROM with starting address from 0000H and 2kB of
RAM with starting address followed by EPROM.
Step-1: To calculate no. of EPROM and RAM chip required
Total EPROM required = 4kB

Chip size available = 4kB
No. of chips required = 4kB/4kB=1
Total RAM required = 2kB

Chip Size Available = 2kB
No. of Chips required = 2kB/2kB=1
Step-2: To calculate starting and ending address of EPROM
EPROM Chip-1:
Starting Address = 0000H
Chip Size = 4kB (i.e. address Line=12, m/m = 212 = 4096B = 4k)
Ending Address = 0FFFH
Step-3: To calculate starting and ending address of RAM

RAM Chip-1:
Starting address = Ending address of EPROM +1
= 0FFFH+1
= 1000H
Chip Size = 2kB = 07FFH
Ending address = 1000H+07FFH
= 17FFH
Step-4: Memory A A A A A A A A A A A A A A A A
Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EPROM 0000 H
4k End
Address
0FFF H 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Start
Address
RAM 1000 H 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
2k End
Address
0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1
17FF H
EPROM chip size = 4kB & RAM chip size = 2kB

smaller chip size RAM = 2kB = 211
Thus neglect lower 11 address lines (A0 to A10), and consider A11 to A15 for Decoding.
A A A A A A A A A A A A A A A A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0000 H
EPROM
End
Address
0FFF H 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
EPROM
• Required Address Lines: A11 to A15.
• Now, EPROM has two Possibilities, either 00000 b or 00001 b.
• Therefore, it requires Y0 and Y1 outputs of decoder.
A A A A A A A A A A A A A A A A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0000 H
EPROM
End
Address
0FFF H 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Start
Address
1000 H 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
RAM
End
Address
17FF H 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1
RAM has 00010 b, hence it requires Y2 output of decoder.

Step-5:
RD
Implementation
IO/M
A0 - A10
WR OE
RD
EPROM
D0
-
Y0 00000 D7
To EPROM
A15 Y1
00001
A14
Y2 To RAM D0 – D7 A0 - A10
A13 5:32 00010
Decoder
A12 OE RAM
A11
85
Topic : 10
Generating Control Signals

I0/M RD WR Operation
0 0 0 Invalid
0 0 1 MEMR
IO/ M 0
MEMR
RD 0
8085
WR 1
0 0 0 Invalid
0 0 1 MEMR
0 1 0 MEMW
IO/ M 0
MEMR
RD 1
8085
WR 0 MEMW
0 0 0 Invalid
0 0 1 MEMR
0 1 0 MEMW
0 1 1 NOP
IO/M 0
MEMR
RD 1
8085
WR 1 MEMW
0 0 1 MEMR
0 1 0 MEMW
0 1 1 NOP
1 0 0 Invalid
IO/M 1
MEMR
RD 0
8085
WR 0 MEMW
0 0 1 MEMR
0 1 0 MEMW
0 1 1 NOP
1 0 1 IOR
IO/M 1
MEMR
RD 0
8085
WR 1 MEMW
IOR
0 0 1 MEMR
0 1 0 MEMW
0 1 1 NOP
1 0 1 IOR
1 1 0 IOW
IO/M 1
MEMR
RD 1
8085
WR 0 MEMW
IOR
IOW
0 0 1 MEMR
0 1 0 MEMW
0 1 1 NOP
1 0 1 IOR
1 1 0 IOW
1 1 1 NOP
IO/M 1
MEMR
RD 1
8085
WR 1 MEMW
IOR
IOW
0 0 0 HLT
0 0 1 MEMR
0 1 0 MEMW
0 1 1 NOP
1 0 0 HLT
1 0 1 IOR
1 1 0 IOW
1 1 1 NOP
THANK YOU

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GYANMANJARI INSTITUTE OF TECHNOLOGY

Bachelor of Engineering | Semester : 6 | Computer Engineering

Prof. Mayank K. Champaneri

UNIT TITLE % WEIGHTAGE

2 Microprocessor Architecture and Operations 7%

3 8085 Microprocessor 12%

4 Assembly Language Basics 13%

5 8085 Assembly Language Programs 12%

6 Stack and Subroutines 13%

7 I/O Interfacing 20%

8 Advanced Microprocessor 15%

 8 bit General purpose microprocessor (i.e. 8 bit data bus).

 It generates 8 bit I/O address so it can access 28 = 256 input ports.

8085 Programming Model

General Purpose Registers

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

 6 general purpose registers to store 8-bit data B, C, D, E, H & L.

Accumulator A (8) Flag Register

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

 8 - bit register, identified as A

Accumulator A (8) Flag Register

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

Bus Organization of 8085

CPU Memory Input/Output

8085 MPU Output

 Group of 8 lines identified as D0 to D7.

 It comprises of various single lines that carry synchronization,

8085 Pin Diagram

Signals are classified into 6 groups:

 16 signal lines are used as address bus.

Multiplexed address/data bus

 Signal lines AD7-AD0 are bidirectional and

To identify nature of operation

Control & Status signals

Control & Status signals

Control & Status signals

Control & Status signals

Control & Status signals

Power Supply & Frequency Signal

 Vcc  Pin 40, +5V Supply.

Power Supply & Frequency Signal

Power Supply & Frequency Signal

 CLK (OUT)  Clock output

Externally Initiated Signals

 INTR(Input)  Interrupt Request

 INTA(Output)  Interrupt Acknowledge.

Externally Initiated Signals

 RST7.5, RST6.5, RST5.5 (Input) 

Externally Initiated Signals

 TRAP(Input)  This is a non maskable

Externally Initiated Signals

 HOLD(Input)  This signal indicates that a

Externally Initiated Signals

READY(Input) → This signal is used to delay

When the signal goes low, the microprocessor

Externally Initiated Signals