Public Version

Photovoltaic Module Integrated dc-dc Converters: Modulation
and Advanced Control Techniques.
Author:
Callegaro, Leonardo
Publication Date:
2018
DOI:
https://doi.org/10.26190/unsworks/20724
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Photovoltaic Module Integrated dc-dc Converters
Modulation and Advanced Control Techniques
by
Leonardo Callegaro
A thesis submitted in fulfilment of the requirements for the degree of
Doctor of Philosophy
School of Electrical Engineering and Telecommunications
The University of New South Wales
c Leonardo Callegaro
September 2018
Sydney, NSW, Australia
Thes.is/Dissertation Sheet
Australia's
Global
University
Surname/Family Name Callegaro

Given Name/s Leonardo
Abbreviation for degree as give in the University calendar PhD
Faculty Engineering
School School of Electrical Engineering and Telecommunications
Photovoltaic Module Integrated de-de Converters Modulation and Advanced
Thesis Title
Control Techniques
Abstract 350 words maximum: (PLEASE TYPE)
In modem photovoltaic (PV) systems, de-de converters are Integrated with every PV module, increasing energy harvest in conditions of non-uniform
solar irradiation and electrical characteristic mismatching. This thesis is focussed on the analysis of a PV module interfacing de-de converter (de-MIC),
covering modelling. modulation and advanced control techniques. In the studied application, each PV module is feeding a dc.-MIC, and the de-MIC
outputs are series-connected. The non-inverting buck-boost is the selected de-MIC topology, as It is one of the most promising candidates for the
chosen application. Before describing the contributions on de-MIC control, a chapter of this thesis Is dedicated to PV modelling. The understanding of
this subject is essential to simulate any PV interfacing converter. As a result, a pragmatic review of PV modelling techniques is made, describing PV
equivalent circuit parameter estimation and simulation of the PV module electrical characteristic. The operation of the non-inverting buck-boost de-MIC
is then analysed. One research contribution presented, gives evidence of the Improvement of the converter performance during the changeover
between buck and boost operating modes. Attention is then devoted to modelling and controller design, according to linear control theory. The 'small
signal model of the non-inverting buck-boost de-MIC is derived, a linear cascaded controller is designed, and its transient performance is assessed in
comparison with a traditional single-loop voltage controller. Finally, a non-linear converter control technique is covered, which is the feedback
linearisation control (FLC) technique. FLC allows analysing the cornverter as a linear system, whose transfer functions are Independent of the operating
point. Furthermore, the FLC technique yields significant simpllficatlon of the controller design and enhances the PV module voltage regulation siuality.
Last. the dynamic performance of the de-MIC under FLC and cascaded control is compared. All converter control techniques are digitally imp1e·mented
in a floating point microcontroller. driving a 250 W de-MIC prototype, having a switching frequency of 200 kHz. The outlined converter control
techniques can be directly implemented in existing dc-MICs, adding value to state of the art control for PV interfacing de-de converters.
Declaration relating to disposition of project thesis/dissertation
I hereby grant to the University of New South Wales or its agents the right to archive and to make available my thesis or dissertation in whole or in part
in the University libraries in all forms of media, now or here after kn own, subject to the provisions of the Copyright Act 1968. I retain all property rights.
such as patent rights. I also retain the right to use In future works (such as articles or books) all or part of this thesis or dissertation.
I also authorise University Microfi!ms to use the 350 word abstract of my thesis in Dissertation Abstracts International (this is applicable to doctoral
theses only).
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for a period of up to 2 years must be made In writing. Requests for a longer period of restriction may be considered in exceptional circumstances and
require the approval of the Dean of Graduate Research.
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ORIGINALITY STATEMENT
‘I hereby declare that this submission is my own work and to the best of my
knowledge it contains no materials previously published or written by another
person, or substantial proportions of material which have been accepted for the
award of any other degree or diploma at UNSW or any other educational
institution, except where due acknowledgement is made in the thesis. Any
contribution made to the research by others, with whom I have worked at
UNSW or elsewhere, is explicitly acknowledged in the thesis. I also declare that
the intellectual content of this thesis is the product of my own work, except to
the extent that assistance from others in the project's design and conception or
in style, presentation and linguistic expression is acknowledged.’
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‘I hereby grant the University of New South Wales or its agents the right to
archive and to make available my thesis or dissertation in whole or part in the
University libraries in all forms of media, now or here after known, subject to the
provisions of the Copyright Act 1968. I retain all proprietary rights, such as patent
rights. I also retain the right to use in future works (such as articles or books) all
or part of this thesis or dissertation.
I also authorise University Microfilms to use the 350 word abstract of my thesis in
Dissertation Abstract International (this is applicable to doctoral theses only).
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Abstract
Photovoltaic (PV) energy generation is one of the most prominent technologies for the
clean production of electricity. In PV systems of any scale, power electronic converters
are the essential interface between the renewable energy generators and the load. Tra-
ditionally, multiple PV modules are interfaced to one converter with maximum power
point tracking (MPPT) capability. Although this is a well-known and simple architecture,
research has highlighted the loss of energy attributed to partial shading and electrical
characteristic mismatching among PV modules. During the last two decades, substantial
research and industry efforts converged towards distributed maximum power point track-
ing (DMPPT) architectures adopting interfacing converters, referred to as module inte-
grated converters (MICs), on a per-PV module basis. These architectures maximise energy
harvest, regardless of partial shading or electrical characteristic mismatching among PV
modules. Other advantages include the possibility of operating PV modules of distinct
technology together, or of varying power rating, or installed along different orientations.
Moreover, MICs provide opportunities for granular monitoring and diagnostic of PV sys-
tems, since the health status of individual PV modules may be observed through the con-
verters.
This thesis is focussed on the analysis of a PV interfacing dc-dc converter (dc-MIC),
involving modelling, modulation and advanced control techniques. In the studied appli-
cation, each PV module feeds a dc-MIC, and the dc-MIC outputs are connected in series.
The non-inverting buck-boost is the selected converter topology, as it is one of the most
promising candidates for DMPPT. Before describing the contributions on dc-MIC control,
a chapter of this thesis is dedicated to PV modelling, as the understanding of this topic
is necessary to simulate any PV interfacing converter. Firstly, a pragmatic review of PV
modelling techniques is undertaken, describing the PV equivalent circuit parameter esti-
mation. Secondly, a contribution to the practical simulation of the PV module electrical
characteristic is outlined. The operation of the non-inverting buck-boost dc-MIC is then
analysed. One research contribution presented, gives evidence of the improvement of the
converter performance during the changeover between buck and boost operating modes.
Attention is then devoted to modelling and controller design, according to linear control
techniques. The small-signal model of the non-inverting buck-boost dc-MIC is derived,
and a cascaded controller is designed. Its performance is compared against a traditional
ii
single-loop voltage controller. It is verified that the cascaded controller yields a consid-
erable improvement in the regulation of the PV module voltage, as it greatly reduces the
disturbance caused by the operation of the gate driving circuit. The final contribution re-
gards the utilisation of the feedback linearisation control (FLC) technique to the dc-MIC
application. This emerging non-linear control technique provides the benefit of analysing
the converter as a linear system, whose dynamic behaviour is independent of the oper-
ating point. The dynamic performance of the dc-MIC under FLC and cascaded control is
experimentally compared. It is proven that, with FLC, the converter transient response is
indeed insensitive to the system operating point, further enhancing the PV module volt-
age regulation. All converter control techniques are digitally implemented in a floating
point microcontroller, driving a 250 W dc-MIC prototype, having a switching frequency of
200 kHz. The outlined converter control techniques can be applied in existing dc-MICs,
adding value to state of the art control for PV interfacing dc-dc converters.
Acknowledgements
I would like to express my heartfelt gratitude to my main supervisor, Dr Mihai Ciobotaru,

for his invaluable contribution to my professional development, for his patience, and for
openly sharing his research experience. I am thankful to my co-supervisor, Prof. John
Fletcher, for the guidance he kindly provided, and for his active and generous involve-
ment in my research. Thanks also to Prof. Vassilios Agelidis, for the inspiring technical
discussions we had at the start of my research project.
I am profoundly thankful to Dr Lóránd Bede, from Aalborg University (Denmark), for
passionately transmitting necessary know-how in the area of microcontroller program-
ming, power electronics converter design and manufacturing technology. Thanks also to
Mr Eugenio Turano, from the Polytechnic University of Milan (Italy), for engaging in pro-
ductive research talks on photovoltaic module interfacing converters. I sincerely thank
Prof. Daniel Pagano, from the Federal University of Santa Catarina (Brazil), for sharing
his knowledge of control for power electronics, for the genuine interest demonstrated in
my research, and for the productive collaboration. Thanks to Dr Baburaj Karanayil, for the
tireless support he provided on matters concerning with the power electronics laboratory,
and thanks to Dr Ricardo Aguilera, Dr Pablo Acuna, Dr Georgios Konstantinou and Prof.
Josep Pou for the constructive technical consultations.
I would like to thank the fellow PhD students of the School of Electrical Engineering
and Telecommunications of The University of New South Wales. It was a pleasure to work
alongside Milad, Roky, Harith, Ghias, Taekyun, Damith, Guishi, Amer, Rosheila and all
those who I have inadvertently forgotten to mention, and who contributed to creating a
helpful and friendly research environment.
Finally, this endeavour would not have been possible without the unconditional love
and support of my wife, Amanda, to whom I am grateful for inspiring me to be open-
minded and to look forward. I would like to thank my family and my friends for always
standing by my side.
This research was funded by the Australian Government Research Training Program Schol-
arship and The University of New South Wales’ School of Electrical Engineering and
Telecommunications.
iii
Contents
Abstract i
Acknowledgements iii
List of Figures vii
List of Tables ix
1 Introduction 1
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Energy Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 Architectures of Grid Connected PV systems . . . . . . . . . . . . . . 2
1.1.3 Energy Recovery Potential of dc-MICs . . . . . . . . . . . . . . . . . 4
1.2 Overview of the Non-Inverting Buck-Boost Converter . . . . . . . . . . . . . 6
1.3 Motivation and Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Methodology and Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Scientific Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5.1 List of Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.6 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 PV Modelling Techniques
for Power Electronics Simulation 15
2.1 PV Modelling Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Equivalent Circuit Parameter Estimation . . . . . . . . . . . . . . . . . . . . 17
2.3 Review of Parameter Estimation Techniques . . . . . . . . . . . . . . . . . . 18
2.3.1 First Analytical Method . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.2 Second Analytical Method . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.3 First Numerical Method . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.4 Second Numerical Method . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.5 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4 Environmental Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5 EN5030 Standard Modelling . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.6 Modelling Based on 3D Lookup Tables . . . . . . . . . . . . . . . . . . . . . 27
2.6.1 3D Lookup Table for the PV Current . . . . . . . . . . . . . . . . . . 28
2.6.2 Non-Uniform Solar Irradiation Effects . . . . . . . . . . . . . . . . . 31
iv
Contents v
2.6.3 General Considerations on the Creation and Use of 3D LUTs . . . . . 34

2.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3 Non-Inverting Buck-Boost Converter 38

3.1 Integration with PV Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2 Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3 Buck-Boost Transition Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.1 Transition Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.2 Ideal Operating Scenario: Unconstrained Duty Cycles . . . . . . . . . 47
3.3.3 Actual Operating Scenario: Constrained Duty Cycles . . . . . . . . . 48
3.3.4 Review of Smooth Transition Techniques . . . . . . . . . . . . . . . . 51
3.3.5 Proposed Smooth Transition Technique . . . . . . . . . . . . . . . . . 52
3.4 Experimental Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.4.1 Experimental Setup Description . . . . . . . . . . . . . . . . . . . . . 55
3.4.2 Operational Constraints . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.4.3 Open-Loop Test Results . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.4.4 Closed-Loop Test Results . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4 Linear Control of the Non-Inverting Buck-Boost dc-MIC 70

4.1 Small-Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.1.1 Output Voltage vs. Input Voltage Regulated Converters . . . . . . . 71
4.1.2 Small-Signal Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.2 Controller Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.2.1 Single Loop Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.2.2 Cascaded Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5 Non-linear control of the Non-Inverting Buck-Boost dc-MIC 86

5.1 Feedback Linearisation Control Technique . . . . . . . . . . . . . . . . . . . 86
5.2 Feedback Linearisation Control Laws . . . . . . . . . . . . . . . . . . . . . . 87
5.2.1 Buck Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.2.2 Boost Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.3 Controller Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6 Conclusions 99
6.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Appendix A 103
Appendix B 105
Contents vi
Bibliography 115
List of Figures
1.1 Evolution of PV installations . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Power electronics architectures in grid connected PV systems . . . . . . . . . 3
1.3 String composed of two series connected PV modules, with bypass diodes . 5
1.4 Electrical characteristics of the PV string, in function of the string voltage . . 5
2.1 PV module equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2 Evaluation of Rso and Rpo . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3 Comparison of curves obtained using the parameters from the reviewed
estimation methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4 Current vs. voltage curves, for a 185 W multicrystalline PV module . . . . . 26
2.5 3D lookup table for the PV current . . . . . . . . . . . . . . . . . . . . . . . 29
2.6 3D lookup table calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.7 PV module current ipv for varying PV module voltage vpv and solar irradia-
tion G, at a constant temperature . . . . . . . . . . . . . . . . . . . . . . . . 31
2.8 String composed of three series connected PV modules, with bypass diodes . 32
2.9 Electrical characteristics of the PV string in Fig. 2.8 . . . . . . . . . . . . . . 33
2.10 Comparison between equation based and 3D-LUT based models . . . . . . . 34
2.11 Comparison of i-v curves calculated by means of modelling equations and
via the PLECS 3D Lookup Table function . . . . . . . . . . . . . . . . . . . . . 35
2.12 Comparison of i-v curves calculated by means of (2.27) and via the PLECS
3D Lookup Table function [44] having a fine ∆T . . . . . . . . . . . . . . . . 36
3.1 PV string equipped with dc-MICs, feeding a single phase PV inverter . . . . . 39

3.2 PV string with two dc-MICs and the PV inverter . . . . . . . . . . . . . . . . 40
3.3 PV module and dc-MIC operating points, for the string in Fig. 3.2 . . . . . . 41
3.4 PV string without dc-MICs, and non-uniform solar irradiation, feeding a
single phase PV inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.5 PV string with multiple dc-MICs, feeding a single phase PV inverter . . . . . 43
3.6 Non-inverting buck-boost dc-MIC, with synchronous rectifier switches, power
and control stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.7 Non-inverting buck-boost dc-MIC power stage with dedicated pass-through
switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.8 Non-inverting buck-boost converter modulation strategy . . . . . . . . . . . 46
3.9 Ideal duty cycle characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.10 Gate driver and bootstrap circuit operation . . . . . . . . . . . . . . . . . . . 48
3.11 Control signal pulsed waveforms . . . . . . . . . . . . . . . . . . . . . . . . 49
vii
List of Figures viii
3.12 Actual duty cycle characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.13 Ideal vs. actual voltage gain function . . . . . . . . . . . . . . . . . . . . . . 50
3.14 Non-inverting buck-boost converter voltage gain function, when both legs
are operated with identical duty cycle . . . . . . . . . . . . . . . . . . . . . 51
3.15 Duty cycle variation when the proposed compensation technique is applied . 54
3.16 Control signal compensation logic to obtain the duty cycles displayed in
Fig. 3.15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.17 Elements designed and built for the experimental setup . . . . . . . . . . . . 56
3.18 Circuit modelling the charge of the bootstrap capacitor . . . . . . . . . . . . 58
3.19 Configuration adopted for the open loop tests . . . . . . . . . . . . . . . . . 60
3.20 Open loop test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.21 Configuration adopted for the closed loop tests . . . . . . . . . . . . . . . . 62
3.22 Effect of operating mode transition due to output voltage change, with con-
stant input voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.23 Effect of operating mode transition due to output voltage change, with input
voltage tracking the MPP reference . . . . . . . . . . . . . . . . . . . . . . . 67
3.24 Effect of operating mode transition due to output voltage change, with input
voltage tracking the MPP reference, in a worst case scenario . . . . . . . . . 68
4.1 Power stage considered for deriving the dc-MIC small-signal model . . . . . 72
4.2 Voltage mode control block diagram (VMC) . . . . . . . . . . . . . . . . . . 76
4.3 Cascaded control block diagram (ACMC) . . . . . . . . . . . . . . . . . . . . 76
4.4 Bode plot of duty cycle to (measured) PV module voltage transfer functions 78
4.5 Bode plot of duty cycle to (measured) inductor current transfer functions . . 78
4.6 Bode plot of the open-loop transfer function, in VMC . . . . . . . . . . . . . 79
4.7 Bode plot of closed-loop transfer function for the inner current loop . . . . . 80
4.8 Bode plot of the plant transfer function for the outer voltage loop, in ACMC 81
4.9 Bode plot of the open-loop transfer function for the outer voltage loop, in
ACMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.10 PV module voltage and inductor current behaviour in response to PV mod-
ule voltage reference step of 1 V . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.11 PV voltage and inductor current steady-state behaviour between two boot-
strap capacitor recharging pulses . . . . . . . . . . . . . . . . . . . . . . . . 84
4.12 Steady state waveforms when the converter is operating under the special
buck-boost mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.1 Block diagram for designing the current controller . . . . . . . . . . . . . . 88

5.2 Block diagram for designing the voltage controller . . . . . . . . . . . . . . 90
5.3 Feedback linearization control scheme for buck operation . . . . . . . . . . 91
5.4 Feedback linearisation control scheme for boost operation . . . . . . . . . . 92
5.5 Cascaded controller used for comparison purpose . . . . . . . . . . . . . . . 94
5.6 Operating points on the PV module i-v curve at which different step re-
sponses have been observed . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.7 PV module voltage and inductor current dynamics in response to PV voltage
reference steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
List of Tables
1.1 Configuration overview of grid connected PV systems . . . . . . . . . . . . . 4

1.2 Documented energy recovery potential of dc-MICs . . . . . . . . . . . . . . 7
1.3 Notable research contributions on dc-MIC topologies . . . . . . . . . . . . . 8
1.4 Relationship between publications and thesis chapters . . . . . . . . . . . . 14
2.1 Estimated modelling parameters for the PV module KC200GT . . . . . . . . 23

2.2 Technology dependent parameters . . . . . . . . . . . . . . . . . . . . . . . 28
3.1 Operating modes and switch duty cycles for the converter in Fig. 3.6) . . . . 44
3.2 dc-MIC prototype parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3 Emulated PV module parameters . . . . . . . . . . . . . . . . . . . . . . . . 63
4.1 Steady state regime of a PV string with 2 dc-MICs . . . . . . . . . . . . . . . 77
5.1 PV module voltage step response overshoot (OS) and settling time (TS), for
buck mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.2 PV module voltage step response overshoot (OS) and settling time (TS), for
boost mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
B.1 Characteristics of the PV module used for designing the dc-MIC . . . . . . . 105
ix
List of Acronyms
ac alternating current.
ACMC average current mode control.
ADC analog to digital converter.
AM air mass.
CSR current source region.
dc direct current.
DMPPT distributed maximum power point tracking.
FLC feedback linearisation control.
GaN Gallium Nitride.
MIC module integrated converter.
MOSFET moetal oxide field effect transistor.
MPP maximum power point.
MPPR maximum power point region.
MPPT maximum power point tracking.
OS overshoot.
PCB printed circuit board.
PI proportional integral.
PV photovoltaic.
SiC Silicon Carbide.
SPDT single-pole double-throw.
STC standard test condition.
TS settling time.
U.S. United States of America.
UVLO under voltage lock out.
VMC voltage mode control.
VSR voltage source region.
x
Dedicated to my wife, Amanda, and to our families
xi
Chapter 1
Introduction
1.1 Overview
1.1.1 Energy Outlook
As societies across the world evolve and developing countries raise their living standards,
the global consumption of energy continues to increase. Most of the world total primary
energy supply comes from fossil fuels, such as oil (31.7 %), coal (28.1 %) and natural
gas (21.6 %). The remaining share of energy is supplied by nuclear fission of Uranium
(4.9 %) and conversion from renewable sources (13.7 %), as reported in [1, p. 6] for
the year 2015. Fossil fuel reserves are expected to deplete within the next 200 years [2],
posing a dramatic challenge to the life as we know it. Apart from the limited time given to
humanity to rely on fossil fuels, the prominent side effect of this reliance comes from the
pollution generated in the energy conversion process. Carbon Dioxide (CO2 ) and other
pollutants are released in the atmosphere, creating an imbalance in the ecosystem and
leading to the increase of global temperatures, with catastrophic consequences on the
environment and its inhabitants [2]. In this dramatic scenario, production of energy from
renewable sources is seen as a key technology to stop today’s damaging trends and help
the environment become clean again.
Among the renewables, such as wind, hydro and geothermal, production of energy
via solar PV technologies have experienced the steepest growth in recent years [3]. Ac-
cording to the International Energy Agency, the global cumulative installed PV capacity is
exponentially increasing, as in Fig. 1.1, and reached 303 GW by the end of 2016, covering
1.8 % of the world’s electricity generation [4].
Favourable political regulations and the commitment of developed nations to reduce
their greenhouse emissions, together with a diminishing cost and increasing efficiency of
1
Chapter 1. Introduction 2
350
300
GWp dc 250
200
150
100
50
0
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
year
F IGURE 1.1: Evolution of PV installations, showing the yearly world cumulative PV in-
stalled capacity, in dc gigawatt-peak (GWp dc), adapted from [4].
PV modules, have placed PV technologies in a prime position in the global energy portfolio
of the future.
1.1.2 Architectures of Grid Connected PV systems
In PV systems, power electronic converters are the pivotal mean enabling the efficient har-
vest of energy. PV system architectures are usually classified according to the processed
amount of power, while the PV module arrangement is used to name each converter con-
figuration [5].
For large-scale PV systems, of power up to 850 kW [5] to about 1.5 MW [7], the
central inverter technology, in Fig. 1.2a, is adopted. PV modules are series connected in
strings. Each string is terminated by a blocking diode, whose function is to restrain the
energy flow between PV strings in situations of non-uniform solar irradiation. Multiple
strings are connected in parallel to increase the output current, forming an array, whose
terminals connect to a central inverter. This configuration is simple and well known in
the industry; however, the MPPT efficiency is not optimal, since one central inverter sets
the operating point of multiple PV modules, which may be exposed to different values
of solar irradiation. This issue can be mitigated adopting special matrix relay boxes, and
an additional layer of control, configuring in real time the connection among PV modules
giving the maximum energy harvest. Such a solution, however, increases the number
and complexity of cabling connections and requires a power supply for the matrix relays.
Besides, energy is not produced when the PV module connections are reconfigured, as the
load is disconnected for safety purposes during this action [8].
1 or 3 phase 1 or1 13oror

phase
13 3phase
phase 1 or 13 or
phase
1 phase
31phase
1phase
phase 1 or1 13oror
1phase
3phase
3phase
phase
1 phase 11phase
phase
1 1orphase
3 1phase
phase 1 phase1 phase
1 phase
1 phase 1 phase
connection connection
connection
connection
connection
connection
connection
connection
connection
connection
connection
connection
connection
connection
(a) (b) (c) (d) (e)

i pv ,1 dc-MIC1 io i pv ,1i pvi pv
,1i,1
dcdc-MIC
dc-MIC
dc-MIC
1 11 io ioio i pvidc,1 idcidcdc-MIC1 io idc
+
v pv ,1
F+IGURE+ ++ +1.2: Power electronics + ++ + + ++ architectures + in grid
+ connected PV systems, partly adapted
vo ,1v pvv,1vpvpv,1C
,1 v vov,1o ,1 v pv ,1 C vo ,1
- Ci ,1 Co ,1 from
- - - [6]. - CC(a): Central
i ,1 i ,1i ,1 C CC - o ,1- Inverter.
- -
o ,1 o ,1o ,1 (b): Multi-string
C - inverters. (c): String Inverters. (d): ac-
i ,1 o ,1
i pv ,2 dc-MIC2 MICs.i pv(e): ,2

dc-MICs.
i pvi pv,2 ,2dc-MIC
dc-MIC
dc-MIC
2 22 i pv ,2 dc-MIC2
+ + + ++ PV Inverter + ++ + PVPV Inverter +
Inverter
PVInverter PV Inverter
v pv ,2 vo,2v pvv,2vpvpv,2,2 vo,2 v pv ,2
vo,2vGrid
o,2 vo,2Grid
Grid Grid Grid
- Ci ,2 Co,2 - - - Ci ,2CC Co,2CC - Ci ,2 Co,2
- i ,2i ,2 o,2o,2- - - -
i pv ,k
The multi-string
v
i i idc
inverter technology,
vvdcvvdcdc
i
in Fig. 1.2b,
v vvvdc is adopted for medium
v and large scale
dc-MICk Cdc , k , kdc-MIC
pv , kpvpv dc-MIC
dc-MIC
k kk CdcCC ac, k
pv dc-MICk Cdc ac acac ac
dcdc
+
v pv ,k
PV plants
+ + ++ of power up +to
v vv
++ 500
+
v
kW; it was developed
+ to add more flexibility to the system
vo ,k pv ,kpvpv
,k ,k vo ,kvov,ko ,k pv ,k vo ,k
- Ci ,k Co,k
- - - - Ci ,kCC Co,kCC - Ci ,k Co,k
and improve the MPPT- -efficiency
- -
in respect
i ,ki ,k
to the case in Fig. 1.2a. An inverter with a
o,ko,k
i pv ,n dc-MICn i pv ,ni pvi pv,n ,ndc-MIC

dc-MIC
dc-MIC
n nn i pv ,n dc-MICn
+ dc-dc+ stage
+ ++ is mandatory
+ ++[5].
+ +
v pv ,n vo,nv pvv,nvpvpv,n,n vo,nv pv ,n
vo,nvo,n vo,n
Ci ,n Co,n - -- C
- i ,nCC Co,nCC - -Ci ,n Co,n
- The
- string inverter technology, in Fig 1.2c,
i ,ni ,n - is- adopted for small to medium scale PV
o,no,n- - - - - G1 G1 G1G1 G1
Power Supply PowerPower

Supply
Power
Supply
Supply Power Supply
systems, having power smaller than 10 kW [5] until about 120 kW [7]. Also, this archi-
tecture brings an improvement in the MPPT efficiency compared to the central inverter.
String blocking diodes are not necessary, reducing the component count and associated
energy losses. The inverter can have single or double conversion stage [5].
The configuration with ac-MICs, in Fig. 1.2d, allows further gains in MPPT efficiency,
since each PV module has its own MPPT device. A string inverter is not necessary in this
case, as each ac-MIC output connects directly in parallel to the ac grid. Although the
MPPT efficiency is improved, the power conversion efficiency of the individual ac-MICs is
challenged by the high voltage step-up ratio needed, in order to step the PV module voltage
of roughly 30 V, to the ac grid voltage of 230 V or 240 V. This large voltage step-up ratio
is achieved through an additional dc-dc conversion stage or the use of a high-frequency
transformer, increasing the component count, power losses and costs [5].
The last configuration, in Fig.1.2e, employs a dc-MIC for each PV module. The dc-MIC
TABLE 1.1: Configuration overview of grid connected PV systems, adapted from [5]
Large Scale Medium Scale Small Scale

Fig. 1.2a Fig. 1.2b Fig. 1.2c Fig. 1.2d Fig. 1.2e
Power
<850 kW to 1.5 MW <500 kW <120 kW <10 kW
range
IGBT/
Devices IGBT MOSFET MOSFET MOSFET
MOSFET
MPPT
Good High Good Very high Very high
efficiency
One MPPT one one one one one
for each: array large string small string module module
Converter
up to 98.6% up to 98 % up to 97.8 % up to 96.5 % up to 99 %∗
efficiency
*
efficiency value referred to the dc-MIC only, from [10].
outputs are series connected and feed a PV inverter. Contrarily to ac-MICs, dc-MICs can
be carried out by single stage dc-dc converters, with a moderate voltage conversion ratio;
hence they present higher efficiencies compared to their ac counterparts. dc-MIC permit
to use more economical and low voltage rated components, with better performance. The
MPPT is executed independently on each PV module, guaranteeing high energy yield, and
the PV inverter structure can be kept simple and efficient. Nevertheless, the fact that a PV
inverter is still required leaves the debate still open on which configuration, ac-MICs or
dc-MICs, is the most efficient at a system level.
The last two configurations, in Fig. 1.2d and Fig. 1.2e, are mostly adopted for small to
medium scale PV systems. However, the use of the dc-MIC solution has also been recorded
in large power plants [9].
Salient features of the discussed power electronics architectures in grid-connected PV
systems are reported in Table 1.1.
1.1.3 Energy Recovery Potential of dc-MICs
Diminishing costs of power electronics components, higher efficiencies and technologi-

cal improvements concerning lifetime and reliability, have immensely contributed to the
development of PV MICs. However, the primary reason behind the deployment of these
devices is their ability to overcome the negative effects of partial shading. In traditional
installations, such the ones of Fig. 1.2a, 1.2b and Fig. 1.2c, several PV modules are con-
nected in series, in order to build up the dc input voltage required by the grid-connected
inverter.
C1 io idc
+
Co ,1
vo ,1
-
C2
+ Chapter 1.
PV Inverter Introduction 5
vo,2 Grid
Co,2 -
vdc vac ipv1
Ck Cdc
+ +
+ G1
vo ,k
Co,k - vpv1 D1
T1
Cn -
+ ipv2 vs
vo,n +
Co,n - G1 G2 is
Power Supply
vpv1 D2
T2
- -
F IGURE 1.3: String composed of two series connected PV modules, with bypass diodes.
1.2
2
1 G1=1.0 kW/m2
G1=1.0 kW/m2 G2=1.0 kW/m2
1.5
0.8 2
[p.u.]
G2=1.0 kW/m
[p.u.]
2
0.6 G1=1.0 kW/m 1
Pmpp
Impp
ps
G2=0.5 kW/m2
is
0.4
0.5
0.2 G1=1.0 kW/m2
G2=0.5 kW/m2
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
vs vs
Vmpp
[p.u.] Vmpp
[p.u.]
(a) (b)
F IGURE 1.4: Electrical characteristics of the PV string, in function of the string voltage.
(a) String current. (b) String Power.
The series connection shares the same string current. When the solar irradiation is not
equal across series connected PV modules, the energy harvested is negatively affected. A
string with two series connected PV modules is represented in Fig. 1.3. Assuming that
both PV modules are at the same temperature, T1 = T2 = 25 ◦ C, Fig. 1.4a represents the
string current and Fig. 1.4b the string power, in function of the string voltage. Values are
in per unit (p.u.), where the individual PV module voltage Vmpp , current Impp and power
Pmpp are the base factor for the string voltage, current and power, respectively.
When the solar irradiation is uniform, G1 = G2 = 1 kW/m2 , the maximum power
which can be extracted from the series is 2 p.u. (continuous curve in Fig. 1.4b), i.e. the
sum of each PV module maximum power Pmpp . In non-uniform irradiation conditions,
for instance G1 = 1 kW/m2 and G2 = 0.5 kW/m2 , the (dotted) power characteristic in
Fig. 1.4b presents multiple peaks. In this case, the maximum power which can be deliv-
ered by the string is about half than before. By observing the dotted i-v curve, in Fig. 1.4a,
is
it can be seen that if the desired string current is Impp = 1 p.u. (i.e. Impp ), then this can
vs
only be delivered when the string voltage across the two PV modules is Vmpp = 1 p.u. (i.e.
Vmpp ). This implies that the voltage across the shaded PV module is clamped to 0 V, by
the action of the bypass diode D2 , which in turn conducts the full string current. In other
words, the bypass diode conduction causes the shaded PV modules to deliver no power to
the load. Employing bypass diodes mitigates hot-spot issues [11], preventing shaded PV
modules acting as loads and adsorbing power, at the cost of totally forgoing any energy
that could still be harvested from them. Mismatches in the electrical characteristics of
series connected PV modules, due to manufacturing tolerances, different ageing, different
technologies or even different installation orientation, are known to have similar effects
to the non-uniform irradiation condition [12]. Module integrated converters decouple the
operation of PV modules in the same string, providing the ability to collect the maximum
power from each PV module regardless of the distribution of solar irradiation, PV technol-
ogy, ageing or manufacturing tolerances. Furthermore, having a power electronic device
on each PV module can increased monitoring capability, data gathering and diagnostic
features, with immediate benefits on the safety, performance and maintenance of a PV
installation.
Recovering the energy lost due to partial shading and electrical mismatching has been
one of the drivers behind the growing interest towards power conversion executed on a
per-PV module basis. For the past two decades, academia and industry have invested in
the research and development of module integrated converters, and today these devices
are an established reality of modern and more efficient PV systems. While the debate on
which concept is best between ac-MICs and dc-MICs is still open, facts suggest that dc-MICs
present a more efficient and economical solution compared to ac-MICs, as pointed out in
Section 1.1.2. The energy recovery potential of dc-MICs has been quantified. According
to the studies summarised in Table 1.2, up to 20 % of the energy yield can be lost due to
partial shading [12]. Up to 42 % of such amount could be recovered if dc-MICs are used on
every PV module, with an annual system performance improvement reaching 6 % [13, 14].
In particular, [14] deserves special attention, as data were directly gathered from dc-MICs,
across 542 PV installations in the U.S., mostly residential PV systems between 5 kW and
15 kW.
1.2 Overview of the Non-Inverting Buck-Boost Converter
PV MICs have been in the agenda of researchers across the world for almost two decades.
Initial studies focussed on power stage considerations, with the three basic dc-dc con-
verter topologies, the buck, boost and inverting buck-boost, being analysed as suitable
TABLE 1.2: Documented energy recovery potential of dc-MICs
Energy lost Fraction of the Overall system

Ref. due to energy lost recovered performance
partial shading using MICs increase
[14] 13 % 36 % 5-6 %
[13] 3-14 % 34-42 % 5-6 %
[12] 18-20 % 3-17 % 3.5 %
candidates for the PV application. In [15] the buck and the boost power stages, connected
to a PV source and feeding a battery, were compared for different solar irradiation and
temperature. The author of [15] expressed a preference for the boost topology, as it could
always supply the load while extracting the maximum power from the source. In [16],
Walker and Sernia deepened the analysis on the buck and boost power stages adopted
in the cascaded connection of PV modules, as well as including analysis of the inverting
buck-boost and Cúk topologies. The buck and the boost were deemed to be the most ef-
ficient topologies, with the buck best suited for long PV strings, and the boost best suited
for short PV strings. The inverting buck-boost and the Cúk converter were considered least
efficient and unsuitable for cascaded connection in the PV application.
A significant step forward in the field occurred thanks to Linares et al. [17], who were
the pioneers in the idea of using a non-inverting buck-boost converter in the cascaded
connected MIC application. In [17], the non-inverting buck-boost is intended to operate
either in the buck or the boost mode, with an intermediate pass-through mode where
the PV module directly feeds the load without any power processing. This topology was
chosen as it is very flexible and tailored for the cascaded connection in the PV application,
due to the ability to step up or step down the PV module voltage.
It is worth noting that the inverting buck-boost converter features higher component
stresses [18, 19], poorer switch utilization [16] and noisier behaviour [20], compared to
the buck or boost topology; therefore it is usually disregarded for the PV application.
Shortly after [17], Texas Instruments proposed a non-inverting buck-boost converter
for a PV module integrated application, with details about its operation and digital con-
trol [21].
A thorough study was undertaken by Kasper et al., in [22], where the non-inverting
buck-boost converter was demonstrated again to be a favourite candidate for the PV mod-
ule integrated application. The reasons reported in [22] deal with the flexibility in the
number of PV modules which can be fit in a PV string, and the optimal ratio between en-
ergy stored and volume of passive components. Following the mentioned major research
TABLE 1.3: Notable research contributions on dc-MIC topologies
Walker [15], 2001 General evaluation of buck and boost

topologies
Walker and Sernia [16], 2004 Efficiency study of buck, boost, inverting
buck-boost and Cúk topologies
Linares et al. [17], 2009 Non-inverting buck-boost topology iden-
tified as optimal candidate
Hester et al. [21], 2011 Texas Instruments publishes research on
non-inverting buck-boost control
Kasper et al. [22], 2014 High efficiency GaN non-inverting buck-
boost converter: design optimization
works [17, 21, 22], other institutions worldwide (e.g. [23–25]) have chosen the non-
inverting buck-boost as a “go-to” topology for the PV module integrated converter applica-
tion. Table 1.3, reports a research timeline of main articles regarding dc module integrated
converters.
1.3 Motivation and Objectives
Recent research has covered power electronic converters suitable for PV module integra-
tion, with the non-inverting buck-boost topology becoming a leading candidate. The
industry is moving fast in this area, with several products firmly present in the mar-
ket [8, 10, 26]. As a result, the study of dc-MICs is a very current research topic, with
immediate repercussions on industrial products and trends. There are still unexplored
areas requiring more research effort and investigation. The literature on dc module inte-
grated converters has mainly covered the power stage design of basic converter topologies.
In contrast, operation and control of the non-inverting buck-boost converter, are relatively
unexplored aspects when this topology is used the PV application.
The non-inverting buck-boost converter has a known operational issue, the “dead-
zone”, when the input and output voltages are required to be in close proximity, causing
a degradation in the voltage regulation performance [27–31]. This issue is identified as a
candidate for further investigation in this thesis.
Converter control is another main aspect of this work. While voltage regulation in dc-
dc converters with constant output voltage is well established in the literature [18, 32, 33],
the problem of controlling the input voltage of a dc-MIC, is different and relatively new,
with the first in-depth studies carried out in [34] and [35]. The regulation of the PV
module voltage (i.e. the converter input voltage), as opposed to the regulation of the con-
verter output voltage, poses a peculiar controller design challenge, complicated by the fact
that both the switching converter and the PV module feature operating point-dependent
dynamic models. From the reviewed literature, it appears that the voltage mode control
(VMC), i.e. a single control loop regulating the PV module voltage, is the most frequently
applied technique. The investigated dc-MIC topology, has its switching legs driven by
bootstrap capacitor gate drivers, similarly to commercial converters. When the PV mod-
ule voltage is regulated by a traditional proportional integral (PI) controller, in a single
VMC loop, the bootstrap circuit operation negatively affects the regulation of the PV mod-
ule voltage, causing a ripple and poor transient performance, potentially decreasing the
energy harvest. To overcome these issues, the cascaded control technique, entailing regu-
lation of the PV module voltage and inductor current, has been studied and implemented
on the dc-MIC prototype. This control technique improves the PV module voltage regula-
tion and transient performance, significantly reducing the ripple caused by the operation
of the bootstrap circuit. Moreover, none of the existing literature has investigated, with
experimental outcomes, the performance of the cascaded control in a non-inverting buck-
boost dc-MIC, providing an opportunity for this research to fill this gap.
Another aspect requiring further insight regards the application of innovative non-
linear control techniques to accomplish the PV module voltage regulation task. The feed-
back linearisation control technique, is rapidly evolving from its theoretical status, articu-
lated in [36], and finding direct application in power electronics [37–40]. The use of this
technique in the control of dc-MICs has not been previously explored. In this research, an
effort is made to study, implement and analyse strengths and weaknesses of this control
technique, applied to the chosen dc-MIC topology.
Finally, since prior to performing experimental tests, PV interfacing dc-MICs have been
simulated, it has been necessary to develop an understanding of PV modelling techniques
for power electronics. The challenge faced was to translate the data found in a PV module
datasheet, into a suitable model to use in power electronics simulation software. Multiple
methods to do so exist in the literature, therefore, to simplify the modelling task, selected
methods are thoroughly reviewed and compared.
After introducing the motivation in support of the undertaken work, a summary of the
research objectives is given as follows:
1) Develop practical models to simulate the electrical behaviour of PV modules, which

are to be interfaced with the selected dc-MIC topology. In order to do so, it is nec-
essary to review existing PV modelling techniques for power electronics, aimed to
translate PV module datasheet values into a reliable electrical model.
2) Understand and improve the operation of the non-inverting buck-boost topology,

when adopted as a PV module interfacing converter. In particular, propose a solution
to the dead-zone issue, occurring when input and output voltage of the converter is
in close proximity.
3) Investigate and highlight the benefits of the cascaded control technique in the regu-
lation of the PV module voltage, in the non-inverting buck-boost dc-MIC.
4) Explore the application of the feedback linearisation control technique for regulating
the PV module voltage, through the non-inverting buck-boost topology. Implement
and compare its performance against linear control techniques.
1.4 Methodology and Limitations
A. Methodology
The methodology refers to the tools, systems and software used to accomplish the planned
research.
The central means to achieve the stated research objectives is the non-inverting buck-
boost converter, whose design was carried out using Altium Designer [41].
The converter control platform is the device interfacing the converter driving and sens-
ing signals to the digital microcontroller, a Texas Instruments TMS320F28377D [42]. This
platform was developed thanks to the collaboration with Dr. Lóránd Bede, from Aalborg
University (Denmark).
The converter control algorithms were programmed using Code Composer Studio, free
software from Texas Instruments, allowing the TMS320F28377D [42] to execute driving,
sensing and control commands needed to operate the converter. All the control algorithms
were written directly in C code.
Simulation of the PV modules, converter operation and control were carried out using
MATLAB/Simulink [43] and PLECS [44], the latter either in its blockset or stand-alone
variants.
In the laboratory, the PV module function has been carried out by a Regatron 16 kW PV
simulator enhanced by a post-processing unit (Regatron TC.LIN) [45]. The latter was used
to improve the emulating accuracy in the maximum power point area of the PV module
characteristic.
The converter load has been assumed to be a constant voltage source, and this function
has been carried out in the lab using a Kikusui PLZ1004WH [46] electronic dc load. All
the experiments reported in this thesis were carried out on one dc-MIC, where its output
voltage was varied by manually adjusting the voltage value setup in the electronic dc
load [46], operated in constant voltage mode.
B. Limitations
Several limitations have influenced the direction and schedule of the research carried out.
The first limitation lies in the fact that a PV emulator has been used in the laboratory,
as actual outdoor PV modules were not available. The only means of ensuring that the
Regatron PV simulator performed as a real PV module has been through simulations. This
is explained in Chapter 4, where the frequency response of the converter connected to a
PV module has been simulated and compared with the frequency response measured on
the converter prototype connected to the PV emulator. Since the PV emulator is made by
complex power electronic apparatus, it remains unknown whether undesired interferences
are hindering the operation of the non-inverting buck-boost interfacing converter. The
same consideration applies to the load. In fact, a constant voltage is used in the analytical
models and simulation; however, its physical implementation in the laboratory is through
a controllable electronic dc load [46].
In the targeted PV application, dc-MICs have their output connected in series and
feeding the dc input of a single phase or three phase inverter (Fig. 1.2e). The dc voltage
at the input of the inverter (dc-link) has a small ac component, whose amplitude depends
on the size of the dc-link capacitor, and whose frequency is different for single-phase or
three-phase inverters [47]. This ac voltage on the dc-link is distributed among the dc-MIC
output ports, and may propagate to the input port of each dc-MIC, degrading the quality
of the PV voltage regulation. The dc-MIC control system, if designed appropriately, can
reject the ac output voltage ripple, attenuating its influence on the PV voltage. However,
this phenomenon has not been investigated in this thesis, because of two reasons. Firstly,
only one dc-MIC has been built , and its output voltage was not high enough to feed a
single phase inverter. Secondly, the load at the dc-MIC output was carried out by a dc
electronic load [46], operating in constant voltage mode. This electronic load could only
be set up as a constant dc voltage load, without the ability to superimpose a small ac
voltage to the dc voltage. Therefore, it was not possible to emulate the ac voltage ripple
at the output of the dc-MIC, and test the disturbance rejection of the controller.
1.5 Scientific Contributions
This work has contributed to advancing the knowledge of the non-inverting buck-boost
converter, framed in the PV MIC application. Special attention has been given to the con-
verter operation and control. Furthermore, insight into practical PV modelling techniques,
suitable for power electronic simulations, has been gained. In summary, these are the
main contributions of this thesis:
• Improved operation of the non-inverting buck-boost converter.

A new modulation strategy, overcoming the negative effects of the dead-zone in the
operation of the non-inverting buck-boost converter, has been proposed. This strat-
egy is demonstrated to improve the converter performance, compared with existing
strategies, minimising the ripple in the regulated voltage.
• Improved PV module voltage regulation quality employing the cascaded control

technique.
Compared to a traditional single voltage control loop, the cascaded control technique
is demonstrated to achieve a better performance in the regulation of the PV module
voltage. It has been verified that the cascaded control scheme is more effective than
the traditional voltage control scheme, in eliminating the disturbance caused by the
action of the bootstrap circuit.
• Applied an emerging non-linear control technique to a new research problem.

The feedback linearisation control technique has been applied for the first time to
regulate the input voltage of the non-inverting buck-boost converter, interfaced to
a PV module. Controller tuning and design criteria are given, while experimental
results compare the performance of this control technique with the converter under
cascaded control. The results demonstrate improvements in the consistency of the
transient response, regardless of the system operating point.
• Given insight on practical modelling of PV modules for power electronics

simulation.
A fast PV modelling procedure, based on 3D lookup tables, has been developed.
Thanks to this method, a PLECS user can rapidly simulate the electrical behaviour
of any crystalline silicon PV module, in different solar irradiation and temperature
conditions, only starting from the module datasheet values.
• Comprehensively reviewed PV module parameter estimation techniques based

on datasheet values.
An extensive review of methods to extract the electrical modelling parameters of a
PV module, starting from datasheet values, has been carried out. There is a vast
literature on this subject, and the review conducted serves to concisely present few
important parameter estimation methods, with practical suggestions for their imple-
mentation.
1.5.1 List of Publications
The research outcomes of the work carried out in this thesis have been published in inter-
national conference proceedings and journals. The titles are listed below in chronological
order:
I L. Callegaro, M. Ciobotaru and V. G. Agelidis, “Analysis and comparison of electrical

PV modelling techniques based on datasheet values” in Proc. 31st European Pho-
tovoltaic Solar Energy Conf. and Exhibition, Hamburg, Germany, Sept. 2015, pp.
1998-2003.
II L. Callegaro, M. Ciobotaru and V. G. Agelidis, “Implementation of 3D lookup tables in

PLECS for modeling photovoltaic modules”, in Proc. Australasian Universities Power
Engineering Conf., Brisbane, Australia, Sept. 2016.
III L. Callegaro, M. Ciobotaru, V. G. Agelidis and E. Turano, “A solution for the gain
discontinuity issue of the non-inverting buck-boost converter”, in Proc. 42nd Annu.
Conf. of the IEEE Industrial Electronics Society, Florence, Italy, Oct. 2016, pp. 1245-
1250.
IV L. Callegaro, M. Ciobotaru, J. E. Fletcher, P. A. Rios and D. J. Pagano, “Design of

cascaded control loop for solar power optimizer based on a buck-boost converter”,
in Proc. IEEE 2nd Annu. Southern Power Electronics Conf., Auckland, New Zealand,
Dec. 2016.
V L. Callegaro, D. J. Pagano, M. Ciobotaru and J. E. Fletcher, “Feedback linearization

control of non-inverting buck-boost PV power optimizers”, in Proc. IEEE 8th Int.
Symp. on Power Electronics for Distributed Generation Systems, Florianopolis, Brazil,
Apr. 2017.
VI L. Callegaro, M. Ciobotaru, D. J. Pagano, E. Turano and J. E. Fletcher, “A Sim-

ple Smooth Transition Technique for the Non-Inverting Buck-Boost Converter”,
IEEE Trans. on Power Electron., vol. 33, no. 6, pp. 4906-4915, June 2018.
A cross-reference between the above publication list and the thesis chapters is reported in
Table 1.4.
TABLE 1.4: Relationship between
publications and thesis chapters
Publication Thesis chapter

I Chapter 2
II Chapter 2
III Chapter 3
IV Chapter 4
V Chapter 5
VI Chapter 3
1.6 Thesis Outline
The research contributions documented in this thesis are spread across four main chapters.
Chapter 2 presents a review of PV modelling techniques useful for power electronics
simulation. The techniques presented allows the reader to construct PV models starting
from the datasheet values of commercial PV modules.
Chapter 3 outlines the working principle of PV strings equipped with MICs. Operating
details and modulation technique of the non-inverting buck-boost dc-MIC are presented,
with special attention to the transition issue between buck and boost operating modes,
and the proposed solution.
Chapter 4 is about linear control of the selected converter and the influence of the
bootstrap circuit operation on the regulation of the PV module voltage. The small-signal
analysis of the non-inverting buck-boost dc-MIC is performed, and two linear control tech-
niques are discussed. Based on PV module voltage step responses, the performance of a
single loop and a cascaded loop control scheme are experimentally assessed.
Chapter 5 illustrates the application of an emerging non-linear control technique to
the non-inverting buck-boost dc-MIC. The feedback linearisation technique is described,
and its control laws for the chosen dc-MIC are derived. An experimental validation, based
on PV module voltage step responses, compares the converter performance under the
feedback linearisation and the cascaded control.
Finally, Chapter 6 summarizes the work presented in Chapter 2 to Chapter 5, draws
the conclusions, and provides future work directions.
Chapter 2
PV Modelling Techniques
for Power Electronics Simulation
This chapter addresses the multifaceted task of modelling the electrical characteristics of
PV modules, for power electronics simulation. The modelling task is divided into two
parts: estimating the PV equivalent circuit parameters, and including the effect of solar
irradiation and temperature in the model. A comprehensive and detailed review of PV
module parameter estimation techniques is carried out and a framework to include en-
vironmental factors into the model is given. A streamlined procedure to simulate a PV
module characteristic by means of 3D lookup tables is discussed.
2.1 PV Modelling Overview
In order to simulate the behaviour of a converter connected to a PV module, it is first

necessary to develop a model of the PV source. The latter is intended as a two terminal
device, which outputs a current dependent on the value of the voltage across the termi-
nals, as well as on the solar irradiation and temperature. Once a PV model is available,
voltage control and maximum power point tracking algorithms can be simulated on the
PV interfacing converter.
Each PV technology is associated to an electrical equivalent circuit. In general, a PV
cell is represented by a non-linear circuit. A current generator, whose current value is pro-
portional to the collected solar irradiation, temperature and semiconductor area, is placed
in parallel with either one or two diodes. One diode represents the diffusion and recom-
bination of charge carriers taking place in the semiconductor, while the second diode is
associated to the recombination of charge carriers occurring in the space-charge zone of
the of the solar cell. The series and shunt resistance associate to the losses occurring in
15
Chapter 2. PV Modelling Techniques for Power Electronics Simulation 16
Iph Iph id id ip ip + + Iph Iph id1 id1id2 id2ip ip + + Iph Iph id

Rs Rs ipv ipv Rs Rs ipv ipv
Rp Rp vpv vpv Rp Rp vpv vpv
- - - -
(a) (b)
Iph id1 id2 ip ipv + Iph id ip ipv +

Rs Rs
Rp vpv Rp vpv
Irec
- -
(c)
F IGURE 2.1: PV module equivalent circuits. (a) Single diode equivalent for crystalline
Start
Start
technology. (b) Double diode equivalent. (c) Equivalent circuit for amorphous technolo-
gies [49].
T =TT=min
Tmin
the conducting ribbon interconnecting series connected cells and leakage currents, respec-
G =G0= 0circuit are represented in Fig. 2.1a
tively [48]. The single and double diode equivalent
and Fig. 2.1b, respectively.
V =V0= 0diode circuit is appropriate for the
Although in [50] it is suggested that the double
Start
simulation of cells exhibiting a sharp knee in the i-v curve, especially those constructed
T = Tmin
of multicrystalline Silicon, it is usual to
Nomodel
No crystalline and multicrystalline PV tech-
V <
V V<max
Vmax
nologies with the single diode circuit [49]. The latter, is considered to balance simplicity
V =VV= +VDV
+ DV
G=0 =GG= +GDG
+ DGthin-film technologies can be represented by the circuit
and accuracy [51].GAmorphous
YesYes
shown in Fig. 2.1c [49]. For organic PV technologies, a single diode circuit, like the one
YesYes
V=0 in Fig. 2.1a, is adopted [52].
G <G G<max Estimation of theSolve
Gmax Solve
parameters
Start for the circuits of Fig. 2.1, are
i i– f(i
– f(i,V ,V,G,T)
pv pv pv pvpv pv
carried out using different strategies, depending
,G,T)= 0= 0
on the PV material considered.
NoNo j =jj+1
= j+
In this research, the multi-crystalline PV technology j = is1 selected, as it is widespread and
No T =TT=+TDT+ DT
V < Vmax Store
commonly encountered in existing installations. Storecalculated
calculated
The single-diode equivalent circuit of 2.1a
ipvj-1 0
V = V + DV ipv pvpv pv,G,T)
(V
i (V,G,T)
YesYes Its parameters can be estimated by means of measurements, or else
is therefore of interest.
Yes T <TT<max
Tmax in 3D
in 3D LUT LUT
 
by manipulating equations using the PV module datasheet values j-1 as the only inputs.
f i
ipvj in Fig
ipvj-1 2.1a are
pv
The five modelling parameters
NoNo of the circuit Iph (photo-generated cur-
 
Solve j-1
f i
ipv – f(ipv,Vpv,G,T) = 0 rent), n (diode ideality factor), Io (diode dark saturation current), Rs (PV module series
pv
j = j+1 End End
resistance) and Rp (PV module shunt resistance). These parameters are considered at the
ipv  f  ipv   
Store calculated standard test condition (STC), i.e. whenNo
the PV module
j
is
j
tested with a solar irradiation
ipv(Vpv,G,T)
in 3D LUT
i pv ,1i pv ,1 dc-MIC
dc-MIC io io idc idc Yes
i  ipv Vpv , G, T 
1 1
j
+ + + + pv
v pvv,1 pv ,1 v vo ,1
- - Ci ,1Ci ,1 Co ,1Co ,1 - o ,1-
End End
i i dc-MIC
dc-MIC
G
of G = 1 kW/m2 and its surface temperature is T = 25 ◦ C. Once the named five parame-
ters are known, the PV module output current, ipv , a function of the voltage at the output
terminals, vpv , can be calculated. In order to calculate the PV module output current, for
values of solar irradiation and temperature other than the STC (G = 1 kW/m2 , T = 25
◦ C) values, an additional set of modelling equations, reported later in this chapter, must
be considered.
2.2 Equivalent Circuit Parameter Estimation
With attention to the single diode equivalent circuit of Fig. 2.1a, for a PV module made of
Ns series connected cells, the output current ipv is expressed as:
vpv +Rs ipv
vpv + Rs ipv
ipv = I ph − Io e nNs Vth
−1 − , (2.1)
Rp
which is an implicit and non-linear equation of the type ipv = f (ipv , vpv ), where the terms
Iph (photo-generated current), Io (diode dark saturation current), n (diode ideality fac-
tor), Rs (PV module series resistance) and Rp (PV module series resistance), are unknown
constants; while Ns (number of series connected cells within a PV module) and Vth (semi-
conductor thermal voltage), are known. Several methods to estimate these parameters
are proposed in the literature. Frequently, the number of unknown parameters in (2.1)
is reduced. For instance, in [53] the diode ideality factor n is fixed, and assumed to be
0 < n < 1.5. Accordingly, in [15] a diode ideality factor of n = 1.2, is chosen for a mul-
ticrystalline PV module. A further simplification often adopted, is to disregard the shunt
resistance, by considering Rp = ∞. In this way, by choosing n a priori and considering
Rp = ∞, the unknown terms in (2.1) can be reduced from five to three, at the expense of
having a less accurate model.
In order to reproduce a model with the greatest accuracy, all the five unknown terms
in (2.1) are here estimated. Four notable 5-parameter estimation methods are discussed
in the following sections.
2.3 Review of Parameter Estimation Techniques
The five unknown parameters Iph , Io , n, Rs and Rp can be estimated by using values found
in the PV module datasheet, such as the maximum power point (MPP), current and power,
Vmpp , Impp and Pmpp , the open circuit voltage, Voc , and its temperature coefficient, αv , the
short circuit current, Isc , and its temperature coefficient αi . In the following subsections,
two analytical and two numerical methods to estimate the five unknown parameters are
reviewed.
2.3.1 First Analytical Method
The first analytical method to estimate the five unknown parameters in (2.1), is from
Phang et al. [54], and Chan and Phang [55], who specified one direct equation for each
unknown parameter in (2.1), to be solved in the order:
Rp =Rpo (2.2)
Vmpp + Rso Impp − Voc

n= n o (2.3)
Vmpp Impp
Ns Vth ln Isc − Rpo − Impp − ln Isc − VRocp + Isc −(Voc /Rpo )

Voc − Voc
Io = Isc − e nNs Vth (2.4)
Rp

Rs Isc Rs
Iph =Isc 1 + + Io e nNs Vth
−1 (2.5)
Rp
nNs Vth − nNVsocV

Rs =Rso − e th (2.6)
Io
In order to be resolved, (2.3) to (2.2) require the datasheet values Vmpp , Impp , Voc and
Isc , plus the two additional quantities, namely Rso and Rpo . According to [55], these are
related with the slope of the PV module i − v curve at the open circuit and short short
circuit points, and are given by:
1 dipv
=− (2.7)
Rpo dvpv vpv =0
ipv =Isc
1 dipv
=− (2.8)
Rso dvpv vpv =Voc
ipv =0
Estimation of Rpo and Rso is done by evaluating the slope of the i−v curve reported in the
8
-
1 dipv --
=!
6 Rpo dvpv -(vpv =0;ipv =Isc )
ipv [A]
4
-
1 dipv --
2 = !
Rso dvpv -(vpv =Voc ;ipv =0)
0
0 5 10 15 20 25 30 35
vpv [V]
F IGURE 2.2: Evaluation of Rso and Rpo according to [55].
datasheet, at the points of intersection with the axes, (0,Isc ) and (Voc ,0), as per Fig. 2.2.
This process introduces a degree of uncertainty on the final results.
2.3.2 Second Analytical Method
Similar to the previous method, this method elicits the five unknown parameters in (2.1),
as function of the PV module datasheet values. The equations given by Femia et al. [48]
are:
Iph ∼
=Isc (2.9)
Voc
αv − TSTC
n= (2.10)
αi 3 Egap
Ns Vth Iph − TSTC − 2
kB TSTC
Voc − Rs Isc

− Voc − Voc
Io = Isc − e nNs Vth ∼
= Isc e nNs Vth (2.11)
Rp
nNs Vth x − Vmpp

Rs = (2.12)
Impp
nNs Vth x
Rp = (2.13)
Iph − Impp − Io (ex − 1)
The term x inside (2.12) and (2.13), is given by:
Vmpp (Vmpp −2nNs Vth )

 
2 2
Vmpp n2 Ns2 V th
 
2Vmpp V
mpp (2Impp − Iph − Io ) e 
x= − +W (2.14)
nNs V th n2 Ns2 V 2th 
 nNs2 Io Vth 

The notation W {...}, in (2.14), indicates the Lambert-W function. This special function is
used to resolve equations of the like y = xex , where if an expression for y is known, then
x can be directly calculated as x = W {y}.

This second analytical method does not need additional inputs other than the numer-
ical datasheet values. However the evaluation of the Lambert-W function requires spe-
cialised computational software, or otherwise an involved mathematical approximation.
2.3.3 First Numerical Method
This method relies on the resolution of a system of multivariable non-linear equations,

avoiding usage of the Lambert-W function. Iph , n and Io , are calculated from (2.9), (2.10)
and (2.11), respectively. The parameters Rs and Rp are estimated by solving the system:
(
x1 (Rs , Rp ) = 0
(2.15)
x2 (Rs , Rp ) = 0
with the equations in (2.15) inferred from maximum power point considerations [48]. It
is:
Vmpp +Impp Rs
1 Io
Rp + nNs Vth e
nNs Vth
x1 (Rs , Rp ) =Impp − Vmpp Vmpp +Impp Rs (2.16)

Rs R s Io
1+ Rp + nNs Vth e
nNs Vth
Vmpp + Impp Rs
x2 (Rs , Rp ) = Vmpp +Isc Rs − Rp . (2.17)
Iph − Impp − Io e nNs Vth − 1
Since x1 (Rs , Rp ) and x2 (Rs , Rp ) are non-linear functions, the system (2.15) can be re-
solved by means of the multivariable Newtown-Raphson algorithm [56]. The algorithm
computes Rs and Rp after a sequence of iterations, however, in order to get the first it-
eration started, this must be initialized with a guess of the solution, said Rso and Rpo . An
appropriate initialization is achieved by posing Rso = 0 Ω and consequently calculating Rpo
by equating (2.17) to zero (with Rs = Rso = 0 Ω).
This method requires to set up a non-trivial iterative algorithm, whose convergence is
dependent on a correct initial guess of the solution.
2.3.4 Second Numerical Method
As per the previous case, this method derives Iph and Io , only using datasheet values, by
means of the simplified relationships:
Iph ∼
=Isc (2.18)
Voc − Rs Isc

−Voc
− Voc
Io = Isc − e nNs Vth ∼
= Isc e nNs Vth , (2.19)
Rp
noting that (2.19) is also found in [53]. Alternatively to the method of Section 2.3.3, a
system with three unknown parameters, Rs , Rp and n, is written:

 y1 (Rs , Rp , n) = 0


y2 (Rs , Rp , n) = 0 (2.20)


 y (R , R , n) = 0
3 s p
Here y1 (Rs , Rp , n), is derived from posing the power derivative with respect to the voltage
equal to zero at the maximum power point [57, 58]. y2 (Rs , Rp , n) is obtained by substi-
tuting (2.18) and (2.19) into (2.1) evaluated at the maximum power point. y3 (Rs , Rp , n)
is obtained by evaluating the derivative of (2.1) at short circuit, knowing that the slope of
dipv
the i-v curve at the short circuit point is dvpv vpv =0 = − R1p [57, 58]. It is:
ipv=Isc
Vmpp +Impp Rs −Voc

Isc Rp −Voc +Isc Rs 1
− nNs Vth Rp e nNs Vth
− Rp
y1 =Impp + Vmpp Vmpp +Impp Rs −Voc (2.21)
Isc Rp −Voc +Isc Rs Rs
1 + Rs nNs Vth Rp e nNs Vth
+ Rp
Vmpp + Impp Rs − Isc Rs

Vmpp +Impp Rs −Voc
Voc + Isc Rs
y2 =Isc − Impp − − Isc − e nNs Vth
(2.22)
Rp Rp
Isc Rs −Voc
Isc Rp −Voc +Isc Rs
− nNs Vth Rp e nNs Vth − R1p 1
y3 = Isc Rs −Voc + , (2.23)
R

Isc Rp −Voc +Isc Rs Rs p
1 + Rs nNs Vth Rp e nNs Vth
+ Rp
where the function of Rs , Rp , n notation has been dropped, for simplicity. The system (2.20)
features three non-linear equations, each with the three unknown: Rs , Rp and n; it can
be solved by means of a Newton-Raphson algorithm [56], requiring an initial guess of the
solution at the first iteration, said Rso , Rpo , no . The research performed in [58] suggests to
choose the initial guess values equal to:
Voc Isc
no = , (2.24)
Vmpp Impp

Iph −Impp
Voc − Ns Vth ln Ioo
Rso = , (2.25)
Impp
Vmpp + Rso Impp

Rpo =
Vmpp +Rso Impp
, (2.26)
no Ns Vth
Iph − Ioo e − 1 − Impp
where Iph is from (2.18), while Ioo inside of (2.25) and (2.26), is calculated by posing n = 1
inside of (2.19)1 . In [57], a similar approach to [58] is undertaken, however the choice
of the initial values needed to carry out the Newtown-Raphson algorithm is not specified.
This is an important matter, as the convergence of this algorithm is often dependent on
the initial guess of the solution.
In summary, with this method Iph is directly taken from the datasheet, by means of
(2.18). Rs , Rp and n are calculated by solving (2.20). The system is resolved with the
Newton-Raphson method, starting from the initial guesses (2.24), (2.25), (2.26). Finally,
Io is derived from (2.19).
2.3.5 Results
The techniques discussed above have been implemented in MATLAB. A 200 W multicrys-
talline PV module, Kyocera KC200GT [59], has been chosen as a reference. This PV
module is used as a reference also in similar studies, e.g. [53, 58]. The STC datasheet
values2 of KC200GT, are Pmpp = 200 W, Vmpp = 26.3 V, Impp = 7.61 A, Voc = 32.9 V,
αv = −1.23 × 10−1 V/◦ C, Isc = 8.21 A and αi = 3.18 × 10−3 A/◦ C, Ns = 54 series
connected cells.
Table 2.1 reports the parameters resulting from the application of the described meth-
ods. With exception of the dark saturation current Io , the parameters estimated from each
method were of the same order of magnitude. Also, the numerical methods have con-
verged to a solution, using the initial guess for the Newton-Raphson algorithm specified in
Section 2.3.3 and 2.3.4.
In order to evaluate the quality of the parameters estimated using different methods,
the i-v curve given by (2.1) has been plotted and compared with the curve reported in the
1
The authors of [58], use Io from (2.19) inside (2.25) and (2.26), without specifying the value of n. The
choice of using Ioo inside (2.25) and (2.26) has demonstrated to yield reasonable values for Rso and Rso .
2
The MPP power is specified with a tolerance of +10 %, -5 %.
TABLE 2.1: Estimated modelling parameters for the PV module KC200GT [I]
Iph Io n Rs Rp Additional
[A] [nA] [p.u.] [Ω] [Ω] inputs
1st analytical Rso = 0.45 Ω
8.22 6.14 1.13 0.26 135
method Rpo = 127 Ω
2nd analytical
8.21 2.14 1.08 0.28 157
method
1st numerical Rso = 0 Ω
8.21 2.14 1.08 0.31 214
method Rpo = 45 Ω
no = 1.35 p.u.
2nd numerical Rso = 0.48 Ω
8.21 170 1.35 0.22 952
method Rpo = 50 Ω
Ioo = 0.42 nA
PV module datasheet, in Fig 2.3a. The power vs. voltage (p-v) curve is also displayed, in
Fig 2.3b, while the error on the PV power, in percentage, is shown in Fig 2.3c.
The parameters estimated with the first analytical method, from [55], yield an i-v
curve which is the best agreement with the i-v reported in the PV module datasheet, as
observable from Fig. 2.3a and Fig. 2.3c. Nevertheless, the first analytical method relies
on the additional input parameter Rpo and Rso , which must be interpreted from the i-
v curve supplied by the manufacturer. This matter undoubtedly introduces an arbitrary
interpretation and bias on the results. On the other hand, the second analytical method,
from [48], is still very accurate as observed in Fig. 2.3c. No other inputs than the datasheet
values are needed for the second analytical method.
The numerical parameter estimation methods output a higher value for the shunt re-
sistance Rp , in respect to the analytical methods. Also, in the case of the second numerical
method, a much higher dark saturation current Io is results. A high shunt resistance de-
creases the slope of the calculated i-v curve for 0 ≤ vpv ≤ Vmpp , causing it to drift
above the i-v curve provided in the datasheet, hence the positive error sign in Fig. 2.3c
for 0 ≤ vpv ≤ Vmpp .
All four estimation methods lead to an i-v curve closely tracking the one reported in
the datasheet. The maximum error (2.3c) is 2 % in the current source region of the i-v
curve, and approaches 10 % in the voltage source region of the i-v curve. The modelling
error at the maximum power point is always lower than or at most equal to 2%.
In conclusion, all parameter estimation techniques have lead to reliable results. The
numerical methods however are carried out by means of the iterative Newton-Raphson
200
2 nd numerical method
8 1 st analytical method
2 st analytical method
150 1 st numerical method
6 From datasheet
ppv [W]
ipv [A]
100
4
nd
2 numerical method
2 2 st analytical method 50
1 st numerical method
From datasheet
0
0 5 10 15 20 25 30 35 0
0 5 10 15 20 25 30 35
vpv [V]
vpv [V]
(a) (b)
0
Error on ppv [%]
-2
-4
-6
2 nd numerical method
1 st analytical method Vmpp
-8
1 st numerical method
-10
0 5 10 15 20 25 30 35
vpv [V]
(c)
F IGURE 2.3: Comparison of curves obtained using the parameters from the reviewed
estimation methods. (a): i-v curve comparison. (b): p-v curve comparison. (c) Percentage
error on the PV power vs. datasheet values.
algorithm, which requires a guess estimate of the solution at the first iteration. This
algorithm may be non-trivial to implement, and the correct guess estimate of the solu-
tion is nowadays a research topic on its own. In contrast, the analytical methods are of
more straightforward implementation, especially the method presented in Section 2.3.2,
from [48], which does not require any user defined input. The only drawback of the
method in Section 2.3.2 is the use of the Lambert-W function, which is estimated by means
of specialized mathematical software, such as MATLAB [43].
2.4 Environmental Variables
The analysis presented so far served to estimate the value of the five electrical modelling
parameters, Iph , Io , n, Rs and Rp , belonging to the single diode equivalent circuit in
Fig. 2.1a. With the five modelling parameters known, it is possible to trace the i-v curve
for the STC, i.e. with the PV module irradiated at 1 kW/m2 , at an air mass (AM) path AM
= 1.5 [53], and at a (cell) temperature of 25 ◦ C. In (2.1), the expected dependence of the
PV module current, ipv , on the solar irradiation (G) and temperature (T ) is not specified.
The sought expression, where the environmental parameter dependence is highlighted, is:
vpv +Rs ipv
vpv + Rs ipv
ipv = Iph (G, T ) − Io (T ) e nNs Vth (T )
−1 − . (2.27)
Rp
In (2.27), Iph , Io , n, Rs and Rp are now known at the STC condition, by applying one of the
reviewed parameter estimation techniques. Solar irradiation and temperature affect the
value of the photo generated current Iph , hence becoming Iph (G, T ), while the diode dark
saturation current Io and the thermal voltage Vth are only influenced by the temperature,
hence the notation Io (T ) and Vth (T ) in (2.27) [57]. It is assumed for simplicity that the
other parameters, Rs , Rp and n, do not depend on environmental factors [15, 48, 53, 57].
It remains to find the expression for Iph (G, T ) and Io (T ).
In order to derive an expression for Io (T ), firstly the short circuit current dependency
on the temperature is expressed as:
h αi i
Isc (T ) = Isc 1 + (T − TSTC ) ; (2.28)
100
secondly, the open circuit and thermal voltage temperature dependence are respectively
specified as:
Voc (T ) =Voc + αv (T − TSTC ) , (2.29)
T
Vth (T ) =Vth ; (2.30)
TSTC
thirdly, using (2.11), the wanted expression for Io (T ) is:
Voc (T ) − Rs Isc (T )
−Voc (T )
Io (T ) = Isc (T ) − e nNs Vth (T ) . (2.31)
Rp
The above equations, are used to elicit Iph (T ):
Voc (T )
Voc (T )
Iph (T ) = Io (T )e nNs Vth (T ) + , (2.32)
Rp
9 9
G4 = 1 kW/m2 T1 = 5 °C
8 8
7 G3 = 0.75 kW/m2 7 T2 = 15 °C
6 6
ipv [A]
ipv [A]
5 G2 = 0.5 kW/m2 5
4 4
3 2 3 T3 =25 °C
G1 = 0.25 kW/m
2 2
1 1 T4 =35 °C
T = 25 °C G = 1 kW/m2
0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
vpv [V] vpv [V]
(a) (b)
F IGURE 2.4: Current vs. voltage curves, for a 185 W multicrystalline PV module [60]. (a)
Solar irradiation dependence. (b) Temperature dependence.
noting that (2.32) is given by the Kirchhoff’s current law applied to the circuit of Fig. 2.1a,
when vpv = Voc and ipv = 0. The desired expression for Iph (G, T ) is:
Iph (G, T ) = Iph (T )G. (2.33)
Among the above equations, (2.28), (2.29), (2.31) and (2.32) are from [57]. Having
derived an expression for Iph (G, T ) and Io (T ), the PV module current (2.27) can be cal-
culated from for any value of solar irradiation and temperature, producing the graphs in
Fig. 2.4.
2.5 EN5030 Standard Modelling
It is worth reporting the model for the PV module i-v curve given by [61], which concerns
testing of grid connected PV inverters. In [61], a model for the PV generator i-v curve is
given by means of direct formulas. This model is deemed to be tailored for MPPT perfor-
mance testing. It is reported in this thesis because of its straightforward implementation.
Two ratios are defined from the PV module datasheet values (at STC), as:
Vmpp
F Fv = (2.34)
Voc
Impp
F Fi = (2.35)
Isc
The PV module current is then given as:

vpv

CAQ Voc (G,T )
ipv = Isc (G, T ) − Io (G) e −1 (2.36)
in which the solar irradiation and temperature dependent terms are:
G
Isc (G, T ) =Isc [1 + α (T − TST C )] (2.37)
GST C

G
Voc (G, T ) =Voc [1 + β (T − TST C )] CV ln + 1 − CR G , (2.38)
CG
while the PV module temperature is expressed as:
k
T = Ta + To + G (2.39)
1 + sτ
becoming T = Ta + To + kG in steady state. In (2.39) Ta is the ambient temperature in

◦ C, T = −3 ◦ C is the temperature correction factor (accounting for the difference between
o
measured and computed temperature [62]), the irradiance gain is k = 0.03 km2 /W, the
solar irradiance is G in W/m2 , s is the Laplace domain variable, and τ = 5 min is the
time constant. In (2.36), the irradiance dependent dark saturation current Io (G) and the
parameter CAQ , are respectively:
1 G
Io (G) =Isc (1 − F Fi ) 1−F Fv , (2.40)
GSTC
F Fv − 1
CAQ = . (2.41)
ln (1 − F Fi )
which only use the datasheet value Isc and the previously defined parameters F Fv and
F Fi . Finally, the technology dependent parameters CG , CR and CV , α and β are reported
in Table 2.2.
2.6 Modelling Based on 3D Lookup Tables
In the previous sections, the mathematical background required to reproduce the PV mod-
ule electrical i-v characteristic has been reviewed. Eventually, in Section 2.4 and 2.5, an
expression for the PV current as a function of the PV current itself, PV voltage, solar irradi-
ation and temperature has been derived. This section discusses practical aspects regarding
the implementation of a PV model for power electronics simulation. The software adopted
TABLE 2.2: Technology dependent parameters [61]
cSi-technology Thin film technology

F Fv [p.u.] 0.8 0.72
F Fi [p.u.] 0.9 0.8
CG [W/m2 ] 2.514×10−3 1.252×10−3
CV [p.u.] 8.593×10−2 8.419×10−2
CR [m2 /W] 1.088×10−4 1.476×10−4
α [%/◦ C] 0.04 0.02
β [%/◦ C] -0.4 -0.2
is PLECS, where the PV module electrical i-v characteristic is implemented via a 3D lookup
table (3D LUT).
3D LUTs allow the fast simulation of the PV characteristic, since (2.27) is resolved
offline for a set of voltage, solar irradiation and temperature values. Therefore, during a
circuit simulation, the PV current values calculated offline are simply taken from the table,
with minimal computational effort. The only resource discussing the implementation of
a 3D LUT for PV modelling purposes is [63]. However, [63] adopts a simplified single
diode PV model, with only three parameters (Iph , Io and Rs ), rather that the full five
parameter model discussed in Section 2.3. Furthermore, [63] does not outline a method
to construct the 3D LUT, leaving the task open to interpretation. These gaps are addressed
here, where the five parameter single diode circuit is used, and the construction of the 3D
LUT is discussed in detail.
2.6.1 3D Lookup Table for the PV Current
A 3D LUT table storing values of the PV module current is shown in Fig. 2.5. The PV mod-
ule current, given by (2.27), is an implicit, multivariable and non linear fuction of the type
ipv = f (ipv , vpv , G, T ). In the 3D LUT, ipv is calculated for the voltage Vpv1 , Vpv2 , ..., Vpvk ,
solar irradiation G1 , G2 , ..., G` and temperature T1 , T2 , ..., Tm .
The values of the step in the voltage, ∆Vpv , solar irradiation, ∆G, and temperature,
∆T , for which (2.27) is solved, must be decided a priori. The PV module temperature, T ,
relates to the ambient temperature, Ta , by means of [11]:
(NOCT − 20)
T = Ta + G (2.42)
0.8
where the nominal operating cell temperature (NOCT) parameter is given in the PV mod-
ule datasheet and G is in kW/m2 . Minimum and maximum ambient temperature must be
selected according to the installation location. The temperature increment can be chosen
∆T = 5 to 10 ◦ C. Similar considerations apply for the solar irradiation. Its maximum
value can be chosen as high as 1.3 kW/m2 [16] or above, in order to account for the effect
of scattered and reflected solar irradiation, bringing the collected irradiation above the
1 kW/m2 figure. A step ∆G = 100 W/m2 is suggested for the 3D LUT. The maximum
voltage can be chosen greater than the PV module open circuit voltage Voc , to account for
the increase of Voc at low temperatures. A value of ∆Vpv = 0.1 V or 0.05 V can be used as
typical voltage increment in the 3D LUT.
Once established the increment ∆Vpv , ∆G and ∆T , the 3D LUT can be calculated.
Considering a generic point in the 3D LUT, of known coordinates Vpvx , Gy , and Tz , the
right hand side term in (2.27) is moved to the left hand side, yielding:
Vpvx −Rs ipv
Vpvx + Rs ipv
ipv − Iph (Gy , Tz ) + Io (Tz ) e nNs Vth (Tz )
−1 + =0 (2.43)
Rp
where only ipv is unknown. In other words, (2.43) has been written in the form:
ipv − f (ipv ) = 0 (2.44)
This equation can be solved with Newton-Raphson method. The value of ipv , satisfying the
equality (2.44), is found after running a few iterations, where the current value at the j-th
ipv (Vpv1 , G1 , Tm ) ··· ipv (Vpv1 , G` , Tm )
ipv (Vpv2 , G1 , Tm ) ··· ipv (Vpv2 , G` , Tm )
ipv (Vpv1 , G1 , T2 ) ··· ..i (V ,. .G , T ) ..

. pv pv1 . ` 2 .
ipv (Vpv2 , G1 , Ti2pv
) (Vpvk
· · ,· G1 , iTpv ) pv2 ·, ·G· ` , T2i)pv (Vpvk , G` , Tm )
m(V
|←−−−−→|
ipv (Vpv1 , G1 , T1 ) ··· ..i (V .,.G , T ) ..

∆Vpv . pv pv1 . ` 1 .
ipv (Vpv2 , G1 , Ti1pv
) (Vpvk 2 )(Vpv2·,·G
· · ,· G1 , iTpv · ` , Ti1pv
) (Vpvk , G` , T2 )
.. .. .. |←−
. . . −−
−−
ipv (Vpvk , G1 , T1 ) ··· ipv (Vpvk , G` , T1 ) −−
→ T
∆ |
∆G
|←−−−−−→|
F IGURE 2.5: 3D lookup table for the PV current, ipv , calculated for voltage
Vpv1 , Vpv2 , ..., Vpvk , solar irradiation G1 , G2 , ..., G` and temperature T1 , T2 , ..., Tm .
iteration, ijpv , is updated according to [56]:

f ij−1
pv
ijpv = ij−1
pv − j−1 . (2.45)
f˙ ipv
In the first iteration (j = 1), a guess estimate of the solution for the previous iteration is

j−1
given as ipv = iopv = 0. In (2.45) term f ij−1
pv is:
j−1
!
Vpvx +Rs ipv
Vpvx + Rs ij−1
pv
f (ij−1 j−1
pv ) = ipv − Iph (Gy , Tz ) + Io (Tz ) e
nNs Vth (Tz )
−1 + , (2.46)
Rp

and the derivative term f 0 ij−1
pv equals:
j−1
Vpvx +Rs ipv
d Rs Io (Tz )Rs e nNs Vth (Tz )
f˙ ipv
j−1 j−1

= f ipv =− − − 1. (2.47)
dij−1
pv Rp nNs Vth (Tz )

Following, ijpv is substituted in place of ipv in (2.44), which becomes ijpv −f ijpv = 0. The

process of updating ijpv is executed until ijpv − f ijpv ≤ ε, where ε is the solution tol-
erance, selected arbitrarily small and approaching zero. The procedure for solving (2.27)
and constructing the 3D LUT is reported in Fig. 2.6.
As an example, the 3D LUT has been calculated for a Kyocera 200 W multicrystalline PV
module [59]. The resulting function, representing the PV current, is displayed in Fig. 2.7.
Rp Rp vpv vpv Rp Rpvpv vpv Rp Rp vpv vpv
Irec Irec
- - - - - -
Start Start
T = Tmin T = Tmin
G=0 G=0
V=0 V=0 Start Start
j=1 j=1
No No
V < VmaxV < Vmax ipvj-1  0 ipvj-1  0
DV= V + DV
V = V +V
DG= G + DG
G = G +G
Yes Yes
Yes Yes
ipvj  ipvj-1 
f  ipvj-1
ipvj  ipv j-1
 f ipvj-1  
f  ipv  f ' ipv
Solve Solve
G < GmaxG < Gmax
ipvpv–,G,T)
ipv – f(ipv,V f(ipv,V=pv0,G,T) = 0
j-1 j-1
 
No No j = j+1 j = j+1
T = T + DT
T = T + DT
pv f  ipv   
ipvjNo f  ipv
Store calculated
Store calculated No jj j
ipv(Vpv,G,T) ipv(Vpv,G,T)
Yes Yes
T < Tmax T < Tmax in 3D LUT in 3D LUT
Yes Yes
No No ipvj  ipv iVpvj pv, Gipv, TV pv , G, T 
End End End End

(a) (b)
F IGURE 2.6: 3D lookup table calculation. (a) General procedure. (b) Details of the block
i pv ,1 “Solve
i
dc-MIC
ipv − f (ipv
1 dc-MIC1 i , Vpvi,iG, T ) i= 0” in Fig. 2.6a.
pv ,1 o dco dc
+ + + +
v pv ,1 v v vo ,1
- Ci ,1- pv ,1 Ci ,1 Co ,1 o ,1
- Co ,1 - ipv1
10 + +
i pv ,2 i pv ,2 2 dc-MIC2
dc-MIC
G1
+ + + + PV Inverter
PV Inverter T1 vpv1 D1
v pv ,2 v vo,2 vo,2 8 Grid Grid
Ci ,2- pv ,2 Ci ,2 Co,2
- - Co,2 - -
vdc 6 vdc vac vac ipv2 ipv1
i pv ,k i pv ,k k dc-MICk C
ipv [A]
dc-MIC Cdc
dc
+ + +
+ + + + G2 G1
v pv ,k v pv ,k vo ,k vo ,k 4 v
- Ci ,k- Ci ,k Co,k - Co,k - T2 vTpv2 D2vpv1s D1
1
i pv ,n i pv ,n n dc-MICn
dc-MIC 2 is
- -
+ + + + 1 ipv3 ipv2 vs
v pv ,n v pv ,n vo,n vo,n 0
Ci ,n- Ci ,n Co,n 0.5 G + +
- - Co,n - 0 10 3 G2
vpv [V] 20 30
G1 G1
0 G [kW/m2 ] is
40
Power Supply Power Supply
T3 vTpv3 D3vpv1 D2
2
F IGURE 2.7: PV module current ipv for varying PV module voltage vpv and
-
solar- -irradia-
-
tion G, at a constant temperature of 25 ◦ C.
2.6.2 Non-Uniform Solar Irradiation Effects
The mathematical framework discussed up to this point, allows to express the current
generated by a PV module as a function of the voltage at its terminals, as well as the
value of solar irradiation and temperature. A recurring situation is one where multiple PV
V=0 Start
j=1
No
V < Vmax ipvj-1  0
V = V + DV
DG
Yes
Chapter 2. PV Modelling Techniques for Power 

f ipvj-1
ipvj  ipvj-1 Electronics
 
Simulation 32
 
Solve
ax
ipv – f(ipv,Vpv,G,T) = 0 f ipvj-1
No j = j+1
DT modules are connected in series. A PV module is itself belonging to this category, since it
 
Store calculated No
ipvj 
ipv(Vpv,G,T) is usually composed of multiple groups of cells 
f ipvjconnected in series, each group forming
ax in 3D LUT a sub-module, with each sub-module paralleled to a bypass diode, similarly to Fig. 2.8.
Yes
ipv  ipv Vpv , G, T 
No When multiple PV modules are connected
j in series, the overall i-v string characteristic
may not be as simple as a scaled version of the individual PV module i-v curve. If the PV
End End
modules are not subjected to the same solar irradiation or temperature, or their i-v curve
is not identical due to manufacturing tolerances, different ageing or PV technology, they
are said to be mismatched. In the mismatched case, special considerations apply to the
io idc
calculation of the string i-v curve. As an example, a string made of three series connected
+
Co ,1
vo ,1 ipv1
-
+ +
G1
+ PV Inverter T1 vpv1 D1
vo,2 Grid
Co,2 - -
vdc vac ipv2
Cdc
+
+ G2
vo ,k vs
Co,k - T2 vpv2 D2
- is
+ ipv3
vo,n +
Co,n - G3
G1
Power Supply
T3 vpv3 D3
- -
F IGURE 2.8: String composed of three series connected PV modules, with bypass diodes.
PV modules is displayed in Fig. 2.8.

In [48, 64] a mathematical method relying on the Lambert-W function is proposed in
order to trace the i-v curve of a string with mismatched PV modules. Although effective,
such method is based on the construction of a matrix, which assumes large proportions
for a PV string with multiple modules. The matrix is non-linear, and its components are
calculated with extensive use of the Lambert-W function and its derivatives, which may
be non-trivial to compute. On the other hand, in this thesis an alternative and simpler
method is adopted, using the 3D LUT methodology. Rather than representing the PV
module electrical characteristic as a current generator whose current is a function of the
PV module voltage, i.e. ipv = f (Vpv , G, T ), the PV module is represented as a voltage
source, whose voltage is a function of the PV module current, i.e. vpv = f (Ipv , G, T ).
The voltage source representation allows circuit simulation software, such as PLECS, to
work with series connected PV modules, since voltage generators can be connected in
series, whereas current generators can not. In order to obtain a PV module characteristic,
where the PV voltage is given in function of the PV current, a similar procedure to the one
described in Section 2.6.1 is followed. This time, the 3D lookup table points (Fig. 2.5)
are voltages, rather than currents. The point for the generic coordinate Ipvx , Gy and Tz is
Vpv = f (Ipvx , Gy , Tz ). Rather than writing (2.27) in the form ipv − f (ipv ) = 0, it is written
as:
vpv − f (vpv ) = 0 (2.48)
which, for the coordinate Ipvx , Gy and Tz , becomes:

vpv +Rs Ipvx
vpv − Rp Iph (Gy , Tz ) − Rp Io (Tz ) e nNs Vth (Tz )
− 1 − (Rs + Rp ) Ipvx = 0 (2.49)
The only unknown in (2.49) is vpv , which can be calculated by solving (2.49) with the
Newton-Raphson algorithm, as per (2.45) to (2.47).
A string made of three 200 W Kyocera [59] PV modules, connected as in Fig. 2.8 has
been simulated in PLECS. Each module was simulated by means of a 3D LUT for the PV
module voltage. The string current (is ) and power (ps ) characteristics are displayed in
Fig. 2.9, for uniform and non-uniform solar irradiation across the PV modules. The dotted
700
G1 = G 2 = G 3 = 1 [kW/m 2 ]
8
600 G1 =1, G 2 =0.6, G 3 =0.2 [kW/m 2 ]
500 T 1 = T 2 = T 3 = 25 °C
6
400
ps [W]
is [A]
4 300
G1 = G 2 = G 3 = 1 [kW/m 2 ] 200
2
2
G1 =1, G 2 =0.6, G 3 =0.2 [kW/m ] 100
T 1 = T 2 = T 3 = 25 °C
0 0
0 20 40 60 80 100 0 20 40 60 80 100
vs [V] vs [V]
(a) (b)
F IGURE 2.9: Electrical characteristics of the PV string in Fig. 2.8. (a) String current vs.
voltage curve. (b) String power vs. voltage curve.
curve in Fig. 2.9b represents the PV string power characteristic, when the solar irradiation
across the PV modules is not uniform. In such case, the MPPT algorithm must be able to
identify the global maximum among all the power peaks.
In order to design and test this special feature of the MPPT algorithm, a methodology for
modelling non uniformly irradiated PV strings, such as the one described in this paragraph,
is essential.
2.6.3 General Considerations on the Creation and Use of 3D LUTs
The previous paragraphs dealt with the computation and applications of 3D LUTs. This
tool has been proposed to ease the representation of PV modules in power electronics sim-
ulation software. In summary, the 3D LUT stores the value of the PV current for a set of PV
voltage, solar irradiation and temperature values. The value of the PV current is calculated
a priori, running a set of computations (cf. MATLAB code given in [II]) for different values
of solar irradiation and temperature, sweeping a defined PV voltage range, as outlined in
Fig. 2.6.
One alternative to using 3D LUTs is to solve the equation of the PV current (2.27) at
every integration step. In a simulation of a non-inverting buck-boost converter fed by a
PV module, the author has found a 30 % improvement in the simulation speed, when the
PV module was implemented by means of a 3D LUT, rather than by direct resolution of
(2.27) for every integration step. This performance gap also depends on the type of PV
current equation being solved. If a simpler equation is chosen to calculate the PV current,
such as (2.36), proposed in the Standard EN 50530 [61], then calculating the value of the
current at every integration step requires a shorter time, since (2.36) is a direct equation,
while (2.27) is implicit.
Assuming a fixed voltage increment, important parameters in the 3D LUT are the so-
lar irradiation and temperature steps, ∆G and ∆T , chosen by the user. In this regard, a
comparison between the results given by the equation-based model and the 3D LUT-based
model is undertaken, according to Fig. 2.10.
Equation Based Model

(Simulink)
G
ieq
T
3D-LUT Based Model
itable
V = 0 ¸ Voc
i-v curve
3D Lookup Table plot
Function
(PLECS)
3D LUT matrix
(MATLAB)
F IGURE 2.10: Simulation result comparison between equation based and 3D-LUT based
models.
9 0.14
Eq. @ G1 err% @ G1
8 3D LUT @ G1 err% @ G2
0.12
Eq. @ G2 err% @ G3
7
3D LUT @ G2 0.1 err% @ G4
6
Current [A]
Eq. @ G3
Error [%]
5 3D LUT @ G3 0.08
Eq. @ G4
4 0.06
3D LUT @ G4
3
0.04
2
" G = 0.1kW/m2 0.02 " G = 0.1kW/m2
1
T = 25°C T = 25°C
0 0
0 10 20 30 40 0 10 20 30 40
Voltage [V] Voltage [V]
(a) (b)
9 5
err% @ T1
8 err% @ T2
Eq. @ T1
7 4 err% @ T3
3D LUT @ T1
err% @ T4
6 Eq. @ T2
Current [A]
5 3D LUT @ T2 Error [%] 3

Eq. @ T3
4 3D LUT @ T3 2
G = 1kW/m2
3 Eq. @ T4
" T = 25°C
3D LUT @ T4
2 1
G = 1kW/m2
1
" T = 25°C
0 0
0 10 20 30 40 0 10 20 30 40
(c) (d)
F IGURE 2.11: Comparison of i-v curves calculated by means of (2.27) and via the PLECS
3D Lookup Table function [44] with ∆G = 0.1 kW/m2 and ∆T = 25 ◦ C, for a 3D LUT
calculated considering ∆G = 0.1 kW/m2 and ∆T = 25 ◦ C. PV module datasheet [60]. (a)
i-v characteristics calculated for G1 = 0.25 kW/m2 , G2 = 0.5 kW/m2 , G3 = 0.75 kW/m2 ,
G4 = 1 kW/m2 , at T = 25 ◦ C. (b) Current error at the four chosen solar irradiation values.
(c) i-v characteristics calculated for T1 = 5 ◦ C, T2 = 15 ◦ C, T3 = 25 ◦ C, T4 = 35 ◦ C, at G
= 1 kW/m2 . (d) Current error at the four chosen temperatures.
In Fig. 2.11, a ∆T of 25 ◦ C has been selected between the three temperatures (0 ◦ C, 25 ◦ C,

50 ◦ C) for which the 3D LUT has been calculated. The solar irradiation interval chosen for
the calculation of the PV current is 0.1 kW/m2 . Fig. 2.11a compares the i-v curve calcu-
lated by means of the PLECS 3D Lookup Table function [44] and the i-v curve calculated by
means of (2.27), for four different solar irradiation values, while the temperature is held
constant (at 25 ◦ C). The solar irradiation values chosen for the comparison (0.25, 0.5,
0.75, 1 kW/m2 ) do not necessarily correspond to the solar irradiation values at which the
3D LUT is computed, these going from 0 to 1 kW/m2 , in steps of 0.1 kW/m2 . Fig. 2.11b
reports the error between the current whose value is given by the PLECS 3D Lookup Table
function [44] and the current calculated by means of the modelling equations. It is no-
ticeable how the error is close to zero, and the error is the highest when the irradiance is
0.25 kW/m2 . For such value the 3D Lookup Table function [44] output is the result of a
linear interpolation between the current calculated at 25 ◦ C for 0.2 kW/m2 and the cur-
rent calculated at 25 ◦ C for 0.3 kW/m2 . From Fig. 2.11a and Fig. 2.11b, it is apparent
that a solar irradiation interval of ∆G = 0.1 kW/m2 for the 3D LUT allow the results of
the 3D Lookup Table function [44] to be in close accordance with the results given by the
modelling equation (2.27). Fig. 2.11c displays the comparison between the PV current
calculated by means of (2.27) and the PV current given by the PLECS 3D Lookup Table
function [44], similarly to the previous case, but this time holding the solar irradiation
constant at 1 kW/m2 and varying the temperature of interest. It is noticeable how the
output given by the 3D Lookup Table function [44] is different from the PV current cal-
culated solving (2.27). This difference is more prominent for temperatures at which the
3D Lookup Table function [44] has to perform linear interpolation between current values
of the calculated 3D LUT. Fig. 2.12a and Fig. 2.12b display the results of the comparison
between the current calculated by means of (2.27) and by means of the 3D Lookup Table
function [44], at the constant solar irradiation of 1 kW/m2 , with a finer temperature inter-
val ∆T = 10 ◦ C. In the case of Fig. 2.12 it is apparent that the current calculated via the
equations and the current value calculated by the PLECS 3D Lookup Table function [44]
are now in close agreement, as the smaller percent error indicates.
In conclusion, while a 0.1 kW/m2 solar irradiation interval in the 3D LUT was suffi-
cient for the 3D Lookup Table function [44] to output results matching the values given by
(2.27), a ∆T of 25 ◦ C lead to significant error (4 - 5 %) in the current estimated using the
3D LUT when compared to the current calculated with (2.27). A ∆T of 10 ◦ C significantly
reduced the error on the PV current calculated adopting the 3D Lookup Table function [44]
of PLECS.
9
1.5 err% @ T1
8 err% @ T2
Eq. @ T1
7 3D LUT @ T1 err% @ T3
Eq. @ T2 err% @ T4
6
Current [A]
3D LUT @ T2 1
Error [%]
5 Eq. @ T3
4 3D LUT @ T3
Eq. @ T4
3 0.5
3D LUT @ T4
2
1 G = 1kW/m2 G = 1kW/m2
" T = 10°C " T = 10°C
0 0
0 10 20 30 40 0 10 20 30 40
(a) (b)
F IGURE 2.12: Comparison of i-v curves calculated by means of modelling equations and
via the PLECS 3D Lookup Table function [44] with ∆G = 0.1 kW/m2 and ∆T = 10 ◦ C.
(a) Comparison made for four different temperatures: T1 = 5 ◦ C, T2 = 15 ◦ C, T3 = 25 ◦ C,
T4 = 35 ◦ C. PV module datasheet [60]. (b) Current error at the four chosen temperatures.
Clearly, the 3D LUT solar irradiation and temperature resolution influence the precision
of the result, and therefore must be chosen appropriately. Further investigation is required
to determine the trade-off between size, speed of calculation and accuracy offered by the
3D LUT with respect to modelling the PV module by direct resolution of (2.27).
2.7 Summary
This chapter has given an extensive overview of PV modelling for power electronics sim-
ulation. Firstly, selected methods to extract the five electrical parameters Iph , Io , n, Rs
and Rp , from the PV module datasheet values, have been described and compared. These
methods were chosen based on their simplicity of implementation. The comparison re-
vealed a good agreement between the electrical characteristic found in the datasheet and
the one generated by each of the selected methods. Secondly, a complete model allowing
the simulation of the PV module electrical characteristic in solar irradiation and tempera-
ture other than at STC, has been described. The 3D LUT table concept for implementing
simulation models has been introduced, while the process of computing the 3D LUT for
the PV current has been illustrated in detail. Thirdly, the 3D LUT has been used to sim-
ulate a power-mismatched PV string, where the solar irradiation across series connected
PV modules is non-uniform, providing a simpler alternative to the methods found in the
literature. Finally, general considerations on the creation and use of 3D LUTs have been
discussed.
The methodologies presented are suitable for the simulation of one or more series
connected PV modules, while simulation of large arrays including parallel connected PV
strings is left to the dedicated literature. Finally, the content of this chapter is essential for
developing a general understanding of the PV modelling task, which must be faced by any
researcher and practitioner studying and designing PV interfacing converters.
Chapter 3
Non-Inverting Buck-Boost Converter
In this chapter, the working principle of a PV string equipped with non-inverting buck-
boost dc-MICs is introduced. Attention is then drawn to the operation of a single converter.
In particular, the operating mode transition issue, occurring when the converter is required
to work with similar input and output voltage, is discussed in detail. A new smooth-
transition technique, proposed to overcome the presented issue, is described. The benefits
of the new technique are highlighted through comparison with existing techniques and
experimental results performed on a purposely built converter prototype.
3.1 Integration with PV Strings
The importance and energy saving potential brought by distributed maximum power point
tracking in PV systems were discussed in Chapter 1. In the same chapter, it was highlighted
the convergence of researchers towards a non-inverting buck-boost dc-MIC topology. This
section describes the operating principles of a PV string equipped with non-inverting buck-
boost dc-MICs. The discussion on other dc-MIC topologies, such as buck or boost, is left to
the dedicated literature, referenced in Chapter 1.
A string in which every PV module is equipped with a dc-MIC is represented in Fig. 3.1.
The PV string feeds a single phase PV inverter. Each dc-MICk in Fig. 3.1, is represented with
its input and output capacitor outside of the dc-dc converter symbol, for practicality. The
same is valid for the PV inverter, whose input capacitor Cdc has been represented outside
of the dc-ac symbol, in order to help a “physical” visualisation of the dc-link. The Schottky
diode connected in anti-parallel with the output of each dc-MIC, is a solution adopted by
the industry [65]. In fact, if for instance dc-MICk becomes damaged, the current which
is common to the series connected dc-MIC output stages, io , flows through the diode at
the output of dc-MICk , bypassing the converter altogether. In this way the system keeps
38
* PWM
vpv,1 v Cdc
MPPT -+ Cv(s) u vdc
ipv,2 dc-MIC2
G2 + +
T vpv,2 vo,2
- Ci,2 Co,2 - -
q
Chapter 3. Non-Inverting Buck-Boostvpv,2
Converter
* PWM 39
 *
vdc  vdc idc
-+ -+
v
MPPT Cv(s) u Cv(s)
ipv,1 dc-MIC1 io idc

+ + +
vpv,1 vo,1
- Ci,1 Co,1 -
ipv,2 dc-MIC2
+ + PV Inverter Filter G1
vpv,2 vo,2 Lf iac Grid
- Ci,2 Co,2 -
T
vdc +
vac
ipv,k dc-MICk Cdc -
+ +
vpv,k vo,k Lf
- Ci,k Co,k - G2
T
ipv,n dc-MICn
+ +
vpv,n vo,n
- Ci,n Co,n - -
F IGURE 3.1: PV string equipped with dc-MICs, feeding a single phase PV inverter.
operating in case of failure of one or more dc-MICs, thus improving the reliability of the
entire PV system. Finally, it is assumed that the PV inverter interfaces the system to the
ac grid. The switching harmonics in the current at the output of the inverter are removed
by means of a filter, carried out in Fig. 3.1 by two inductors, Lf , for simplicity. Indeed,
higher order filters such as LCL types, with two inductors and one capacitor, are possible,
however they are not needed for the sake of the study described here.
Now that an overview of the operation of a PV string equipped with dc-MICs has been
given, the behaviour of a single dc-MIC is treated more closely. A simplified string made
of two series connected PV modules, each attached to a dc-MIC, is shown in Fig. 3.2. The
bypass diode at each dc-MIC output stage has been omitted for ease of representation.
Each converter input voltage is regulated to track the maximum power point voltage of
the PV module, by means of an MPPT algorithm. The MPPT block supplies the voltage
∗ , and the output of the dc-MIC voltage controller, C (s), is the modulation
reference vpv v
signal u. This signal is compared to a triangular (or sawtooth) high-frequency carrier

inside the PWM block, which outputs the driving pulses q, commanding the on-time of the
converter switches. On the right-hand side of Fig. 3.2, the PV inverter has been replaced
by its simplified average model, which reflects the action of the inverter on the dc-link.
∗ , by varying its current
The inverter maintains a constant dc-link voltage, set to equal vdc
∗ = 2V
input idc . It is assumed that the reference for the dc-link voltage is vdc mpp , i.e. the
PV module rated MPP voltage, Vmpp times the number of PV modules in the string, that is
two in Fig. 3.2.
G < Gmax pv pv
ipv – f(ipv,Vpv,G,T) = 0
No j = j+1
T = T + DT
Store calculated No
ipv(Vpv,G,T) ipvj  f
Yes
T < Tmax in 3D LUT
No ipvj  ipv 
Chapter 3. Non-Inverting Buck-Boost Converter 40
End E
PV Inverter
(average model)
G1 + + +
T vpv,1 vo,1
- Ci,1 Co,1 - ic
q
* PWM
vpv,1 v Cdc
MPPT -+ Cv(s) u vdc
ipv,2 dc-MIC2
G2 + +
T vpv,2 vo,2
- Ci,2 Co,2 - -
q
PWM
v
*
vpv,2
+ v *
vdc idc
MPPT - Cv(s) u -+ Cv(s)
ipv,1PVdc-MIC
F IGURE 3.2:
1 io
string with two dc-MICs iand
dc the PV inverter.
+ + +
vpv,1 vo,1
- Ci,1 Co,1 -
The dc-link current is:
ipv,2 dc-MIC2
+ p+dc Vmpp,1 IPV + Vmpp,2 Impp,2
Inverter
mpp,1
vpv,2 idc = vo,2= Filter iac Grid (3.1)
- Ci,2 Co,2 v-dc 2Vmpp +
vdc Lf
dc-MIC vac
i
and it can be expressed
k Lf
Cdc of one, when normalized
as a fraction with
- respect to the MPP
pv,k
+ +
vpv,k PV module, Impp .vo,k
current of one
- Ci,k Co,k -
When both the PV modules in Fig. 3.2 are collecting the same solar irradiation, in
ipv,n dc-MICn 2 , the dc-link current is i
+ G1 = G2 = 1 kW/m
this instance + dc = 1 × Impp , since in (3.1)
it is Vmpp,1vpv,n
-= VCmpp,2
i,n
= Vmpp vo,n
Co,n and
- Impp,1
- = Impp,2 = Impp . The voltage and the current
at the input of each converter are the same as at the output, as shown in Fig. 3.3a for
I DC-DC2
dc-MIC1 and Fig. 3.3b for dc-MIC2 . In fact, it is (vpv,1 , ipv,1 ) = (vo,1 , io ) forG dc-MICpv,2
1 and
2
+
(vpv,2 , ipv,2 ) = (vo,2 , io ) for dc-MIC2 . Disregarding any power loss, each PV
T module
Vpv,2 is
- Ci,2
operating at its maximum power point, delivering its rated power to the load, which is
receiving pdc = 2 × Vmpp Impp . In the case described, both dc-MICs operate with a voltage
conversion ratio equal to one.
Fig. 3.3c and Fig. 3.3d refer to a condition of non-uniform solar irradiation, where the
PV module connected to dc-MIC1 receives G1 = 1 kW/m2 , and the PV module connected
to dc-MIC2 receives half of the solar irradiation, i.e. G2 = 0.5 kW/m2 . The MPPT action
is such that the maximum power is still extracted from each PV module, regardless of the
solar irradiation value, hence the location of the input operating points (vpv,1 , ipv,1 ) and
(vpv,2 , ipv,2 ), along the constant power curves. In this second case, the string current is
idc = 0.75 × Impp , since in (3.1), it is Vmpp,1 = ∼ Vmpp,2 ∼
= Vmpp and Impp,1 = Impp , while
Impp,2 ∼ = 0.5 × Impp , due to the lower solar irradiation on the second PV module. dc-MIC1 ,
1.5 G1 = 1 kW/m2 1.5 G2 = 1 kW/m2

ppv;2 = 1
ppv;1 = 1
1.25 1.25
in1 = out1 in2 = out2
ipv;1 , io [p.u.]
ipv;2 , io [p.u.]
1 1
idc = 1 idc = 1
0.75 0.75 (vpv;2 ; ipv;2 ) = (vo;2 ; io )
(vpv;1 ; ipv;1 ) = (vo;1 ; io )
0.5 0.5
0.25 0.25
dc-MIC1 dc-MIC2
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
vpv;1 , vo;1 [p.u.] vpv;2 , vo;2 [p.u.]
(a) (b)
1.5 G1 = 1 kW/m2 1.5 G2 = 0.5 kW/m2

ppv;1 = 1 ppv;2 9
= 0.5
1.25 (vpv;1 ; ipv;1 ) 1.25
ipv;1 , io [p.u.]
ipv;2 , io [p.u.]
1 1 (vo;2 ; io )
in1 (vo;1 ; io )
idc = 0.75 idc = 0.75
0.75 0.75 out2
out1
in2
0.5 0.5
0.25 0.25 (vpv;2 ; ipv;2 )

dc-MIC1 dc-MIC2
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
vpv;1 , vo;1 [p.u.] vpv;2 , vo;2 [p.u.]
(c) (d)
F IGURE 3.3: PV module and dc-MIC operating points, for the string in Fig. 3.2. (a): PV
module 1 and dc-MIC1 , when G1 =G2 . (b): PV module 2 and dc-MIC2 , when G1 =G2 . (c)
PV module 1 and dc-MIC1 , when G1 >G2 . (d) PV module 2 and dc-MIC2 , when G1 >G2 .
connected to the fully irradiated PV module, is forced to boost its output voltage, in or-
der to meet the new demand for a lower string current, as per the location of (vo,1 , io ) in
Fig. 3.3c. On the other hand, dc-MIC2 , connected to the shaded PV module, operates as
a buck converter, bringing the output operating point to (vo,2 , io ) in Fig. 3.3d, in order to
meet the required dc-link current. The power transferred to the load in this non-uniform
irradiation case is pdc = 1.5 × Vmpp Impp . If the string of two PV modules is connected
directly to the inverter without dc-MICs, as per Fig. 3.4a, and the inverter input voltage
∗ = 2V
is regulated to vdc mpp , as per the previous case with dc-MICs, then the power trans-
ferred to the inverter is much less, and equal to pdc ∼ = 1 × Vmpp Impp , as per the operating
point highlighted in Fig. 3.4b.
dc
 vdc idc
-+ Cv(s) Chapter 3. Non-Inverting Buck-Boost Converter 42
PV Inverter
(average model)
ipv,1 io idc
+ +
2 G1=1.0 kW/m2
G1
ilter iac Grid vpv,1 ic G2=0.5 kW/m2
T D1
Lf +
1.5
vac - Cdc
pdc [p.u.]
Lf - ipv,2 vdc
+ 1
G2
vpv,2 D2
T
0.5
- -
*
vdc v idc
0
0 0.5 1 1.5 2 2.5
-+ Cv(s) vdc [p.u.]
(a) (b)
F IGURE 3.4: PV string without dc-MICs, and non-uniform solar irradiation (G1 = 1
kW/m2 , G2 = 0.5 kW/m2 ), feeding a single phase PV inverter. (a) PV string configu-
ration. (b) Power transferred to the load, the red circle indicates the operating point,
with vdc = 2Vmpp .
The operating principle of a string equipped with a dc-MIC in every PV module has
been illustrated. Furthermore, the benefit in terms of greater power collected in non-
uniform irradiation conditions has been clarified. Systems with a higher number of PV
modules and dc-MICs, work on the same principle. Each dc-MIC can either operate as a
buck, or as a boost converter, while the PV inverter maintains the dc-link voltage constant,
by varying the current drawn from the dc-link.
Another important concept in a PV string equipped with dc-MICs is the distribution
of the voltages at the converter outputs. In fact, each dc-MIC output voltage is not reg-
ulated [22]. If a string as in Fig. 3.5 is equipped with multiple dc-MICs, for the generic
dc-MICk in the string, it is:
ppv,k ppv,k ppv,k

vo,k = = Pn = vdc Pn (3.2)
idc i=1 ppv,i
i=1 ppv,i
vdc
According to (3.2), the output voltage of the generic dc-MICk , vo,k , is a fraction of the
dc bus voltage, vdc , varying proportionally to the ratio between the power output of the
PV module directly connected to it, ppv,k , and the total PV power delivered by the string,
Pn
i=1 ppv,i . Two main points emerge from (3.2). Firstly, it is the power contribution of the
k-th PV module, ppv,k , with respect to the power delivered by all the PV modules in the
string, ni=1 ppv,i , that determines the portion of vdc at the output of dc-MICk . Secondly,
P
the output voltage of a dc-MIC varies with the solar irradiation, since this is responsible
for the value of the PV power terms in (3.2).
PV Inverter
(average model)
G1 + + +
T vpv,1 vo,1
- Ci,1 Co,1 -
q
* PWM
vpv,1 v
MPPT -+ Cv(s) u
ic
ipv,1 dc-MICk
Gk + + Cdc
T vpv,k vo,k
- Ci,k Co,k - vdc
q
* PWM
vpv,k v
MPPT -+ Cv(s) u
ipv,n dc-MICn
Gn + +
T vpv,n vo,n
- Ci,n Co,n - -
q
* PWM
vpv,n
+ v *
vdc v idc
MPPT - Cv(s) u -+ Cv(s)
F IGURE 3.5: PV string with multiple dc-MICs, feeding a single phase PV inverter.
This section discussed the operating principle of the non-inverting buck-boost dc-MIC
in a PV string. The dc-MIC output stages are series-connected and interfaced to a PV
inverter, which maintains its input voltage constant. The inverter has been represented
with its average model, which excludes the presence of any ac ripple in the dc-link.
In the next section, the operation of an individual non-inverting buck-boost dc-MIC is
explained in more detail, with particular attention to the modulation technique adopted.
3.2 Converter Operation
The power and control stages of the non-inverting buck-boost dc-MIC are represented in
Fig. 3.6. This converter is intended to operate either in the buck mode, or in the boost
mode. In the former case, the buck leg switches are operated according to the duty cycle
d1 of the buck-control switch S1 , while the boost-control switch S3 is permanently off. In
the latter case, S1 is always on, while the duty cycle d2 of the boost-control switch S3
determines the boost operation. Each control switch (S1 , S3 ) has a respective synchronous
rectifier switch (S2 , S4 ) [18, p. 73]. These are used in order to increase the converter
efficiency, as the power loss due the synchronous switches’ on-resistance is generally lower
PLANT ipv Buck leg Boost leg io

+ +
q1 S1 (d1) q4 S4 (1-d2)
G L
vpv Ci Co
vo
T
q2 S2 (1-d1) q3 S3 (d2)
- -
q1 q2 q3 q4
Buck Boost
MOSET MOSFET
Drivers Drivers
ipv vpv * vpv Buck PWM Boost PWM
vpv
MPPT -+ modulator modulator
ev
Voltage
controller
u1 u2
DIGITAL u Duty compensation logic
MICROCONTROLLER
F IGURE 3.6: Non-inverting buck-boost dc-MIC, with synchronous rectifier switches,

power and control stage.
than the power loss which would occur because of the forward voltage drop of power
diodes replacing S2 and S4 .
When the output voltage vo approaches the input voltage vpv , the converter is required to
operate at a voltage conversion ratio close to one, which may not be achievable via the
buck or boost operation alone. In such instance, either a special buck-boost mode, or a
pass-through mode, is applied, as described later in this chapter. In the buck-boost mode,
both legs are switched simultaneously in every switching cycle, while in the pass-through
mode, the upper switches, S1 and S4 , are constantly turned-on, with the lower switches,
S2 and S3 , constantly turned-off. A summary of the converter operating modes is reported
in Table 3.1.
TABLE 3.1: Operating modes and switch duty cycles for the converter
in Fig. 3.6
Switch duty cycle

Operating mode
S1 S2 S3 S4
Buck d1 > 0 1 − d1 > 0 d2 = 0 1 − d2 = 1
Boost d1 = 1 1 − d1 = 0 d2 > 0 1 − d2 > 0
Buck-boost d1 > 0 1 − d1 > 0 d2 > 0 1 − d2 > 0
or
Pass-through d1 = 1 1 − d1 = 0 d2 = 0 1 − d2 = 1
uck leg Boost leg io
Chapter
+ 3. Non-Inverting Buck-Boost Converter 45
S1 (d1) q4 S4 (1-d2)
L iL
Co
vo S5
S2 (1-d1) q3 S3 (d2)
-
Pass-through
q2 q3 q4 ipv Buck leg Boost leg io
Buck Boost
MOSET MOSFET + +
Drivers Drivers q1 S1 (d1) q4 S4 (1-d2)
L
PWM Boost PWM vpv Ci Co
vo
ator modulator
q2 S2 (1-d1) q3 S3 (d2)
- -
u1 u2
ty compensation logic F IGURE 3.7: Non-inverting buck-boost dc-MIC power stage with dedicated pass-through
switch S5 , adapted from [65].
It must be mentioned that in commercial non-inverting buck-boost dc-MICs, the pass-

through operation is achieved by means of an extra switch, (S5 ) in Fig. 3.7 [65], directly
connecting the positive input bus (vpv ), with the positive output bus (vo ), while all other
i
Buck[65]
leg points
Boost leg that theio pass-through mode is
switches are turned off. As pvan example, out
engaged when vpv and vo are+within about ± 2 % of each
S1 (d1)
+
other. The
S4 (1-d2)
extra pass-through
G q1 q4
switch S5 introduces a layer of complexity in the
L operation and control of the converter;
v C Co v
therefore it has been
T excluded from the prototype built;
pv i
iL however, it iso important to remark
that such configuration can be encountered
q2 in1)practice.
S2 (1-d q3 S3 (d2)
M Boost PWM - -
The duty cycles d1 and d2 , responsible for the buck and the boost operation, relate to
modulator
the controller output signal, u, according to the modulation strategy illustrated in Fig. 3.8.
u2 The PWM switching waveform for the control switches, q1 and q3 , are also displayed in
u-1 Fig. 3.8. The PWM signals for the synchronous rectifier switches, q2 and q4 , are comple-
+ - 1
mentary to the ones of the control switches, q1 and q3 , respectively. Fig. 3.8 illustrates a
Duty compensation logic
particular case whenipv,1 dc-MIC
a linearly io controlidcsignal, u, brings the operation of the con-
increasing
1
G1 + +
verter from buck (q3 is+vpv,1
constantly low)
vo,1 to boost (q1 is permanently high). The transition
T - -
between the two different operating modes occurs exactly at u = 1.
q
Boost leg io PWM
v
*
vpv,1
+ MPPT -+ Cv(s) u ic
) q4 S4 (1-d2) PV Inverter
Grid
L ipv,k dc-MICk
Co CL Vo Gk
+ + Cdc
T vpv,k vo,k vdc
d1 ) q3 S3 (d2) - -
- q
q3 q4 PWM
v
*
vpv,k
-+
Buck Boost
OSET MOSFET
MPPT Cv(s) u
ivers Drivers
ipv,n dc-MICn
Boost PWM Gn
modulator + +
T vpv,n vo,n
- - -
u2 q
PWM
u-1 *
vpv,n v
*
vdc  vdc idc
+ - 1 MPPT -+ Cv(s) u -+ Ci(s)
F IGURE 3.8: (Top) High frequency carrier and control signals generating the buck and
the boost leg duty cycles. (Middle) Trailing edge PWM signal for the buck leg control
switch S1 . (Bottom) Trailing edge PWM signal for the boost leg control switch S3 .
3.3 Buck-Boost Transition Mode
In this section the operating mode transition issue, pertaining to the non-inverting buck-
boost dc-MIC, is explained. The problem is treated considering the specific type of gate
driver adopted, which is based on a bootstrap capacitor power supply for the high-side
drivers. Special attention is devoted to the converter voltage gain function, which is stud-
ied to propose a solution to the problem, by means of a new smooth transition technique.
3.3.1 Transition Issues
From Section 3.1 and from the relation (3.2), it is understood that a dc-MIC output volt-
age can undergo wide variations depending on the solar irradiation distribution on the PV
string. For different solar irradiation values, the excursion in the value of a dc-MIC output
voltage is much larger than the change in the MPP voltage. In other words, the output
voltage of a dc-MIC can become lower or higher than its input voltage, therefore forcing
the operating mode to change from buck to boost, and vice versa. Ideally, it is desirable
to have a buck operation with a duty cycle d1 extending up to 100%, and a boost opera-
tion commencing from a duty cycle d2 approaching 0%. In general, because of switching
time constraints, dead-times between the control signal and the switch gate signals [31],
and other difficult to account non-linearities [66] in the converter control circuit, the duty
cycle under buck mode cannot be exploited up to 100%, and under boost mode it cannot
reach values near 0%. This causes a discontinuity in the operating mode transition and
abrupt mode change whenever the output and the input voltage are in close proximity,
i.e. when vo ≈ vpv . This discontinuity, or dead-zone, has been proven to provoke nu-
merous issues, including increased voltage ripples [27–29], uncontrolled oscillation in the
regulated voltage, poor regulation and instability [31].
3.3.2 Ideal Operating Scenario: Unconstrained Duty Cycles
In the ideal operating scenario, the duty cycle d1 and d2 are allowed to vary within the
entire range from zero to one. If the control signal u (in Fig. 3.6) covers the range from
zero to two, the converter is operating in the buck-mode for 0 < u < 1, with d1 = u and
d2 = 0, while it operates in the boost mode for 1 < u < 2, with d2 = u − 1 and d1 = 1.
This case is displayed in Fig. 3.9, and was also covered in Fig. 3.8.
As a consequence of introducing u, and neglecting power losses for simplicity, the con-
verter voltage gain can be expressed by the piecewise function:



 d1 (u) if 0 < u < 1,
vo 
G (u) = = (3.3)
vpv  1
if 1 < u < 2,


1 − d2 (u)

noting that in the ideal scenario described, the buck and boost duty cycles assume values
in all the range from 0% to 100%.
buck mode boost mode

1 1
0.8 0.8
d1
d2
0.6 0.6
0.4 0.4
0.2 d1 0.2
d2
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
u
F IGURE 3.9: Ideal d1 (u), d2 (u) duty cycle characteristics.

3.3.3 Actual Operating Scenario: Constrained Duty Cycles
The converter considered in this work has its switches driven by two half-bridge gate
drivers, one for each leg, operating the high-side drivers by means of a bootstrap capacitor
power supply, whose operation is illustrated in Fig. 3.10. This widespread and low-cost
solution is commonly encountered in practice in converters up to several kilowatt [67,
68]. A dead-time, ∆t in Fig. 3.10, is introduced by the driving circuit to avoid current
shoot-trough in the switches belonging to the same leg. Furthermore, the necessity to
periodically recharge the bootstrap capacitor imposes a minimum time, ton(min) , that the
low-side MOSFET needs to spend in the on-state within a switching period (Tsw ), thus
limiting the maximum S1 on-time while in buck mode, and the minimum S3 on-time while
in boost mode. If the modulation signals sent to the buck and boost leg PWM modulator
are respectively named u1 and u2 , as in Fig. 3.6, as a consequence of the dead-time, ∆t,
and bootstrap capacitor charging time, ton(min) , u1 has an upper limit, u1,max , and u2 has
a lower limit, u2,min , defined in (3.4) and (3.5).
∆t + ton(min)
u1,max =1 − , (3.4)
Tsw
∆t + ton(min)
u2,min = . (3.5)
Tsw
Naming PWM1 the pulsed width modulation waveform at the output of the buck modu-
lator in Fig. 3.6, and PWM2 the pulsed width modulation waveform at the output of the
boost modulator, Fig. 3.11 aids the visualization of the limits stated by (3.4) and (3.5).
Db Rb vpv Db Rb vpv
+Vcc +Vcc
iCb + iCb +
+ Cb + HI Cb
S1 DRV S1
PWM HI + PWM +
q1 ig 1 q
IN Dt - DRV -
L IN Dt - -1
L
iL iL
+Vcc LO +Vcc
+ + LO
DRV S2 DRV S2
ig 2 + +
Dt - q2
-
Dt - q2
-
(a) (b)
F IGURE 3.10: Gate driver and bootstrap circuit operation. (a) Lower switch S2 is on (S1
is off) and the bootstrap capacitor Cb is being charged by the auxiliary power source Vcc .
(b) High side switch S1 is on (S2 is off), Db is reverse biased, and the bootstrap capacitor
Cb discharges to provide power to the high-side gate driver.
1 Dt1+ Dt
PWMPWM + ton(min)
ton(min) 2 Dt2+ tDt
PWMPWM + ton(min)
on(min)
t t t t
Dt TDt
Dt Tsw sw Dt Dt Dt Tsw Tsw
q1 q1 q3 q3Dt Dt Dt Dt
ton(min)ton(min)
ton(min)ton(min)
ton(min) ton(min)
t t t t
Dt Dt Dt Dt Dt Dt Dt Dt Dt Dt
q2 2
ton(min)ton(min)ton(min)
tqon(min) ton(min)ton(min) q4 q4
t t t t
(a) (b)
F IGURE 3.11: Control signal pulsed waveforms. (a) PWM1 is the pulsed waveform at the
output of the Buck PWM modulator of Fig. 3.6 when u1 = u1,max . (b) PWM2 is the pulsed
waveform at the output of the Boost PWM modulator of Fig. 3.6 when u2 = u2,min .

1 1
d1,max
d2,max
0.8 dead zone 0.8
d1
d2
0.6 0.6
0.4 0.4
d1
0.2 u1,max 0.2
1+u2,min d2
d1,min d
0 0 2,min
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
u
F IGURE 3.12: Actual d1 (u), d2 (u) duty cycle characteristics.
The dead time and the minimum on-time constraint for the lower side switches limit the
maximum buck duty cycle and the minimum boost duty cycle, as shown in Fig. 3.12.
G
2
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
u
1.2 G(1+u2,min)
ideal
G(u1,max)
G
1 actual
u1,max 1+u2,min
0.8
0.7 0.8 0.9 1 1.1 1.2 1.3
u
F IGURE 3.13: Ideal vs. actual voltage gain function, obtained from (3.3) and (3.6),
respectively. The difference is due to dead-time ∆t between the controller output and
switch gate signals and ton(min) to recharge Cb .
By taking into account the limitations displayed in Fig. 3.12, it is possible to elicit the
voltage gain in the piecewise form:



 0 if 0 < u < u1,min






d1 (u) if u1,min ≤ u ≤ u1,max











vo 1

if u1,max < u < 1 + u2,min
G(u) = = (3.6)
vpv 

1


if 1 + u2,min ≤ u ≤ 1 + u2,max






 1 − d2 (u)




1


if u > 1 + u2,max .



1 − d2,max
Fig. 3.13 displays the static voltage gain of the converter, in the ideal case expressed by
(3.3) in which d1 and d2 are unconstrained and can exploit the whole range 0-100%,
and in the constrained case expressed by (3.6), where the variation range of d1 and d2 is
limited.
The discontinuity of the voltage gain function is caused by the dead-zone. When the
converter is operated in closed loop and a gain close to unity is required, this discontinuity
is the cause of random jumps in the regulated voltage [27, 31]. Therefore, the ripple in
the regulated voltage increases [27], and the voltage regulation performs poorly when
the gain approaches one [28]. In the PV application, the maximum power point tracking
operation can be jeopardised, and the power conversion efficiency diminished.
3.3.4 Review of Smooth Transition Techniques
The existing literature presents several smooth transition techniques to overcome the ef-
fects of the dead-zone. Most of them avoid the dead-zone by PWM-switching the buck and
the boost leg in the same swithcing cycle, when the buck or boost operation alone would
otherwise not be possible [21, 27, 31]. Furthermore, the majority of the existing literature
on this issue deals with constant output voltage converters and does not examine the PV
application, where it is the converter input voltage to be controlled.
Within the PV scope, only [21] briefly discusses a smooth transition technique, al-
though without proposing a mathematical framework for it. An alternative strategy is
given in [30], where in order to reach a unitary voltage gain, both legs of the non-inverting
buck-boost converter are induced to operate at a duty cycle of 0.5, only during the mode
transition. In [30], when the value of the converter output voltage is close to the input
voltage, the duty cycle of the buck-leg, d1 , is gradually decreased from a value nearing
one, down to 0.5, and the duty cycle of the boost leg, d2 , is progressively increased from
a value close to zero, up to 0.5, yielding d1 = d2 = d = 0.5 at mode transition. Fig. 3.14
represents the converter voltage gain when both legs are operated at the same duty cycle,
with d1 = d2 = d = u. Note that the gain is exactly one when u = 0.5. The objective
in [30], is to have an independent buck or boost operation, with d1 6= d2 as in Table 3.1,
and to work with d1 = d2 = 0.5, when the required voltage gain is one, only at this
point operating on the curve of Fig. 3.14. While this strategy eliminates the dead-zone
when vpv ≈ vo , it requires a large variation of the converter leg duty cycles, which may
be non-trivial to implement. Moreover, for d1 = d2 = d = 0.5, and since the inductor is
connected to the load only during S1 and S3 off-time, the average output current, io , is
4
u
G= 1!u
3
G
d1 = d2 = d = u
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
u
F IGURE 3.14: Non-inverting buck-boost converter voltage gain function, when both legs
are operated with the same duty cycle [18].
io = iL (1 − d), with iL being the average inductor current. This implies that, with d = 0.5,
it is iL = 2 × io , thus with the technique proposed in [30], the inductor conduction loss
is significant at mode transition, decreasing the power conversion efficiency, if compared
with techniques aiming at keeping iL ≈ io during the operating mode transition.
Other smooth transition techniques have been discussed in the literature outside of
the PV scope, nevertheless referring to non-inverting buck-boost converters. In [28], a
dead-zone avoidance technique is examined and tested on a digitally controlled converter,
whose power stage is similar to the one in Fig. 3.6. However, the solution presented to
solve the problem is rather complex, as also pointed out by [31]. On the other hand,
the authors of [31], based on the analysis of three other candidate techniques, describe
an improved hysteretic smooth transition technique, which can be implemented in a dig-
ital microcontroller, and therefore it is used later for comparison purposes. It must be
emphasised that, although various smooth transition methods have been proposed in the
technical literature, the papers cited above do not provide enough details on the type and
the constraints of gate driving circuit, which significantly affects the width of the dead-
zone. Furthermore, although the literature often mentions that the buck and boost duty
cycles have some limitations, this information is rarely associated with the requirements
of the gate driving circuit.
3.3.5 Proposed Smooth Transition Technique
An overlap of buck and boost operating mode is proposed to resolve the mode transition
issue. The principle of the proposed technique is new and is derived from the idea of
maintaining the ideality of the gain function across the dead-zone range, exactly as if the
converter were maintaining buck operation in the range from u = u1,max to u = 1, and
boost operation in the range from u = 1 to u = 1 + u2,min . This is achieved by enforcing
simultaneous switching of the buck and boost legs of the converter during mode transition,
depending on the value of the control signal u.
The discontinuous gain function (3.6) is transformed as follows, with attention de-
voted to the gain value in the dead-zone range, going from u > u1,max to u < 1 + u2,min :



 0 if 0 < u < u1,min






d1 (u) if u1,min ≤ u ≤ u1,max









d1 0 (u)



if u1,max < u < 1


1 − d2,min





vo 
G(u) = = (3.7)
vpv d1,max
if 1 < u < 1 + u2,min


d2 00 (u)




 1 −




1


if 1 + u2,min ≤ u ≤ 1 + u2,max






 1 − d2 (u)




1


if u > 1 + u2,max .


1 − d2,max

In the first part of the dead-zone range, u1,max < u < 1, the boost leg is operated at its
minimum duty cycle d2,min , while the buck leg is operated with a compensated duty cycle
d1 0 (u), which depends on the control signal u and such that d1 0 (u) ≤ d1,max . In the second
part of the dead-zone range, 1 < u < 1 + u2,min , the buck leg is operated at its maximum
duty cycle d1,max and the boost leg is operated with a compensated duty cycle d2 00 (u), such
that d2 00 (u) ≥ d2,min . It remains to find the expressions for d1 0 (u) and d2 00 (u).
In order to comply with the stated goal of having a voltage gain resembling a pure
buck characteristic when u1,max < u < 1, the following constraint must be satisfied:
d1 0 (u)
G(u) = = d1 (u) (3.8)
1 − d2,min
leading to the desired expression for the compensated buck leg duty cycle:
d1 0 (u) = d1 (u) × (1 − d2,min ) (3.9)
When the control signal is within 1 < u < 1 + u2,min , i.e. in the second part of the
dead-zone range, the goal is to have a voltage gain varying as if the converter were purely
operating in the boost mode. Hence, the constraint to be satisfied is:
d1,max 1
G(u) = 00 = (3.10)
1 − d2 (u) 1 − d2 (u)

1 1
d1,max
0.8 0.8
buck-boost
modes
d1
d2
0.6 0.6
0.4 d1 0.4
d2
0.2 u1,max 0.2
1+u2,min
d2,min
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
u
F IGURE 3.15: Duty cycle variation when the proposed compensation technique is ap-
plied.
yielding the sought expression for the compensated boost leg duty cycle:
d2 00 (u) = 1 − d1,max × [1 − d2 (u)] (3.11)
Fig. 3.15 displays the duty cycle d1 (u) and d2 (u) variation with respect to the con-
trol signal u. The presented compensation technique applies in the range u1,max < u <
1 + u2,min , where the duty cycle d1 (u) and d2 (u) vary according to (3.9) and (3.11),
respectively.
By means of the proposed buck-boost operating modes, the control signal vs. voltage
gain function of the actual system with the limitations discussed in Section 3.3.3, resem-
bles the behaviour of the ideal system without duty cycle limitations across the range
u1,max < u < 1 + u2,min , as shown in Fig. 3.13.
Fig. 3.16 displays the duty cycle compensation logic, as programmable in a microcon-
troller. As per the associated block in Fig. 3.6, the duty compensation logic acts on the
incoming control signal, u, and decides the signals u1 and u2 sent to the PWM modulators,
in order to achieve the desired duty cycles.
Start Sta
Read u from voltage conrtroller Read u from vol
u1 = u
u £ u1,max Y u£u
u2 = u-1
N N
u1,max < u < 1 Y u1 = u ´ (1-d2,min)

u2 = u2,min u1,max <
N
N
Y u1 = u1,max
1 < u < 1+u2,min u2 = 1 - d1,max ´ (2-u) 1<u£1
N
N
u1 = u
1+u2,min £ u £ 1+u2,max Y
u2 = u-1 1+u2,min < u
N
u1 = u N
u2 = u2,max u1 = u
u2 = u
Load u1 and u2 to PWM modulators

Load u1 and u2 to P
End
En
F IGURE 3.16: Control signal u compensation logic to obtain the duty cycles displayed in
Fig. 3.15 and eliminate the dead-zone in the range u1,max < u < 1 + u2,min .
3.4 Experimental Validation
In this section, the elements which have been purpose-built to perform the experimental
validation are described: these are the non-inverting buck-boost dc-MIC and the digital
control platform. Following, a set of experiments will validate the principles described
in Section 3.3.5. The performance of the proposed technique is then compared with the
results given by the smooth transition technique of [31].
3.4.1 Experimental Setup Description
A non-inverting buck-boost dc-MIC has been designed and built, with the value of the
power stage passive components calculated as recommended in [65]. The converter, dis-
played in Fig. 3.17a, can process power up to 250 W, with a maximum input voltage of
50 V, and a maximum output voltage of 100 V. The current carrying capability is 10 A
at most for the input port, and 20 A for the output. The converter voltage and current
are sensed utilising Hall effect sensors, providing galvanic isolation between the converter
power stage and the analog to digital converter (ADC) circuits, located in the digital mi-
crocontroller. The measured values are scaled to a voltage level which is suitable for the
ADCs operation (i.e. from 0 to 3.3 V), thanks to a dedicated scaling circuit in the control-
interfacing platform. The control platform is displayed in Fig. 3.17b. In the same platform,
optic transmitters and receivers provide isolation between the PWM signal at the output
of the digital microcontroller and the input of the gate driver, located in the dc-MIC. The
digital microcontroller is a floating point Texas Instruments TMS320F28377D, which has
a maximum clock frequency of 200 MHz, and supports a maximum PWM resolution of
100 MHz [42]. Table 3.2 reports relevant data regarding the converter.
(a)
(b)
F IGURE 3.17: Elements designed and built for the experimental setup. (a) Non-inverting
buck-boost converter. (b) TMS320F28377D control card vertically mounted on the cus-
tomized digital control interface platform.
TABLE 3.2: dc-MIC prototype parameters
Parameter Value Notes

Inductance L = 22 µH Coilcraft AGP4233 [69]
Input capacitance Ci = 110 µF X7R ceramic capacitors
Output capacitance Co = 2.35 µF X7R ceramic capacitors
Switching frequency fsw = 200 kHz Tsw = 5 µs
I/V ratings Silicon, Infineon
MOSFETs
100 A/150 V IPP075N15N3G [70]
Bootstrap supply Texas Instruments
Gate drivers
voltage up to 118 V LM5106 [71]
Primary voltage LEM LV 25-P
vpv , vo sensors RP = 3.75 kΩ (vpv ), 8.3 kΩ (vo )
VPN =10 - 500 V
RM =100 Ω (vpv ), RM =200 Ω (vo )
Primary current LEM LA 55-P
ipv sensor
IPN = 50 A NP =5, RM =200 Ω
Primary current LEM LAX 100-NP
iL sensor
IPN = 16 - 100 A NP =3, RM =200 Ω
3.4.2 Operational Constraints
As discussed in Section 3.3.3, the modulating signal u1 and u2 sent to the buck and boost
PWM modulators are limited as per (3.4) and (3.5), in which the terms ∆t and ton(min) ,
related to the experimental setup being used, need to be elicited. While the dead-time ∆t
is imposed by the gate driver to equal 180 ns, the time to recharge the bootstrap capacitor
can be estimated and depends on the bootstrap capacitor size and MOSFET parameters.
The bootstrap capacitor powers up the high side gate driver, which requires its supply
voltage to be above the under voltage lock out (UVLO) threshold, in order to function.
The UVLO is a protection feature inherent to the gate driver, disabling its own output if the
supply voltage is too low [71]. For this reason, the voltage across the bootstrap capacitor
must not fall below the UVLO threshold. The minimum on-time to recharge the bootstrap
capacitor, ton(min) , can be estimated, and the following example refers to the buck leg of
the converter. During the on-time of the high side switch S1 (Fig. 3.10b), the voltage drop
across the bootstrap capacitor Cb is approximately ∆VCb = Qg /Cb . Qg is the MOSFET
total gate charge supplied by the high side driver to the gate of S1 , and provided by Cb .
The value of Qg is found in the MOSFET datasheet. In order to avoid a gradual decrease
of the voltage across Cb to a value below the UVLO threshold, the charge Qg taken from
t 0 Db Rb
t 0
iCb +
Vcc Cb vCb
-
F IGURE 3.18: Circuit modelling the charge of the bootstrap capacitor Cb . For the buck
leg of the converter, at t = 0: S1 on, S2 off; when t > 0: S1 off, S2 on.
the capacitor Cb during the upper switch (S1 ) on-time (Fig. 3.10b), must be replenished
during the lower switch (S2 ) on-time (Fig. 3.10a). In other words, if the voltage across
Cb has dropped of ∆VCb by the end of the S1 on-time, reaching VCbo , it must be raised to
at least VCbo + ∆VCb by the end of the minimum S2 on-time. For the sake of calculating
the time needed to increase the voltage on Cb of the amount ∆VCb , namely ton(min) , the
charge of the bootstrap capacitor Cb can be modelled, according to the simplified diagram
of Fig 3.18.
The initial (t = 0) capacitor voltage is vCb (0) = VCbo and the capacitor charge is governed
by the time domain equation:
dvCb
vCb = Vcc − VF − Rb Cb (3.12)
dt
where quantities in capital letters are constants, and VF is the voltage drop across the
bootstrap diode Db . In the Laplace domain, accounting for the initial condition of the
capacitor voltage, vCb (0) = VCbo , (3.12) becomes:
Vcc − VF
vCb (s) = − sRb Cb vCb (s) + Rb Cb VCbo (3.13)
s
whose time domain solution (derived step by step in Appendix A) is
t
−R
vCb = Vcc − VF − (Vcc − VF − VCbo )e b Cb (3.14)
Hence, the current flowing into the capacitor, iCb , and the charge being deposited, Q, can
be respectively expressed as:
dvCb (Vcc − VF − VCbo ) − R tC

iCb = Cb = e b b, (3.15)
dt Rb
Z t
− t

Q= iCb dt = (Vcc − VF − VCbo )Cb 1 − e Rb Cb . (3.16)
0
Finally, the time ton(min) , necessary to restore the charge Qg in the bootstrap capacitor Cb ,
can be calculated from (3.16). In fact:
ton(min)
− R C
Qg = (Vcc − VF − VCbo )Cb 1 − e b b (3.17)
which, solved for ton(min) , leads to the sought-after equation:

Qg
ton(min) = −Rb Cb ln 1 − (3.18)
(Vcc − VF − VCbo )Cb
In the dc-MIC built for the experiment, the bootstrap capacitor has been sized according
to the guideline provided in the gate driver datasheet [71] with some margin, its value
resulting in Cb = 1 µF. The resistance in series with the bootstrap capacitor, has the
function of limiting the capacitor inrush current, and it has been chosen equal to Rb = 2 Ω.
The voltage drop on the bootstrap diode Db , has been assumed to be VF ∼ = 1 V [72],
while the total gate charge parameter is Qg = 93 nC, reported in the Infineon MOSFET
datasheet [70]. With the auxiliary power supply voltage equal to Vcc = 12 V, and assuming
the initial voltage on the capacitor to be VCbo = 10 V, the minimum on-time for the lower
side switch in order to recharge the bootstrap capacitor, is ton(min) ∼
= 200 ns. With ∆t and
ton(min) known, the maximum value of the modulation signal for the buck leg, u1,max , can
be calculated from (3.4) and the minimum value of the modulation signal for the boost
leg, u2,min , can be calculated from (3.5). It follows that the control signal for the buck
operation is limited to the maximum value u1,max = 0.924, while the control signal for the
boost operation has a minimum value limit equal to u2,min = 0.076. As per Fig. 3.15, these
values correspond to a maximum buck duty cycle d1,max = u1,max and a minimum boost
duty cycle d2,min = u2,min .
3.4.3 Open-Loop Test Results
The aim of this experimental validation is to verify the relation between the gain and the
control signal, i.e. G (u), without any compensation as in (3.6), with the compensation
technique outlined in [31], and with the proposed compensation technique applied as per
(3.7). In order to do so, the converter is operated in open-loop, supplied by a constant
input voltage, Vin = 25 V, and feeding a dc electronic load (Kikusui PLZ1004WH) operating
under constant resistance mode, with Ro = 14 Ω. A 220 µF capacitor (CL in Fig. 3.19) is
connected at the load input, for the sake of limiting the ripple on the measured voltage.
The control signal, u, is programmed to increase linearly from 0 to 1.5, forcing the output
voltage to vary and the buck to boost transition to occur. A dual test is performed, with
the control signal programmed to decrease linearly from u = 1.5 to u = 0, to observe the
behaviour during the boost to buck transition. A schematic representation of the dc-MIC
under the described testing conditions is depicted in Fig. 3.19.
With a dead-time ∆t imposed by the gate driver of 180 ns, and a minimum on-time
constraint for the lower side switches of ton(min) = 200 ns, the maximum value of the
control signal for the buck leg and the minimum value of the control signal for the boost
leg are u1,max = 0.924 PLANT
and u2,minipv= 0.076, as explained
Buck leg in Section
Boost leg io 3.4.2. When the
+
operation mode required the high-side +
switch of one leg to be permanently conducting, as
1 q 4
S1 (d1) q S4 (1-d2)
in the pure buck or G
boost mode, the bootstrap capacitor
L of that leg is recharged at every
vo
0.8 ms. This means that during vboost
pv Coperation,
i Co at every
S1 is turned off 0.8 ms, while in
T
the buck operation S4 is turned off at everyS0.8
(1-dms.
) S3 (d2)
-
q2 2 1 q3 -
From Figs. 3.20a-3.20b it is possible to observe the discontinuity in the gain func-
q1 q2 q3 q4
tion, zoomed around a control signal value u = 1, if no compensation
Buck Boost technique is ap-
MOSET MOSFET
plied. Figs. 3.20c-3.20d show the behaviour of Drivers
the gain functionDrivers
if the technique proposed
ipv vIn
in [31] is implemented. pv the v case, albeit the Boost
latter dead-zone
PWM is avoided employing the
v*pv + pv Buck PWM
simultaneous buck-boost
MPPT operation,
- modulator modulator
G (u) still presents discontinuities at the boundary
v These gain discontinuities, although undesired, are
between different operating modes.
Voltage
[31] andu can unot
inherent to the technique of controller u2 When the proposed compen-
1 be avoided.
DIGITAL Duty compensation logic
sation technique is tested, Figs. 3.20e-3.20f, the discontinuity is eliminated as intended,
MICROCONTROLLER
PLANT ipv Buck leg Boost leg io PLANT i pv B

+ +
+
q1 S1 (d1) q4 S4 (1-d2) S
q1
L
Vin vpv Ci Co CL Ro
vo v pv
Vin Ci
q2 S2 (1-d1) q3 S3 (d2) S
- - q2
-
q1 q2 q3 q4
Buck Boost
MOSET MOSFET
Drivers Drivers
Buck PWM Boost PWM
u = 0…1.5 modulator modulator
u1 u2
u = 1.5…0 u u-1
u + - 1
DIGITAL MICROCONTROLLER ipv,1 dc-MIC1
G1 + +
F IGURE 3.19: Configuration adopted for the open loop tests. The single-pole double- vpv,1 v
T
throw (SPDT) switches within the digital microcontroller represent decisions driven by -
the user. q
PWM
v
*
vpv,1
MPPT -+ Cv(s) u
ipv,k dc-MICk
Gk
+ +
T vpv,k v
-
CH2: G(u)
CH2: G(u)
C2
BUCK DEAD-ZONE BOOST C2
BOOST DEAD-ZONE BUCK
CH1: u
C1 C1
CH1: u
CH1: 0.5p.u./div CH2: 0.4p.u./div TB: 500ms/div CH1: 0.5p.u./div CH2: 0.4p.u./div TB: 500ms/div
(a) (b)
CH2: G(u)
CH2: G(u)
C2
BUCK BUCK-BOOST BOOST BOOST BUCK-BOOST BUCK
C2
CH1: u
C1 C1
CH1: u
(c) (d)
CH2: G(u)
CH2: G(u)
C2
BUCK BUCK-BOOST BOOST C2
BOOST BUCK-BOOST BUCK
CH1: u
CH1: u
C1 C1
(e) (f)
F IGURE 3.20: Open loop test results displaying the converter gain and the control signal
variation. (a) Uncompensated buck to boost transition. (b) Uncompensated boost to
buck transition. (c) Compensated buck to boost transition, with the technique of [31].
(d) Compensated boost to buck transition, with the technique of [31]. (e) Compensated
buck to boost transition with the proposed technique. (f) Compensated boost to buck
transition with the proposed technique.
and the gain function G (u) follows the ideal pattern as if the buck and boost leg duty
cycle could vary across the entire range from zero to one. Another observation on these
results emerges by comparing Figs. 3.20c-3.20d with Figs. 3.20e-3.20f, where it can be
noticed that the width of the simultaneous buck-boost switching operation is wider in
Figs. 3.20c-3.20d than it is in Figs. 3.20e-3.20f. Moreover, in Figs. 3.20c-3.20d the buck-
boost operation is not symmetrically occurring around a control signal u = 1, as it is in
contrast apparent in Figs. 3.20e-3.20f. These discrepancies are caused by the duty cycle
vs. control signal variation strategy of [31, Fig. 9a], which is significantly different from
G L
vpv Ci Co
vo
T
q2 S2 (1-d1) q3 S3 (d2)
- -
q1 q2 q3 q4
Buck Boost
MOSET MOSFET
Drivers Drivers
Chapter 3. Non-Inverting Buck-Boost
*
Converter 62
v pv Buck PWM Boost PWM
MPPT -+ modulator modulator
the one proposed here (Fig. 3.15). v
Voltage
Both the strategy proposed here u1 of [31] employ
and the one
controller
u2 simultaneous switching
DIGITAL u Duty compensation logic
of the buck and the boost leg at mode transition, increasing the switching losses compared
MICROCONTROLLER
to the buck or boost operation alone. Nevertheless, the proposed technique improves the
PV module voltage regulation, decreasing its ripple at the operating mode transition,
PLANTas i pv
demonstrated in the following sections. +
q1 S
v pv
3.4.4 Closed-Loop Test Results Vin Ci
A. Closed Loop Performance with Constant Input Voltage q2 S

-
This experimental testing phase is focused on the closed loop operation of the converter
as if it was employed in a PV string as per Fig. 3.1. The objective here is to observe the
Buck PWM Boost PWM
u = 0…1.5 during the
input voltage ripple occurring mode transition,
modulator with and without the proposed
modulator
compensation technique. The schematic of the test setup is shown in Fig. 3.21.
u1 u2
u = 1.5…0 u u-1
u + - 1
DIGITAL MICROCONTROLLER ipv,1 dc-MIC1
G1 +
vpv,1
T -
q
PLANT ipv Buck leg Boost leg io PWM
v
*
v pv,1
+ + MPPT -+ Cv(s) u
i q1 S1 (d1) q4 S4 (1-d2)
L ipv,k dc-MICk
vpv Ci Co CL Vo Gk
+
v vpv,k
T
q2 S2 (1-d1) q3 S3 (d2) -
PV simulator - - q
q1 q2 q3 q4 PWM
v
*
vpv,k
-+
Buck Boost
MOSET MOSFET
MPPT Cv(s) u
Drivers Drivers
ipv,n dc-MICn
ipv vpv vpv Buck PWM Boost PWM Gn
+
vpv* modulator modulator
T vpv,n
MPPT -+ -
v u1 u2 q
Voltage PWM
Vmpp u u-1 v
*
controller vpv,n
+ - 1 MPPT -+ Cv(s) u
u
DIGITAL MICROCONTROLLER
F IGURE 3.21: Configuration adopted for the closed loop tests. The voltage reference
∗
input (vpv ) is either coming from the MPPT algorithm or it is a constant (Vmpp ). In the up
∗
position of the leftmost SPDT switch the votlage reference vpv is determined by the MPPT
∗
algorithm, whereas in the down position vpv is fixed by the user and equal to Vmpp (the
PV module MPP voltage at the given solar irradiation and temperature).
This time the converter is connected to a Regatron PV simulator (TopCon with TC.LIN post-
processing unit [45]) emulating the current vs. voltage (i-v) terminal characteristic of a
100 W crystalline Silicon (cSi) PV module, whose values are given in Table 3.3. The i − v
curve produced by the simulator is according to the PV modelling method recommended
in the standard EN 50530 [61], described in Section 2.5.
TABLE 3.3: Emulated PV module parameters
Parameter Value
Power Ppv = 100 W
Open circuit voltage Voc = 32.9 V
Short circuit current Isc = 4.27 A
Maximum power point voltage Vmpp = 26 V
Maximum power point current Impp = 3.84 A
Voc temperature coefficient* β = −0.4 %/◦ C
Isc temperature coefficient* α = 0.04 %/◦ C
* value given in [61] for cSi technology
In the layout of Fig. 3.1, as mentioned in Section 3.1 and in [17, 22, 73], the output
voltage of each converter varies according to (3.2). Hence, assuming an input voltage
always constant at the Vmpp (note that this is close to reality, since Vmpp is anyway between
70% and 82% of the PV module open circuit voltage [35]), a converter may have its output
voltage varying above and below Vmpp , depending on (3.2), forcing the operation mode
to change from buck to boost and vice versa. This is the scenario recreated in this test,
where the input voltage is held at Vmpp and the output voltage is varied.
A proportional integral (PI) voltage controller, suitable for both buck and boost opera-
tion, was calculated and implemented in the microcontroller to perform the regulation of
the input voltage at the reference value of the panel, Vmpp = 26 V. The discrete PI control
law, with the integration performed via the backward-Euler approximation [74], is:
z
GPI (z) = kp + ki Ts , (3.19)
z−1
with kp = 5 × 10−3 , ki = 40, and a sampling time of Ts = 5 µs as the input voltage is sam-
pled at every switching cycle. In order to cause the buck-boost transition, while the input
reference voltage is held constant at Vmpp , the output voltage is varied by means of an
electronic load, operating in constant voltage mode and having a 220 µF capacitor across
its input terminals, so as to recreate the configuration of Fig. 3.1, where each converter
output sees a portion of the dc-link capacitance (which is usually valued up to a few mF).
The load output voltage was increased from 15 V to 35 V in 1 s, forcing the buck to boost
transition on the converter. Also the opposite output voltage variation, from 35 V to 15 V,
was implemented to observe the boost to buck transition. Both tests were performed with
and without the compensation technique applied at the transition mode.
From Fig. 3.22a it is noticeable the ripple generated in the PV voltage due to the dead-
zone when the output voltage approaches or equals the input voltage and no compensation
technique is applied. Fig. 3.22b presents the case where the compensation technique from
[31] is implemented, while Fig. 3.22c shows the result obtained with the compensation
technique proposed in this paper. It is apparent that the duty cycle compensation reduces
both the duration of the input voltage ripple and its magnitude, smoothing the operating
mode transition. When the compensation technique from [31] is applied, the PV voltage
ripple is still present at the boundaries of the simultaneous buck-boost operation mode.
Although considerably reduced, the input voltage ripple is not completely cancelled when
the proposed compensation is applied, meaning that the formulas (3.9) and (3.11) should
account for additional factors whose modelling and identification is rather involved. These
could be for instance non-linearities introduced by the turn-on and turn-off time of the
switches, propagation delays introduced by integrated circuits used, parasitic elements in
the converter PCB. Moreover, as an actual PV module was not available at the time of
testing, the effect of the internal dynamics of the PV simulator adopted should be taken
into account; however, this is out of the scope of this work.
Dvpv » 7V TB: 50ms/div Dvpv » 7V TB: 50ms/div
Dt » 200ms Dt » 200ms
CH4: vpv
CH3: vo
C4
CH2: q3
C3
C2
BUCK BOOST BUCK
C1
CH1-2: 5V/div CH3-4: 10V/div CH1: q1 TB: 500ms/div

(a)
Dvpv » 3V Dvpv » 6V
TB: 50ms/div TB: 50ms/div Dv » 6V
pv
Dvpv » 3V
Dt » 25ms Dt » 100ms Dt » 100ms Dt » 35ms
CH4: vpv
CH3: vo
CH2: q3 BUCK-BOOST
C4 BUCK-BOOST
C3
C2
BUCK BOOST BUCK
C1

(b)
TB: 50ms/div Dvpv » 3.5V TB: 50ms/div

Dvpv » 3.5V
Dt » 50ms Dt » 50ms
CH4: vpv
CH3: vo
C4 BUCK-BOOST CH2: q3 BUCK-BOOST
C3
C2
BUCK BOOST BUCK
C1

(c)
F IGURE 3.22: Effect of operating mode transition due to output voltage change, with
constant input voltage reference. (a) Without compensation. (b) With compensation
technique from [31]. (c) With proposed compensation technique.
B. Closed-Loop Performance with Input MPPT
The same tests of Section 3.4.4 have been reapplied, with the only difference that the
input voltage is now tracking the maximum power point of the emulated PV module.
The schematic of the test setup is again the one of Fig. 3.21. The scope here is to verify
the impact of the dead-zone on the steady state MPPT operation and, once again, the
effectiveness of the proposed compensation technique in reducing the voltage ripple at
the PV module terminals. The Perturb and Observe [75] algorithm was implemented in
the microcontroller, with a voltage perturbation step of 0.5 V and a perturbation time
interval of 100 ms. Also in this instance, the results given by the proposed technique have
been compared with the results obtained with the smooth transition technique of [31].
High voltage ripple at the PV module terminals is noticeable in the presence of the
dead-zone in Fig. 3.23a when there is not any compensation technique applied, and it is
significantly attenuated when the proposed compensation technique is executed as shown
in Fig. 3.23c. With the compensation technique of [31] implemented in the microcon-
troller, Fig. 3.23b, the buck to boost and boost to buck operating mode transitions are
also considerably improved, for the case where no compensation is applied. However, it
is still possible to observe some voltage ripple when simultaneous buck-boost switching is
engaged or disengaged. Such behaviour is attributed to the discontinuity in the converter
gain G (u) vs. control signal u function, as highlighted in Figs. 3.20c-3.20d, pertaining to
the open loop experiments.
Dvpv » 7V TB: 50ms/div Dvpv » 8V TB: 50ms/div
Dt » 200ms Dt » 250ms
CH4: vpv
CH3: vo
C4
CH2: q3
C3
C2
BUCK BOOST BUCK
C1

(a)
Dvpv » 3V Dv » 6VTB: 50ms/div Dvpv » 6V TB: 50ms/div

pv Dvpv » 3V
Dt » 20ms Dt » 60ms Dt » 60ms Dt » 20ms
CH4: vpv
CH3: vo
C3
C2 BUCK BOOST BUCK

C1

(b)
v  7
v pv pv V 3V TB: TB:
50ms/div
50ms/div vpv  3V TB: 50ms/div
tms
t  200 50ms t  50ms
CH4: vpv
CH3: vo
C3
C2 BUCK BOOST BUCK

C1

(c)
input voltage tracking the MPP reference. (a) Without compensation. (b) With compen-
sation technique from [31]. (c) With the proposed compensation technique.
The last test, with the converter in closed-loop control and input voltage tracking the
MPPT reference, shows a worst case scenario where the output voltage could maintain its
value close to the PV module voltage reference, causing the converter to operate around
the dead-zone area for a significant amount of time. In this last case the benefit of the
proposed compensation technique applied is most visible, as seen in Fig. 3.24c. The results
obtained with the technique of [31], Fig. 3.24b, show a voltage ripple at the PV module
terminals occurring when the simultaneous buck-boost operation is engaged.
CH3: vo
CH4: vpv
C4 BOOST CH2: q3
C3
C2 BOOST BOOST
C1 BUCK
(a)
CH3: vo
CH4: vpv
C4
CH2: q3
C3
C2
BOOST BUCK-BOOST BOOST
C1

(b)
CH3: vo
CH4: vpv
C4
CH2: q3
C3
C2
BOOST BUCK-BOOST BOOST
C1

(c)
input voltage tracking the MPP reference, in a worst case scenario where the output
voltage stabilizes close to the input voltage reference. (a) Without compensation. (b)
With compensation technique from [31]. (c) With the proposed compensation technique.
3.5 Summary
In this chapter, the operating principles of dc-MICs were reviewed. It was pointed out
that the non-inverting buck-boost topology is well suitable for this application, due to its
ability to step up or step down the PV module voltage. This is an essential feature, since
the converter output voltage depends on the distribution of the solar irradiation across the
PV string.
The non-inverting buck-boost topology has a known operational issue, due to the dead-
zone occurring at the changeover between the buck and the boost operating modes. The
dead-zone problem, caused by the duty cycle limitations, was studied in depth, and a novel
technique to overcome it has been detailed. The proposed smooth transition technique
is based on an overlap of buck and boost operation at mode transition, with values of
the buck and boost duty cycles such that the continuity of the converter gain function is
maintained across the dead-zone. A set of open-loop experiments served to validate this
principle. Further experimental results, with the converter in a closed feedback loop, have
shown a significant reduction in the magnitude and duration of the voltage ripple at the
converter input terminals, occurring during the operating mode transition.
Overall, the proposed technique has demonstrated to improve the quality of the voltage
regulation and to perform better than existing smooth transition techniques.
Chapter 4
Linear Control of the Non-Inverting

Buck-Boost dc-MIC
In this chapter, the PV module voltage is regulated using linear control techniques, imple-
mented in the non-inverting buck-boost dc-MIC previously described. When the converter
is regulated by a traditional single voltage loop, the operation of the bootstrap capacitor
drivers causes an undesired ripple in the PV module voltage and inductor current, degrad-
ing the quality of the voltage regulation. In order to resolve this issues, a cascaded control
scheme is proposed, resulting in a reduced ripple in the PV module voltage and improved
converter transient response.
4.1 Small-Signal Model
Prior to investigating the challenges posed by the bootstrap driving circuit, small-signal
model and controller design for the non-inverting buck-boost dc-MIC are explained in
detail. Some historical notes and a preamble on small-signal models are necessary.
Power electronics converters are non-linear systems since their circuit configuration
changes according to the state of the switching elements in it. Despite this fact, it is
common practice to analyse these systems using linear control techniques. In fact, starting
from the 1970s [76, 77] and through the 1990s [78–80], enough theory and practice
has been developed, allowing to study power electronics converters like linear systems,
providing that their operation is maintained in the proximity of a quiescent point. This
theory is especially well established for dc-dc converters, and it has also been applied to
ac-dc and dc-ac three phase converters (e.g. [81]).
70
Chapter 4. Linear Control of the Non-Inverting Buck-Boost dc-MIC 71
There are several ways to derive a linearised model, also called the “small-signal”
model, for a switching converter, and these are well explained in [18, 32, 82]. Con-
troller design based on small-signal models is a broadly accepted practice, and it is un-
derstood that these models hold their validity for a relatively wide range of operating
conditions [33, p. 384],[83], around a quiescent point.
4.1.1 Output Voltage vs. Input Voltage Regulated Converters
Small-signal models for constant output voltage dc-dc converters [18, 33] are commonly
found in the literature. In such models, the converter output voltage is a state variable,
subjected to measurement and regulation. Control issues of constant output voltage con-
verters are well known; a typical example is the right half-plane zero [84] of the boost
converter. Assuming that a boost converter is operating in the open-loop, at a quiescent
point having duty cycle D, when this is incremented to D + d, ˜ unexpectedly, the boost
converter output voltage tends to initially decrease, rather than increasing. This occurs
because a greater duty cycle means to charge the inductor for a longer fraction of the
switching period. Therefore, since the load is connected to the inductor for a shorter frac-
tion of the switching period, the output capacitor needs to supply the load for a longer
fraction of the switching period, hence its voltage will initially decrease, rather than in-
crease, when the duty cycle is incremented. If the system were operating in the closed-loop,
after the control senses a decrement of the output voltage following an increase of the duty
cycle, the controller would further increment the duty cycle, causing a further decrement
of the output voltage, and so forth until the output voltage becomes zero. This behaviour
can be understood by studying the small-signal model, and it can be adequately addressed
by a proper controller design, as reported in [18, 33].
If the input voltage, rather than the output voltage, is the regulated variable in a con-
verter whose load is a constant voltage source, like in a boost dc-MIC, the above phenom-
ena would not exist. This fact is visible by the small-signal transfer function, not including
a right half plane zero.
By means of this example, it is understood that input voltage controlled converters
have a different dynamic behaviour from output voltage controlled converters. While
the study of the latter is well documented in the literature, the analysis of input voltage
controlled dc-dc converters is more recent, often associated with converters interfacing
renewable energy generators. In PV systems, the input voltage of the converter interfac-
ing the PV generator is the regulated variable, tracking the reference given by an MPPT
algorithm.
4.1.2 Small-Signal Analysis
While previous texts analysed the dynamics of the simple buck and boost dc-MIC, with the
regulation of the input voltage [34, 35], a dynamic model for the input voltage controlled
non-inverting buck-boost dc-MIC was proposed only recently in [85]. In the resources
mentioned above, the PV module voltage is regulated through a single voltage control
loop. While case studies on the buck [86] and boost [87] dc-MICs with cascaded con-
trol of input voltage and inductor current can be found in the literature, there is limited
knowledge in regards to modelling and cascaded control of the non-inverting buck-boost
dc-MIC. Only [88], reports a small-signal model for the non-inverting buck-boost dc-MIC
suitable for a dual control of inductor current and the input voltage, however the buck-
boost dc-MIC in [88] is permanently operated in the buck-boost mode (as per Fig. 3.14),
contrarily to the modulation strategy adopted by the converter of this thesis, and explained
in Chapter 3. For these reasons, a small-signal model for the non-inverting buck-boost dc-
MIC, suitable for the dual control of the converter input voltage and inductor current is
presented in [IV], and detailed here.
The converter power stage is displayed in Fig. 4.1. Although the dc-MIC is inserted
in a PV string, observing the configuration of Fig. 3.1, the output voltage is represented
by a constant voltage source. In fact, the variation of a dc-MIC output voltage depends
on the PV power, which in turns varies with solar irradiation and temperature. Since the
rate of change of these environmental variables is slow, the variation of the dc-MIC output
voltage is also slow, and its rate of change is negligible when compared to the bandwidth
of the PV voltage and inductor current control loops, hence justifying the constant output
voltage assumption.
The following switching-cycle-averaged state equations apply to the circuit in Fig. 4.1:
dvpv ipv d1 iL
= − (4.1)
dt Ci Ci
diL d1 vpv RL iL (1 − d2 )vo
= − − (4.2)
dt L L L
ipv Buck leg Boost leg io

+ +
q1 S1 (d1) q4 S4 (1-d2)
G
L RL
vpv Ci Co vo
T iL
q2 S2 (1-d1) q3 S3 (d2)
- -
F IGURE 4.1: Power stage considered for deriving the dc-MIC small-signal model.
where the input capacitor voltage, vpv , and the inductor current, iL , are the state variables.
The output capacitor voltage is not a state variable, because, its value is imposed by the
output voltage source, vo , whose rate of change is negligible compared to the other electri-
cal quantities in the system, as previously discussed. Equations (4.1) - (4.2) are non-linear
due to the cross-products between the duty cycles and voltage/current and the presence
of ipv , which is a non-linear function of vpv depending on the PV module i-v characteristic.
In order to derive a linear model, (4.1)-(4.2) can be perturbed about an equilibrium point
(Vpv , IL , Vo , D1 , D2 ). Substituting any average quantity with its equilibrium value plus a
small-signal variation about the equilibrium, yields:
iL = IL + ĩL (4.3)
vo = Vo + ṽo (4.4)
d1 = D1 + d˜1 (4.5)
d2 = D2 + d˜2 (4.6)
vpv = Vpv + ṽpv (4.7)
ipv = Ipv + ĩpv (4.8)
where the tilde sign indicates a small-signal deviation from the steady-state value written
in capital letters. By replacing the average variables in (4.1)-(4.2) with the perturbed
variables (4.3)-(4.8), two sets of equations can be derived. Firstly, the steady-state equa-
tions are derived (where D1 , D2 , Vo are the inputs, while Ipv and Vo are known); these
equations allow to calculate Vpv and IL :
dVpv
= 0 = Ipv − D1 IL (4.9)
dt
dIL
= 0 = D1 Vpv − RL IL − Vo (1 − D2 ) (4.10)
dt
Secondly, disregarding the cross products between small-signal terms, the linear small-
signal equations are:
dv˜pv 1 ˜ D1 ˜ IL
= ipv − iL − d˜1 (4.11)
dt Ci Ci Ci
di˜L D1 RL ˜ Vpv ˜ Vo (1 − D2 )
= v˜pv − iL + d1 + d˜2 − v˜o (4.12)
dt L L L L L
The small-signal equations (4.11)-(4.12) can be arranged according to the state-space

modelling notation [84]:
dx̃
= Ax̃ + Bũ (4.13)
dt
ỹ = Cx̃ + Dũ (4.14)
where x̃ = [ṽpv ĩL ]T is the vector of the small-signal state variables, ũ = [d˜1 d˜2 ṽo ]T the
vector of the small-signal inputs (with d˜1 and d˜2 : control inputs, ṽo : disturbance input)
and ỹ = x̃ = [ṽpv ĩL ]T is the small-signal output vector. With the PV module dynamic
resistance (also known as differential resistance) defined as [48, p. 47]:
v˜pv
rpv , − (4.15)
˜
ipv
using (4.11)-(4.12), the state-space model (4.13)-(4.14) written in the matrix form is:
 
       d˜1
dv˜pv −1 −D1 −IL
Ci  v˜ 0 0
pv
 
dt 
=  rpv Ci  +  Ci d˜2 
 (4.16)
 
di˜L −RL Vpv
dt
D1
L L i˜L L
Vo
L
1−D2  
L
v˜o
    
v˜pv 1 0 v˜
 =   pv  (4.17)
i˜L 0 1 i˜L
dx̃
where (4.16) and (4.17) correspond to dt = Ax̃ + Bũ, and ỹ = Cx̃ + Dũ, respectively
(with D = 0).
Aiming to deduce Laplace domain transfer functions, relating each small-signal input
h i
to each output, (4.13) is used to get x̃ (s) = (sI − A)−1 B ũ (s), with I the diagonal 2 × 2
identity matrix. The output vector in the Laplace domain can be consequently written
h i
as ỹ (s) = C(sI − A)−1 B + D ũ (s), and in this simple case ỹ (s) = x̃ (s). This vector
can be written in the matrix form (4.18), where the elements of the matrix multiplying
ũ (s) = [d˜1 (s) d˜2 (s) ṽo (s)]T are the single input - single output, small-signal transfer
functions.  
" # " # d˜1 (s)
ṽpv (s) Gvpv d1 Gvpv d2 Gvpv vo 
d˜2 (s)

= (4.18)
ĩL (s) G iL d 1 GiL d 2 GiL vo  
ṽo (s)
The transfer functions (4.19) - (4.24) are those used for the controller design:

Vpv −D1 IL rpv Ci rpv Vpv
ĩL D12 rpv +RL
s Vpv −D 1 IL rpv
+ 1
GiL d1 = = (4.19)
d˜1

d˜2 =0 rpv LCi C R r +L
ṽo =0 s2 D12 rpv +RL
+ s Di 2 rL pv
+R
+1
1 pv L

Vo
ĩL D12 rpv +RL
(sCi rpv + 1)
GiL d2 = = (4.20)
d˜2

d˜1 =0 rpv LCi C R r +L
+ s Di 2 rL pv
+R
+1
1 pv L

D1 Vpv +RL IL IL L
ṽpv rpv D12 rpv +RL
s D1 Vpv +RL IL + 1
Gvpv d1 = =− (4.21)
d˜1

d˜2 =0 rpv LCi Ci RL rpv +L
+ s D2 r +R +1
1 pv L

D1 rpv Vo
ṽpv D12 rpv +RL
Gvpv d2 = =− (4.22)
d˜2

d˜1 =0 rpv LCi Ci RL rpv +L
+s D12 rpv +RL
+1
ṽpv
D1 Vpv +RL IL IL L
d˜1 d˜2 =0 rpv Vpv −D1 IL rpv s D1 Vpv +RL IL + 1
ṽo =0
Gvpv iL 1 = =− (4.23)
ĩL Ci rpv Vpv
d˜1 d˜2 =0
s Vpv −D1 IL rpv + 1
ṽo =0
ṽpv
d˜2 d˜1 =0 rpv D1
ṽo =0
Gvpv iL 2 = =− (4.24)
ĩL (sCi rpv + 1)
d˜2 d˜1 =0
ṽo =0
with (4.23) and (4.24) representing the relationship between the variation of inductor
current, ĩL , and the variation of PV voltage, ṽpv , needed to design the PV voltage controller
when the inductor current is also being controlled. Another transfer function of interest is
the one relating the variation of output voltage, ṽo , to the variation of PV module voltage,
ṽpv , being:
D1 (1−D2 )
ṽpv D12 rpv +RL
Gvpv vo = = (4.25)
d˜1 =0

ṽo s2
rpv LCi
+s
Ci RL rpv +L
+1
d˜2 =0 D12 rpv +RL D12 rpv +RL
By means of this transfer function, the change in the input voltage due to the double-line
frequency ripple present at the converter output can be evaluated.
1 1 Gv pv d2 ( s )
1is 1vs
1 1 Gv pv d2 ( s )
1is 1vs
v*pv -  v d1
C (s) e  sTsw Gv pv d1 ( s )
v *
pv +
- v d1
C (s)
v meas
pv
e  sTsw Gv pv d1 ( s ) v
pv
+ T
 s sw
v meas
pv e 2 v pv
T
 s sw
2
e
F IGURE 4.2: Voltage mode control block diagram (VMC).
Inner current loop
v*pv -  v iL* +  i d1 current
Cv ( s ) * Ci ( s ) Inner e  sTsw GG
loop:
iL di1L (, cls1)
(s) Gv pviL1 ( s )
v*pv +-  v iL +- i d1  sT
Cv ( s )
v meas i measCi ( s ) e sw GiL d1 ( si) Gv pviL1 ( s )v
pv L L pv
+ -
meas meas
v pv
iL
T
 s sw iL v pv
2
e
T
 s sw
e T2
 s sw
2
e
T
 s sw
2
e
F IGURE 4.3: Cascaded control block diagram (ACMC), where the inner loop is within the
dashed lines.
In the following sections, a voltage control and a cascaded control scheme are com-
pared. The former is also referred as voltage mode control (VMC), as the PV module
voltage is being regulated. The latter is referred to as average current mode (ACMC)
control, emphasizing that the average inductor current, as well as the PV module voltage
are regulated. The control block diagram for each scheme is represented in Fig. 4.2 and
Fig. 4.3. Here the subscript “1” in the transfer functions and duty cycle stands for the buck
operating mode. For the boost operating mode, the diagrams are identical, substituting
the subscript “1” with “2”.
The delay blocks in Figs. 4.2-4.3 are characteristic of the digital implementation. The
Tsw
half switching period delays in the feedback loop, e−s 2 , represent the delay inherent
with the sample and hold process, as the PV module voltage and the inductor current are
sampled once for each switching cycle, Tsw . The delay of one switching period in the
forward path, e−sTsw , represents the calculation delay because the new value of duty cycle
calculated by the digital controller is executed in the next switching cycle.
4.2 Controller Design
The parameters of the dc-MIC and PV module considered in the forthcoming sections are
the ones reported in Table 3.2 and Table 3.3, respectively.
With the dual control loop, the objective is to design a controller for the outer voltage
loop and a controller for the inner current loop, each suitable for both the buck and
the boost operating mode. In order to verify the controller operation in either of these
TABLE 4.1: Steady state regime of a PV string with 2 dc-MICs, with non-uniform solar
irradiation
PV MODULE & dc-MIC 1 PV MODULE & dc-MIC 2 DC LINK

G1 = 1 kW/m2 G2 = 0.2 kW/m2
T = 25 ◦ C T = 25 ◦ C
Ppv,1 = 100 W Ppv = 19 W
Impp,1 = 3.84 A Impp,2 = 0.77 A
Vmpp,1 = Vpv,1 = 26 V Vmpp,2 = Vpv,2 = 24.5 V Vdc = 52 V
rpv,1 = 6.77 Ω rpv,2 = 31.7 Ω Ppv,1 +Ppv,2
Io = Vdc = 2.29 A
Vo,1 = 43.3 V Vo,2 = 8.7 V
D1,1 = 1 D1,2 = 0.35
D2,1 = 0.4 D2,2 = 0
IL,1 = Impp,1 = 3.84 A IL,2 = Io = 2.29 A
operating modes, a PV string as in Fig. 3.1, but only made of two PV modules with dc-
MICs, is envisaged. In this string, one PV module receives full irradiation, G1 , while the
other PV module is subjected to G2 << G1 . As a consequence, dc-MIC1 operates in the
boost mode, while dc-MIC2 in the buck mode. For the mentioned configuration, the dc
link voltage is regulated by the inverter at vdc∗ = 52 V, i.e. twice the rated PV module MPP
voltage, and the dc-MICs operate their PV modules at the MPP.
Solar irradiation and temperature are known for every PV module in the string, there-
fore, Vpv and Ipv equal respectively Vmpp and Impp , which are determined by the above-
mentioned environmental parameters. It follows that the PV power processed by each
dc-MIC is also known, and disregarding losses for simplicity, this equals the output power
of each dc-MIC. As a result, the output voltage of each converter can be deduced using
(3.2). Finally, the steady-state regime for each dc-MIC in the string can be estimated
from (4.9)-(4.10), is reported in Table 4.1 and is referred in the analysis that follows
(case of PV strings with two dc-MICs). In Table 4.1, the dynamic resistance is calculated
as rpv = Vmpp /Impp [48, p. 47], as each PV module is operated at the MPP. With the
evaluated steady-state values (Vpv , IL , Vo , D1 , D2 ), all the entries in the transfer functions
(4.19)-(4.24) are known, allowing their validation and controller design.
The experimental setup on which the transfer functions are validated is made of a
PV simulator (Regatron TopCon with TC.LIN post-processing unit [45]), an electronic dc
load Kikusui PLZ1004WH operating in constant voltage mode, one prototype non-inverting
buck-boost converter and its control interface, based on the digital microcontroller Texas
Instruments TMS320F28377D. The converter and the control interface are displayed in
Fig. 3.17. The transfer functions have been measured through the software frequency
response analyser (SFRA) tool [89], implemented in the microcontroller without the need
for any additional measuring instrumentation.
Fig. 4.4 and Fig. 4.5 compare the plant transfer functions obtained with different meth-
ods, including: analytical calculation by means of the small-signal model presented in Sec-
tion 4.1.2; results of a PLECS [44] simulation circuit; measurements on the experimental
hardware by means of the SFRA tool. The steady-state points relevant to Fig. 4.4 and
Fig. 4.5 are reported in Table 4.1. The time delays represented in Figs. 4.2-4.3 are taken
into account in the transfer functions plotted. The small-signal model and the PLECS [44]
simulation are in good agreement with the measured transfer functions.
40 50 ~imeas
Magnitude (dB)
Magnitude (dB)
L
20 40 Gimeas d1 =
L
d~1
0 30
meas
v~pv 20
-20 Gvpv
meas d =
d~1
1
-40 10
0 0
90
-45 45
Phase (deg)
0
Phase (deg)
-90
-135 -45
-180 -90
model -135 model
-225 simulation -180
-270 -225 simulation
-315 measurement -270 measurement
-360 -315
-360
102 103 104 105 102 103 104 105
Frequency (Hz) Frequency (Hz)
(a) (a)
40 50 ~imeas
Magnitude (dB)
Magnitude (dB)
L
20 40 Gimeas d2 =
L
d~2
0 30
meas 20
-20 v~pv
Gvpvmeas d2 = d~2 10
-40
0
0 90
-45 45
0
Phase (deg)
Phase (deg)
-90 -45
-135 -90
-180 model -135 model
-225 -180
simulation -225 simulation
-270 measurement -270
-315 measurement
-315
-360 -360
102 103 104 105 102 103 104 105
Frequency (Hz)
Frequency (Hz)
(b) (b)
F IGURE 4.4: Bode plot of duty cycle to F IGURE 4.5: Bode plot of duty cycle
(measured) PV module voltage transfer to (measured) inductor current transfer
functions. (a) Buck mode. (b) Boost functions. (a) Buck mode. (b) Boost
mode. mode.
The measured duty cycle to PV module voltage transfer functions, in Fig. 4.4, are
affected by error over 10 kHz, because this is the bandwidth of the voltage sensor. Data
over 20 kHz produced unreliable results and had been excluded from the analysis of the
transfer functions involving the voltage sensor.
The measured duty cycle to inductor current transfer functions, in Fig. 4.5, are in
accordance with the simulated ones for high-frequency values, as the inductor current
sensor has a bandwidth greater than 200 kHz. The transfer functions in Fig. 4.5 present
visible discrepancies from the calculated ones; the cause of these discrepancies can be
due to errors in the calibration of the current sensor, actual values of passive components
being different from the ones used in the simulation and analysis, and due to the effect of
unmodelled parasitic elements in the printed circuit board (PCB) design.
4.2.1 Single Loop Control
A PI controller for the regulation of the PV module voltage, according to the VMC scheme
in Fig. 4.2, can be designed based on the analysis of the plant transfer function in Fig. 4.4.
The controller is in the form:

2πfz ki
C (s) = kp 1 + = kp + , (4.26)
s s
A choice of kp = 0.005 and ki = 50, is suitable for both the buck and boost operating mode,
and it provides a trade-off between optimal performance and robustness. The open-loop
transfer function for the buck and boost operating modes, with VMC scheme, is shown in
Fig. 4.6.
40 3 40
CGvpv d1 e!s 2 Tsw
Magnitude (dB)
Magnitude (dB)
20 20
0 0
-20 -20
-40 -40
-60 -60
-80 -80
-100 -100
0 0
-45 -45
Phase (deg)
Phase (deg)
-90 -90
-135 -135
-180 model -180
-225 simulation -225
-270 measurement -270
-315 -315
-360 -360
102 103 104 105 102 103 104 105
(a) (b)
F IGURE 4.6: Bode plot of the open-loop transfer function, in VMC. (a) Buck mode. (b)
Boost mode.
The cross-over frequency of the compensated system is less than 1 kHz. Hence the
settling time of the PV module voltage is expected to be longer than 1 ms. If a faster re-
sponse is desired, then kp should be increased. However greater values of kp would cause
the crossover frequency to occur where the phase lag tends to approach -180 ◦ , compro-
mising the control loop stability. Again, the measured results are overlapping with the
predicted ones for most of the frequency range. The behaviour of the measured transfer
functions around and past 10 kHz is due to the limited bandwidth of the voltage sensor
(documented in Table 3.2).
4.2.2 Cascaded Control
This case conforms to the control diagram depicted in Fig. 4.3, where an inner loop regu-
lates the average value of the inductor current, while an outer loop regulates the value of
the PV module voltage.
In order to achieve a current loop cross-over frequency of at least 10 kHz, for both buck
and boost operating modes, a PI controller, in the form (4.26), is designed for the inner
current loop. The PI zero is located at fzi = 2 kHz, while the proportional and integral
gains are chosen as kpi = 0.06 and kii = 800, respectively.
Before designing the controller for the outer voltage loop, the speed of the inner cur-
rent loop can be evaluated by observing its closed-loop frequency response. The results
are displayed in Fig. 4.7.
Up to few tens of kHz, the measured values are in very good accordance with the
PLECS [44] simulation and show a closed-loop bandwidth for the inner current loop
10 10
Magnitude (dB)
Magnitude (dB)
0 0
-3 -3
-10 -10
GiL ;cl1 GiL ;cl2
-20 -20
0 0
-45 -45
Phase (deg)
Phase (deg)
-90 -90
-135 -135
-180 model -180 model
-225 simulation -225 simulation
-315 -315
-360 -360
102 103 104 105 102 103 104 105
(a) (b)
F IGURE 4.7: Bode plot of closed-loop transfer function for the inner current loop. (a)
Buck mode. (b) Boost mode.
Uncompensated voltage loop gain
40 60 3
Cv GiL ;cl1 Gvpv iL1 e!s 2 Tsw
3
GiL ;cl1 Gvpv iL1 e!s 2 Tsw
Magnitude (dB)
Magnitude (dB)
20 40
0 20
0
-20
-20
-40 -40
-60 -60
-80 -80
0 0
-45 -45
Phase (deg)
Phase (deg)
-90 -90
-135 -135
-180 model
-180
-225 -225 model
simulation simulation
-270 -270
-360 -360
102 103 104 105 102 103 104 105
(a) (a)
40 60 3
Cv GiL ;cl2 Gvpv iL2 e!s 2 Tsw
Magnitude (dB)
Magnitude (dB)
20 40
0 20
0
-20
-20
-40 -40
-60 -60
-80 -80
0 0
-45 -45
Phase (deg)
Phase (deg)
-90 -90
-135 -135
-180 -180
-225 model
-225
-270 -270 simulation
-315 -315 measurement
-360 -360
102 103 104 105 102 103 104 105
(b) (b)
F IGURE 4.8: Bode plot of the plant F IGURE 4.9: Bode plot of the open-loop
transfer function for the outer voltage transfer function for the outer voltage
loop, in ACMC. (a) Buck mode. (b) loop, in ACMC. (a) Buck mode. (b)
Boost mode. Boost mode.
greater than 10 kHz. If the speed of the outer voltage loop is now chosen to be much
lower than 10 kHz, then from the outer voltage control loop perspective it is i∗L ≈ iL , as
if iL reached its reference value instantly. Fig. 4.8 displays the frequency response of the
plant seen by the outer voltage loop.
Aiming to achieve a cross-over frequency between 1 kHz and 2 kHz for the outer
voltage loop, the PI controller for this loop is chosen with a proportional gain kpv = 1.
The PI zero is located at fzv = 200 Hz, and finally, kiv = 2πfzv kpv ∼= 1250. The open-
loop transfer function for the outer voltage loop, calculated using the small-signal model
and the circuit simulation, is compared with the measured one in Fig. 4.9. A crossover
frequency between 1 kHz and 2 kHz is guaranteed for the buck and boost operation with
a phase margin approaching 90 ◦ .
4.3 Experimental Results
In the previous sections, small-signal model and controller design for the non-inverting
buck-boost dc-MIC were analysed. In this section, the impact of the bootstrap circuit
operation on the regulation of the PV module voltage is investigated in two cases. In the
first case, the dc-MIC input voltage is controlled by a traditional single voltage loop, while
in the second case the input voltage it is regulated by the proposed cascaded control loop.
A. Bootstrap Capacitor Recharge Issue
As explained in Section 3.3.3, the bootstrap capacitor must be recharged to ensure the cor-
rect function of the high-side driver. In the buck and the boost mode (Table 3.1), one of
the switching legs of the converter must be held with the high-side switch on, which even-
tually discharges the high-side capacitor. Specifically, during boost operation, the high side
switch S1 is supposed to be permanently on. During buck operation, the high-side switch
S4 is supposed to be permanently on. In either case, the high-side switch cannot be kept
permanently turned on; otherwise the bootstrap capacitor would be entirely depleted of
its charge, failing to supply the high side driver. Hence, there is a necessity of regularly
turning-off S1 (while turning-on S2 ) during boost operation, and similarly, S4 must be pe-
riodically turned-off (while S3 is turned-on), during buck operation, to allow the recharge
of the bootstrap capacitor. During the simultaneous buck-boost operation mode, since
both legs of the dc-MIC are being switched, the recharge of the bootstrap capacitor occurs
naturally.
Following, it is shown that when the non-inverting buck-boost input voltage is regu-
lated by means of a single voltage loop (VMC), recharging the bootstrap capacitor causes
an undesired ripple in the PV module voltage and the inductor current. The ripple can
hinder the proper MPPT operation and decrease the energy yield. On the other hand, if
the cascaded control technique is used, the ripple on the PV module voltage induced by
the periodic recharge of the bootstrap capacitor is dramatically reduced, thanks to the fast
action of the current loop, regulating the average value of the inductor current.
B. PV Module Voltage Regulation
The PV module voltage regulation dynamic is here compared in the case of VMC (Fig. 4.2)
and ACMC (Fig. 4.3). With the controller designed as per Section 4.2.1 and Section 4.2.2,
the PV module voltage regulation in response to 1 V step-variations in the PV module
voltage reference, is analysed for VMC and ACMC, in Fig 4.10. The comparison is made
for the buck and boost operating mode at the MPP, with the steady-state calculated in
Section 4.2.
The switching action to recharge the bootstrap capacitors can be deduced from the
waveform at the bottom of Fig. 4.10. In the buck mode, Figs. 4.10a - 4.10b, the lowermost
waveform represents q4 , driving S4 . q4 is set to low at every 0.8 ms, in order to turn-on
S3 and allow the recharge of the boost leg bootstrap capacitor. When S4 is set to low, its
duty cycle is 0.9, i.e. S3 is on for 0.1×Tsw = 0.5 µs, where Tsw = 5 µs. This time is greater
than the minimum on-time of the lower switch needed to recharge the bootstrap capacitor,
calculated in (3.18). Similarly, in the boost mode step responses displayed in Figs. 4.10c -
4.10d, the bottom waveform represents q1 , driving S1 . q1 is set to low at every 0.8 ms (with
0.1×Tsw duty cycle), in this way turning off S1 and turning on S2 , allowing the recharge
of the buck leg bootstrap capacitor. Fig. 4.10 shows that the PV module voltage regulation
is achieved since this voltage settles to the new reference value without steady-state error.
This occurs both in the buck and in the boost mode, for the VMC and the ACMC scheme,
with improved dynamics in the latter case, especially in the boost mode.
Steady-state waveforms in the buck and the boost mode are plotted in Fig. 4.11. These
show the PV module voltage and the inductor current between two bootstrap capacitor
q4:q54:V/div iL: i2L:A/div

5 V/div 2 A/divvpvv: pv
1 :V/div
1 V/div 2 ms/div
2 ms/div q4:q54:V/div iL: i2L:A/div
1 :V/div
1 V/div 2 ms/div
2 ms/div
vpvv=pv25.5
= 25.5
V V vpvv=pv25.5
= 25.5
V V
vpvvpv vpvvpv
vpvv=pv24.5
= 24.5
V V vpvv=pv24.5
= 24.5
V V
iL iL iL iL
iL iL iL iL
q4 q4 q4 q4 S4 SON
4 ON q4 q4 S4 SON
4 ON S4 SOFF
4 OFF
q4 q4
(a) (b)
q1:q51:V/div iL: i2L:A/div

1 :V/div
1 V/div 2 ms/div
1 :V/div
1 V/div 2 ms/div
2 ms/div
vpvv=pv27= V
27 V vpvv=pv27= V
27 V
vpvvpv vpvvpv
vpvv=pv26= V
26 V vpvv=pv26= V
26 V
iL iL iL iL
iL iL iL iL
q1 q1 q1 q1 S1 SON
1 ON S1 SOFF
1 OFF q1 q1 q1 q1 S1 SON
1 ON S1 SOFF
1 OFF
(c) (d)
q4: q5V/div
4: 5V/div
iL: 1A/div
iL: 1A/div vpv:v2V/div
pv: 2V/div TB:TB:
500µs/div
500µs/div q1: q5V/div
1: 5V/div
iL: 1A/div
iL: 1A/div vpv:v2V/div
pv: 2V/div TB:TB:
500µs/div
500µs/div
F IGURE 4.10: PV module
v v(ACMC)
voltage and inductor current behaviour
(ACMC) pv pv
in response to PV mod-
v v(ACMC)
(ACMC) pv pv
vpv v= 28.5V
= 28.5V
pv
ule voltage reference step of 1 V. (a) Buck withv VMC. v= 31V
= 31V
(b) Buck mode with ACMC. (c)
pv pv
v v(VMC)
(VMC) v v(VMC)
(VMC)
vpv
Boost
v= 26.5V
pv = 26.5V
mode with VMC. (d) Boost mode with ACMC.
pv pv
v v= 29V
= 29V
pv pv
pv pv
iL (ACMC)
iL (ACMC)
iL (VMC)
iL (VMC)
iL (ACMC)
iL (ACMC) iL (VMC)
iL (VMC)
iL iLq4 (ACMC)
q4 (ACMC) iL qiL1 (VMC)
q1 (VMC)
q1 (ACMC)
q1 (ACMC)
q4 q4 q4 (VMC)
q4 (VMC) q1 q1
q4:q54V/div iL: i2LA/div

: 5 V/div vpvv: pv
: 2 A/div 1 V/div
: 1 V/div 1 ms/div
1 :V/div
1 V/div 1 ms/div
1 ms/div
q4:q54V/div iL: i2LA/div

: 5 V/div vpvv: pv
: 2 A/div 1 V/div
: 1 V/div 1 ms/div
1 :V/div
1 V/div 1 ms/div
1 ms/div
vpvvpv vpvvpv
vpvv=pv24.5 V V
= 24.5 i i vpvv=pv24.5 V V
= 24.5 i i
L L L L
vpvvpv vpvvpv
iL viL v= 24.5 V V iL vipv
L v= 24.5 V V
pv pv = 24.5 iL iL pv = 24.5 iL iL
q4 q4 q4 q4 S4 SON S4 SOFF
4 OFF
4 ON
qi4L qi4L qi4L qi4L
q4 q4 (a) q4 q4 S4 SOFF
(b) S4 SON
4 ON 4 OFF
q4 q4 q4 q4
q1:q51V/div
DvD iL: i2L» 1 Vvpvv: pv q1:q51:V/div DiLv:Di2Lv:A/div pvv:V
pvv»
: 5 V/div : 2 A/div
A/div : 1 V/div
1 V/div 100100
µs/div 1 ms/div
µs/div 1 ms/div 5 V/div
»2 A/divvV
»0.20.2 1 :V/div
pv 1 V/div 1 ms/div
1µs/div
ms/div
pv 1 V pv pv
100100
µs/div
DvD pvv»pv »
1 V1 V vpvvpv Dt D»t »750 µsµs
750 DvDpvv»
pv »
0.20.2
VV
Dt D»t »2020
µsµs vpvvpv
vqpvv=1V/div
:=
26
1:q5pv
26 Vi : i2 A/div
5V
V/divL L: 2 A/div v v: pv1 V/div
: 1 V/div 1 ms/div
1 ms/div :qv
qv1pv51=pv5=V/div
26 26
V iVL: i2 :A/div
:V/div L 2 A/divvpvv: pv
1 :V/div
1 V/div 1 ms/div
1 ms/div
Dt D»t pv»750
750µs µs iL iL DtD»t »0.20.2
msms
vpvvpv vpvvpv
vpvv=pv26= V
26 V vpvv=pv26= 26
V V
Dt D»t »750750
µsµsiL iL iL iL DtD»t »750 µsµs
750
iL iL iL iL
iL iL q1 q1 1 ON S1 S
S1 SON 1 OFF
OFF q1 q1 1 ON S1 SOFF
S1 SON 1 OFF
qi1L qi1L qi1L qi1L
q1 q1 1 ON S1 S
S1 SON OFF
1 OFF
q1 q1 S1 SON
1 ON S1 SOFF
1 OFF
q1 qq41 : q4: 5V/div

5V/div iL: 1A/div vpv:v2V/div
iL: 1A/div pv: 2V/div TB:TB: 500µs/div
500µs/div q1 q11: q5V/div
1: 5V/div iL: 1A/div vpv:v2V/div
iL: 1A/div pv: 2V/div TB:TB: 500µs/div
500µs/div
vpv v(ACMC)
pv (ACMC) vpv v(ACMC)
pv (ACMC)
vpv28.5V
vpv = = 28.5V (c) vpv v=pv31V
= 31V (d)
q4: q5V/div
iL: 1A/div pv: 2V/divvpv vpv (VMC)
(VMC) TB:TB: 500µs/div
500µs/div q1: q5V/div
iL: 1A/div pv: v2V/div TB:TB: 500µs/div
500µs/div
pv v(VMC)
pv (VMC)
F
vpv26.5V
vpv = =IGURE
26.5V
vpv28.5V
vpv = = 28.5V
4.11: PV voltage and inductor current steady-state
v v(ACMC)
(ACMC) pv pv
v v= 29V
= 29V behaviour
v v(ACMC) between two boot-
(ACMC) pv pv
pv pv
v v= 31V
= 31V pv pv
strap capacitor recharging pulses. (a) Buck mode with VMC. (b)
i (ACMC)
i (ACMC) i (VMC) mode with ACMC.
Buck
i (VMC) L L
L
v v(VMC)
(VMC) pv pv v v(VMC)
(VMC) L
pv pv
v (c) Boost mode with
i (ACMC)
i (ACMC)
L L i VMC.
(VMC) (d) Boost mode with ACMC.
i (VMC) L L
vpv =
pv = 26.5V
26.5V v v= 29V
= 29V pv pv
iL (ACMC)
(ACMC)
iL q(ACMC)
q1 (VMC)
q4 (ACMC)
iL iLq4 (ACMC) iL1 (VMC)
iL q 1 q1 (ACMC) iL (VMC)
iL (VMC)
iL (ACMC)
q4 i(VMC)
q4 (VMC) L (ACMC)
iL (VMC)
iL (VMC)
q4 q4
charging pulses. While the converter is in qbuck
q
mode, as per Fig. 4.11a (VMC) and 1 1
q4 (ACMC)
iL iLq4 (ACMC) i q (VMC) q (ACMC) iL1 q1 (VMC)1 q1 (ACMC)
Fig. 4.11b (ACMC), the recharge of the boost
q (VMC)
q (VMC) 4 4
leg bootstrap capacitor does not seem to L
q4 q4 q1 q1
influence the PV module voltage and inductor current, regardless of the control scheme
adopted. On the contrary, the recharge of the buck leg bootstrap capacitor has a marked
influence on the PV module voltage and inductor current, while the converter operates in
the boost mode, as per Fig. 4.11c (VMC) and Fig. 4.11d (ACMC). This is logical since, in
the boost mode, the buck leg bootstrap capacitor recharge forces the switching of S1 and
S2 , which are more closely connected to the PV module (cf. Fig. 4.1).
The benefit of the ACMC scheme is apparent in the boost mode, where the disturbance
introduced by the buck leg bootstrap capacitor recharge is minimised. The oscillations in
the PV module voltage and inductor current are rapidly compensated by the action of the
dual control loop, as clearly visible in Fig. 4.11d. On the contrary, the VMC scheme does
not dampen the oscillation of the inductor current and the PV module voltage, while in
boost mode, as shown in Fig. 4.11c, degrading the converter steady-state and transient
performance.
500 µs/div
q4: 5 V/div iL: 2 A/div vpv: 1 V/div
vpv
q1,3: 5 V/div iL: 2 A/div vpv: 1 V/div 100 µs/div iL

vpv = 26 V vpv
iL
iL
iL q4
q3 q1
q1 q3 q4
F IGURE 4.12: Steady state waveforms when the converter is operating under the special
buck-boost mode, with vpv ≈ vo .
q1: 5 V/div iL: 2 A/div vpv: 1 V/div 500 µs/div q1: 5 V/div iL: 2 A/div vpv: 1 V/div
Finally, it is worth reporting the

vpv waveforms during the special buck-boost operating
vpv = 26 V vpv = 26 V
mode, where the technique of Fig. 3.15 is applied. In this condition, the converter input
and output voltage are in close proximity, and both the buck and boost legs are switched in
the same switching cycle. The results
iL are displayed for the ACMC scheme only, in Fig. 4.12,iL
iL iL
since the VMC yield an almost identical set of waveforms. Here, the bootstrap capacitor
q1 S1 ON q1
recharge issue does not occur, since both converter legs are switched. Nevertheless, it is
S1 OFF q1
worth pointing out the benefits of the designed special buck-boost operation, leading to
negligible ripple in the inductor current and PV module voltage.
q4: 5V/div iL: 1A/div vpv: 2V/div TB: 500µs/div q1: 5V/div iL: 1A/div vpv: 2V/div
vpv (ACMC) vpv (ACMC)

vpv = 28.5V vpv = 31V
4.4 Summary vpv (VMC) vpv (VMC

vpv = 26.5V vpv = 29V
This chapter considered the non-inverting buck-boost dc-MIC, driven by bootstrapiL capac-
(ACMC)
iL (VMC)
iL (ACMC) iL (VMC)
itor type gate drivers. It was highlighted that the PV module voltage regulation performs
poorly when the dc-MIC
i is regulated by a traditional single voltage loop ischeme,
q4 (ACMC)
L q1 (VMC) qas the
1 (ACMC) L
q4
q4 (VMC) q1
bootstrap capacitor recharge causes undesired oscillations of the PV module voltage and
inductor current. To solve this issue, a cascaded control technique, entailing the regulation
of the PV module voltage and inductor current, was designed and implemented.
The small-signal model of the converter was derived and experimentally validated,
before performing the controller design. Experimental results proved that the presented
cascaded control technique significantly improves the transient and steady-state behaviour
of the converter. In comparison with the traditional single loop control technique, the
cascaded control technique substantially reduces the ripple on the PV module voltage and
the inductor current during the boost operation.
Chapter 5
Non-linear control of the

Non-Inverting Buck-Boost dc-MIC
In this chapter, the non-linear control technique of feedback linearisation is introduced and
implemented on the non-inverting buck-boost dc-MIC, in order to regulate the PV module
voltage. Contrarily to the linear control techniques presented in the previous chapter,
leading to operating point dependent dynamics, the feedback linearisation technique is
shown to yield transient responses independent of the operating point, improving the
quality of the PV module voltage regulation.
5.1 Feedback Linearisation Control Technique
In the previous chapter were discussed linear control techniques used in dc-dc convert-
ers and dc-MICs. Although these are non-linear systems, it was recalled that they can
be linearised about a steady state operating point and, thanks to this process, the well
established tools for the control of linear systems can be applied.
In this chapter, the non-linear control technique of feedback linearisation is introduced,
and its implementation on the non-inverting buck-boost dc-MIC is outlined. The feedback
linearisation control (FLC) technique acts on different principles from the ones described
in Chapter 4. Taking the non-linear equations of a dc-dc converter, averaged over a switch-
ing cycle, these are not perturbed and linearised in order to deduce a linearised model.
Instead, the set of non-linear average equations, are “transformed” into a set of linear
equations [90, p. 646], by appropriately introducing an auxiliary control variable, can-
celling the non-linear terms. This approach is better detailed in the next section, where
this technique is applied explicitly to the non-inverting buck-boost dc-MIC.
86
Chapter 5. Non-linear control of the Non-Inverting Buck-Boost dc-MIC 87
The mathematical foundations and the formalisms of feedback linearisation date back
to 1989 and are reported in [36]. Since then, researchers have applied this control tech-
nique in the field of power electronics. In [91], an introduction can be found, together
with some application examples for simple output voltage controlled dc-dc converters. In
other instances, the FLC technique has been applied to control a three-phase PV inverter
with an LCL filter [38], bi-directional converters in dc microgrids [39, 92] and modular
multilevel converters [40]. In the existing literature, the advantages of adopting the FLC
technique for controlling the input voltage of dc-MICs has not yet been studied, creating a
knowledge gap which is fulfilled in [V], as presented in the following paragraphs.
5.2 Feedback Linearisation Control Laws
The non-inverting buck-boost dc-MIC power stage considered, is the one in Fig. 4.1, op-
erating in accordance with Table 3.1, while the average dynamic equations necessary to
carry out the feedback linearisation technique are (4.1) - (4.2), rewritten below for sim-
plicity as:
dvpv
Ci = ipv − d1 iL (5.1)
dt
diL
L = d1 vpv − RL iL − (1 − d2 )vo (5.2)
dt
The non-linearity in (5.1) - (5.2) is caused by the cross product between time dependent
variables with the duty cycles, and by the presence of the PV module current, ipv , which is
a non-linear function of the PV module voltage, vpv , according to the PV module i-v curve.
In (5.1) and (5.2), the PV module voltage, vpv , and the (average) inductor current, iL ,
are the state variables. These are also chosen as the outputs of interest, whereas the duty
cycles d1 and d2 are the converter control inputs. Application of the FLC technique to (5.1)
and (5.2), allows to design a cascaded controller where an inner current loop regulates the
average inductor current, iL , and an outer voltage loop regulates the PV module voltage,
vpv , with the assumption that the inner current loop is much faster than the outer voltage
loop.
The control laws are derived separately for the buck and the boost operation of the dc-
MIC. As per Table 3.1, when the former operating mode applies, it is d1 > 0 and d2 = 0,
while when the latter operating mode applies, it is d1 = 1 and d2 > 0.
5.2.1 Buck Mode
When the dc-MIC operates in the buck mode, and considering the inductor series resis-
tance RL null for simplicity, (5.1) remains as is, while (5.2) becomes:
diL
L = d1 vpv − vo (5.3)
dt
remembering that in the buck mode it is d2 = 0 (as per Table 3.1). In (5.3), iL is the state
variable as well as the chosen output, while d1 is the control input. If a new control input,
vL , is defined to satisfy:
vL = d1 vpv − vo , (5.4)
then (5.3) is transformed in:

diL
L = vL (5.5)
dt
which is linear from the new control input, vL , to the output, iL . In the Laplace domain,
(5.5) yields:
1
iL (s) = vL (s), (5.6)
sL
noting that the plant relating the new control signal, vL (s), to the current, iL (s), is simply
an integrator, multiplied by 1/L. Based on (5.6), a linear controller, Gci (s), can be de-
signed. This provides the value of, vL , based on the error between the reference current,
i∗L , and the measured current, iL . The current control loop is displayed in Fig. 5.1.
If Gci (s) is carried out by a PI controller, (5.5) can be written as:
diL
L = kpi (i∗L − iL ) + kii ψi (5.7)
dt
dψi
= i∗L − iL (5.8)
dt
where ψi is the integrator output.

It is now worth reminding that the actual control input driving the converter is the
iL* vL 1 iL
Gci(s)
+
-
sL
Ti(s)
F IGURE 5.1: Block diagram for designing the current controller Gci (s). The new linear
plant described by (5.5) is between vL and iL . Ti (s) is the open-loop transfer function,
for the inner current loop.
duty cycle d1 . This needs to be calculated and fed to the buck PWM modulator, once vL is
known. d1 is derived from (5.4) and it is:
vo + kp i (i∗L − iL ) + kii ψi

d1 |d2 =0 = (5.9)
vpv
with ψi conforming to (5.8), and the subscript d2 = 0 is reminding that (5.9) is valid for
the buck mode.
The function of the inner current loop is to regulate the average value of the inductor
current, iL , by setting the value of the duty cycle d1 . The outer voltage loop regulates
the value of the PV module voltage, vpv , by setting the reference value for the average
inductor current, i∗L , which is fed to the inner loop. Assuming an inner current loop faster
that the outer voltage loop, then from the perspective of the outer loop it is i∗ ∼= iL , and
L
the inductor current dynamic can be neglected. In the strength of this assumption, for the
outer voltage loop in the buck mode, (5.9) yields d1 ∼
= vo . When this expression for d1 is
vpv
substituted into (5.3), it results in diL ∼
= 0, as anticipated. Furthermore, with the stated
dt
assumptions for iL and d1 , the PV module voltage dynamic equation (5.1) becomes:
dvpv vo ∗
Ci = ipv − i (5.10)
dt vpv L
which is non-linear because of the presence of ipv and 1/vpv . If the non-linear terms are
substituted with the new control input, iCi , being:
vo ∗
iCi = ipv − i (5.11)
vpv L
the PV module voltage dynamic becomes linear, from the new control input, iCi , to the
output, vpv , and expressed by:
dvpv
Ci = iCi (5.12)
dt
which in the Laplace domain is:
1
vpv (s) = iC (s) (5.13)
sCi i
The plant relating the new control signal, iCi , to the PV module voltage, vpv , is simply
represented by an integrator, multiplied by 1/Ci . Based on (5.13), a linear controller
Gcv (s), can be designed. This provides the value of iCi , based on the error between the
∗ , and the measured, v , PV module voltage. The PV module voltage control
reference, vpv pv
loop is represented in Fig. 5.2.

With Gcv (s) carried out by a PI controller, since iCi is the PI output, (5.12) can be written
as:
dvpv ∗

Ci = kpv vpv − vpv + kiv ψv (5.14)
dt
dψv ∗
= vpv − vpv (5.15)
dt
where ψv is the integrator output. The voltage controller, Gcv (s), outputs the value of the
new control variable iCi , however the actual control input required by the inner current
loop is i∗L , and this can be derived from (5.11), resulting in:
vpv
i∗L |d2 =0 = ∗

ipv − kp v (vpv − vpv ) + kiv ψv (5.16)
vo
with ψv complying with (5.15).

In summary, the designed cascaded control loop for the dc-MIC working in the buck
mode, is represented by (5.9), governing the inner current loop, and (5.16), governing
the outer voltage loop, together with the integrator laws (5.8) and (5.15). The controller
is graphically represented in Fig. 5.3.
5.2.2 Boost Mode
With the dc-MIC working in the boost mode, and disregarding RL as before, (5.1) and
(5.2) become:
dvpv
Ci = ipv − iL (5.17)
dt
diL
L = vpv − (1 − d2 )vo (5.18)
dt
reminding that in the boost mode d1 = 1. In a similar fashion to Section 5.2.1, (5.18) can
be made linear, by means of the new control signal vL , and the control law for the inner
*
vpv iCi 1 vpv
- Gcv(s)
+
sCi
Tv(s)
F IGURE 5.2: Block diagram for designing the voltage controller Gcv (s). The new linear
plant described by (5.12) is between iCi and vpv . Tv (s) is the open-loop transfer function
for the displayed outer voltage loop.
Measurements: vpv ipv iL vo
vpv ipv iL vpv vo
*
vpv iCi iL* - vL 
d2
-
-+ kpv ++ ++ + kpi ++ -+  +
1 1 1
kiv kii
s s
PV module
Chapter 5. Non-linear voltage
control Inductor
of the Non-Inverting current
Buck-Boost dc-MIC 91
control control
vpv ipv vo vpv iL vo vpv
v*
iCi  i * d1
pv  vL 
 
L
-+ kpv ++ ++ +- kpi ++ ++
kiv 1 kii 1
s s
PV module voltage Inductor current
control control
F IGURE 5.3: Feedback linearization control scheme for buck operation (d2 = 0).
Measurements: vpv iL
current loop is deduced to be: vpv iL
* *
vpv + iL - d
- kp1 + ∗ −ki
vpv++− [kpi (i p2L ) + kii ψ
++ ]
i
L
d2 |d1 =1 = 1 − (5.19)
ki1 1 vo k 1
i2
s s
again with ψi conforming to (5.8). For the voltage loop perspective it is again i∗L ∼ = iL ,
as long as the inner current loop is much faster than
control the outer voltage loop. With this
control
assumption, (5.19) becomes 1 − d2 = ∼ v pv
, which substituted in (5.18) returns diL ∼
= 0, as
vo dt
assumed. The PV module voltage dynamic becomes:
dvpv
Ci = ipv − i∗L (5.20)
dt
remaining non-linear because of the presence of ipv . The non-linearity can be removed, by
using the new control signal iCi , as the output of the voltage controller Gcv (s), and such
that:
i∗L = ipv − iCi (5.21)
Similarly to Section 5.2.1, the control law for the outer voltage loop can be elicited, re-
sulting in the actual control signal sent to the inner loop to equal:
i∗L |d1 =1 = ipv − kpv (vpv

∗
− vpv ) − kiv ψv (5.22)
Finally, the designed cascaded control loop for the dc-MIC working in the boost mode, is
represented by (5.19), governing the inner current loop, and (5.22), governing the outer
voltage loop, with the integrator laws as per (5.8) and (5.15). The controller is displayed
in Fig. 5.4.

vpv ipv iL vpv vo
v*
iCi *
iL - vL 
d2
-
pv
-+ kpv ++ ++ + kpi ++ -+  +
1 1 1
kiv kii
s s
control control
F IGURE 5.4: Feedback linearisation control scheme
Measurements: vpv for iL vo operation (d1 = 1).
ipv boost
5.3 Controller
v Design
*
iCi  * d1
pv  i vL 
 
L
+ - kpv ++ ++ +- kpi ++ ++
A unified cascaded controller,

kiv 1 suitable for the buck andkii the boost
1 operation, is now de-
s s
signed based upon the control laws derived in the previous section. The coefficients of the
PI controllers, Gcv (s) and Gcontrol
ci (s), remain the same for either the buck or the boost opera-
control
tion. The measured variables are employed either according to the control laws (5.9) and
(5.16), when the dc-MIC is working in the buck
Measurements: vpv mode,
iL as per the scheme in Fig. 5.3, or
conforming to (5.19) and (5.22),
v when the dc-MIC i is working in the boost mode, as per
pv L
the scheme in Fig. 5.4. v* iL* - d
pv
-+ kp1 ++ + kp2 ++
The inner loop PI controller, Gci (s), is determined based on the analysis of Fig. 5.1,
ki1hold1for both the buck
derived from (5.5) and (5.6), which ki2 and1the boost operating modes.
s s
In principle, a simple proportional (P) controller would be adequate to achieve the desired
1
control ( sL ) containscontrol
regulation, as the plant transfer function in itself an integrator. In practice
though, parasitic resistances should be accounted in the plant transfer function, having
the effect of reducing the system gain at low frequencies, therefore causing a small steady
state error. For this reason Gci (s) and Gcv (s) include a small integral part, so that steady
state errors due to parasitic resistances in the plant transfer function can be eliminated.
With attention to Fig. 5.1, the open-loop transfer function is given by:
Gci (s)
Ti (s) = (5.23)
sL
while the the PI controller is expressed as:

kii kii kpi
Gci (s) = kpi + = s +1 (5.24)
s s kii
highlighting the pole at the origin and the zero at the angular frequency ωzi = kii /kpi . The
speed of the inner current loop relates to its open-loop transfer function Ti (s) cross-over
frequency [32, p. 288], ωi = 2πfi , at which |Ti (jωi )| = 1. If 0 fi fsw , with fsw the
converter switching frequency, then at ωi it is Gci (s) ≈ kpi . Evaluating (5.23) at ωi gives:
kpi
|Ti (jωi )| = 1 ≈ (5.25)
ωi L
from which kpi is chosen as kpi = 2πfi L. The integrator gain, kii , is found imposing that
the zero at ωzi in Gci (s) is far removed from the cross-over frequency ωi . It is chosen:
kii
= 10−3 ωi (5.26)
kpi
resulting in kii = 10−3 ωi kpi .

In a similar fashion, the gains kpv and kiv for the outer loop controller Gcv (s) can be
established. As the aim is to have an outer voltage loop slower than the inner current loop,
the cross-over frequency of the outer loop, named ωv , is chosen to be significantly smaller
than the cross-over frequency of the inner current loop, ωi , such that ωv = 0.1ωi or 0.2ωi .
The gains kpv and kiv are elicited adopting the same framework used to derive kpi and
kii . This time the reference is made to Fig. 5.2, where the plant transfer function has been
derived by applying the Laplace transform to (5.12). The open-loop transfer function is in
this case:
Gcv (s)
Tv (s) = (5.27)
sCi
Finally, it is kpv = ωv Ci and kiv = 10−3 ωv kpv .
Considering the same converter as in Table 3.2, switching at fsw = 200 kHz, and the
PV module as in Table 3.3, the current loop cross-over frequency is chosen sufficiently
lower than fsw , and equal to fi = 10 kHz. Adopting the presented analysis, it follows
that kpi = 1.38 and kii = 87. Selecting a cross-over frequency for the outer voltage loop
fv = 0.2fi , gives fv = 2 kHz, and in turn kpv = 0.69 and kiv = 9. The strategy adopted
so far, has provided a straightforward design for the inner and outer loop PI controllers,
Gci (s) and Gcv (s). This is owing to the simple plant transfer functions (5.13) and (5.6),
including either only the input capacitor or the inductor, as parameters.
5.4 Experimental Results
The performance of the proposed controller, designed with the feedback linearisation con-
trol (FLC) technique, is now compared with the results given by a cascaded controller
(ACMC), designed around the small-signal converter transfer functions, as it was done in
Chapter 4. Also, the latter control structure consists of an outer voltage loop regulating
the PV module voltage, and an inner loop, regulating the average value of the inductor
*
v iCi  * d1
pv  i vL 
 
L
-+ kpv ++ ++ +- kpi ++ ++
1
kiv kii 1
s s
control control
Measurements: vpv iL
vpv iL
*
vpv iL* d
-+ kp1 ++ +- kp2 ++
1
ki1 ki2 1
s s
control C1(s) control C2(s)
F IGURE 5.5: Cascaded controller used for comparison purpose. The variable d at the
controller output is either the duty cycle d1 during buck operation (with d2 = 0), or d2
during boost operation (with d1 = 1).
current. While the FLC controller is summarized in Fig. 5.3 and Fig. 5.4, the controller
for the ACMC scheme is represented in Fig. 5.5, noting that it does not make use of the
feedback signals ipv and vo .
C1 (s), with coefficients kp1 , ki1 , is assigned to regulate the PV module voltage, while
C2 (s), having coefficients kp2 , ki2 , is responsible for the regulation of the average value of
the inductor current. These coefficients have been chosen to ensure a trade-off between
the converter response in the buck and in the boost modes, at different operating points
in the PV module i-v curve. The coefficients are: kp1 = 1, ki1 = 1250 and kp2 = 0.06,
ki2 = 800.
Since the scope of the dc-MIC is to regulate its input voltage, i.e. the PV module
voltage, the converter response to input voltage reference steps, when the FLC or the
ACMC technique is adopted, is experimentally evaluated. It is well known that in the PV
application, it is difficult for the converter to ensure a consistent dynamic performance, as
this greatly depends on the quiescent point on the PV module i-v curve. For this reason, the
voltage regulation of the two compared control schemes is tested with a series of different
∗ = 2 V is
steady-state operating points on the PV module i-v curve. A reference step of ∆vpv
given, starting from a steady state operating point in the current source region (i.e. where
ipv variations are small ∀ vpv ), around the maximum power point (MPP) region (i.e. where
ppv variations are small ∀ vpv ), and in the voltage source region (i.e. where vpv variations
are small ∀ ipv ). The transient response has been recorded for both the buck and the boost
operation.
In the buck case, the solar irradiation on the PV simulator was set to G = 0.5 kW/m2
(lower, blue, curve in Fig. 5.6) and the dc-MIC output voltage was set to Vo = 15 V by
means of a dc electronic load (Kikusui PLZ1004WH) operating in constant voltage mode.
In the boost case it was G = 1 kW/m2 (upper, red, curve in Fig. 5.6) and Vo = 45 V.
5 Current source MPP MPP

Fig. 5.7b Fig. 5.7d Fig. 5.7f
4 Voltage
2 ° source
G = 1 kW/m T = 25 C Fig. 5.7h
3 Current source MPP
i pv [A]
Fig. 5.7a Fig. 5.7c MPP
Fig. 5.7e
2
G = 0.5 kW/m2 T = 25 °C
1 Voltage
source
Fig. 5.7g
0
0 5 10 15 20 25 30 35
v pv [V]
F IGURE 5.6: Operating points on the PV module i-v curve at which different step re-
sponses have been observed.
This choice was made to reflect the dc-MICs behaviour in the output-series connected con-
figuration of Fig. 3.1. In such configuration, the dc-MIC connected to a shaded PV module
is forced to operate in buck mode, increasing its output current, while the dc-MIC con-
nected to the fully irradiated PV module is forced to operate in the boost mode, decreasing
its output current in order to match the string current, as explained in Section 3.1.
The results reported in Fig. 5.7 display the response to step changes in the PV module
∗ . Fig. 5.7a, Fig. 5.7c, Fig. 5.7e and Fig. 5.7g compare the results after
voltage reference vpv
the voltage reference is given a 2 V step, with the converter operating in the buck mode.
While in Fig. 5.7a the PV module is in the current source region (CSR), in Fig. 5.7c and
Fig. 5.7e it is around the maximum power point region (MPPR), and in Fig. 5.7g the PV
module voltage is in the voltage source region (VSR). The same can be said respectively for
Fig. 5.7b, Fig. 5.7d, Fig. 5.7f and Fig. 5.7h, when the dc-MIC is working in the boost mode.
An important remark can be drawn from these waveforms, as they compare the transient
response obtained using the two different control methods. In the case of ACMC, where
the controller has been designed following a classical local linearisation technique [18],
the PV module voltage transient response is significantly different in each case, depending
on the operating point on the PV module i-v curve. The difference in the performance
is apparent, in terms of overshoot and settling time discrepancies. On the other hand,
if the FLC controller is adopted, the transient responses are robust and insensitive to the
operating point on the i-v curve. Only in the case of Fig. 5.7e, ACMC and FLC produce
similar results. With the FLC controller, the transient responses remain consistent when
the converter is operating in buck mode. Also when the converter is operating in the
boost mode, the transient response presents a consistent behaviour, although the transient
evolution is only slightly different from the one experienced in the buck mode.
TB:
TB:
TB:500µs/div
TB: 500µs/div
500µs/div
500µs/div TB:
TB:
TB:500µs/div
TB: 500µs/div
500µs/div
500µs/div
TB:
TB:
TB:500µs/div
TB: 500µs/div
500µs/div
500µs/div TB:
TB:
TB:500µs/div
TB: 500µs/div
500µs/div
500µs/div
vvvvpvpv= =20.5V
20.5V vvvvpv pv::::1V/div
1V/div vvvvpvpv==21V
21V vvvvpv pv::1V/div
1V/div
pv==20.5V
pv 20.5V vvvvpvpv(ACMC)
(ACMC)
pv(ACMC)
pv (ACMC) pv pv 1V/div
1V/div pv==21V
pv 21V pv
pv::1V/div
1V/div
vvvvpvpv= vvvviipvLiipvL::::2A/div
1V/div
1V/div
pv
pv ==
=20.5V
20.5V
20.5V
20.5V vvvvpvpv(FLC)
(FLC)
pv(FLC)
pv (FLC)vvvvpvpv(ACMC)
(ACMC)
pv(ACMC)
pv (ACMC) pvL pv
2A/div
2A/div
2A/div
L 1V/div
1V/div vvvvpvpv==21V
21V
21V vvvvpv
pv==21V
pv pv(ACMC)
(ACMC)
pv(ACMC)
pv (ACMC) vvvvpvpv(FLC)
(FLC)
vvvvipvLipvL::::2A/div
1V/div
1V/div
2A/div
ipvLipvL 1V/div
1V/div
2A/div
2A/div
vvvvpvpv(FLC)
(FLC) iqiq
q iqi4L4::::5V/div
2A/div
2A/div
5V/div pv(FLC)
pv (FLC) iqiq
q iqi1L1::::5V/div
2A/div
2A/div
5V/div
pv
pv (FLC)
(FLC) L
L 4L 5V/div
5V/div
4 2A/div
2A/div vvvvpvpv(ACMC)
(ACMC)
(ACMC)
(ACMC) vvvvpvpv(FLC)
(FLC) L 5V/div
5V/div
L1L1 2A/div
2A/div
q q 44::5V/div
5V/div pv
pv
pv
pv (FLC)
(FLC) q q 11::5V/div
5V/div
vvvvpvpv===18.5V
18.5V qq ::5V/div
44 5V/div vvvvpvpv= =19V
19V qq ::5V/div 5V/div
pv =18.5V
18.5V 11
pv==19V
19V
pv pv
iiLLiiLL(FLC)
(FLC)
(FLC)
(FLC)
vvvvpvpv=
==
=18.5V
18.5V
18.5V
18.5V vvvvpvpv=
==
=19V
19V
19V
19V
pv
pv pv
pv
iiLiiL(FLC)
LL
(FLC)
(FLC)
(FLC)
iiLLiiLL(FLC)
(FLC)
(FLC)
(FLC)
iiLiiL(FLC)
(FLC)
(FLC)
(FLC)
LL
qqqq4444(FLC)
(FLC) qqqq4444(ACMC)
(ACMC) qq
q1111(ACMC)
(ACMC)
(ACMC)
iiLiiL iiLLiiLL(ACMC)
(ACMC)
(ACMC)
(ACMC) (FLC)
(FLC) (ACMC)
(ACMC) iiLiiL iiLLiiLL(ACMC)
(ACMC)
(ACMC)
(ACMC) qq
qq1111(FLC)
(FLC)
(FLC)
(FLC) q (ACMC)
LL qqqq44(FLC)
(FLC) qqq
q44(ACMC)
(ACMC) LL
q
iLiL iiLiiL(ACMC)
(ACMC)
LL(ACMC)
(ACMC) 44 (FLC)
(FLC) 44 (ACMC)
(ACMC) iLiL iiLiiL(ACMC)
(ACMC)
LL(ACMC)
(ACMC) q
qq
q1111(FLC)
(FLC)
(FLC)
(FLC) qq
q1111(ACMC)
(ACMC)
(ACMC)
(ACMC)
qqiqqLi4L4 qiLiL
qqq1111
44
qq44 qq11
qq44 qq11
(a) (b)
TB:
TB:
TB:500µs/div
TB: 500µs/div
500µs/div
500µs/div TB:
TB:
TB:500µs/div
TB: 500µs/div
500µs/div
500µs/div
TB:
TB:
TB:500µs/div
TB: 500µs/div
500µs/div
500µs/div TB:
TB:
TB:500µs/div
TB: 500µs/div
500µs/div
500µs/div
vvvvpvpv==25.5V
pv 25.5V
pv==25.5V
25.5V vvvvpvpv(ACMC)
(ACMC)
pv(ACMC)
(ACMC) vvvvpv pv pv::1V/div
1V/div
pv::1V/div
1V/div vvvvpvpvpv==26V
pv==26V
26V
26V vvvvpv pv pv::1V/div
1V/div
pv::1V/div
1V/div
vvvvpvpv==25.5V
25.5V
pv==25.5V
25.5V vvvvpv (FLC) vvpv
pv(FLC)
pv(FLC)
pv (FLC) pv(ACMC)
(ACMC) vvvviipvLiipvL::::1V/div
1V/div
2A/div
2A/div
2A/div
2A/div
L 1V/div
1V/div vvvvpvpv= =26V
pv==26V
26V
vvvvpv
26V pv(ACMC)
(ACMC)
pv(ACMC)
pv (ACMC) vvvvpvpv(FLC)
(FLC)
pv(FLC)
pv (FLC) vvvviipv
pv iipv
pv 1V/div
1V/div
L::2A/div
2A/div
2A/div
2A/div
L::1V/div
1V/div
L
pv
vvvvpvpv(FLC)
(FLC) vvpvpv(ACMC)
pv (ACMC) iq
pvL
i
pv
: :2A/div
2A/div
pv
vvvvpvpv(ACMC)
(ACMC) vvvvpvpv(FLC)
(FLC) L
qiq qLLi44LL44::2A/div
5V/div
5V/div
5V/div
5V/div (FLC)
(FLC) iq
qiq i : :2A/div
2A/div
qLLi11LL11::2A/div
5V/div
5V/div
pv(FLC)
pv (FLC) 2A/div pv(ACMC)
pv (ACMC) pv
pv 5V/div
5V/div
2A/div
q q
qq44::5V/div : :5V/div
5V/div
5V/div q q : :5V/div
5V/div
vvvvpvpv= =23.5V
23.5V
pv==23.5V
pv 23.5V 44 vvvvpvpv= =24V
24V
pv==24V
pv 24V qq11::5V/div
11 5V/div
vvvvpvpv=
==
=23.5V
23.5V
23.5V
23.5V vvvvpvpv=
==
=24V
24V
24V
24V
pv
pv pv
pv
iiLLiiLL(FLC)(FLC)
(FLC)
(FLC) qq (FLC) q
q4444(FLC)
(FLC) q4444(ACMC)
(ACMC)
(ACMC) qq (FLC) q
q1111(FLC)
(FLC) q1111(ACMC)
(ACMC)
(ACMC)
iiLLiiLL iiiiLiLLiiLL(FLC)
(ACMC)
(ACMC)
(FLC)
(ACMC)
(ACMC) q (FLC) qq (ACMC)
iiLLiiLL
iiLLiiLL(FLC)
(FLC)
(FLC)
(FLC) iiLLiiLL(ACMC)
(ACMC)
(ACMC)
(ACMC)
q (FLC) qq (ACMC)
(FLC)
(FLC) qq (FLC) qq44(ACMC)
q44(FLC)
(FLC) (ACMC) qq (FLC) qq11(ACMC)
q11(FLC)
(FLC) (ACMC)
iLiL iiLLiiLL(ACMC)
(ACMC)
LL(ACMC)
(ACMC) q 44 (FLC) qq44(ACMC)
(ACMC) iLiL iiLiiL(FLC)
LL
(FLC)
(FLC)
(FLC) iiLiiL(ACMC)
(ACMC)
(ACMC)
(ACMC)
q 11 (FLC) qq11(ACMC)
(ACMC)
qqiqqLi4L4 qiLi1L1
qqq11
LL
44
qq44 qq11
qq44 qq11
(c) (d)
vvvvpvpv(ACMC)
(ACMC) TB:
TB:
pv(ACMC)
pv (ACMC) TB:
TB:500µs/div
TB:
TB: 500µs/div
500µs/div
500µs/div TB:500µs/div
TB: 500µs/div
500µs/div
500µs/div
vvvvpvpv(ACMC)
(ACMC) TB:
TB:
pv
pv (ACMC)
(ACMC) TB:
TB:
TB:500µs/div
TB: 500µs/div
500µs/div
500µs/div vv ::1V/div TB:500µs/div
TB: 500µs/div
500µs/div
500µs/div
vvvvpvpv==27.5V
pv 27.5V
pv==27.5V
27.5V vvpv pv pv 1V/div1V/div
pv::1V/div vvvvpvpv==28V
28V
pv==28V
pv 28V vvvvpvpv pv::1V/div
pv::1V/div
1V/div
1V/div
vvvvpvpv==27.5V
27.5V vvvvpvpv(FLC)
(FLC) vvvviipvLiipvL::::1V/div
1V/div vvvvpvpv(ACMC)
pv (ACMC)
pv(ACMC)
(ACMC) vvvvipvLipvL::::1V/div
1V/div
pv==27.5V
27.5V pv(FLC)
pv (FLC) L
2A/div
2A/div
2A/div
2A/div
L 1V/div
1V/div vvvvpvpv=
==
=28V
28V
28V
28V vvvvpvpv(ACMC)
(ACMC) 2A/div
ipvLipvL 1V/div2A/div
1V/div
2A/div
2A/div
vvvvpvpv(FLC)
(FLC)
pv pv pv pv
pv
vvvvpvpv(FLC)
(FLC) iq
qiq i : :2A/div
2A/div
qLLi44LL44::2A/div
5V/div
5V/div pv(FLC)
pv (FLC) pv(ACMC)
pv (ACMC) qiiq
qLii11L11::::2A/div
2A/div
2A/div
5V/div
5V/div
pv
pv (FLC)
(FLC) 5V/div
5V/div
2A/div vvvvpvpv(FLC)
(FLC) q LL 5V/div 5V/div
2A/div
q q : :5V/div
5V/div pv(FLC)
pv (FLC) q q : :5V/div
5V/div
vvvvpvpv= =25.5V
25.5V
pv==25.5V
25.5V qq44::5V/div
44 5V/div vvvvpvpv= =26V
26V qq11::5V/div 5V/div
pv==26V
26V
pv 11
pv
vvvvpvpv=
==
=25.5V
25.5V vvvvpvpv=
pv
pv 25.5V
25.5V iiLLiiLL(ACMC)
(ACMC) pv
pv ==
=26V
26V
26V
26V iiLLiiLL(FLC)
(FLC)
(FLC)
(FLC)
(ACMC)
(ACMC) iiLiiL(FLC)
(FLC)
iiLiiL(ACMC)
(ACMC) LL (FLC)
(FLC)
LL (ACMC)
(ACMC)
iiLLiiLL(FLC)
(FLC)
(FLC)
(FLC) q
qq
q4444(FLC)
(FLC) q
qq
q4444(ACMC)
(ACMC) iiLLiiLL(ACMC)
(ACMC)
(ACMC)
(ACMC) q
qq
q1111(FLC)
(FLC) q
qq
q1111(ACMC)
(ACMC)
iiLLiiLL iiLiiL(FLC)
(FLC)
(FLC)
(FLC)
(FLC)
(FLC) (ACMC)
(ACMC) iiLLiiLL (FLC)
(FLC) (ACMC)
(ACMC)
q iiLiiL(ACMC)
(ACMC)
q
qq
q44(FLC)
(FLC) qq
q44(ACMC)
(ACMC) q
qq
q11(FLC)
(FLC) q
qq
q11(ACMC)
(ACMC)
iLiL LL iLiL
iLiL (FLC)
(FLC) (ACMC)
(ACMC) (ACMC)
(ACMC) (FLC)
(FLC) (ACMC)
(ACMC)
qqqq4444
44 44
qiq
q qLi1L1 LL 11 11
11
qq44 qq11
qq44 qq11
(e) (f)
vvvvpvpv(FLC)
(FLC) TB:
TB: vvvvpvpv(FLC)
(FLC) TB:
TB:
TB:500µs/div
500µs/div
pv(FLC)
pv (FLC) TB:500µs/div
TB: 500µs/div
500µs/div
500µs/div pv(FLC)
pv (FLC) TB: 500µs/div
500µs/div
vvvvpvpv(FLC)
(FLC) vvvvpvpv(FLC)
(FLC) TB:
TB:
vvvvpv pv
pv (FLC)
(FLC) TB:
TB:
TB:500µs/div
TB: 500µs/div
500µs/div
500µs/div (FLC)
(FLC) TB:500µs/div
TB: 500µs/div
500µs/div
500µs/div
pv= =30.5V
30.5V vvvvpv pv
pv
pv==30.5V
30.5V vvvvpv pv::1V/div
1V/div pv==31V
31V vvvvpv pv::1V/div
1V/div
pv::1V/div
1V/div pv==31V
31V pv::1V/div
1V/div
pv pv pv pv
vvvvpvpv=
==
=30.5V
30.5V
30.5V
30.5V vvvvpvpv(ACMC)
pv (ACMC)
pv(ACMC)
(ACMC) vvvviipvLiipvL::::2A/div
1V/div
1V/div
2A/div vvvvpvpv=
==
=31V
31V
31V
31V vvvvipvLipvL::::2A/div
1V/div
1V/div
2A/div
pv
pv
vvvvpvpv(ACMC)
(ACMC) L
pv pv 2A/div
2A/div
L 1V/div
1V/div pv
pv vvvvpvpv(ACMC)
(ACMC) ipvLipvL 1V/div
1V/div
2A/div
2A/div
pv(ACMC)
(ACMC)
pv(ACMC)
(ACMC) iqiqLii4L4::::::2A/div
2A/div iqiq
iqi1L1::::5V/div
2A/div
2A/div
pv q 5V/div
pv
qqL4L4 2A/div 5V/div
5V/div
2A/div
5V/div
5V/div vvvvpvpv(ACMC)
(ACMC) L 5V/div
5V/div
L1L1 2A/div
2A/div
q q : :5V/div
5V/div pv
pv (ACMC)
(ACMC) q q 11::5V/div
5V/div
vvvvpvpv==28.5V
28.5V
pv==28.5V
pv 28.5V qq44::5V/div
44 5V/div vvvvpvpv==29V
29V
pv==29V
pv 29V qq ::5V/div
11 5V/div
vvvvpvpv=
pv
pv
==
=28.5V
28.5V
28.5V
28.5V vvvvpvpv=
pv
pv
==
=29V
29V
29V
29V
iiLLiiLL(ACMC)
(ACMC)
(ACMC) iiLLiiLL(FLC)
(FLC)
(FLC) iiLLiiLL(ACMC)
(ACMC)
(ACMC)
(ACMC)
(ACMC) (FLC) iiLLiiLL(FLC)
(FLC)
(FLC)
(FLC)
iiLiiL(ACMC)
(ACMC) iiLiiL(FLC)
(FLC) iiLiiL(ACMC)
(ACMC)
(ACMC)
(ACMC)
LL(ACMC)
(ACMC) LL(FLC)
(FLC) LL
iiLiiL(FLC)
LL
(FLC)
(FLC)
(FLC)
qq (FLC)
(FLC) qq (ACMC)
iiLiiLqq4444(FLC)
(ACMC)
(FLC) qq4444(ACMC)
(ACMC) iiLiiL q
LLqq (FLC) LL qq
q1111(ACMC)
(ACMC)
(ACMC) q
(ACMC) qq
q1111(FLC)
(FLC)
(FLC)
(FLC)
(FLC)
(FLC) qqqq4444(ACMC)
iLiLqq4444(FLC)
(ACMC)
(ACMC)
(ACMC) iLiL qq11(ACMC)(ACMC)
(ACMC) q
iqLi1L1 qq11(ACMC) qq
q1111(FLC)
(FLC)
(FLC)
(FLC)
qqiqqLi4L4 q
qq11
44
qq44 qq11
qq44 qq11
(g) (h)
F IGURE 5.7: PV module voltage and inductor current dynamics in response to PV voltage
∗
reference steps (green: FLC, blue: ACMC, pink: vpv ). (a) Buck mode in the CSR. (b)
Boost mode in the CSR. (c) Buck mode in the MPPR (23.5-25.5 V). (d) Boost mode in
the MPPR (24-26 V). (e) Buck mode in the MPPR (25.7-27.5 V). (f) Boost mode in the
MPPR (26-28 V). (g) Buck mode in the VSR. (h) Boost mode in the VSR.
TABLE 5.1: PV module voltage step response overshoot (OS) and settling time (TS), with
the converter working in the buck mode. G = 0.5 kW/m2 , Vo = 15 V
vpv OS (ACMC) OS (FLC) TS (ACMC) TS (FLC) Fig.

[V] [%] [%] [ms] [ms] [-]
18.5 → 20.5 27.3 6 2 0.4 5.7a
23.5 → 25.5 23.7 11.8 2 0.4 5.7c
25.5 → 27.5 16.6 17 0.8 0.4 5.7e
28.5 → 30.5 5 12.8 2.5 0.8 5.7g
Standard deviation 9.8 4.5 0.7 0.2
TABLE 5.2: PV module voltage step response overshoot (OS) and settling time (TS), with
the converter working in the boost mode. G = 1 kW/m2 , Vo = 45 V
vpv OS (ACMC) OS (FLC) TS (ACMC) TS (FLC) Fig.

[V] [%] [%] [ms] [ms] [-]
19 → 21 27.3 0 1 0.4 5.7b
24 → 26 25.6 0 1 0.4 5.7d
26 → 28 28.3 0 1.4 0.6 5.7f
29 → 31 17.5 0 2.5 0.6 5.7h
Standard deviation 4.9 0 0.7 0.1
Table 5.1 and 5.2 report a summary of the overshoot (OS) and settling time (TS1 ) param-
eters, related to the PV module voltage transient responses displayed in Fig. 5.7.
5.5 Summary
In this chapter the feedback linearisation control technique, FLC was applied to design
a unified controller for the non-inverting buck-boost dc-MIC. The process of deriving the
control laws, for the converter operating in the buck or the boost mode, has been outlined
and controller design criteria have been discussed.
The major advantage of adopting the controller designed with the FLC technique has
been revealed in the observation of the PV module voltage transient responses. The PV
module voltage regulation occurs with a fast and consistent dynamic, regardless of the
operating point in the PV module i-v characteristic. The superior performance of the FLC
controller is apparent when compared with the average current mode controller, ACMC,
whose performance is shown to depend heavily on the i-v curve operating point. Overshoot
and settling time are both reduced when the FLC scheme is applied.
1
Time taken by transient response to settle within ± 5 % of its final value.
Compared to the ACMC technique, which only needs the measurement of the PV mod-
ule voltage and the average inductor current, the cascaded controller designed with the
FLC technique requires additional measurement of the PV module current and the output
voltage to perform the control algorithm. This does not necessarily imply that additional
sensors should be used, as the PV module current is often measured for MPPT purposes,
while the converter output can be monitored for protection purposes. The last observa-
tion regards the controller gains derived with the FLC technique, which have shown to
depend on the value of the converter passive components. This dependency demands a
tight tolerance in the value of the passive components, or parameter estimation methods.
Chapter 6
Conclusions
This brief chapter summarises the work and the research contributions documented through-
out the thesis. Conclusions are drawn based on the logical flow of topics and experiments
reported in each chapter. Finally, based on the experience gained by the author, sugges-
tions for future research endeavours are made.
6.1 Summary
The research contributions reported in this thesis have been presented across four parts.
Chapter 2 dealt with PV modelling techniques for power electronics simulation. Four
methods to pragmatically estimate the modelling parameters of the single-diode equiv-
alent circuit were reviewed. A methodology to simulate the i-v characteristic of a PV
module, for different values of solar irradiation and temperature, was proposed. This
methodology is based on the construction of a 3D LUT for the PV current, and a stream-
lined procedure for the calculation of the 3D LUT points was outlined. Making use of
3D LUTs, an approach to model the i-v characteristic of multiple PV modules connected
in series and affected by non-uniform solar irradiation was also discussed. By means of
the contributions presented in Chapter 2, users of power electronics simulation software
can rapidly gain knowledge on PV modelling parameter estimation and i-v characteristic
simulation, in uniform and non-uniform solar irradiation conditions.
Chapter 3 focussed on the operation of the non-inverting buck-boost dc-MIC, while
also discussing principles of a PV string equipped with dc-dc converters on each PV mod-
ule. The problem of the smooth transition between the buck and the boost operating
modes was studied in depth. The research contribution proposing a new solution to solve
this problem was documented and explained in its details. Experimental results show
99
Chapter 6. Conclusions 100
that, with the proposed smooth transition technique, the PV voltage regulation quality is
significantly improved at the changeover between buck and boost operating modes.
Chapter 4 described the non-inverting buck-boost dc-MIC small-signal model, linear
control and the influence of the bootstrap circuit on the regulation of the PV module
voltage. Since the dc-MIC prototype has its switching legs driven by bootstrap type gate
drivers, the effect of the bootstrap capacitor recharge on the quality of the PV module
voltage was investigated. The PV module voltage was shown to be affected by significant
ripple, when the dc-MIC input voltage is regulated by a traditional single voltage loop.
On the other hand, the cascaded control technique, entailing regulation of the PV module
voltage and average inductor current, contributed to a dramatic improvement in the qual-
ity of the PV module voltage. The disturbance induced by the operation of the bootstrap
circuit was shown to be minimized in amplitude and duration, when the cascaded control
scheme was adopted, especially when the converter was operating in the boost mode.
In Chapter 5, an emerging non-linear control technique was covered. This is the feed-
back linearisation control technique. The research contribution consisted in adopting this
technique for the dc-MIC application, undocumented in previous literature. Thanks to
this technique, the controller design was deeply simplified, since the transfer functions for
the inner and the outer loop were reduced to simple first order systems. Furthermore,
it was shown that the derived converter model is independent of the operating point in
the PV module i-v curve or the load. This is very important, since PV interfacing convert-
ers can operate with MPP voltages ranging from 45 % to 90 % of the PV module open
circuit voltage. In addition, rapid changes in the solar irradiation may temporarily move
the operating point on the PV module i-v curve [86], outside of the MPP region. While a
linear controller would result in a significant variation of the converter transient response
when operating outside of the MPP region, the FLC technique has demonstrated to ensure
a consistent converter performance, and fast dynamic response, in all the operating re-
gions of the i-v curve. In short, the advantage of using a non-linear controller with respect
to the linear control schemes of Chapter 4, consist in a straightforward controller design
for the inner and outer loops, and decoupling of the converter performance from the PV
source operating point. On the other hand, the gains of the controller designed with the
FLC technique are dependent on the value of the dc-MIC power stage components, and
therefore sensitive to their variation. Furthermore the FLC technique is not as widely em-
ployed as linear techniques for controlling power electronic converters, since it requires
an understanding of non-linear control theory.
In summary, the effort and contributions of this work ranged from modelling PV mod-
ules and systems, to applying digital control techniques to a dc-dc converter designed for
PV module interfacing applications. A sound understanding of PV modelling techniques

and converter control have been gained. Experimental results, through Chapter 3 to 5,
have demonstrated the performance improvements on the PV interfacing non-inverting
buck-boost converter.
6.2 Future Work
The converter designed and developed for this work has been used in a set of different
experiments. Novel control techniques have been tested, demonstrating improvements
of the converter operation. The converter was considered individually, in a configuration
where it was connected to a PV simulator and a programmable dc load. This work can
be continued by studying configurations with multiple PV simulators, each connected to
a non-inverting buck-boost converter with MPPT capability. With the converter outputs
connected in series, the PV string can feed a three-phase or single-phase PV inverter, thus
replicating a commercial setup employing dc-MICs. In this arrangement, the impact of
the dc-link voltage ripple on the operation of each dc-MIC could be investigated. Other
areas of research enabled by the described set-up, can involve the mutual control of the
PV inverter and the individual PV module integrated converters, in order to maximise
energy harvest and overall power conversion efficiency. With a similar setup, previous
research articles have investigated coupling effects between dc-MICs having their output
connected in series [19, 24, 93, 94]. Drawing on these previous studies, eventual coupling
effects between dc-MICs could be studied when the cascaded control technique, described
in Chapter 4, and the feedback linearisation control technique, described in Chapter 5, are
adopted.
Current literature suggests that in the future an increasing number of solutions, em-
ploying multiple dc-dc converters for a single PV module, could be developed and com-
mercialised. Innovative converter topologies, known as partial power processing convert-
ers, which only process the energy mismatch between adjacent PV sub-modules, are also
receiving attention in the research debate. Power electronic technologies can now guar-
antee efficiencies which were unimaginable in the past, especially thanks to wide band
gap semiconductors, such as GaN and SiC. Not only these new materials contributed to
an efficiency increase, but also they have allowed higher switching frequencies, achieving
extremely high power densities. Furthermore, the reliability of power electronic systems
has also considerably improved, so much that the life expectancy of module integrated
converters and PV modules is now equivalent. In this scenario there seems to be one
certainty: the era of bypass diodes as the only electronic components embedded in a PV
module is coming to an end, and power electronics converters are going to be an integral
part of future PV modules. Manufacturers of PV modules will eventually adapt to include
converters in their product portfolio and adjust their production lines accordingly.
Appendix A
Derivation of the voltage across the bootstrap capacitor
Equation (3.14) for the evolution of the voltage across the bootstrap capacitor, presented
in Chapter 3 is derived in this appendix.
Eq. (3.12) is re-written below:
dvCb
vCb = Vcc − VF − Rb Cb (A.1)
dt
where the terms written in capital letters are constants. Applying the Laplace transform
(by means of the operator L [ ]) to each side of (A.1), yields

dvCb
L [vCb ] = L [Vcc − VF ] − L Rb Cb (A.2)
dt
resulting in
Vcc − VF
vCb (s) = − sRb Cb vCb (s) + Rb Cb VCbo (A.3)
s
where:
L [vCb ] = vCb (s) (A.4a)
Vcc − VF
L [Vcc − VF ] = (A.4b)
s

dvCb
L Rb Cb = sRb Cb vCb (s) − Rb Cb vCb VCbo (A.4c)
dt
in which, VCbo is voltage across the bootstrap capacitor when t = 0, i.e. vCb (0). Collecting
the terms multiplying vCb (s) in (A.3), gives
Vcc − VF
(sRb Cb + 1) vCb (s) = + Rb Cb VCbo (A.5)
s
103
Appendix A. Derivation of the voltage across the bootstrap capacitor 104
which is the same as
Vcc − VF

1
s+ vCb (s) = + VCbo (A.6)
Rb Cb sRb Cb

1
and dividing both sides by s + R b Cb , finally it is
Vcc − VF VCbo V − VF + sRb Cb VCbo

vCb (s) = + = cc (A.7)
sRb Cb s + Rb1Cb s + Rb1Cb sRb Cb s + Rb1Cb
Eq. (A.7), has real and distinct poles, one pole located in s = 0 and the other pole located
in s = − Rb1Cb . In order to solve (A.7) by means of the inverse Laplace transform, since it
is known that L −1 [ s+a
1
] = e−at (where a is a constant), it is convenient to write (A.7) in
the form:
N1 N2
vCb (s) = + (A.8)
s s + Rb1Cb
with N1 and N2 to be determined. These can be calculated as [84] (case of partial fraction
expansion of a transfer function, (A.8), having real and distinct poles):
 
V cc − VF + sR C V
b b Cbo 
N1 = lim s  = Vcc − VF (A.9)
s→0
sRb Cb s + Rb1Cb
 
 Vcc − VF

1 + sRb Cb VCbo 
N2 = lim s+ = − [Vcc − VF − VCbo ] (A.10)
s→− R 1C Rb Cb sRb Cb s + Rb1Cb
b b
yielding
Vcc − VF Vcc − VF − VCbo
vCb (s) = − (A.11)
s s + Rb1Cb
Applying the inverse Laplace transform to (A.11) by means of the L −1 [ ] operator:

 
Vcc − VF Vcc − VF − VCbo 

L −1 [vCb (s)] = L −1 − L −1  (A.12)
s s+ 1 R b Cb
finally gives the sought formula in the time domain:
t
−R
vCb = Vcc − VF − (Vcc − VF − VCbo )e b Cb (A.13)
Appendix B
dc-MIC Design Considerations
This section of Appendix B documents the design equations which were used to select
the passive components of the dc-MIC. The procedures used in this appendix are largely
based on the guideline [65]. The choices of components values have been influenced not
only by the calculations, but also by the component availability at the time of building the
hardware. The dc-MIC designed and built for this work was considered for interfacing a
200 W multi-crystalline PV module [59], whose characteristics are reported in Table B.1.
TABLE B.1: Characteristics of the PV module

used for designing the dc-MIC
Parameter Value
MPP power Pmpp = 200 W
MPP voltage Vmpp = 26.3 V
MPP current Impp = 7.61 A
Open circuit voltage Voc = 32.9 V
Short circuit current Isc = 8.21 A
105
Appendix B. dc-MIC Design Considerations 106
dc-MIC Operating Waveforms
The below waveforms, from [65], are useful as a reference when considering the equations
reported in the following sections.
S1 S3
GATE GATE
S2 S4
GATE GATE
Vpv-Vo (Vpv)
vL vL
(-Vo) (Vpv-Vo)
DQ1 DQ2
iL Io iL Ipv
-DQ1 -DQ2
DiL,2
iS1 Ipv iS3
DiL,1
iS2 iS4 Io
D1Tsw Tsw D2Tsw Tsw
(a) (b)
F IGURE B.1: dc-MIC operating waveforms, adapted from [65]. (a) Buck mode key wave-
forms. (b) Boost mode key waveforms.
Inductor Selection
Prior to select the inductor it is necessary to establish the indicative minimum buck duty
cycle, D1,min and the maximum boost duty cycle, D2,min , stated as:
Vo,min
D1,min = = 0.286 (B.1)
Vmpp,max
Vo,max − Vmpp,min
D2,max = = 0.85 (B.2)
Vo,max
where the dc-MIC minimum output voltage is chosen as Vo,min = 10 V, the dc-MIC max-
imum output voltage as Vo,max = 100 V, the PV module minimum MPP voltage Vmpp,min
= 15 V and the PV module maximum MPP voltage Vmpp,max = 35 V, accounting for vari-
ations occurring to the MPP voltage due to different temperatures. The ripple component
of the inductor current, in the worst case scenario fo the buck, ∆iLmax,1 , and the boost
mode, ∆iLmax,2 , is:
Vo,min (1 − D1,min )
∆iLmax,1 = (B.3)
L fsw
Vmpp,min D2,max
∆iLmax,2 = (B.4)
L fsw
The inductor has been calculated considering a maximum current ripple limited to ± 30
% of the maximum dc current processed by the converter, according to the design practice
suggested by [65]. Therefore, considering the maximum average inductor current in the
Pmax Pmax
buck and in the boost mode to be ILmax,1 = 2
Vout,min
and ILmax,2 = 2
Vmpp,min
, respectively,
then inserting these formulae into (B.3) and (B.4) gives the minimum value to be selected
for the inductance. This must be the greatest between:
2
Vo,min (1 − D1,min )
Lmin,1 ≥ = 2.43 µH (B.5)
0.6Pmax fsw
2
Vmpp,min D2,max
Lmin,2 ≥ = 6.5 µH (B.6)
0.6Pmax fsw
where the switching frequency is fsw = 200 kHz and Pmax is the maximum power pro-
cessed by the dc-MIC, when the PV module output is 245 W (considering a solar irradiation
G = 1 kW/m2 and T = -20 ◦ C). Based on these considerations and on component avail-
ability, it has been decided to use an inductance of 22 µH, available from Coilcraft R [69].
The chosen inductor maintains its inductance constant up to more than 20 A current, and
for frequency higher than 1 MHz, according to the manufacturer data reported in Fig. B.2.
F IGURE B.2: Inductance properties reported in the datasheet [69].
Output Capacitor Selection
The formula for sizing the output capacitor was taken from [65], and it refers to the buck
operation of the dc-MIC. Under this mode, the charge exchanged with the output capacitor
is:
1 ∆iLmax,1 Tsw 1 Vo,min
∆Q1 = = 2 L
(1 − D1,min ) (B.7)
2 2 2 8 fsw
from which the minimum output capacitance value can be calculated based on the voltage
ripple on the output capacitor, in the worst case buck operation, considering a maximum
voltage ripple ∆Vo limited to 5 % of the minimum output voltage Vo,min , i.e. ∆Vo ≤ 0.5 V:
Vmpp,max − Vo,min

∆Q1 1 Vout,min 1 Vo,min
Co ≥ = 2
(1 − D1,min ) = 2 L
= 2 µF (B.8)
∆Vo 8 ∆Vo fsw L 8 ∆Vo fsw Vmpp,max
Therefore, based on the above calculation, components availability and recommendation

from [65] the output capacitance value chosen is Co = 2.35 µF, made by five parallel
ceramic capacitors (X7R dielectric) of 0.47 µF value each. The voltage rating of the output
capacitors has been chosen equal to 200 V, twice the value of the dc-MIC maximum output
voltage.
Input Capacitor Selection
According to [65], the input capacitor is sized based on the worst operating condition
of the dc-MIC, in the boost mode. In such case, the charge exchanged with the input
capacitor is:
1 ∆iLmax,2 Tsw 1 Vmpp,min
∆Q2 = = 2 L
D2,max (B.9)
2 2 2 8 fsw
from which, if the input voltage ripple ∆Vpv is limited to the 5 % of the minimum input
voltage Vmpp,min = 15 V, it is:
Vout,max − Vmpp,min

∆Q2 1 Vmpp,min 1 Vmpp,min
Ci ≥ = 2
D2,max = 2 L
= 12 µF (B.10)
∆Vpv 8 ∆Vpv fsw L 8 ∆Vpv fsw Vout,max
Considering that ripple in dc-MIC input voltage affects the voltage on the PV module,
and considering the availability of components, it has been decided to use a conservative
value for the input capacitance, equal to Ci = 100 µF, made by five parallel 22 µF ceramic
capacitor (X7R dielectric), with a maximum voltage rating of 100 V.
Considerations Regarding the Switches
From the guideline [65] the following values represent the worst case scenario for the
switches.
Switch S1 - The worst case rms current for this switch is:
 Pmax

 p = 13 A buck mode


 Vout,min Vmpp,max
Irms,S1 = (B.11)
Pmax




 = 16 A boost mode
Vmpp,min
while the worst case peak current is:
Pmax Vo,min (1 − D1,min )



 + = 25.3 A buck mode
 Vo,min 2L fsw


Ipk,S1 = = (B.12)
Pmax Vmpp,min D2,max


+ = 17.8 A boost mode



Vmpp,min 2L fsw
The voltage rating of S1 must be greater than the maximum open circuit voltage of the PV
module.
s
Pmax Vo,min
Irms,S2 = 1− = 20.7 A (B.13)
Vo,min Vmpp,max
while the worst case peak current is the same as the one in S1 . The voltage rating of S2 is
the same as S1 .
 Pmax
 = 24.5 A buck mode
Vo,min





Irms,S3 = s (B.14)
Pmax Vo,max − Vmpp,min




 = 15 A boost mode
Vmpp,min Vo,max

while the worst case peak current is the same as the one in S1 . The voltage rating of S3
must be higher than the maximum dc-MIC output voltage.
Pmax
Irms,S4 = p = 6.3 A (B.15)
Vo,max Vmpp,min
while the worst case peak current formulas are the same as for S1 . The voltage rating of
S4 must be higher than the maximum dc-MIC output voltage.
The switch chosen is a silicon MOSFET, from Infineon R , model IPP075N15N3 [70]
(also adopted in [22]), featuring a drain current ID = 100 A, a drain to source voltage
VDS = 150 V and low on-resistance equal to RDS(on) = 7.2 mΩ.
1 2 3 4 5 6 7 8
VB1 VB2
R116 R117
2 2
2
2
2/3W 5% 2/3W 5%
A TP108GND TP109GND A
D106 D107
KA
KA
CTL_GND TP108 200V 2A L118 CTL_GND TP109 200V 2A
UCC100 UCC101
1 2
12 Bst_Input 8 2
Bk_Input 8 2 78ohm 25MHz IN HB
1
IN HB
1
1uF
Enable 7 3 Gate_Pulse_Q100 VB2 Enable 7 3 Gate_Pulse_Q101 C109 1uF
EN HO C108 EN HO
50V 5% 50V 5%
RDT_1 6 4 Bk_Leg_Mid RDT_2 6 4 Bst_Leg_Mid
L119 RDTHS RDTHS
dc-MIC Electrical Schematics
VB1
1 2 1 10 Gate_Pulse_Q102 1 10 Gate_Pulse_Q103
+12V VDDLO
Appendix B. dc-MIC Design Considerations
+12V 12 VDDLO
78ohm 25MHz C111 5 9
C1105 9 R118 No BOM NCVSS
R119 No BOM 3.3uF NCVSS 3.3uF
50V 10% LM5106MM/NOPB_BK 10 50V 10% LM5106MM/NOPB_BST
10
2/3W 2/3W Mounted on LCQT-MSOP10CTL_GND
Mounted on LCQT-MSOP10CTL_GND 5%
5% CTL_GND
CTL_GND
Gate drivers and dead-time control

RDT_2
Deat-time control resistors

RDT_1 633-MRF206 0.25W
J101 RSW100 0.1%
Open 1
B 2 B
F IGURE B.3: Schematic diagram of the gate driving stage.

J100 CTL_GND
Shorted 1
2
R110 10K A1
R110a 10K B1
R115 39.2KA6
R114 34K A5
R113 23.7KA4
R112 18.2KA3 A
R111 13K A2
R115a 39.2KB6
R114a 34K B5
R113a 23.7KB4
R112a 18.2KB3 B
R111a 13K B2
When shorted J100 and J101

sets dead-time to minimum CTL_GND
C C
111
1 2 3 4 5 6 7 8
A A
Copper Link for

ac operation
PVPWR PVPWR-1 PVPWR-2 VOPWR-2 VOPWR

2
JAC1 No BOM TP101 PWR_OUT

PWR_IN TP100
N1 N2 D100
No BOM No BOM No BOM No BOM
1 2x15A 2
Ci_100 Ci_101 Ci_102 Ci_103 Ci_104 Co_100 Co_101 Co_102 Co_103 Co_104 Co_105 Co_106 1
2 Ci_105 Ci_106 200V
22uF 22uF 22uF 22uF 22uF JAC2 No BOM 0.47uF 0.47uF 0.47uF 0.47uF 0.47uF
22uF 22uF
100V 100V 100V 100V 100V 200V 200V 200V 200V 200V 250V 250V
100V 100V N1 N2
1
3
20% 20% 20% 20% 20% 10% 10% 10% 10% 10% 20% 20%
20% 20%
PVRTN PVRTN
TP103 TP102
D0 D101 30V 2A D1 D102 30V 2A
PVRTN RD101 RD102 R not in BOM PVRTN
2 1 2 1
AK AK
2
5.1 5.1
2
2
Q100 1/2W 1% D108 Q101 1/2W 1%
R102 R103
Appendix B. dc-MIC Design Considerations
150 V 1 Gate_Pulse_Q100 150 V 1 Gate_Pulse_Q101

100 A 2x15A 100 A
24.9 200V 15
R104 2/3W 1% R105 2/3W 1%
2/3W
B 2/3W 10K B
1
3
10K G0 G1
5% 5%
3
3
2
1
AC_LOAD
S0_1 S0 SW_BK SW_BST S1_1 S1
L N
L100
Bk_Leg_Mid IND_IM IND_I Bst_Leg_Mid
F IGURE B.4: Schematic diagram of the power stage.

D103 30V 2A 22uH
D104 30V 2A
2 1 RD103 R not in BOM D3 2 1 RD104
2
D2 AK AK
5.1
2
5.1
2
D105 Q102 1/2W 1% Q103 1/2W 1%

150 V 1 R106 Gate_Pulse_Q102 R107
2x15A 150 V 1 Gate_Pulse_Q103
100 A 15 100 A 20
200V R108 R109
2/3W 2/3W 1% 2/3W 1%
1
3
10K G2 2/3W 10K
5% 5% G3
3
3
S2 S3
S2_1 S3_1
PVRTN PVRTN
C C
112
D D
Title
Size Number Revision

A3
2 3 4 5 6 7
VB1 VB2
R116 R117
Appendix B. dc-MIC Design Considerations 2 113 2
2
2
2/3W 5% 2/3W 5%
TP108GND D106 TP109GND D107
KA
KA
CTL_GND TP108 200V 2A L118 CTL_GND TP109 200V 2
UCC100 UCC101
1 2
12 Bst_Input 8 2
1 2 Bk_Input 8 3 2 4 5
78ohm 25MHz
6
IN HB 7 8
IN HB
1uF
1
1
Enable 7 3 Gate_Pulse_Q100 VB2 Enable 7 3 Gate_Pulse_Q101 C109 1
EN HO C108 EN HO
50V 5% 50V 5
RDT_1 6 4 Bk_Leg_Mid RDT_2 6 4 Bst_Leg_
L119 RDTHS RDTHS
VB1 +12V -12V
1 +12V -12V
2 1 +12V -12V
10 Gate_Pulse_Q102 +12V -12V 1 10 Gate_Pulse_Q103
+12V 12 VDDLO Resistors:
+12V VDDLO
78ohm 25MHz 1W C111 5 9
C1105 9 0.1% R118 No BOM C1001 C1011
NCVSS 0.1uF
C102 R119 No BOMC103
3.3uF NC
C104VSS C105 C100 C101 3.3uF
0.1uF
A 0.1uF 0.1uF
50V 10%
0.1uF 0.1uF 0.1uF 0.1uF 50V100V
10% LM5106MM/NOPB_BST
100V
100V 10
R101p2
Resistors:
100V 10 100V LM5106MM/NOPB_BK
100V 100V 24.9K 100V 10% 10%
10% 10% 10% 10% 10% 10%2/3W Mounted on LCQT-MSOP10 CTL_GND
5/8W
R100p
2/3W Mounted on LCQT-MSOP10CTL_GND R101p1
5%
CTL_GND CTL_GND
0.1%
7.5K
CTL_GND 5% CTL_GND CTL_GND CTL_GND 24.9K CTL_GND CTL_GND
CTL_GND
+
CTL_GND
-
+
+
-
-
Bst_Leg_Mid
4
R101 4
R100 24.9Kdead-time control 1
PVPWR 7.5K +HV V_IN Gate drivers and
VOPWR +HV V_OUT 5
1 I_IND
-
+
+HV I_IN +HV 5
1
M 1
M 2 1
M
+
+
-
-
M PVRTN M 2 M
PVRTN -HV M
1 RDT_2 -HV 6
-HV M -HV 6
IND_I 3
3
LV_IN LV_OUT LAX_IND
Deat-time controlCurrent_sensor_high_BW_IND
resistors
GND
GND
GND
Voltage_transducer_IN Voltage_transducer_OUT
LA 55-P
RDT_1 633-MRF206
GND
Input current sensor 0.25W
J101 RSW100 0.1%
CTL_GND CTL_GND CTL_GND CTL_GND
Open 1
2
R112 18.2KA3 A
R112a 18.2KB3 B
R115 39.2KA6
R114 34K A5
R113 23.7KA4
R111 13K A2
R110 10K A1
F IGURE B.5: Schematic diagram of the current and voltage transducers.
R115a 39.2KB6
R114a 34K B5
R113a 23.7KB4
R111a 13K B2
R110a 10K B1
J100 CTL_GND
Shorted 1
B
2
When shorted J100 and J101
sets dead-time to minimum CTL_GND
PVPWR
PVRTN 5V
5V
C112 C113
47uF 0.1uF
C DC-DC converter power 100V 100V
1 TP110 TP111
L101 AUX_DC_DC100 CTL_GND
A1 2 1 7
1 3 VCC OUT1 5V
A2 15uH C114
2 +12V
47uF +12V
P100 4 2 4
100V GND OUT 2 +12V C116 C115 CTL_GND3 CTL_GND2 CTL_GND1
5
47uF 0.1uF
6 100V 100V
3 6 CTL_GND
REM ON/OFF COM
S100 TP112
C117 C118 N1 N2
5 47uF 0.1uF
OUT 3 -12V 100V
100V
Net_tie
TEN 30-2431WIN
CTL_GND PVRTN
-12V
-12V
D
Note the only link between CTL_GND and PVRTN
(Net Tie)
Title

F IGURE B.6: Schematic diagram of the auxiliary power supply. A3
Date: 3/23/2018 Sheet of
File: Sheet1.SchDoc Drawn By:
1 2 3 4 5 6 7 8
Title
1 2 3 4 Size Num
A3
Date: 3/23/2
BK 5V Gate driving singals BST 5V File: Sheet
2 AFBR_2624Z 3 4 AFBR_2624Z 5 6 7
4 4
NC NC
Buck PWM light 3 Boost PWM light 3
A VCC VCC A
signal from DSP C200 signal from DSP C201 100V
2 0.1uF 2 0.1uF 10%
GND GND
1 LED200_GN 1 LED201_GN LED:
D_OUT D_OUT
CTL_GND CTL_GND If=2mA
Vf=2V
Resistors
R200 R201 in this sheet:
5
1.5K 1.5K 1/8W

Buck_Drive Boost_Drive
1%
CTL_GND Buck gate driver input CTL_GND Boost gate driver input
CTL_GND CTL_GND
B B
F IGURER_EN200
B.7: Schematic 5V
diagram of the optical receivers for the
Enable circuitry S_EN200buck and5V boost PWM
AFBR_1624Z
AFBR_2624Z
signal coming
NC
4 from the control platform. VCC
1
3 2
VCC NC
Receive enable light C203 100V Send enable light C202 100V
2 0.1uF 10% to next converter 3 0.1uF 10%
from previous converter GND GND
or from DSP (for first converter) 4
1 D_In
D_OUT CTL_GND
CTL_GND
LED203_GN
R202 R203
5
8
5
1.5K 1.5K
CTL_GND LED202_RD CTL_GND

CTL_GND CTL_GND
C C
CTL_GND
Enable signal for the next converter
A2
Push-button contact (NC) 2
A1 5V
1 R204
10K
TB200
5
5V
1
A 4 Enable signal for the gate drivers
1
1 2 3 4
Enable circuitry S_EN200

R_EN200 5V 5V
AFBR_1624Z
AFBR_2624Z
A 4 1 A
NC VCC
3 2
VCC NC
Receive enable light C203 100V Send enable light C202 100V
to next converter 3 0.1uF 10% LED:
from previous converter 2 0.1uF 10% GND
GND If=2mA
or from DSP (for first converter) 4 Vf=2V
1 D_In
D_OUT CTL_GND
CTL_GND
Resistors
LED203_GN in this sheet:
1/8W
R202 R203 1%
8
5
1.5K 1.5K
CTL_GND LED202_RD CTL_GND

CTL_GND CTL_GND
CTL_GND
Enable signal for the next converter
B A2 B
Push-button contact (NC) 2
A1 5V
1 R204
10K
TB200
5
5V
1
A 4 Enable signal for the gate drivers
by-pass push-button 1 2 Y En
contact when 2 & 3 are 2 B
shorted 3 U200
TB201 Mounted on LCQT-SOT23-6
3
CTL_GND
R206p R206
20K 20K C204
10pF
50V
5%
C C
CTL_GND CTL_GND
F IGURE B.8: Schematic diagram of the Enable optical receiver and transmitter.
Title
D D

A4
Date: 3/23/2018 Sheet of
File: C:\Users\..\200_Opto_and_enable_si_v3.1.SchDoc
Drawn By:
1 2 3 4
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Photovoltaic Module Integrated dc-dc Converters: Modulation

and Advanced Control Techniques.

Downloaded from http://hdl.handle.net/1959.4/60423 in https://

A thesis submitted in fulfilment of the requirements for the degree of

School of Electrical Engineering and Telecommunications

The University of New South Wales

Surname/Family Name Callegaro

Abstract 350 words maximum: (PLEASE TYPE)

Declaration relating to disposition of project thesis/dissertation

-=oR OFFICE USE ONLY Date of completion of requirements for Award:

I would like to express my heartfelt gratitude to my main supervisor, Dr Mihai Ciobotaru,

List of Figures vii

2.6.3 General Considerations on the Creation and Use of 3D LUTs . . . . . 34

3 Non-Inverting Buck-Boost Converter 38

4 Linear Control of the Non-Inverting Buck-Boost dc-MIC 70

5 Non-linear control of the Non-Inverting Buck-Boost dc-MIC 86

1.1 Evolution of PV installations . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1 PV module equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1 PV string equipped with dc-MICs, feeding a single phase PV inverter . . . . . 39

3.12 Actual duty cycle characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.1 Block diagram for designing the current controller . . . . . . . . . . . . . . 88

1.1 Configuration overview of grid connected PV systems . . . . . . . . . . . . . 4

2.1 Estimated modelling parameters for the PV module KC200GT . . . . . . . . 23

4.1 Steady state regime of a PV string with 2 dc-MICs . . . . . . . . . . . . . . . 77

1.1.1 Energy Outlook

1.1.2 Architectures of Grid Connected PV systems

1 or 3 phase 1 or1 13oror

(a) (b) (c) (d) (e)

i pv ,2 dc-MIC2 MICs.i pv(e): ,2

i pv ,n dc-MICn i pv ,ni pvi pv,n ,ndc-MIC

Power Supply PowerPower

Large Scale Medium Scale Small Scale

1.1.3 Energy Recovery Potential of dc-MICs

Diminishing costs of power electronics components, higher efficiencies and technologi-

1.2 Overview of the Non-Inverting Buck-Boost Converter

TABLE 1.2: Documented energy recovery potential of dc-MICs

Energy lost Fraction of the Overall system

TABLE 1.3: Notable research contributions on dc-MIC topologies

Walker [15], 2001 General evaluation of buck and boost

1.3 Motivation and Objectives

1) Develop practical models to simulate the electrical behaviour of PV modules, which

2) Understand and improve the operation of the non-inverting buck-boost topology,

1.4 Methodology and Limitations

1.5 Scientific Contributions

• Improved operation of the non-inverting buck-boost converter.

• Improved PV module voltage regulation quality employing the cascaded control

• Applied an emerging non-linear control technique to a new research problem.

• Given insight on practical modelling of PV modules for power electronics

• Comprehensively reviewed PV module parameter estimation techniques based

1.5.1 List of Publications

I L. Callegaro, M. Ciobotaru and V. G. Agelidis, “Analysis and comparison of electrical

II L. Callegaro, M. Ciobotaru and V. G. Agelidis, “Implementation of 3D lookup tables in

IV L. Callegaro, M. Ciobotaru, J. E. Fletcher, P. A. Rios and D. J. Pagano, “Design of

V L. Callegaro, D. J. Pagano, M. Ciobotaru and J. E. Fletcher, “Feedback linearization

VI L. Callegaro, M. Ciobotaru, D. J. Pagano, E. Turano and J. E. Fletcher, “A Sim-

Publication Thesis chapter

1.6 Thesis Outline

2.1 PV Modelling Overview

In order to simulate the behaviour of a converter connected to a PV module, it is first

Iph Iph id id ip ip + + Iph Iph id1 id1id2 id2ip ip + + Iph Iph id

Iph id1 id2 ip ipv + Iph id ip ipv +

2.2 Equivalent Circuit Parameter Estimation

2.3 Review of Parameter Estimation Techniques

2.3.1 First Analytical Method

Vmpp +Impp Rs −Voc