CPEN 211: Introduction to Microcomputers

Sequential Logic
(Flipped Lecture - In Class)

Prof. Tor Aamodt

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 The Plan for Today

• [2-3 min.] Discuss question as group.

• [20 min.] You solve question; ask for help from
2-3x
TAs/me if you get stuck.
• [15 min.] We take up solutions as a group.

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Q1: Create a digital circuit that implements the following finite
state machine using a one-hot code for the states. Put your
final answer in the form of a logic diagram using logic gates.

Inputs are 1-bit signals “s” and “t”, Same state machine, but different style
output is “f”. (2-bit input “in”, 1-bit output, self loops
from A to A and C to C are implicit).
Implicit self loop from C to C. 3
Q2: Create a digital circuit that implements the following finite
state machine using a binary code for the states. Put your final
answer in the form of a logic diagram using logic gates.

Inputs are 1-bit signals “s” and “t”, Same state machine, but different style
output is “f”. (2-bit input “in”, 1-bit output, self loop
from A to A is implicit).
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Q3: Create a digital circuit that implements the following finite state machine
using a binary code for the states. In the figure below a value of “x” for
output label means “don’t care” and for input means the expression is true for
both 0 and 1 values. Put your final answer in the form of a logic diagram using
logic gates. Only draw a circuit for the most significant state bit and output s.
Note this is a Mealy machine and the outputs depend upon both input and the
current state. To indicate this, the output is labeled on the transition edges
using the format: <input condition>/<output>.

uv=11/st=x0 uv=x1/st=x0

uv=00/st=xx uv=x0/st=00
A B
uv=11/st=01
uv=10/st=1x uv=10/st=00

uv=01/st=11

C D

uv=xx/st=00 uv=0x/st=10