NAANMUDHALVAN

ANALOG IC DESIGN

TASK 3

NAME:R.ROHITH
REG.NO:820621121009
ARASU ENGINNERING COLLEGE

ANALOG IC DESIGN
Task 3
DesignaCommonSourceAmplifier with W/L value 20/2 for NMOS, 5/2 for PMOS and 300nm AMI
Semiconductor's C5 Process andanalyzeitsperformance.
A.Design of Schematic and Simulation of Commonsourceamplifier Using EDA Tool
 B.Design of Layout and Simulation of Commonsourceamplifier Using Electric EDA Tool
Part A
◆ Explain the concept of a common-source amplifier and its importance in analog circuit design
◆ Design a schematic representation of the common-source amplifier in the Electric VLSI EDA tool
◆ Perform the design verification checks such as DRC and ERC to verify the integrity of the schematic
design and identify any potential errors or violations
◆ Simulate the common-source amplifier schematic to evaluate its performance through waveform
analysis Part B
◆ Learn the process of creating a layout representation for a common source amplifier using the
Electric VLSI EDA tool
◆ Perform DRC and ERC to ensure that the layout meets the specified design rules and to address any
potential electrical connectivity concerns
◆ Verify the layout's connectivity and compatibility through Layout vs. Schematic (LVS) checking
◆ Simulate the layout of the Common Source Amplifier to analyze its performance and characteristics
Software Tools: Electric VLSI EDA Tool- Open Source Equivalent EDA tool to Cadence

SOLUTION :
PART A
Design of Schematic and Simulation of Common-Source AmplifierUsing EDA Tool

SCHEMATIC DESIGN

Perform the design verification checks such as DRC to verify the integrity of
theschematicdesign and identifyanypotentialerrors orviolations
DRCCHECK

Simulate the common-source amplifier schematic to evaluate its performance through waveform
analysis

DC OPERATING POINT (For SCHEMATIC Design)/ .OP

SPICE ERROR LOG (For SCHEMATIC Design)

TRANSIENT ANALYSIS –COMMONSOURCEAMPLIFIER\.tranAnalysis

FREQUENCYRESPONSEANALYSIS\.acAnalysis
 PART B
Learntheprocessofcreatingalayoutrepresentationforacommonsourceamplifierusingthe
ElectricVLSIEDAtool

LAYOUTDESIGN

Perform DRC and ERC to ensure that the layout meets the specified design rules and toaddress anypotential
electrical connectivityconcerns

DRCCHECK
ERCCHECK

Verifythe layout'sconnectivityand compatibilitythroughLayoutvs. Schematic(LVS)checking

NCCCHECK
SimulatethelayoutoftheCommonSourceAmplifiertoanalyzeitsperformanceandcharacteris
ticsDC OPERATING POINT (For LAYOUT Design)/ .OP

SPICE ERROR LOG (For LAYOUT Design)

TRANSIENT ANALYSIS \.trananalysis

FREQUENCYRESPONSEANALYSIS\.acanalysis